[VHDL] 7-Segment Display Controller designed to display the number "1515" as an example.

1.seven_segments_controller.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

-- * Author: Dante Mendoza Leyva (4CV13)

entity seven_segments_controller is Port (
    clk:                in      std_logic;
    anodes:             out     std_logic_vector(3 downto 0);
    display_glyph:      out     std_logic_vector(6 downto 0)
);
end seven_segments_controller;

architecture Behavioral of seven_segments_controller is
    -- This function encodes 4-bit values to seven segment display data
    function as_seven_segment(input_bits: std_logic_vector(3 downto 0)) return std_logic_vector is
        variable converted_value : std_logic_vector(6 downto 0);
    begin
        case input_bits is
            when "0000" => converted_value := "0000001"; -- 0
            when "0001" => converted_value := "1001111"; -- 1
            when "0010" => converted_value := "0010010"; -- 2
            when "0011" => converted_value := "0000110"; -- 3
            when "0100" => converted_value := "1001100"; -- 4
            when "0101" => converted_value := "0100100"; -- 5
            when "0110" => converted_value := "0100000"; -- 6
            when "0111" => converted_value := "0001111"; -- 7
            when "1000" => converted_value := "0000000"; -- 8
            when "1001" => converted_value := "0000100"; -- 9
            when others => converted_value := "1111111";
        end case;
        return converted_value;
    end as_seven_segment;
    
    ------------------------------------------------------------
    
    signal DISPLAY_REFRESH_COUNTER:   integer range 0 to 6000 := 0;
    signal ANODE_SELECTOR:  std_logic_vector(1 downto 0);
    
    signal display_0: std_logic_vector(6 downto 0) := as_seven_segment("0001");
    signal display_1: std_logic_vector(6 downto 0) := as_seven_segment("0101");
    signal display_2: std_logic_vector(6 downto 0) := as_seven_segment("0001");
    signal display_3: std_logic_vector(6 downto 0) := as_seven_segment("0101");
    
begin
    -- Clocking Process
    process (clk)
    begin
        if (clk'event and clk = '1') then
            DISPLAY_REFRESH_COUNTER <= DISPLAY_REFRESH_COUNTER + 1;
            -- ! Assuming 100MHz clock !
            -- Update each 6μs (100_000_000 = 1_000_000μs -> 6_000 = 6μs)
            if (DISPLAY_REFRESH_COUNTER < 6000) then
                DISPLAY_REFRESH_COUNTER <= DISPLAY_REFRESH_COUNTER + 1;
            else
                -- Dispatch event for: `process (ANODE_SELECTOR)`
                ANODE_SELECTOR <= ANODE_SELECTOR + 1;
                DISPLAY_REFRESH_COUNTER <= 0;
            end if;
        end if;
    end process;

    -- "Rendering" Process
    process (ANODE_SELECTOR)
    begin
        case ANODE_SELECTOR is
            when "00" => display_glyph <= display_0;
            when "01" => display_glyph <= display_1;
            when "10" => display_glyph <= display_2;
            when "11" => display_glyph <= display_3;
            when others => display_glyph <= "0000000";
        end case;

        case ANODE_SELECTOR is
            when "00" => anodes <= "0111"; -- 0
            when "01" => anodes <= "1011"; -- 1
            when "10" => anodes <= "1101"; -- 2
            when "11" => anodes <= "1110"; -- 3
        end case;
    end process;
end Behavioral;

constraints.xdc

set_property -dict { PACKAGE_PIN W7   IOSTANDARD LVCMOS33 } [get_ports {display_glyph[6]}]
set_property -dict { PACKAGE_PIN W6   IOSTANDARD LVCMOS33 } [get_ports {display_glyph[5]}]
set_property -dict { PACKAGE_PIN U8   IOSTANDARD LVCMOS33 } [get_ports {display_glyph[4]}]
set_property -dict { PACKAGE_PIN V8   IOSTANDARD LVCMOS33 } [get_ports {display_glyph[3]}]
set_property -dict { PACKAGE_PIN U5   IOSTANDARD LVCMOS33 } [get_ports {display_glyph[2]}]
set_property -dict { PACKAGE_PIN V5   IOSTANDARD LVCMOS33 } [get_ports {display_glyph[1]}]
set_property -dict { PACKAGE_PIN U7   IOSTANDARD LVCMOS33 } [get_ports {display_glyph[0]}]

# set_property -dict { PACKAGE_PIN V7   IOSTANDARD LVCMOS33 } [get_ports dp]

set_property -dict { PACKAGE_PIN U2   IOSTANDARD LVCMOS33 } [get_ports {anodes[0]}]
set_property -dict { PACKAGE_PIN U4   IOSTANDARD LVCMOS33 } [get_ports {anodes[1]}]
set_property -dict { PACKAGE_PIN V4   IOSTANDARD LVCMOS33 } [get_ports {anodes[2]}]
set_property -dict { PACKAGE_PIN W4   IOSTANDARD LVCMOS33 } [get_ports {anodes[3]}]

set_property -dict { PACKAGE_PIN W5   IOSTANDARD LVCMOS33 } [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

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