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disable-virtualization-gigabyte-h410m-no-bios-mod.md

Disable Virtualization on Gigabyte H410M Without BIOS Mod

This was tested on Gigabyte H410M H V3 (rev. 1.0)
BIOS version: F9 (Dec 20, 2023)

Preparation

Steps

  1. Format the USB stick to FAT32

  2. Place the file modGRUBShell.efi on the USB stick in this directory, so it looks like this X:\EFI\BOOT\modGRUBShell.efi.

  3. Disable Secure Boot and then enable CSM in the BIOS.

  4. Press F12 to boot from the USB stick. Select the one with UEFI: at the beginning.

  5. Now type this command:

    To disable virtualization:

    setup_var_cv CpuSetup 0xB9 0x1 0x0

    To enable virtualization:

    setup_var_cv CpuSetup 0xB9 0x1 0x1

  6. Type reboot when you're done

Where do I get these commands?

I followd this guide: https://github.com/BoringBoredom/UEFI-Editor

image

Raw
flashing-custom-bios-gigabyte-motherboard.md

Flashing Custom BIOS on Gigabyte Motherboard

This was tested on Gigabyte H410M H V3 (rev. 1.0)
Downgrade BIOS version from F9 (Dec 20, 2023) to F2 (Sep 23, 2021)

1) Unlock Intel Flash Descriptor/SPI Servicing ("pinmod")

  1. Shutdown the system completely
  2. Short DVDD pin(1) & SDATA-OUT pin(5)
  3. Keep shorting the pins and power on the system
  4. Fans should blasting full speed
  5. Once the BIOS/OS starts to load, stop shorting
  6. The Flash Descriptor should now be unlocked!

Realtek ALC888/ALC887 Pinouts:

image image

2) Flash BIOS via FPT

  1. Download the correct CSME System Tools according the motherboard chipset
  2. Open terminal under CSME System Tools v15.0 r15\Flash Programming Tool\WIN64
  3. Type this command to start flashing:
    fptw64 -SAVEMAC -f <BIOSNAME.bin>
  4. Reboot after it finished
Raw
formatted_Section_PE32_image_Setup_Setup.sct.0.0.en-US.ifr.txt
This file has been truncated, but you can view the full file.
Advanced Frequency Settings
BCLK Output Source | VarStore: Setup | VarOffset: 0xA2F | Size: 0x1
Auto: 0x0
ICC: 0x1
Buffer: 0x2
Advanced Frequency Settings
CPU Base Clock | VarStore: Setup | VarOffset: 0xA0A | Size: 0x4
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced Frequency Settings
Host Clock Value | VarStore: Setup | VarOffset: 0xA1B | Size: 0x4
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced Frequency Settings
Processor Graphics Clock | VarStore: Setup | VarOffset: 0xA23 | Size: 0x4
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced Frequency Settings
IGP Ratio | VarStore: Setup | VarOffset: 0xA27 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced Frequency Settings
CPU Clock Ratio | VarStore: Setup | VarOffset: 0xA04 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced Frequency Settings
CPU Frequency | VarStore: Setup | VarOffset: 0xA06 | Size: 0x4
Min: 0xFFFFFFFF | Max: 0xFFFFFFFF | Step: 0x1
Advanced Frequency Settings
FCLK Frequency for Early Power On | VarStore: CpuSetup | VarOffset: 0xFC | Size: 0x1
Normal (800Mhz): 0x0
1GHz: 0x1
400MHz: 0x2
Advanced Frequency Settings
Extreme Memory Profile(X.M.P.) | VarStore: Setup | VarOffset: 0xAD5 | Size: 0x1
Disabled: 0x0
Profile1: 0x1
Profile2: 0x2
Advanced Frequency Settings
Extreme Memory Profile(X.M.P.) | VarStore: Setup | VarOffset: 0xAD5 | Size: 0x1
Disabled: 0x0
Profile1: 0x1
Advanced Frequency Settings
Extreme Memory Profile(X.M.P.) | VarStore: Setup | VarOffset: 0xAD5 | Size: 0x1
Disabled: 0x0
Profile2: 0x2
Advanced Frequency Settings
System Memory Multiplier | VarStore: Setup | VarOffset: 0xAD6 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced Frequency Settings
Memory Ref Clock | VarStore: Setup | VarOffset: 0xAE3 | Size: 0x1
Auto: 0x0
100: 0x1
133: 0x2
Advanced Frequency Settings
Memory Odd Ratio (100/133 or 200/266) | VarStore: Setup | VarOffset: 0xAE2 | Size: 0x1
Auto: 0x0
Enabled: 0x1
Disabled: 0x2
Advanced Frequency Settings
Memory Frequency(MHz) | VarStore: Setup | VarOffset: 0xAD8 | Size: 0x2
Min: 0xFFFF | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
CPU Clock Ratio | VarStore: Setup | VarOffset: 0xA04 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
CPU Frequency | VarStore: Setup | VarOffset: 0xA06 | Size: 0x4
Min: 0xFFFFFFFF | Max: 0xFFFFFFFF | Step: 0x1
Advanced CPU Settings
FCLK Frequency for Early Power On | VarStore: CpuSetup | VarOffset: 0xFC | Size: 0x1
Normal (800Mhz): 0x0
1GHz: 0x1
400MHz: 0x2
Advanced CPU Settings
CPU PLL Selection | VarStore: Setup | VarOffset: 0xA57 | Size: 0x1
Auto: 0x0
LCPLL: 0x1
SBPLL: 0x2
Advanced CPU Settings
Filter PLL Level | VarStore: Setup | VarOffset: 0xA58 | Size: 0x1
Auto: 0x0
Low: 0x1
High: 0x2
Advanced CPU Settings
AVX settings | VarStore: Setup | VarOffset: 0xA5F | Size: 0x1
Auto: 0x0
User Defined: 0x1
Advanced CPU Settings
AVX Disable | VarStore: Setup | VarOffset: 0xA60 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
AVX512 Disable | VarStore: Setup | VarOffset: 0xA61 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
AVX Offset | VarStore: Setup | VarOffset: 0xA62 | Size: 0x1
Auto: 0x20
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
9: 0x9
10: 0xA
11: 0xB
12: 0xC
13: 0xD
14: 0xE
15: 0xF
16: 0x10
17: 0x11
18: 0x12
19: 0x13
20: 0x14
21: 0x15
22: 0x16
23: 0x17
24: 0x18
25: 0x19
26: 0x1A
27: 0x1B
28: 0x1C
29: 0x1D
30: 0x1E
31: 0x1F
Advanced CPU Settings
CPU Over Temperature Protection | VarStore: Setup | VarOffset: 0xA69 | Size: 0x1
Auto: 0x0
80°C: 0x2D
81°C: 0x2C
82°C: 0x2B
83°C: 0x2A
84°C: 0x29
85°C: 0x28
86°C: 0x27
87°C: 0x26
88°C: 0x25
89°C: 0x24
90°C: 0x23
91°C: 0x22
92°C: 0x21
93°C: 0x20
94°C: 0x1F
95°C: 0x1E
96°C: 0x1D
97°C: 0x1C
98°C: 0x1B
99°C: 0x1A
100°C: 0x19
101°C: 0x18
102°C: 0x17
103°C: 0x16
104°C: 0x15
105°C: 0x14
106°C: 0x13
107°C: 0x12
108°C: 0x11
109°C: 0x10
110°C: 0xF
111°C: 0xE
112°C: 0xD
113°C: 0xC
114°C: 0xB
115°C: 0xA
Advanced CPU Settings
Ring Ratio | VarStore: Setup | VarOffset: 0xA5D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Ring Frequency | VarStore: Setup | VarOffset: 0xA59 | Size: 0x4
Min: 0xFFFFFFFF | Max: 0xFFFFFFFF | Step: 0x1
Advanced CPU Settings
CPU Flex Ratio Override | VarStore: CpuSetup | VarOffset: 0x3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced CPU Settings
CPU Flex Ratio Settings | VarStore: CpuSetup | VarOffset: 0x1 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Advanced CPU Settings
Intel(R) Turbo Boost Technology | VarStore: Setup | VarOffset: 0xA30 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
Active Turbo Ratios | VarStore: Setup | VarOffset: 0xA9F | Size: 0x1
Auto: 0x0
Manual: 0x1
Advanced CPU Settings
Turbo Ratio (1-Core Active) | VarStore: Setup | VarOffset: 0xA31 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (2-Core Active) | VarStore: Setup | VarOffset: 0xA33 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (3-Core Active) | VarStore: Setup | VarOffset: 0xA35 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (4-Core Active) | VarStore: Setup | VarOffset: 0xA37 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (5-Core Active) | VarStore: Setup | VarOffset: 0xA39 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (6-Core Active) | VarStore: Setup | VarOffset: 0xA3B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (7-Core Active) | VarStore: Setup | VarOffset: 0xA3D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (8-Core Active) | VarStore: Setup | VarOffset: 0xA3F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (9-Core Active) | VarStore: Setup | VarOffset: 0xA41 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (10-Core Active) | VarStore: Setup | VarOffset: 0xA43 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (11-Core Active) | VarStore: Setup | VarOffset: 0xA45 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (12-Core Active) | VarStore: Setup | VarOffset: 0xA47 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (13-Core Active) | VarStore: Setup | VarOffset: 0xA49 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (14-Core Active) | VarStore: Setup | VarOffset: 0xA4B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (15-Core Active) | VarStore: Setup | VarOffset: 0xA4D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (16-Core Active) | VarStore: Setup | VarOffset: 0xA4F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (17-Core Active) | VarStore: Setup | VarOffset: 0xA51 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Ratio (18-Core Active) | VarStore: Setup | VarOffset: 0xA53 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Intel(R) Turbo Boost Max Technology 3.0 | VarStore: CpuSetup | VarOffset: 0xC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced CPU Settings
CPU Power Performance | VarStore: Setup | VarOffset: 0xA6A | Size: 0x2
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
Turbo Power Limits | VarStore: Setup | VarOffset: 0xAA0 | Size: 0x1
Auto: 0x0
POR: 0x1
Enabled: 0x2
Advanced CPU Settings
Package Power Limit1 - TDP (Watts) | VarStore: Setup | VarOffset: 0xA6C | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Package Power Limit1 Time | VarStore: Setup | VarOffset: 0xA6E | Size: 0x2
Auto: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
80: 0x50
96: 0x60
112: 0x70
128: 0x80
160: 0xA0
192: 0xC0
224: 0xE0
256: 0x100
320: 0x140
384: 0x180
448: 0x1C0
Advanced CPU Settings
Package Power Limit2 (Watts) | VarStore: Setup | VarOffset: 0xA70 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Package Power Limit2 Time | VarStore: Setup | VarOffset: 0xA72 | Size: 0x2
Auto: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
80: 0x50
96: 0x60
112: 0x70
128: 0x80
160: 0xA0
192: 0xC0
224: 0xE0
256: 0x100
320: 0x140
384: 0x180
448: 0x1C0
Advanced CPU Settings
Platform Power Limit1 (Watts) | VarStore: Setup | VarOffset: 0xA78 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Platform Power Limit1 Time | VarStore: Setup | VarOffset: 0xA7C | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Platform Power Limit2 (Watts) | VarStore: Setup | VarOffset: 0xA7A | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Power Limit3 (Watts) | VarStore: Setup | VarOffset: 0xA74 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Power Limit3 Time | VarStore: Setup | VarOffset: 0xA76 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
DRAM Power Limit1 (Watts) | VarStore: Setup | VarOffset: 0xA80 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
DRAM Power Limit1 Time | VarStore: Setup | VarOffset: 0xA82 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
DRAM Power Limit2 (Watts) | VarStore: Setup | VarOffset: 0xA84 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
DRAM Power Limit2 Time | VarStore: Setup | VarOffset: 0xA86 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Core Current Limit(Amps) | VarStore: Setup | VarOffset: 0xA67 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Per Core Limit Control | VarStore: Setup | VarOffset: 0xAA3 | Size: 0x1
Auto: 0x0
Manual: 0x1
Advanced CPU Settings
Turbo Core 0 Ratio Limit | VarStore: Setup | VarOffset: 0xAA4 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 1 Ratio Limit | VarStore: Setup | VarOffset: 0xAA6 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 2 Ratio Limit | VarStore: Setup | VarOffset: 0xAA8 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 3 Ratio Limit | VarStore: Setup | VarOffset: 0xAAA | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 4 Ratio Limit | VarStore: Setup | VarOffset: 0xAAC | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 5 Ratio Limit | VarStore: Setup | VarOffset: 0xAAE | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 6 Ratio Limit | VarStore: Setup | VarOffset: 0xAB0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 7 Ratio Limit | VarStore: Setup | VarOffset: 0xAB2 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 8 Ratio Limit | VarStore: Setup | VarOffset: 0xAB4 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 9 Ratio Limit | VarStore: Setup | VarOffset: 0xAB6 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 10 Ratio Limit | VarStore: Setup | VarOffset: 0xAB8 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 11 Ratio Limit | VarStore: Setup | VarOffset: 0xABA | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 12 Ratio Limit | VarStore: Setup | VarOffset: 0xABC | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 13 Ratio Limit | VarStore: Setup | VarOffset: 0xABE | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 14 Ratio Limit | VarStore: Setup | VarOffset: 0xAC0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 15 Ratio Limit | VarStore: Setup | VarOffset: 0xAC2 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 16 Ratio Limit | VarStore: Setup | VarOffset: 0xAC4 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 17 Ratio Limit | VarStore: Setup | VarOffset: 0xAC6 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 18 Ratio Limit | VarStore: Setup | VarOffset: 0xAC8 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 19 Ratio Limit | VarStore: Setup | VarOffset: 0xACA | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 20 Ratio Limit | VarStore: Setup | VarOffset: 0xACC | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 21 Ratio Limit | VarStore: Setup | VarOffset: 0xACE | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 22 Ratio Limit | VarStore: Setup | VarOffset: 0xAD0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
Turbo Core 23 Ratio Limit | VarStore: Setup | VarOffset: 0xAD2 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced CPU Settings
No. of CPU Cores Enabled | VarStore: Setup | VarOffset: 0xA8C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Advanced CPU Settings
Intel(R) Adaptive Boost Technology | VarStore: Setup | VarOffset: 0xAD4 | Size: 0x1
Auto: 0x0
Balanced: 0x3
Power Saver: 0x2
Disabled: 0x1
Advanced CPU Settings
Hyper-Threading Technology | VarStore: Setup | VarOffset: 0xA8E | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
Intel(R) Speed Shift Technology | VarStore: Setup | VarOffset: 0xA99 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
C-States Control | VarStore: Setup | VarOffset: 0xA8F | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
CPU Enhanced Halt(C1E) | VarStore: Setup | VarOffset: 0xA90 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
C3 State Support | VarStore: Setup | VarOffset: 0xA91 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
C6/C7 State Support | VarStore: Setup | VarOffset: 0xA92 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
C8 State Support | VarStore: Setup | VarOffset: 0xA93 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
C10 State Support | VarStore: Setup | VarOffset: 0xA94 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
Package C State limit | VarStore: Setup | VarOffset: 0xA95 | Size: 0x1
C0/C1: 0x0
C2: 0x1
C3: 0x2
C6: 0x3
C7: 0x4
C7s: 0x5
C8: 0x6
C9: 0x7
C10: 0x8
Auto: 0xFF
Advanced CPU Settings
CPU Thermal Monitor | VarStore: Setup | VarOffset: 0xA96 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
Ring to Core offset (Down Bin) | VarStore: Setup | VarOffset: 0xA9E | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
Frequency Clipping TVB | VarStore: Setup | VarOffset: 0xAA1 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
Voltage reduction initiated TVB | VarStore: Setup | VarOffset: 0xAA2 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
CPU EIST Function | VarStore: Setup | VarOffset: 0xA97 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
Race To Halt (RTH) | VarStore: Setup | VarOffset: 0xA9B | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
Energy Efficient Turbo | VarStore: Setup | VarOffset: 0xA9A | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
Hardware Prefetcher | VarStore: Setup | VarOffset: 0xA9C | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
Adjacent Cache Line Prefetch | VarStore: Setup | VarOffset: 0xA9D | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced CPU Settings
Bi-Directional PROCHOT | VarStore: Setup | VarOffset: 0xA98 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Advanced Memory Settings
Extreme Memory Profile(X.M.P.) | VarStore: Setup | VarOffset: 0xAD5 | Size: 0x1
Disabled: 0x0
Profile1: 0x1
Profile2: 0x2
Advanced Memory Settings
Extreme Memory Profile(X.M.P.) | VarStore: Setup | VarOffset: 0xAD5 | Size: 0x1
Disabled: 0x0
Profile1: 0x1
Advanced Memory Settings
Extreme Memory Profile(X.M.P.) | VarStore: Setup | VarOffset: 0xAD5 | Size: 0x1
Disabled: 0x0
Profile2: 0x2
Advanced Memory Settings
System Memory Multiplier | VarStore: Setup | VarOffset: 0xAD6 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced Memory Settings
Memory Ref Clock | VarStore: Setup | VarOffset: 0xAE3 | Size: 0x1
Auto: 0x0
100: 0x1
133: 0x2
Advanced Memory Settings
Memory Odd Ratio (100/133 or 200/266) | VarStore: Setup | VarOffset: 0xAE2 | Size: 0x1
Auto: 0x0
Enabled: 0x1
Disabled: 0x2
Advanced Memory Settings
Gear Mode | VarStore: Setup | VarOffset: 0xAE4 | Size: 0x1
Auto: 0x0
Gear1: 0x1
Gear2: 0x2
Advanced Memory Settings
Memory Boot Mode | VarStore: Setup | VarOffset: 0xADB | Size: 0x1
Auto: 0x0
Normal: 0x1
Enable Fast Boot: 0x2
Disable Fast Boot: 0x3
Advanced Memory Settings
Memory Frequency(MHz) | VarStore: Setup | VarOffset: 0xAD8 | Size: 0x2
Min: 0xFFFF | Max: 0xFFFF | Step: 0x1
Advanced Memory Settings
Realtime Memory Timing | VarStore: Setup | VarOffset: 0xAF3 | Size: 0x1
Auto: 0x0
Enabled: 0x1
Disabled: 0x2
Advanced Memory Settings
Memory Enhancement Settings | VarStore: Setup | VarOffset: 0xADF | Size: 0x1
Auto: 0xFF
Relax OC: 0xF
Enhanced Stability: 0x0
Normal: 0x1
Enhanced Performance: 0x2
High Frequency: 0x3
High Density: 0x4
DDR-4500+: 0x5
Advanced Memory Settings
Memory Channel Detection Message | VarStore: Setup | VarOffset: 0xAE0 | Size: 0x1
Enabled: 0x0
Disabled: 0x1
Advanced Memory Settings
Memory Timing Mode | VarStore: Setup | VarOffset: 0xAE1 | Size: 0x1
Auto: 0x0
Manual: 0x1
Advanced Manual: 0x2
Advanced Memory Settings
Profile DDR Voltage | VarStore: Setup | VarOffset: 0xAE5 | Size: 0x4
Min: 0x0 | Max: 0xFFFFFFFF | Step: 0x1
Advanced Memory Settings
Memory Multiplier Tweaker | VarStore: Setup | VarOffset: 0xADD | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced Memory Settings
Auto Memory | VarStore: Setup | VarOffset: 0xAF0 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Advanced Memory Settings
Channel Interleaving | VarStore: Setup | VarOffset: 0xAED | Size: 0x1
Auto: 0x0
Enabled: 0x1
Disabled: 0x2
Advanced Memory Settings
Rank Interleaving | VarStore: Setup | VarOffset: 0xAEE | Size: 0x1
Auto: 0x0
Enabled: 0x1
Disabled: 0x2
Advanced Memory Settings
Memory Timing Mode | VarStore: Setup | VarOffset: 0xAF4 | Size: 0x1
Dynamic: 0x1
Fixed: 0x2
Advanced Memory Settings
Memory Timing Channels | VarStore: Setup | VarOffset: 0xAF2 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
Channel A Memory Sub Timings
Memory Timing Mode | VarStore: Setup | VarOffset: 0xAE1 | Size: 0x1
Auto: 0x0
Manual: 0x1
Advanced Manual: 0x2
Channel A Memory Sub Timings
CAS Latency | VarStore: Setup | VarOffset: 0xB25 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRCD | VarStore: Setup | VarOffset: 0xB27 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRP | VarStore: Setup | VarOffset: 0xB29 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRAS | VarStore: Setup | VarOffset: 0xB2B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRC | VarStore: Setup | VarOffset: 0xB2D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWR | VarStore: Setup | VarOffset: 0xB2F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tCWL | VarStore: Setup | VarOffset: 0xB31 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRRD_S | VarStore: Setup | VarOffset: 0xB35 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRRD_L | VarStore: Setup | VarOffset: 0xB37 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRRD | VarStore: Setup | VarOffset: 0xB33 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWTR_S | VarStore: Setup | VarOffset: 0xB3B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWTR_L | VarStore: Setup | VarOffset: 0xB3D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWTR | VarStore: Setup | VarOffset: 0xB39 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tCCD_S | VarStore: Setup | VarOffset: 0xB3F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tCCD_L | VarStore: Setup | VarOffset: 0xB41 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRFC | VarStore: Setup | VarOffset: 0xB43 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRTP | VarStore: Setup | VarOffset: 0xB45 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tFAW | VarStore: Setup | VarOffset: 0xB47 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
Command Rate(tCMD) | VarStore: Setup | VarOffset: 0xB49 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tREFI | VarStore: Setup | VarOffset: 0xB75 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tREFIx9 | VarStore: Setup | VarOffset: 0xB77 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tXP | VarStore: Setup | VarOffset: 0xB79 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tXPDLL | VarStore: Setup | VarOffset: 0xB7B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tPRPDEN | VarStore: Setup | VarOffset: 0xB7D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRDPDEN | VarStore: Setup | VarOffset: 0xB7F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWRPDEN | VarStore: Setup | VarOffset: 0xB81 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRDPRE | VarStore: Setup | VarOffset: 0xB83 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWRPRE | VarStore: Setup | VarOffset: 0xB85 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tCPDED | VarStore: Setup | VarOffset: 0xB87 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tAONPD | VarStore: Setup | VarOffset: 0xB89 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tCKE | VarStore: Setup | VarOffset: 0xB8B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
RFR Delay | VarStore: Setup | VarOffset: 0xB8D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tXSDLL | VarStore: Setup | VarOffset: 0xB8F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tXS Offset | VarStore: Setup | VarOffset: 0xB91 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tZQOper | VarStore: Setup | VarOffset: 0xB93 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tMOD | VarStore: Setup | VarOffset: 0xB95 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRDRD_sg | VarStore: Setup | VarOffset: 0xB97 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRDRD_dg | VarStore: Setup | VarOffset: 0xB99 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRDRD_dr | VarStore: Setup | VarOffset: 0xB9B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRDRD_dd | VarStore: Setup | VarOffset: 0xB9D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRDWR_sg | VarStore: Setup | VarOffset: 0xB9F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRDWR_dg | VarStore: Setup | VarOffset: 0xBA1 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRDWR_dr | VarStore: Setup | VarOffset: 0xBA3 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tRDWR_dd | VarStore: Setup | VarOffset: 0xBA5 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWRWR_sg | VarStore: Setup | VarOffset: 0xBA7 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWRWR_dg | VarStore: Setup | VarOffset: 0xBA9 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWRWR_dr | VarStore: Setup | VarOffset: 0xBAB | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWRWR_dd | VarStore: Setup | VarOffset: 0xBAD | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWRRD_sg | VarStore: Setup | VarOffset: 0xBAF | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWRRD_dg | VarStore: Setup | VarOffset: 0xBB1 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWRRD_dr | VarStore: Setup | VarOffset: 0xBB3 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
tWRRD_dd | VarStore: Setup | VarOffset: 0xBB5 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
Round Trip Latency(CHA/DIMM0/Rank0) | VarStore: Setup | VarOffset: 0xBB7 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
Round Trip Latency(CHA/DIMM0/Rank1) | VarStore: Setup | VarOffset: 0xBB9 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
Round Trip Latency(CHA/DIMM1/Rank0) | VarStore: Setup | VarOffset: 0xBBB | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
Round Trip Latency(CHA/DIMM1/Rank1) | VarStore: Setup | VarOffset: 0xBBD | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
Round Trip Latency(CHB/DIMM0/Rank0) | VarStore: Setup | VarOffset: 0xC9F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
Round Trip Latency(CHB/DIMM0/Rank1) | VarStore: Setup | VarOffset: 0xCA1 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
Round Trip Latency(CHB/DIMM1/Rank0) | VarStore: Setup | VarOffset: 0xCA3 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
Round Trip Latency(CHB/DIMM1/Rank1) | VarStore: Setup | VarOffset: 0xCA5 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
IoLatR0D0 (CHA) | VarStore: Setup | VarOffset: 0xBBF | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
IoLatR1D0 (CHA) | VarStore: Setup | VarOffset: 0xBC1 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
IoLatR0D1 (CHA) | VarStore: Setup | VarOffset: 0xBC3 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
IoLatR1D1 (CHA) | VarStore: Setup | VarOffset: 0xBC5 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
IoLatR0D0 (CHB) | VarStore: Setup | VarOffset: 0xCA7 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
IoLatR1D0 (CHB) | VarStore: Setup | VarOffset: 0xCA9 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
IoLatR0D1 (CHB) | VarStore: Setup | VarOffset: 0xCAB | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
IoLatR1D1 (CHB) | VarStore: Setup | VarOffset: 0xCAD | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
RttNom(CHA/Dimm0) | VarStore: Setup | VarOffset: 0xC3B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
RttNom(CHA/Dimm1) | VarStore: Setup | VarOffset: 0xC3D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
RttPark(CHA/Dimm0) | VarStore: Setup | VarOffset: 0xC3F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
RttPark(CHA/Dimm1) | VarStore: Setup | VarOffset: 0xC41 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
RttWr(CHA/Dimm0) | VarStore: Setup | VarOffset: 0xC43 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
RttWr(CHA/Dimm1) | VarStore: Setup | VarOffset: 0xC45 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
RttNom(CHB/Dimm0) | VarStore: Setup | VarOffset: 0xD23 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
RttNom(CHB/Dimm1) | VarStore: Setup | VarOffset: 0xD25 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
RttPark(CHB/Dimm0) | VarStore: Setup | VarOffset: 0xD27 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
RttPark(CHB/Dimm1) | VarStore: Setup | VarOffset: 0xD29 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
RttWr(CHB/Dimm0) | VarStore: Setup | VarOffset: 0xD2B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel A Memory Sub Timings
RttWr(CHB/Dimm1) | VarStore: Setup | VarOffset: 0xD2D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
Memory Timing Mode | VarStore: Setup | VarOffset: 0xAE1 | Size: 0x1
Auto: 0x0
Manual: 0x1
Advanced Manual: 0x2
Channel B Memory Sub Timings
Memory Boot Mode | VarStore: Setup | VarOffset: 0xADB | Size: 0x1
Auto: 0x0
Normal: 0x1
Enable Fast Boot: 0x2
Disable Fast Boot: 0x3
Channel B Memory Sub Timings
CAS Latency | VarStore: Setup | VarOffset: 0xB4D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRCD | VarStore: Setup | VarOffset: 0xB4F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRP | VarStore: Setup | VarOffset: 0xB51 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRAS | VarStore: Setup | VarOffset: 0xB53 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRC | VarStore: Setup | VarOffset: 0xB55 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWR | VarStore: Setup | VarOffset: 0xB57 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tCWL | VarStore: Setup | VarOffset: 0xB59 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRRD_S | VarStore: Setup | VarOffset: 0xB5D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRRD_L | VarStore: Setup | VarOffset: 0xB5F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRRD | VarStore: Setup | VarOffset: 0xB5B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWTR_S | VarStore: Setup | VarOffset: 0xB63 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWTR_L | VarStore: Setup | VarOffset: 0xB65 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWTR | VarStore: Setup | VarOffset: 0xB61 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tCCD_S | VarStore: Setup | VarOffset: 0xB67 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tCCD_L | VarStore: Setup | VarOffset: 0xB69 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRFC | VarStore: Setup | VarOffset: 0xB6B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRTP | VarStore: Setup | VarOffset: 0xB6D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tFAW | VarStore: Setup | VarOffset: 0xB6F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
Command Rate(tCMD) | VarStore: Setup | VarOffset: 0xB71 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tREFI | VarStore: Setup | VarOffset: 0xC5D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tREFIx9 | VarStore: Setup | VarOffset: 0xC5F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tXP | VarStore: Setup | VarOffset: 0xC61 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tXPDLL | VarStore: Setup | VarOffset: 0xC63 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tPRPDEN | VarStore: Setup | VarOffset: 0xC65 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRDPDEN | VarStore: Setup | VarOffset: 0xC67 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWRPDEN | VarStore: Setup | VarOffset: 0xC69 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRDPRE | VarStore: Setup | VarOffset: 0xC6B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWRPRE | VarStore: Setup | VarOffset: 0xC6D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tCPDED | VarStore: Setup | VarOffset: 0xC6F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tAONPD | VarStore: Setup | VarOffset: 0xC71 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tCKE | VarStore: Setup | VarOffset: 0xC73 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
RFR Delay | VarStore: Setup | VarOffset: 0xC75 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tXSDLL | VarStore: Setup | VarOffset: 0xC77 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tXS Offset | VarStore: Setup | VarOffset: 0xC79 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tZQOper | VarStore: Setup | VarOffset: 0xC7B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tMOD | VarStore: Setup | VarOffset: 0xC7D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRDRD_sg | VarStore: Setup | VarOffset: 0xC7F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRDRD_dg | VarStore: Setup | VarOffset: 0xC81 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRDRD_dr | VarStore: Setup | VarOffset: 0xC83 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRDRD_dd | VarStore: Setup | VarOffset: 0xC85 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRDWR_sg | VarStore: Setup | VarOffset: 0xC87 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRDWR_dg | VarStore: Setup | VarOffset: 0xC89 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRDWR_dr | VarStore: Setup | VarOffset: 0xC8B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tRDWR_dd | VarStore: Setup | VarOffset: 0xC8D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWRWR_sg | VarStore: Setup | VarOffset: 0xC8F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWRWR_dg | VarStore: Setup | VarOffset: 0xC91 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWRWR_dr | VarStore: Setup | VarOffset: 0xC93 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWRWR_dd | VarStore: Setup | VarOffset: 0xC95 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWRRD_sg | VarStore: Setup | VarOffset: 0xC97 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWRRD_dg | VarStore: Setup | VarOffset: 0xC99 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWRRD_dr | VarStore: Setup | VarOffset: 0xC9B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
tWRRD_dd | VarStore: Setup | VarOffset: 0xC9D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
Round Trip Latency(CHB/DIMM0/Rank0) | VarStore: Setup | VarOffset: 0xC9F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
Round Trip Latency(CHB/DIMM0/Rank1) | VarStore: Setup | VarOffset: 0xCA1 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
Round Trip Latency(CHB/DIMM1/Rank0) | VarStore: Setup | VarOffset: 0xCA3 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
Round Trip Latency(CHB/DIMM1/Rank1) | VarStore: Setup | VarOffset: 0xCA5 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
IoLatR0D0 (CHB) | VarStore: Setup | VarOffset: 0xCA7 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
IoLatR1D0 (CHB) | VarStore: Setup | VarOffset: 0xCA9 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
IoLatR0D1 (CHB) | VarStore: Setup | VarOffset: 0xCAB | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
IoLatR1D1 (CHB) | VarStore: Setup | VarOffset: 0xCAD | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
RttNom(CHB/Dimm0) | VarStore: Setup | VarOffset: 0xD23 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
RttNom(CHB/Dimm1) | VarStore: Setup | VarOffset: 0xD25 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
RttPark(CHB/Dimm0) | VarStore: Setup | VarOffset: 0xD27 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
RttPark(CHB/Dimm1) | VarStore: Setup | VarOffset: 0xD29 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
RttWr(CHB/Dimm0) | VarStore: Setup | VarOffset: 0xD2B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Channel B Memory Sub Timings
RttWr(CHB/Dimm1) | VarStore: Setup | VarOffset: 0xD2D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced Power Settings
CPU Internal AC/DC Load line | VarStore: Setup | VarOffset: 0xE7B | Size: 0x2
Auto: 0x0
Extreme: 0x1
Turbo: 0x2
Performance: 0x3
Power Saving: 0x4
Advanced Power Settings
CPU Vcore Loadline Calibration | VarStore: Setup | VarOffset: 0xE7D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Advanced Power Settings
CPU Vcore Current Protection | VarStore: Setup | VarOffset: 0xE7F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
CPU VRIN Voltage | VarStore: Setup | VarOffset: 0xE61 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
Vcore Voltage Mode | VarStore: Setup | VarOffset: 0xE6B | Size: 0x1
Auto: 0x0
Adaptive Vcore: 0x1
Override Vcore: 0x2
Fixed Vcore: 0x3
CPU Core Voltage Control
Internal CPU Vcore | VarStore: Setup | VarOffset: 0xE63 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
Internal CPU Vcore Offset | VarStore: Setup | VarOffset: 0xE65 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
Adaptive Mode | VarStore: Setup | VarOffset: 0xEAD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
CPU Core Voltage Control
CPU Graphics Voltage Offset | VarStore: Setup | VarOffset: 0xE69 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
CPU System Agent Voltage | VarStore: Setup | VarOffset: 0xE72 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
CPU Dynamic VCCSA Offset | VarStore: Setup | VarOffset: 0xEB2 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
CPU I/O Analog Voltage | VarStore: Setup | VarOffset: 0xEB4 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
CPU I/O Analog Voltage | VarStore: Setup | VarOffset: 0xEB6 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
CPU I/O Digital Voltage | VarStore: Setup | VarOffset: 0xEB8 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
CPU I/O Digital Voltage | VarStore: Setup | VarOffset: 0xEBA | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
CPU Vcore | VarStore: Setup | VarOffset: 0xE75 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
Dynamic Vcore(DVID) | VarStore: Setup | VarOffset: 0xE77 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
BCLK Adaptive Voltage | VarStore: Setup | VarOffset: 0xA64 | Size: 0x1
Auto: 0x0
Disabled: 0x1
Enabled: 0x2
CPU Core Voltage Control
CPU Graphics Voltage (VAXG) | VarStore: Setup | VarOffset: 0xE67 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
CPU Core PLL Overvoltage (+mV) | VarStore: Setup | VarOffset: 0xE83 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
RING PLL Overvoltage (+mV) | VarStore: Setup | VarOffset: 0xE85 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
GT PLL Overvoltage (+mV) | VarStore: Setup | VarOffset: 0xE87 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
SA PLL Overvoltage (+mV) | VarStore: Setup | VarOffset: 0xE89 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
CPU Core Voltage Control
MC PLL Overvoltage (+mV) | VarStore: Setup | VarOffset: 0xE8B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
DRAM Voltage Control
DRAM Voltage (CH A/B) | VarStore: Setup | VarOffset: 0xE79 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Internal VR Control
IA VR Config Enable | VarStore: CpuSetup | VarOffset: 0x325 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
IA AC Loadline | VarStore: CpuSetup | VarOffset: 0x32A | Size: 0x2
Min: 0x0 | Max: 0x1869 | Step: 0x0
Internal VR Control
IA DC Loadline | VarStore: CpuSetup | VarOffset: 0x334 | Size: 0x2
Min: 0x0 | Max: 0x1869 | Step: 0x0
Internal VR Control
IA PS Current Threshold1 | VarStore: CpuSetup | VarOffset: 0x33E | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Internal VR Control
IA PS Current Threshold2 | VarStore: CpuSetup | VarOffset: 0x348 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Internal VR Control
IA PS Current Threshold3 | VarStore: CpuSetup | VarOffset: 0x352 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Internal VR Control
IA PS3 Enable | VarStore: CpuSetup | VarOffset: 0x35C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
IA PS4 Enable | VarStore: CpuSetup | VarOffset: 0x361 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
IA IMON Slope | VarStore: CpuSetup | VarOffset: 0x366 | Size: 0x2
Min: 0x0 | Max: 0xC8 | Step: 0x1
Internal VR Control
IA IMON Offset | VarStore: CpuSetup | VarOffset: 0x370 | Size: 0x2
Min: 0x0 | Max: 0xFF | Step: 0x1
Internal VR Control
IA IMON Prefix | VarStore: CpuSetup | VarOffset: 0x37A | Size: 0x1
+: 0x0
-: 0x1
Internal VR Control
IA VR Current Limit | VarStore: CpuSetup | VarOffset: 0x37F | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
Internal VR Control
IA VR Voltage Limit | VarStore: CpuSetup | VarOffset: 0x389 | Size: 0x2
Min: 0x0 | Max: 0x1F3F | Step: 0x1
Internal VR Control
IA TDC Enable | VarStore: CpuSetup | VarOffset: 0x39D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
IA TDC Current Limit | VarStore: CpuSetup | VarOffset: 0x393 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x7D
Internal VR Control
IA TDC Time Window | VarStore: CpuSetup | VarOffset: 0x3A2 | Size: 0x4
1 ms: 0x1
2 ms: 0x2
3 ms: 0x3
4 ms: 0x4
5 ms: 0x5
6 ms: 0x6
7 ms: 0x7
8 ms: 0x8
10 ms: 0xA
Internal VR Control
IA TDC Lock | VarStore: CpuSetup | VarOffset: 0x3B6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
GT VR Config Enable | VarStore: CpuSetup | VarOffset: 0x326 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
GT AC Loadline | VarStore: CpuSetup | VarOffset: 0x32C | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
Internal VR Control
GT DC Loadline | VarStore: CpuSetup | VarOffset: 0x336 | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
Internal VR Control
GT PS Current Threshold1 | VarStore: CpuSetup | VarOffset: 0x340 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Internal VR Control
GT PS Current Threshold2 | VarStore: CpuSetup | VarOffset: 0x34A | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Internal VR Control
GT PS Current Threshold3 | VarStore: CpuSetup | VarOffset: 0x354 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Internal VR Control
GT PS3 Enable | VarStore: CpuSetup | VarOffset: 0x35D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
GT PS4 Enable | VarStore: CpuSetup | VarOffset: 0x362 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
GT IMON Slope | VarStore: CpuSetup | VarOffset: 0x368 | Size: 0x2
Min: 0x0 | Max: 0xC8 | Step: 0x1
Internal VR Control
GT IMON Offset | VarStore: CpuSetup | VarOffset: 0x372 | Size: 0x2
Min: 0x0 | Max: 0xFF | Step: 0x1
Internal VR Control
GT IMON Prefix | VarStore: CpuSetup | VarOffset: 0x37B | Size: 0x1
+: 0x0
-: 0x1
Internal VR Control
GT VR Current Limit | VarStore: CpuSetup | VarOffset: 0x381 | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
Internal VR Control
GT VR Voltage Limit | VarStore: CpuSetup | VarOffset: 0x38B | Size: 0x2
Min: 0x0 | Max: 0x1F3F | Step: 0x1
Internal VR Control
GT TDC Enable | VarStore: CpuSetup | VarOffset: 0x39E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
GT TDC Current Limit | VarStore: CpuSetup | VarOffset: 0x395 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x7D
Internal VR Control
GT TDC Time Window | VarStore: CpuSetup | VarOffset: 0x3A6 | Size: 0x4
1 ms: 0x1
2 ms: 0x2
3 ms: 0x3
4 ms: 0x4
5 ms: 0x5
6 ms: 0x6
7 ms: 0x7
8 ms: 0x8
10 ms: 0xA
Internal VR Control
GT TDC Lock | VarStore: CpuSetup | VarOffset: 0x3B7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
SA VR Config Enable | VarStore: CpuSetup | VarOffset: 0x327 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
SA AC Loadline | VarStore: CpuSetup | VarOffset: 0x32E | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
Internal VR Control
SA DC Loadline | VarStore: CpuSetup | VarOffset: 0x338 | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
Internal VR Control
SA PS Current Threshold1 | VarStore: CpuSetup | VarOffset: 0x342 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Internal VR Control
SA PS Current Threshold2 | VarStore: CpuSetup | VarOffset: 0x34C | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Internal VR Control
SA PS Current Threshold3 | VarStore: CpuSetup | VarOffset: 0x356 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Internal VR Control
SA PS3 Enable | VarStore: CpuSetup | VarOffset: 0x35E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
SA PS4 Enable | VarStore: CpuSetup | VarOffset: 0x363 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
SA IMON Slope | VarStore: CpuSetup | VarOffset: 0x36A | Size: 0x2
Min: 0x0 | Max: 0xC8 | Step: 0x1
Internal VR Control
SA IMON Offset | VarStore: CpuSetup | VarOffset: 0x374 | Size: 0x2
Min: 0x0 | Max: 0xFF | Step: 0x1
Internal VR Control
IMON Prefix | VarStore: CpuSetup | VarOffset: 0x37C | Size: 0x1
+: 0x0
-: 0x1
Internal VR Control
SA VR Current Limit | VarStore: CpuSetup | VarOffset: 0x383 | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
Internal VR Control
SA VR Voltage Limit | VarStore: CpuSetup | VarOffset: 0x38D | Size: 0x2
Min: 0x0 | Max: 0x1F3F | Step: 0x1
Internal VR Control
SA TDC Enable | VarStore: CpuSetup | VarOffset: 0x39F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Internal VR Control
SA TDC Current Limit | VarStore: CpuSetup | VarOffset: 0x397 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x7D
Internal VR Control
SA TDC Time Window | VarStore: CpuSetup | VarOffset: 0x3AA | Size: 0x4
1 ms: 0x1
2 ms: 0x2
3 ms: 0x3
4 ms: 0x4
5 ms: 0x5
6 ms: 0x6
7 ms: 0x7
8 ms: 0x8
10 ms: 0xA
Internal VR Control
SA TDC Lock | VarStore: CpuSetup | VarOffset: 0x3B8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PC Health Status
Reset Case Open Status | VarStore: Setup | VarOffset: 0xEEA
CPU_FAN
CPU_FAN Fail Warning | VarStore: GcSensorVarName | VarOffset: 0x203
CPU_FAN
CPU_FAN Speed Control | VarStore: GcSensorVarName | VarOffset: 0xA | Size: 0x1
Normal: 0x0
Silent: 0x1
Manual: 0x2
Full Speed: 0x3
CPU_FAN
Fan Control Use Temperature Input | VarStore: GcSensorVarName | VarOffset: 0x12 | Size: 0x1
CPU: 0x2
CPU_FAN
Temperature Interval | VarStore: GcSensorVarName | VarOffset: 0x11 | Size: 0x1
Min: 0x0 | Max: 0x3 | Step: 0x1
CPU_FAN
CPU_FAN Control mode | VarStore: GcSensorVarName | VarOffset: 0x20E | Size: 0x1
Auto: 0x0
Voltage: 0x1
PWM: 0x2
CPU_FAN
CPU_FAN Stop | VarStore: GcSensorVarName | VarOffset: 0x21D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SYS_FAN1
SYS_FAN1 Fail Warning | VarStore: GcSensorVarName | VarOffset: 0x205
SYS_FAN1
SYS_FAN1 Speed Control | VarStore: GcSensorVarName | VarOffset: 0x64 | Size: 0x1
Normal: 0x0
Silent: 0x1
Manual: 0x2
Full Speed: 0x3
SYS_FAN1
Fan Control Use Temperature Input | VarStore: GcSensorVarName | VarOffset: 0x6C | Size: 0x1
System 1: 0x0
PCH: 0x1
CPU: 0x2
VRM MOS: 0x4
SYS_FAN1
Temperature Interval | VarStore: GcSensorVarName | VarOffset: 0x6B | Size: 0x1
Min: 0x0 | Max: 0x3 | Step: 0x1
SYS_FAN1
SYS_FAN1 Control Mode | VarStore: GcSensorVarName | VarOffset: 0x214 | Size: 0x1
Auto: 0x0
Voltage: 0x1
PWM: 0x2
SYS_FAN1
SYS_FAN1 Stop | VarStore: GcSensorVarName | VarOffset: 0x21F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Temperature Warning Control
CPU_TEMP | VarStore: GcSensorVarName | VarOffset: 0x1F9 | Size: 0x1
Disabled: 0x0
60°C/140°F: 0x3C
70°C/158°F: 0x46
80°C/176°F: 0x50
90°C/194°F: 0x5A
Temperature Warning Control
SYS_TEMP1 | VarStore: GcSensorVarName | VarOffset: 0x1FA | Size: 0x1
Disabled: 0x0
60°C/140°F: 0x3C
70°C/158°F: 0x46
80°C/176°F: 0x50
90°C/194°F: 0x5A
Temperature Warning Control
PCH_TEMP | VarStore: GcSensorVarName | VarOffset: 0x1FC | Size: 0x1
Disabled: 0x0
60°C/140°F: 0x3C
70°C/158°F: 0x46
80°C/176°F: 0x50
90°C/194°F: 0x5A
Temperature Warning Control
VRM_TEMP | VarStore: GcSensorVarName | VarOffset: 0x1FE | Size: 0x1
Disabled: 0x0
60°C/140°F: 0x3C
70°C/158°F: 0x46
80°C/176°F: 0x50
90°C/194°F: 0x5A
Miscellaneous Settings
CPU PCIe Link Speed | VarStore: Setup | VarOffset: 0xEEF | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
Miscellaneous Settings
CPU PCIe Link Speed | VarStore: Setup | VarOffset: 0xEEF | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
Gen4: 0x4
Miscellaneous Settings
PCH PCIe Link Speed | VarStore: Setup | VarOffset: 0xEF0 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
Miscellaneous Settings
3DMark01 Enhancement | VarStore: Setup | VarOffset: 0xEEE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Miscellaneous Settings
Isochronous Support | VarStore: Setup | VarOffset: 0xEED
System
System Language | VarStore: PlatformLang | VarOffset: 0x0 | Size: 0x2
: 0x0
: 0x1
Peripherals
Initial Display Output | VarStore: Setup | VarOffset: 0xF04 | Size: 0x1
IGFX: 0x0
PCIe 1 Slot: 0x1
Peripherals
OnBoard LAN Controller | VarStore: Setup | VarOffset: 0xF03 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Peripherals
LEDs in System Power On State | VarStore: Setup | VarOffset: 0xF61 | Size: 0x1
Off: 0x0
On: 0x1
Peripherals
LEDs in Sleep, Hibernation, and Soft Off States | VarStore: Setup | VarOffset: 0xF62 | Size: 0x1
Off: 0x0
On: 0x1
Peripherals
Intel Platform Trust Technology (PTT) | VarStore: AmiWrapperSetup | VarOffset: 0x3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
PTID Support | VarStore: Setup | VarOffset: 0x4D
RC ACPI Settings
PECI Access Method | VarStore: Setup | VarOffset: 0x55 | Size: 0x1
Direct I/O: 0x0
ACPI: 0x1
RC ACPI Settings
Native PCIE Enable | VarStore: Setup | VarOffset: 0x4B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
Native ASPM | VarStore: Setup | VarOffset: 0x4C | Size: 0x1
Auto: 0x2
Enabled: 0x1
Disabled: 0x0
RC ACPI Settings
BDAT ACPI Table Support | VarStore: SaSetup | VarOffset: 0x1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
ACPI Debug | VarStore: Setup | VarOffset: 0x4E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
Low Power S0 Idle Capability | VarStore: Setup | VarOffset: 0x56 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
PUIS Enable | VarStore: Setup | VarOffset: 0x956 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
RC ACPI Settings
EC Notification | VarStore: Setup | VarOffset: 0x6C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
EC CS Debug Light | VarStore: Setup | VarOffset: 0x6D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
EC Low Power Mode | VarStore: Setup | VarOffset: 0x6E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
Sensor Standby | VarStore: Setup | VarOffset: 0x71 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
CS PL1 Limit | VarStore: Setup | VarOffset: 0x72 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
CS PL1 Value | VarStore: Setup | VarOffset: 0x73 | Size: 0x2
Min: 0xBB8 | Max: 0x4E20 | Step: 0x7D
RC ACPI Settings
LPIT Residency Counter | VarStore: Setup | VarOffset: 0x77 | Size: 0x1
C10: 0x1
SLP S0: 0x3
ATX Shutdown (PS_ON): 0x7
RC ACPI Settings
Intel Ready Mode Technology | VarStore: Setup | VarOffset: 0x78 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
HW Notification | VarStore: AmiWrapperSetup | VarOffset: 0x0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
Intel RMT State | VarStore: AmiWrapperSetup | VarOffset: 0x1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
PCI Delay Optimization | VarStore: Setup | VarOffset: 0x53 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
MSI enabled | VarStore: Setup | VarOffset: 0x6F0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP CPU | VarStore: Setup | VarOffset: 0x57 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP Graphics | VarStore: Setup | VarOffset: 0x58 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP GNA | VarStore: Setup | VarOffset: 0x66 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP SATA | VarStore: Setup | VarOffset: 0x59 | Size: 0x1
No Constraint: 0x0
Adapter D0/F1: 0x1
Raid Volume0: 0x2
Adapter D3: 0x3
PEP Constraints Configuration
PEP enumerated SATA ports | VarStore: Setup | VarOffset: 0x906 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP PCIe Storage | VarStore: Setup | VarOffset: 0x7A8 | Size: 0x1
No Constraint: 0x0
D0/F1: 0x1
D3: 0x3
PEP Constraints Configuration
PEP PCIe LAN | VarStore: Setup | VarOffset: 0x95A | Size: 0x1
No Constraint: 0x0
D0/F1: 0x1
D3: 0x3
PEP Constraints Configuration
PEP PCIe WLAN | VarStore: Setup | VarOffset: 0x95B | Size: 0x1
No Constraint: 0x0
D0/F1: 0x1
D3: 0x3
PEP Constraints Configuration
PEP PCIe GFX | VarStore: Setup | VarOffset: 0x95C | Size: 0x1
No Constraint: 0x0
D0/F1: 0x1
D3: 0x3
PEP Constraints Configuration
PEP PCIe Other | VarStore: Setup | VarOffset: 0x95D | Size: 0x1
No Constraint: 0x0
D0/F1: 0x1
D3: 0x3
PEP Constraints Configuration
PEP UART | VarStore: Setup | VarOffset: 0x5A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP I2C0 | VarStore: Setup | VarOffset: 0x5B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP I2C1 | VarStore: Setup | VarOffset: 0x5C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP I2C2 | VarStore: Setup | VarOffset: 0x5D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP I2C3 | VarStore: Setup | VarOffset: 0x5E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP I2C4 | VarStore: Setup | VarOffset: 0x5F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP I2C5 | VarStore: Setup | VarOffset: 0x60 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP SPI | VarStore: Setup | VarOffset: 0x61 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP XHCI | VarStore: Setup | VarOffset: 0x62 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP Audio | VarStore: Setup | VarOffset: 0x63 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP CSME | VarStore: Setup | VarOffset: 0x67 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP HECI3 | VarStore: Setup | VarOffset: 0x955 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP LAN(GBE) | VarStore: Setup | VarOffset: 0x68 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP THC0 | VarStore: Setup | VarOffset: 0x69 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP THC1 | VarStore: Setup | VarOffset: 0x6A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP TCSS | VarStore: Setup | VarOffset: 0x6B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP VMD | VarStore: Setup | VarOffset: 0x8E2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
CNVi Mode | VarStore: PchSetup | VarOffset: 0x67E | Size: 0x1
Disable Integrated: 0x0
Auto Detection: 0x1
Connectivity Configuration
BT Core | VarStore: PchSetup | VarOffset: 0x67F | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Connectivity Configuration
BT Audio Offload | VarStore: PchSetup | VarOffset: 0x680 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
CoExistence Manager | VarStore: Setup | VarOffset: 0x6D8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
Preboot BLE | VarStore: Setup | VarOffset: 0x6D9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
BLE Reconnection Delay | VarStore: Setup | VarOffset: 0x6DA | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Connectivity Configuration
Discrete Bluetooth Module | VarStore: Setup | VarOffset: 0x545 | Size: 0x1
Disabled: 0x0
Thunder Peak - USB: 0x1
Thunder Peak - UART: 0x2
Connectivity Configuration
BT Interrupt Mode | VarStore: Setup | VarOffset: 0x546 | Size: 0x1
GPIO Interrupt: 0x0
APIC Interrupt: 0x1
Connectivity Configuration
Advanced settings | VarStore: Setup | VarOffset: 0x67F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
Switched Antenna Diversity Selection | VarStore: Setup | VarOffset: 0x6D7 | Size: 0x1
Antenna1: 0x0
Antenna2: 0x1
Diversity: 0x2
Diversity Antenna1: 0x3
Diversity Antenna2: 0x4
Connectivity Configuration
Domain Type SPLC 1 | VarStore: Setup | VarOffset: 0x680 | Size: 0x1
Min: 0x0 | Max: 0x14 | Step: 0x1
Connectivity Configuration
Default Power Limit | VarStore: Setup | VarOffset: 0x681 | Size: 0x2
Min: 0x1 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
Default Time Window | VarStore: Setup | VarOffset: 0x683 | Size: 0x4
Min: 0x1 | Max: 0x186A0 | Step: 0x1
Connectivity Configuration
TRxDelay_A | VarStore: Setup | VarOffset: 0x687 | Size: 0x1
Min: 0x1 | Max: 0x64 | Step: 0x1
Connectivity Configuration
TRxCableLength_A | VarStore: Setup | VarOffset: 0x688 | Size: 0x1
Min: 0x1 | Max: 0x64 | Step: 0x1
Connectivity Configuration
TRxDelay_B | VarStore: Setup | VarOffset: 0x689 | Size: 0x1
Min: 0x1 | Max: 0x64 | Step: 0x1
Connectivity Configuration
TRxCableLength_B | VarStore: Setup | VarOffset: 0x68A | Size: 0x1
Min: 0x1 | Max: 0x64 | Step: 0x1
Connectivity Configuration
Domain Type | VarStore: Setup | VarOffset: 0x68B | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Connectivity Configuration
Country Identifier | VarStore: Setup | VarOffset: 0x68C | Size: 0x2
Min: 0x1 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
WiFi SAR | VarStore: Setup | VarOffset: 0x691 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
SAR 2400 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x692 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x693 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x694 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x695 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5925 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x696 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5945-6165 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x697 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6165-6405 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x698 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6405-6525 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x699 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6525-6705 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x69A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6705-6865 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x69B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6865-7105 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x910 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x911 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x912 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x913 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x914 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5925 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x915 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5945-6165 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x916 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6165-6405 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x917 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6405-6525 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x918 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6525-6705 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x919 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6705-6865 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x91A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6865-7105 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x91B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
WiFi Dynamic SAR | VarStore: Setup | VarOffset: 0x69C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
Extended SAR Range Sets | VarStore: Setup | VarOffset: 0x69D | Size: 0x1
No Additional sets: 0x0
Set 2: 0x1
Set 3: 0x2
Set 4: 0x3
Connectivity Configuration
SAR 2400 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x69E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x69F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x6A0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x6A1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5925 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x6A2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5945-6165 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x6A3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6165-6405 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x6A4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6405-6525 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x6A5 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6525-6705 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x6A6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6705-6865 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x6A7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6865-7105 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x91C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x91D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x91E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x91F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x920 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5925 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x921 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5945-6165 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x922 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6165-6405 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x923 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6405-6525 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x924 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6525-6705 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x925 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6705-6865 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x926 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6865-7105 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x927 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x6A8 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x6A9 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x6AA | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x6AB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5925 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x6AC | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5945-6165 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x6AD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6165-6405 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x6AE | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6405-6525 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x6AF | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6525-6705 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x6B0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6705-6865 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x6B1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6865-7105 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x928 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Set3 Chain B | VarStore: Setup | VarOffset: 0x929 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x92A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x92B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x92C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5925 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x92D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5945-6165 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x92E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6165-6405 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x92F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6405-6525 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x930 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6525-6705 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x931 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6705-6865 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x932 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6865-7105 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x933 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x6B2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x6B3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x6B4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x6B5 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5925 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x6B6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5945-6165 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x6B7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6165-6405 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x6B8 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6405-6525 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x6B9 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6525-6705 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x6BA | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6705-6865 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x6BB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6865-7105 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x934 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x935 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x936 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x937 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x938 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5925 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x939 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5945-6165 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x93A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6165-6405 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x93B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6405-6525 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x93C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6525-6705 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x93D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6705-6865 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x93E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6865-7105 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x93F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Antenna A Current Set | VarStore: Setup | VarOffset: 0x6CE | Size: 0x1
Default OTP table: 0x0
Set 1: 0x1
Set 2: 0x2
Set 3: 0x3
Set 4: 0x4
Connectivity Configuration
Antenna B Current Set | VarStore: Setup | VarOffset: 0x6CF | Size: 0x1
Default OTP table: 0x0
Set 1: 0x1
Set 2: 0x2
Set 3: 0x3
Set 4: 0x4
Connectivity Configuration
SAR 2400 MHz Max Allowed for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x6BC | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Chain A Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x6BD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Chain B Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x6BE | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Max Allowed for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x6BF | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Chain A Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x6C0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Chain B Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x6C1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6000-7000 MHz Max Allowed for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x94C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6000-7000 MHz Chain A Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x94D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6000-7000 MHz Chain B Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x94E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Max Allowed for Group 2 (EU Japan) | VarStore: Setup | VarOffset: 0x6C2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Chain A Offset for Group 2 (EU Japan) | VarStore: Setup | VarOffset: 0x6C3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Chain B Offset for Group 2 (EU Japan) | VarStore: Setup | VarOffset: 0x6C4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Max Allowed for Group 2 (EU Japan) | VarStore: Setup | VarOffset: 0x6C5 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Chain A Offset for Group 2 (EU Japan) | VarStore: Setup | VarOffset: 0x6C6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Chain B Offset for Group 2 (EU Japan) | VarStore: Setup | VarOffset: 0x6C7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6000-7000 MHz Max Allowed for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x94F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6000-7000 MHz Chain A Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x950 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6000-7000 MHz Chain B Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x951 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Max Allowed for Group 3 (ROW) | VarStore: Setup | VarOffset: 0x6C8 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Chain A Offset for Group 3 (ROW) | VarStore: Setup | VarOffset: 0x6C9 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Chain B Offset for Group 3 (ROW) | VarStore: Setup | VarOffset: 0x6CA | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Max Allowed for Group 3 (ROW) | VarStore: Setup | VarOffset: 0x6CB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Chain A Offset for Group 3 (ROW) | VarStore: Setup | VarOffset: 0x6CC | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Chain B Offset for Group 3 (ROW) | VarStore: Setup | VarOffset: 0x6CD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6000-7000 MHz Max Allowed for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x952 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6000-7000 MHz Chain A Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x953 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 6000-7000 MHz Chain B Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x954 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
External 32kHz Clock | VarStore: Setup | VarOffset: 0x8FA | Size: 0x1
Not Valid: 0x0
Valid: 0x1
Connectivity Configuration
Wifi ANT Gain control | VarStore: Setup | VarOffset: 0x8FB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
ANT Gain 2400MHz Chain A | VarStore: Setup | VarOffset: 0x8FC | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
ANT Gain 5150MHz-5350MHz Chain A | VarStore: Setup | VarOffset: 0x8FD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5350MHz-5470MHz Chain A | VarStore: Setup | VarOffset: 0x8FE | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5470MHz-5725MHz Chain A | VarStore: Setup | VarOffset: 0x8FF | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5725MHZ-5945MHz Chain A | VarStore: Setup | VarOffset: 0x900 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5945MHZ-6165MHz Chain A | VarStore: Setup | VarOffset: 0x940 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 6165MHZ-6405MHz Chain A | VarStore: Setup | VarOffset: 0x941 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 6405MHZ-6525MHz Chain A | VarStore: Setup | VarOffset: 0x942 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 6525MHZ-6705MHz Chain A | VarStore: Setup | VarOffset: 0x943 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 6705MHZ-6865MHz Chain A | VarStore: Setup | VarOffset: 0x944 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 6865MHZ-7105MHz Chain A | VarStore: Setup | VarOffset: 0x945 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 2400MHz Chain B | VarStore: Setup | VarOffset: 0x901 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5150MHz-5350MHz Chain B | VarStore: Setup | VarOffset: 0x902 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5350MHz-5470MHz Chain B | VarStore: Setup | VarOffset: 0x903 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5470MHz-5725MHz Chain B | VarStore: Setup | VarOffset: 0x904 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5725MHZ-5945MHz Chain B | VarStore: Setup | VarOffset: 0x905 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5945MHZ-6165MHz Chain B | VarStore: Setup | VarOffset: 0x946 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 6165MHZ-6405MHz Chain B | VarStore: Setup | VarOffset: 0x947 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 6405MHZ-6525MHz Chain B | VarStore: Setup | VarOffset: 0x948 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 6525MHZ-6705MHz Chain B | VarStore: Setup | VarOffset: 0x949 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 6705MHZ-6865MHz Chain B | VarStore: Setup | VarOffset: 0x94A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 6865MHZ-7105MHz Chain B | VarStore: Setup | VarOffset: 0x94B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Bluetooth SAR | VarStore: Setup | VarOffset: 0x6D0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
Bluetooth SAR BR | VarStore: Setup | VarOffset: 0x6D1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Bluetooth SAR EDR2 | VarStore: Setup | VarOffset: 0x6D2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Bluetooth SAR EDR3 | VarStore: Setup | VarOffset: 0x6D3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Bluetooth SAR LE | VarStore: Setup | VarOffset: 0x6D4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Bluetooth SAR LE 2Mhz | VarStore: Setup | VarOffset: 0x6D5 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Bluetooth SAR LE LR | VarStore: Setup | VarOffset: 0x6D6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Disable SRD Active Channels | VarStore: Setup | VarOffset: 0x90A | Size: 0x1
Min: 0x0 | Max: 0x2 | Step: 0x1
Connectivity Configuration
Supported Indonesia 5.15-5.35 GHz Band | VarStore: Setup | VarOffset: 0x90B | Size: 0x1
Min: 0x0 | Max: 0x2 | Step: 0x1
Connectivity Configuration
Ultra High Band Support | VarStore: Setup | VarOffset: 0x90C | Size: 0x4
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
WTAS Selection | VarStore: Setup | VarOffset: 0x95E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
WTAS List Entries | VarStore: Setup | VarOffset: 0x95F | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x960 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x962 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x964 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x966 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x968 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x96A | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x96C | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x96E | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x970 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x972 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x974 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x976 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x978 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x97A | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x97C | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
ISO country code to block | VarStore: Setup | VarOffset: 0x97E | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
WWAN Configuration
WWAN Device | VarStore: Setup | VarOffset: 0x764 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
WWAN Configuration
WWAN Reset Workaround | VarStore: Setup | VarOffset: 0x7B3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
C6DRAM | VarStore: CpuSetup | VarOffset: 0xF5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
CPU Flex Ratio Override | VarStore: CpuSetup | VarOffset: 0x3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
CPU Flex Ratio Settings | VarStore: CpuSetup | VarOffset: 0x1 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x0
CPU Configuration
Hardware Prefetcher | VarStore: CpuSetup | VarOffset: 0xBF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Adjacent Cache Line Prefetch | VarStore: CpuSetup | VarOffset: 0xC0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Intel (VMX) Virtualization Technology | VarStore: CpuSetup | VarOffset: 0xB9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
PECI | VarStore: CpuSetup | VarOffset: 0x4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
AVX | VarStore: CpuSetup | VarOffset: 0x315 | Size: 0x1
Enabled: 0x0
Disabled: 0x1
CPU Configuration
AVX3 | VarStore: CpuSetup | VarOffset: 0x316 | Size: 0x1
Enabled: 0x0
Disabled: 0x1
CPU Configuration
Active Processor Cores | VarStore: CpuSetup | VarOffset: 0x6 | Size: 0x1
All: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
9: 0x9
CPU Configuration
Limit CPUID Maximum | VarStore: AmiWrapperSetup | VarOffset: 0x2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Hyper-Threading | VarStore: CpuSetup | VarOffset: 0x5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
BIST | VarStore: CpuSetup | VarOffset: 0x7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
AP threads Idle Manner | VarStore: CpuSetup | VarOffset: 0xF6 | Size: 0x1
HALT Loop: 0x1
MWAIT Loop: 0x2
RUN Loop: 0x3
CPU Configuration
AES | VarStore: CpuSetup | VarOffset: 0xBA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
MachineCheck | VarStore: CpuSetup | VarOffset: 0xBB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
MonitorMWait | VarStore: CpuSetup | VarOffset: 0xBC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Intel Trusted Execution Technology | VarStore: CpuSetup | VarOffset: 0xC1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Alias Check Request | VarStore: CpuSetup | VarOffset: 0xC4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
DPR Memory Size (MB) | VarStore: CpuSetup | VarOffset: 0xBD | Size: 0x2
Min: 0x0 | Max: 0xFF | Step: 0x1
CPU Configuration
Reset AUX Content | VarStore: CpuSetup | VarOffset: 0xC3 | Size: 0x1
Yes: 0x1
No: 0x0
CPU Configuration
FCLK Frequency for Early Power On | VarStore: CpuSetup | VarOffset: 0xFC | Size: 0x1
Normal (800Mhz): 0x0
1GHz: 0x1
400MHz: 0x2
BIOS Guard
Enable Tools Interface | VarStore: CpuSetup | VarOffset: 0xF1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU SMM Enhancement
SMM MSR Save State Enable | VarStore: CpuSetup | VarOffset: 0x20D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU SMM Enhancement
SMM Use Delay Indication | VarStore: CpuSetup | VarOffset: 0x20E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU SMM Enhancement
SMM Use Block Indication | VarStore: CpuSetup | VarOffset: 0x20F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU SMM Enhancement
SMM Use SMM en-US Indication | VarStore: CpuSetup | VarOffset: 0x210 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Power & Performance
Intel(R) Speed Shift Technology Interrupt Control | VarStore: CpuSetup | VarOffset: 0x1E0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Boot performance mode | VarStore: CpuSetup | VarOffset: 0x13 | Size: 0x1
Max Battery: 0x0
Max Non-Turbo Performance: 0x1
Turbo Performance: 0x2
CPU - Power Management Control
Intel(R) SpeedStep(tm) | VarStore: CpuSetup | VarOffset: 0x9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Race To Halt (RTH) | VarStore: CpuSetup | VarOffset: 0xA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Intel(R) Speed Shift Technology | VarStore: CpuSetup | VarOffset: 0xB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Intel(R) Turbo Boost Max Technology 3.0 | VarStore: CpuSetup | VarOffset: 0xC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Per Core P State OS control mode | VarStore: CpuSetup | VarOffset: 0xE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
HwP Autonomous Per Core P State | VarStore: CpuSetup | VarOffset: 0xF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
HwP Autonomous EPP Grouping | VarStore: CpuSetup | VarOffset: 0x10 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
EPB override over PECI | VarStore: CpuSetup | VarOffset: 0x11 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
HwP Fast MSR Support | VarStore: CpuSetup | VarOffset: 0x12 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
HDC Control | VarStore: CpuSetup | VarOffset: 0x4A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Turbo Mode | VarStore: CpuSetup | VarOffset: 0x16 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Platform PL1 Enable | VarStore: CpuSetup | VarOffset: 0x31 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Platform PL1 Power | VarStore: CpuSetup | VarOffset: 0x32 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
CPU - Power Management Control
Platform PL1 Time Window | VarStore: CpuSetup | VarOffset: 0x36 | Size: 0x1
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
80: 0x50
96: 0x60
112: 0x70
128: 0x80
CPU - Power Management Control
Platform PL2 Enable | VarStore: CpuSetup | VarOffset: 0x37 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Platform PL2 Power | VarStore: CpuSetup | VarOffset: 0x38 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
CPU - Power Management Control
Power Limit 4 Override | VarStore: CpuSetup | VarOffset: 0x2A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Power Limit 4 | VarStore: CpuSetup | VarOffset: 0x2B | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
CPU - Power Management Control
Power Limit 4 Lock | VarStore: CpuSetup | VarOffset: 0x2F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
C states | VarStore: CpuSetup | VarOffset: 0x14 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Enhanced C-states | VarStore: CpuSetup | VarOffset: 0x15 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
C-State Auto Demotion | VarStore: CpuSetup | VarOffset: 0x3E | Size: 0x1
Disabled: 0x0
C1: 0x1
CPU - Power Management Control
C-State Un-demotion | VarStore: CpuSetup | VarOffset: 0x3F | Size: 0x1
Disabled: 0x0
C1: 0x1
CPU - Power Management Control
Package C-State Demotion | VarStore: CpuSetup | VarOffset: 0x40 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Package C-State Un-demotion | VarStore: CpuSetup | VarOffset: 0x41 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
CState Pre-Wake | VarStore: CpuSetup | VarOffset: 0x3D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
IO MWAIT Redirection | VarStore: CpuSetup | VarOffset: 0x48 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Package C State Limit | VarStore: CpuSetup | VarOffset: 0x4B | Size: 0x1
C0/C1: 0x0
C2: 0x1
C3: 0x2
C6: 0x3
C7: 0x4
C7S: 0x5
C8: 0x6
C9: 0x7
C10: 0x8
Cpu Default: 0xFE
Auto: 0xFF
CPU - Power Management Control
Time Unit | VarStore: CpuSetup | VarOffset: 0x204 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
CPU - Power Management Control
Latency | VarStore: CpuSetup | VarOffset: 0x205 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
CPU - Power Management Control
Time Unit | VarStore: CpuSetup | VarOffset: 0x4C | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
CPU - Power Management Control
Latency | VarStore: CpuSetup | VarOffset: 0x51 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
CPU - Power Management Control
Time Unit | VarStore: CpuSetup | VarOffset: 0x4D | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
CPU - Power Management Control
Latency | VarStore: CpuSetup | VarOffset: 0x53 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
CPU - Power Management Control
Time Unit | VarStore: CpuSetup | VarOffset: 0x4E | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
CPU - Power Management Control
Latency | VarStore: CpuSetup | VarOffset: 0x55 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
CPU - Power Management Control
Time Unit | VarStore: CpuSetup | VarOffset: 0x4F | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
CPU - Power Management Control
Latency | VarStore: CpuSetup | VarOffset: 0x57 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
CPU - Power Management Control
Time Unit | VarStore: CpuSetup | VarOffset: 0x50 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
CPU - Power Management Control
Latency | VarStore: CpuSetup | VarOffset: 0x59 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
CPU - Power Management Control
Thermal Monitor | VarStore: CpuSetup | VarOffset: 0x42 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Interrupt Redirection Mode Selection | VarStore: CpuSetup | VarOffset: 0x49 | Size: 0x1
Fixed Priority: 0x0
Round robin: 0x1
Hash Vector: 0x2
No Change: 0x7
CPU - Power Management Control
Timed MWAIT | VarStore: CpuSetup | VarOffset: 0x47 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
EC Turbo Control Mode | VarStore: CpuSetup | VarOffset: 0xC7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
AC Brick Capacity | VarStore: CpuSetup | VarOffset: 0xC8 | Size: 0x1
90W AC Brick: 0x1
65W AC Brick: 0x2
75W AC Brick: 0x3
CPU - Power Management Control
EC Polling Period | VarStore: CpuSetup | VarOffset: 0xC9 | Size: 0x1
Min: 0x1 | Max: 0xFF | Step: 0x1
CPU - Power Management Control
EC Guard Band Value | VarStore: CpuSetup | VarOffset: 0xCA | Size: 0x1
Min: 0x0 | Max: 0x14 | Step: 0x1
CPU - Power Management Control
EC Algorithm Selection | VarStore: CpuSetup | VarOffset: 0xCB | Size: 0x1
Min: 0x1 | Max: 0xA | Step: 0x1
CPU - Power Management Control
Energy Performance Gain | VarStore: SaSetup | VarOffset: 0xC9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
EPG DIMM Idd3N | VarStore: SaSetup | VarOffset: 0xCA | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
CPU - Power Management Control
EPG DIMM Idd3P | VarStore: SaSetup | VarOffset: 0xCC | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
CPU - Power Management Control
Dual Tau Boost | VarStore: CpuSetup | VarOffset: 0x28F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Custom P-state Table
Number of P states | VarStore: CpuSetup | VarOffset: 0x80 | Size: 0x1
Min: 0x0 | Max: 0x28 | Step: 0x0
Custom P-state Table
Max P-State Ratio | VarStore: CpuSetup | VarOffset: 0x81 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x82 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x83 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x84 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x85 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x86 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x87 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x88 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x89 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x8A | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x8B | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x8C | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x8D | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x8E | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x8F | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x90 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x91 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x92 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x93 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x94 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x95 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x96 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x97 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x98 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x99 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x9A | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x9B | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x9C | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x9D | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x9E | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x9F | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0xA0 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0xA1 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0xA2 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0xA3 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0xA4 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0xA5 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0xA6 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0xA7 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0xA8 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
Max P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xA9 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xAA | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xAB | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xAC | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xAD | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xAE | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xAF | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xB0 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xB1 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xB2 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xB3 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xB4 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xB5 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xB6 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xB7 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
Min P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xB8 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Turbo Ratio Limit Options
Turbo Ratio Limit Core0 | VarStore: CpuSetup | VarOffset: 0xE6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Core1 | VarStore: CpuSetup | VarOffset: 0xE7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Core2 | VarStore: CpuSetup | VarOffset: 0xE8 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Core3 | VarStore: CpuSetup | VarOffset: 0xE9 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Core4 | VarStore: CpuSetup | VarOffset: 0xEA | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Core5 | VarStore: CpuSetup | VarOffset: 0xEB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Core6 | VarStore: CpuSetup | VarOffset: 0xEC | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Core7 | VarStore: CpuSetup | VarOffset: 0xED | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Ratio0 (TRLR) | VarStore: CpuSetup | VarOffset: 0xD6 | Size: 0x1
Min: 0x0 | Max: 0x53 | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Ratio1 (TRLR) | VarStore: CpuSetup | VarOffset: 0xD7 | Size: 0x1
Min: 0x0 | Max: 0x53 | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Ratio2 (TRLR) | VarStore: CpuSetup | VarOffset: 0xD8 | Size: 0x1
Min: 0x0 | Max: 0x53 | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Ratio3 (TRLR) | VarStore: CpuSetup | VarOffset: 0xD9 | Size: 0x1
Min: 0x0 | Max: 0x53 | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Ratio4 (TRLR) | VarStore: CpuSetup | VarOffset: 0xDA | Size: 0x1
Min: 0x0 | Max: 0x53 | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Ratio5 (TRLR) | VarStore: CpuSetup | VarOffset: 0xDB | Size: 0x1
Min: 0x0 | Max: 0x53 | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Ratio6 (TRLR) | VarStore: CpuSetup | VarOffset: 0xDC | Size: 0x1
Min: 0x0 | Max: 0x53 | Step: 0x1
Turbo Ratio Limit Options
Turbo Ratio Limit Ratio7 (TRLR) | VarStore: CpuSetup | VarOffset: 0xDD | Size: 0x1
Min: 0x0 | Max: 0x53 | Step: 0x1
View/Configure Turbo Options
Energy Efficient P-state | VarStore: CpuSetup | VarOffset: 0x3C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
View/Configure Turbo Options
Package Power Limit MSR Lock | VarStore: CpuSetup | VarOffset: 0x30 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
View/Configure Turbo Options
Power Limit 1 Override | VarStore: CpuSetup | VarOffset: 0x1B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
View/Configure Turbo Options
Power Limit 1 | VarStore: CpuSetup | VarOffset: 0x17 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
View/Configure Turbo Options
Power Limit 1 Time Window | VarStore: CpuSetup | VarOffset: 0x1C | Size: 0x1
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
80: 0x50
96: 0x60
112: 0x70
128: 0x80
View/Configure Turbo Options
Power Limit 2 Override | VarStore: CpuSetup | VarOffset: 0x1D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
View/Configure Turbo Options
Power Limit 2 | VarStore: CpuSetup | VarOffset: 0x1E | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
View/Configure Turbo Options
Energy Efficient Turbo | VarStore: CpuSetup | VarOffset: 0x198 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU VR Settings
VR Power Delivery Design | VarStore: CpuSetup | VarOffset: 0x322 | Size: 0x1
AUTO: 0x0
RKL S 8+1 35W: 0x30
RKL S 8+1 65W: 0x31
RKL S 8+1 80W: 0x32
RKL S 8+1 125W: 0x33
RKL S 6+1 35W: 0x34
RKL S 6+1 65W: 0x35
RKL S 6+1 80W: 0x36
RKL S 6+1 125W: 0x37
CPU VR Settings
PSYS Slope | VarStore: CpuSetup | VarOffset: 0xFD | Size: 0x1
Min: 0x0 | Max: 0xC8 | Step: 0x1
CPU VR Settings
PSYS Offset | VarStore: CpuSetup | VarOffset: 0xFE | Size: 0x2
Min: 0x0 | Max: 0xF9FF | Step: 0x1
CPU VR Settings
PSYS Prefix | VarStore: CpuSetup | VarOffset: 0x100 | Size: 0x1
+: 0x0
-: 0x1
CPU VR Settings
PSYS PMax Power | VarStore: CpuSetup | VarOffset: 0x101 | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
CPU VR Settings
Min Voltage Override | VarStore: CpuSetup | VarOffset: 0x1DB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU VR Settings
Min Voltage Runtime | VarStore: CpuSetup | VarOffset: 0x1DC | Size: 0x2
Min: 0x0 | Max: 0x7CF | Step: 0x1
CPU VR Settings
Min Voltage C8 | VarStore: CpuSetup | VarOffset: 0x1DE | Size: 0x2
Min: 0x0 | Max: 0x7CF | Step: 0x1
Acoustic Noise Settings
Acoustic Noise Mitigation | VarStore: CpuSetup | VarOffset: 0x1D2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Acoustic Noise Settings
Pre Wake Time | VarStore: CpuSetup | VarOffset: 0x30E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Acoustic Noise Settings
Ramp Up Time | VarStore: CpuSetup | VarOffset: 0x30F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Acoustic Noise Settings
Ramp Down Time | VarStore: CpuSetup | VarOffset: 0x310 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Acoustic Noise Settings
Disable Fast PKG C State Ramp for IA Domain | VarStore: CpuSetup | VarOffset: 0x3C1 | Size: 0x1
FALSE: 0x0
TRUE: 0x1
Acoustic Noise Settings
Slow Slew Rate for IA Domain | VarStore: CpuSetup | VarOffset: 0x3C6 | Size: 0x1
Fast/2: 0x0
Fast/4: 0x1
Fast/8: 0x2
Fast/16: 0x3
Acoustic Noise Settings
Disable Fast PKG C State Ramp for GT Domain | VarStore: CpuSetup | VarOffset: 0x3C3 | Size: 0x1
FALSE: 0x0
TRUE: 0x1
Acoustic Noise Settings
Slow Slew Rate for GT Domain | VarStore: CpuSetup | VarOffset: 0x3C8 | Size: 0x1
Fast/2: 0x0
Fast/4: 0x1
Fast/8: 0x2
Fast/16: 0x3
Acoustic Noise Settings
Disable Fast PKG C State Ramp for SA Domain | VarStore: CpuSetup | VarOffset: 0x3C0 | Size: 0x1
FALSE: 0x0
TRUE: 0x1
Acoustic Noise Settings
Slow Slew Rate for SA Domain | VarStore: CpuSetup | VarOffset: 0x3C5 | Size: 0x1
Fast/2: 0x0
Fast/4: 0x1
Fast/8: 0x2
System Agent VR Settings
SA VR Config Enable | VarStore: CpuSetup | VarOffset: 0x327 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
System Agent VR Settings
SA AC Loadline | VarStore: CpuSetup | VarOffset: 0x32E | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
System Agent VR Settings
SA DC Loadline | VarStore: CpuSetup | VarOffset: 0x338 | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
System Agent VR Settings
SA PS Current Threshold1 | VarStore: CpuSetup | VarOffset: 0x342 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
System Agent VR Settings
SA PS Current Threshold2 | VarStore: CpuSetup | VarOffset: 0x34C | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
System Agent VR Settings
SA PS Current Threshold3 | VarStore: CpuSetup | VarOffset: 0x356 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
System Agent VR Settings
SA PS3 Enable | VarStore: CpuSetup | VarOffset: 0x35E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
System Agent VR Settings
SA PS4 Enable | VarStore: CpuSetup | VarOffset: 0x363 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
System Agent VR Settings
SA IMON Slope | VarStore: CpuSetup | VarOffset: 0x36A | Size: 0x2
Min: 0x0 | Max: 0xC8 | Step: 0x1
System Agent VR Settings
SA IMON Offset | VarStore: CpuSetup | VarOffset: 0x374 | Size: 0x2
Min: 0x0 | Max: 0xFF | Step: 0x1
System Agent VR Settings
IMON Prefix | VarStore: CpuSetup | VarOffset: 0x37C | Size: 0x1
+: 0x0
-: 0x1
System Agent VR Settings
SA VR Current Limit | VarStore: CpuSetup | VarOffset: 0x383 | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
System Agent VR Settings
SA VR Voltage Limit | VarStore: CpuSetup | VarOffset: 0x38D | Size: 0x2
Min: 0x0 | Max: 0x1F3F | Step: 0x1
System Agent VR Settings
SA TDC Enable | VarStore: CpuSetup | VarOffset: 0x39F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
System Agent VR Settings
SA TDC Current Limit | VarStore: CpuSetup | VarOffset: 0x397 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x7D
System Agent VR Settings
SA TDC Time Window | VarStore: CpuSetup | VarOffset: 0x3AA | Size: 0x4
1 ms: 0x1
2 ms: 0x2
3 ms: 0x3
4 ms: 0x4
5 ms: 0x5
6 ms: 0x6
7 ms: 0x7
8 ms: 0x8
10 ms: 0xA
System Agent VR Settings
SA TDC Lock | VarStore: CpuSetup | VarOffset: 0x3B8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Core/IA VR Settings
IA VR Config Enable | VarStore: CpuSetup | VarOffset: 0x325 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Core/IA VR Settings
IA AC Loadline | VarStore: CpuSetup | VarOffset: 0x32A | Size: 0x2
Min: 0x0 | Max: 0x1869 | Step: 0x0
Core/IA VR Settings
IA DC Loadline | VarStore: CpuSetup | VarOffset: 0x334 | Size: 0x2
Min: 0x0 | Max: 0x1869 | Step: 0x0
Core/IA VR Settings
IA PS Current Threshold1 | VarStore: CpuSetup | VarOffset: 0x33E | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Core/IA VR Settings
IA PS Current Threshold2 | VarStore: CpuSetup | VarOffset: 0x348 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Core/IA VR Settings
IA PS Current Threshold3 | VarStore: CpuSetup | VarOffset: 0x352 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Core/IA VR Settings
IA PS3 Enable | VarStore: CpuSetup | VarOffset: 0x35C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Core/IA VR Settings
IA PS4 Enable | VarStore: CpuSetup | VarOffset: 0x361 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Core/IA VR Settings
IA IMON Slope | VarStore: CpuSetup | VarOffset: 0x366 | Size: 0x2
Min: 0x0 | Max: 0xC8 | Step: 0x1
Core/IA VR Settings
IA IMON Offset | VarStore: CpuSetup | VarOffset: 0x370 | Size: 0x2
Min: 0x0 | Max: 0xFF | Step: 0x1
Core/IA VR Settings
IA IMON Prefix | VarStore: CpuSetup | VarOffset: 0x37A | Size: 0x1
+: 0x0
-: 0x1
Core/IA VR Settings
IA VR Current Limit | VarStore: CpuSetup | VarOffset: 0x37F | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
Core/IA VR Settings
IA VR Voltage Limit | VarStore: CpuSetup | VarOffset: 0x389 | Size: 0x2
Min: 0x0 | Max: 0x1F3F | Step: 0x1
Core/IA VR Settings
IA TDC Enable | VarStore: CpuSetup | VarOffset: 0x39D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Core/IA VR Settings
IA TDC Current Limit | VarStore: CpuSetup | VarOffset: 0x393 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x7D
Core/IA VR Settings
IA TDC Time Window | VarStore: CpuSetup | VarOffset: 0x3A2 | Size: 0x4
1 ms: 0x1
2 ms: 0x2
3 ms: 0x3
4 ms: 0x4
5 ms: 0x5
6 ms: 0x6
7 ms: 0x7
8 ms: 0x8
10 ms: 0xA
Core/IA VR Settings
IA TDC Lock | VarStore: CpuSetup | VarOffset: 0x3B6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Core/IA VR Settings
IRMS | VarStore: CpuSetup | VarOffset: 0x3BB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT VR Settings
GT VR Config Enable | VarStore: CpuSetup | VarOffset: 0x326 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT VR Settings
GT AC Loadline | VarStore: CpuSetup | VarOffset: 0x32C | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
GT VR Settings
GT DC Loadline | VarStore: CpuSetup | VarOffset: 0x336 | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
GT VR Settings
GT PS Current Threshold1 | VarStore: CpuSetup | VarOffset: 0x340 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
GT VR Settings
GT PS Current Threshold2 | VarStore: CpuSetup | VarOffset: 0x34A | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
GT VR Settings
GT PS Current Threshold3 | VarStore: CpuSetup | VarOffset: 0x354 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
GT VR Settings
GT PS3 Enable | VarStore: CpuSetup | VarOffset: 0x35D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT VR Settings
GT PS4 Enable | VarStore: CpuSetup | VarOffset: 0x362 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT VR Settings
GT IMON Slope | VarStore: CpuSetup | VarOffset: 0x368 | Size: 0x2
Min: 0x0 | Max: 0xC8 | Step: 0x1
GT VR Settings
GT IMON Offset | VarStore: CpuSetup | VarOffset: 0x372 | Size: 0x2
Min: 0x0 | Max: 0xFF | Step: 0x1
GT VR Settings
GT IMON Prefix | VarStore: CpuSetup | VarOffset: 0x37B | Size: 0x1
+: 0x0
-: 0x1
GT VR Settings
GT VR Current Limit | VarStore: CpuSetup | VarOffset: 0x381 | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
GT VR Settings
GT VR Voltage Limit | VarStore: CpuSetup | VarOffset: 0x38B | Size: 0x2
Min: 0x0 | Max: 0x1F3F | Step: 0x1
GT VR Settings
GT TDC Enable | VarStore: CpuSetup | VarOffset: 0x39E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT VR Settings
GT TDC Current Limit | VarStore: CpuSetup | VarOffset: 0x395 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x7D
GT VR Settings
GT TDC Time Window | VarStore: CpuSetup | VarOffset: 0x3A6 | Size: 0x4
1 ms: 0x1
2 ms: 0x2
3 ms: 0x3
4 ms: 0x4
5 ms: 0x5
6 ms: 0x6
7 ms: 0x7
8 ms: 0x8
10 ms: 0xA
GT VR Settings
GT TDC Lock | VarStore: CpuSetup | VarOffset: 0x3B7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RFI Settings
RFI Frequency | VarStore: CpuSetup | VarOffset: 0x1CF | Size: 0x2
Min: 0x0 | Max: 0x77E | Step: 0x0
RFI Settings
FIVR Spread Spectrum | VarStore: CpuSetup | VarOffset: 0x324 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RFI Settings
RFI Spread Spectrum | VarStore: CpuSetup | VarOffset: 0x1D1 | Size: 0x1
0.5%: 0x0
1%: 0x3
1.5%: 0x8
2%: 0x12
3%: 0x1C
4%: 0x22
5%: 0x27
6%: 0x2C
Power Limit 3 Settings
Power Limit 3 Override | VarStore: CpuSetup | VarOffset: 0x22 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Power Limit 3 Settings
Power Limit 3 | VarStore: CpuSetup | VarOffset: 0x23 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Power Limit 3 Settings
Power Limit 3 Time Window | VarStore: CpuSetup | VarOffset: 0x27 | Size: 0x1
0: 0x0
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
Power Limit 3 Settings
Power Limit 3 Duty Cycle | VarStore: CpuSetup | VarOffset: 0x28 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x0
Power Limit 3 Settings
Power Limit 3 Lock | VarStore: CpuSetup | VarOffset: 0x29 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Config TDP Configurations
Enable Configurable TDP | VarStore: CpuSetup | VarOffset: 0x20C | Size: 0x1
Applies to non-cTDP: 0x0
Applies to cTDP: 0x1
Config TDP Configurations
Configurable TDP Boot Mode | VarStore: CpuSetup | VarOffset: 0x44 | Size: 0x1
Nominal: 0x0
Down: 0x1
Up: 0x2
Deactivate: 0xFF
Config TDP Configurations
Configurable TDP Lock | VarStore: CpuSetup | VarOffset: 0x45 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Config TDP Configurations
CTDP BIOS control | VarStore: CpuSetup | VarOffset: 0x46 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Config TDP Configurations
Power Limit 1 | VarStore: CpuSetup | VarOffset: 0x5B | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Config TDP Configurations
Power Limit 2 | VarStore: CpuSetup | VarOffset: 0x5F | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Config TDP Configurations
Power Limit 1 Time Window | VarStore: CpuSetup | VarOffset: 0x63 | Size: 0x1
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
80: 0x50
96: 0x60
112: 0x70
128: 0x80
Config TDP Configurations
ConfigTDP Turbo Activation Ratio | VarStore: CpuSetup | VarOffset: 0x64 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Config TDP Configurations
Power Limit 1 | VarStore: CpuSetup | VarOffset: 0x65 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Config TDP Configurations
Power Limit 2 | VarStore: CpuSetup | VarOffset: 0x69 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Config TDP Configurations
Power Limit 1 Time Window | VarStore: CpuSetup | VarOffset: 0x6D | Size: 0x1
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
80: 0x50
96: 0x60
112: 0x70
128: 0x80
Config TDP Configurations
ConfigTDP Turbo Activation Ratio | VarStore: CpuSetup | VarOffset: 0x6E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Config TDP Configurations
Power Limit 1 | VarStore: CpuSetup | VarOffset: 0x6F | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Config TDP Configurations
Power Limit 2 | VarStore: CpuSetup | VarOffset: 0x73 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Config TDP Configurations
Power Limit 1 Time Window | VarStore: CpuSetup | VarOffset: 0x77 | Size: 0x1
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
80: 0x50
96: 0x60
112: 0x70
128: 0x80
Config TDP Configurations
ConfigTDP Turbo Activation Ratio | VarStore: CpuSetup | VarOffset: 0x78 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure CPU Lock Options
CFG Lock | VarStore: CpuSetup | VarOffset: 0x43 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
View/Configure CPU Lock Options
Overclocking Lock | VarStore: CpuSetup | VarOffset: 0xEF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
ME State | VarStore: MeSetupStorage | VarOffset: 0x2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
ME Unconfig on RTC Clear | VarStore: MeSetup | VarOffset: 0x10 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
Comms Hub Support | VarStore: MeSetup | VarOffset: 0x4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
JHI Support | VarStore: MeSetup | VarOffset: 0x13 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
Core Bios Done Message | VarStore: MeSetup | VarOffset: 0x11 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PTT Configuration
Intel Platform Trust Technology (PTT) | VarStore: AmiWrapperSetup | VarOffset: 0x3 | Size: 0x1
dTPM: 0x0
PTT: 0x1
PTT Configuration
TPM 1.2 Deactivate | VarStore: MeSetupStorage | VarOffset: 0x6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Firmware Update Configuration
Me FW Image Re-Flash | VarStore: MeSetup | VarOffset: 0x3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Firmware Update Configuration
FW Update | VarStore: MeSetupStorage | VarOffset: 0x1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Unique Platform Id Configuration
Upid State | VarStore: MeSetupStorage | VarOffset: 0xE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Unique Platform Id Configuration
Upid OS Control State | VarStore: MeSetupStorage | VarOffset: 0xF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ME Debug Configuration
HECI Timeouts | VarStore: MeSetup | VarOffset: 0x5
ME Debug Configuration
Force ME DID Init Status | VarStore: MeSetup | VarOffset: 0x6 | Size: 0x1
Disabled: 0x0
0 - Success: 0x1
1 - No Memory in Channels: 0x2
2 - Memory Init Error: 0x3
ME Debug Configuration
CPU Replaced Polling Disable | VarStore: MeSetup | VarOffset: 0x7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ME Debug Configuration
HECI Message check Disable | VarStore: MeSetup | VarOffset: 0x8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ME Debug Configuration
MBP HOB Skip | VarStore: MeSetup | VarOffset: 0x9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ME Debug Configuration
HECI2 Interface Communication | VarStore: MeSetup | VarOffset: 0xA
ME Debug Configuration
KT Device | VarStore: MeSetup | VarOffset: 0xB
ME Debug Configuration
End Of Post Message | VarStore: MeSetup | VarOffset: 0x12 | Size: 0x1
Disabled: 0x0
Send in DXE: 0x2
ME Debug Configuration
D0I3 Setting for HECI Disable | VarStore: MeSetup | VarOffset: 0xC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ME Debug Configuration
MCTP Broadcast Cycle | VarStore: MeSetup | VarOffset: 0xD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
FIPS Mode
FIPS Mode Select | VarStore: MeSetupStorage | VarOffset: 0xA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Anti-Rollback SVN Configuration
Automatic HW-Enforced Anti-Rollback SVN | VarStore: MeSetup | VarOffset: 0x28 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Anti-Rollback SVN Configuration
Set HW-Enforced Anti-Rollback for Current SVN | VarStore: MeSetupStorage | VarOffset: 0xB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Thermal Configuration
Enable All Thermal Functions | VarStore: CpuSetup | VarOffset: 0x1C8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
DTS SMM | VarStore: CpuSetup | VarOffset: 0x19C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Critical Temp Reporting (Out Of spec): 0x2
Cpu Thermal Configuration
Tcc Activation Offset | VarStore: CpuSetup | VarOffset: 0x7F | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x0
Cpu Thermal Configuration
Tcc Offset Time Window | VarStore: CpuSetup | VarOffset: 0x17F | Size: 0x4
Disabled: 0x0
5 ms: 0x5
10 ms: 0xA
55 ms: 0x37
156 ms: 0x9C
375 ms: 0x177
500 ms: 0x1F4
750 ms: 0x2EE
1 sec: 0x3E8
2 sec: 0x7D0
3 sec: 0xBB8
4 sec: 0xFA0
5 sec: 0x1388
6 sec: 0x1770
7 sec: 0x1B58
8 sec: 0x1F40
10 sec: 0x2710
12 sec: 0x2EE0
14 sec: 0x36B0
16 sec: 0x3E80
20 sec: 0x4E20
24 sec: 0x5DC0
28 sec: 0x6D60
32 sec: 0x7D00
40 sec: 0x9C40
48 sec: 0xBB80
56 sec: 0xDAC0
64 sec: 0xFA00
80 sec: 0x13880
96 sec: 0x17700
112 sec: 0x1B580
128 sec: 0x1F400
160 sec: 0x27100
192 sec: 0x2EE00
224 sec: 0x36B00
256 sec: 0x3E800
320 sec: 0x4E200
384 sec: 0x5DC00
448 sec: 0x6D600
Cpu Thermal Configuration
Tcc Offset Clamp Enable | VarStore: CpuSetup | VarOffset: 0x183 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
Tcc Offset Lock Enable | VarStore: CpuSetup | VarOffset: 0x184 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
Bi-directional PROCHOT# | VarStore: CpuSetup | VarOffset: 0x7A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
Disable PROCHOT# Output | VarStore: CpuSetup | VarOffset: 0x7B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
Disable VR Thermal Alert | VarStore: CpuSetup | VarOffset: 0x7C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
PROCHOT Response | VarStore: CpuSetup | VarOffset: 0x7E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
PROCHOT Lock | VarStore: CpuSetup | VarOffset: 0x7D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
ACPI T-States | VarStore: CpuSetup | VarOffset: 0x79
Platform Thermal Configuration
Critical Trip Point | VarStore: Setup | VarOffset: 0x60F | Size: 0x1
15 C: 0xF
23 C: 0x17
31 C: 0x1F
39 C: 0x27
47 C: 0x2F
55 C: 0x37
63 C: 0x3F
71 C: 0x47
79 C: 0x4F
87 C: 0x57
95 C: 0x5F
100 C: 0x64
103 C: 0x67
111 C: 0x6F
119 C (POR): 0x77
127 C: 0x7F
130 C: 0x82
Platform Thermal Configuration
Active Trip Point 0 | VarStore: Setup | VarOffset: 0x60B | Size: 0x1
Disabled: 0x7F
15 C: 0xF
23 C: 0x17
31 C: 0x1F
39 C: 0x27
47 C: 0x2F
55 C: 0x37
63 C: 0x3F
71 C: 0x47
79 C: 0x4F
87 C: 0x57
95 C: 0x5F
103 C: 0x67
111 C: 0x6F
119 C (POR): 0x77
Platform Thermal Configuration
Active Trip Point 0 Fan Speed | VarStore: Setup | VarOffset: 0x60D | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Platform Thermal Configuration
Active Trip Point 1 | VarStore: Setup | VarOffset: 0x60A | Size: 0x1
Disabled: 0x7F
15 C: 0xF
23 C: 0x17
31 C: 0x1F
39 C: 0x27
47 C: 0x2F
55 C: 0x37
63 C: 0x3F
71 C: 0x47
79 C: 0x4F
87 C: 0x57
95 C: 0x5F
103 C: 0x67
111 C: 0x6F
119 C (POR): 0x77
Platform Thermal Configuration
Active Trip Point 1 Fan Speed | VarStore: Setup | VarOffset: 0x60C | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Platform Thermal Configuration
Passive Trip Point | VarStore: Setup | VarOffset: 0x60E | Size: 0x1
Disabled: 0x7F
15 C: 0xF
23 C: 0x17
31 C: 0x1F
39 C: 0x27
47 C: 0x2F
55 C: 0x37
63 C: 0x3F
71 C: 0x47
79 C: 0x4F
87 C: 0x57
95 C: 0x5F
103 C: 0x67
111 C: 0x6F
119 C (POR): 0x77
Platform Thermal Configuration
Passive TC1 Value | VarStore: Setup | VarOffset: 0x610 | Size: 0x1
Min: 0x1 | Max: 0x10 | Step: 0x1
Platform Thermal Configuration
Passive TC2 Value | VarStore: Setup | VarOffset: 0x611 | Size: 0x1
Min: 0x1 | Max: 0x10 | Step: 0x1
Platform Thermal Configuration
Passive TSP Value | VarStore: Setup | VarOffset: 0x612 | Size: 0x1
Min: 0x2 | Max: 0x20 | Step: 0x2
Platform Thermal Configuration
Active Trip Points | VarStore: Setup | VarOffset: 0x613 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
Passive Trip Points | VarStore: Setup | VarOffset: 0x614 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
Critical Trip Points | VarStore: Setup | VarOffset: 0x615 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
PCH Temp Read | VarStore: Setup | VarOffset: 0x61B
Platform Thermal Configuration
CPU Energy Read | VarStore: Setup | VarOffset: 0x61A
Platform Thermal Configuration
CPU Temp Read | VarStore: Setup | VarOffset: 0x619
Platform Thermal Configuration
Alert Enable Lock | VarStore: Setup | VarOffset: 0x61C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
PCH Alert | VarStore: Setup | VarOffset: 0x61D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
DIMM Alert | VarStore: Setup | VarOffset: 0x61E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
CPU Temp | VarStore: Setup | VarOffset: 0x61F | Size: 0x1
Min: 0x1 | Max: 0x6E | Step: 0x1
Platform Thermal Configuration
CPU Fan Speed | VarStore: Setup | VarOffset: 0x620 | Size: 0x1
Min: 0x1 | Max: 0x64 | Step: 0x1
Intel(R) Dynamic Tuning Technology Configuration
Intel(R) Dynamic Tuning Technology | VarStore: Setup | VarOffset: 0x621 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
INT3400 Device | VarStore: Setup | VarOffset: 0x62E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
Processor Thermal Device | VarStore: Setup | VarOffset: 0x623 | Size: 0x1
Disabled: 0x0
SA Thermal Device: 0x1
Intel(R) Dynamic Tuning Technology Configuration
PPCC Step Size | VarStore: Setup | VarOffset: 0x624 | Size: 0x4
0.5 Watts: 0x1F4
1.0 Watts: 0x3E8
1.5 Watts: 0x5DC
2.0 Watts: 0x7D0
Intel(R) Dynamic Tuning Technology Configuration
Intel(R) Dynamic Tuning Technology Configuration | VarStore: Setup | VarOffset: 0x622 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Intel(R) Dynamic Tuning Technology Configuration
FAN1 Device | VarStore: Setup | VarOffset: 0x628 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
FAN2 Device | VarStore: Setup | VarOffset: 0x907 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
FAN3 Device | VarStore: Setup | VarOffset: 0x908 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
Charger participant | VarStore: Setup | VarOffset: 0x629 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
Power participant | VarStore: Setup | VarOffset: 0x62A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
Battery Participant | VarStore: Setup | VarOffset: 0x62D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
Intel(R) Dynamic Tuning Technology Battery Sampling Period | VarStore: Setup | VarOffset: 0x62B | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Intel(R) Dynamic Tuning Technology Configuration
PCH FIVR Participant | VarStore: Setup | VarOffset: 0x635 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
Sensor Device 1 | VarStore: Setup | VarOffset: 0x630 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
Sensor Device 2 | VarStore: Setup | VarOffset: 0x631 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
Sensor Device 3 | VarStore: Setup | VarOffset: 0x632 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
Sensor Device 4 | VarStore: Setup | VarOffset: 0x633 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
Sensor Device 5 | VarStore: Setup | VarOffset: 0x634 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Technology Configuration
Discret Graphics Sensor Device | VarStore: Setup | VarOffset: 0x909 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OEM variable and Object
Design Variable 0 | VarStore: Setup | VarOffset: 0x642 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
OEM variable and Object
Design Variable 1 | VarStore: Setup | VarOffset: 0x643 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
OEM variable and Object
Design Variable 2 | VarStore: Setup | VarOffset: 0x644 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
OEM variable and Object
Design Variable 3 | VarStore: Setup | VarOffset: 0x645 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
OEM variable and Object
Design Variable 4 | VarStore: Setup | VarOffset: 0x646 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
OEM variable and Object
Design Variable 5 | VarStore: Setup | VarOffset: 0x647 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
OEM variable and Object
PPCC Object | VarStore: Setup | VarOffset: 0x636 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
ARTG Object | VarStore: Setup | VarOffset: 0x637 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
PMAX Object | VarStore: Setup | VarOffset: 0x638 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 1 Object | VarStore: Setup | VarOffset: 0x639 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 2 Object | VarStore: Setup | VarOffset: 0x63A | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 3 Object | VarStore: Setup | VarOffset: 0x63B | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 4 Object | VarStore: Setup | VarOffset: 0x63C | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 5 Object | VarStore: Setup | VarOffset: 0x63D | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 6 Object | VarStore: Setup | VarOffset: 0x63E | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 7 Object | VarStore: Setup | VarOffset: 0x63F | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 8 Object | VarStore: Setup | VarOffset: 0x640 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
Optional Objects | VarStore: Setup | VarOffset: 0x641 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
Platform Settings
Charging Method | VarStore: Setup | VarOffset: 0x797 | Size: 0x1
Normal Charging: 0x0
Fast Charging: 0x1
Platform Settings
Firmware Configuration | VarStore: Setup | VarOffset: 0x4A | Size: 0x1
Ignore Policy Update: 0x0
Production: 0x1
Test: 0x2
Platform Settings
PS2 Keyboard and Mouse | VarStore: Setup | VarOffset: 0x608 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Platform Settings
Power Loss Notification Feature | VarStore: Setup | VarOffset: 0x980 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Settings
Device password support | VarStore: Setup | VarOffset: 0x8E1
Platform Settings
Pmic Vcc IO Level | VarStore: Setup | VarOffset: 0x616 | Size: 0x1
Disable Link: 0x7
1.05V: 0x0
1.071V: 0x1
1.023V: 0x2
0.997V: 0x3
0.850V: 0x4
0.900V: 0x5
0.950V: 0x6
Platform Settings
Pmic Vddq Level | VarStore: Setup | VarOffset: 0x617 | Size: 0x1
Disable Link: 0x8
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
Platform Settings
HEBC value | VarStore: Setup | VarOffset: 0x75F | Size: 0x4
Min: 0x0 | Max: 0xFFFFFFFF | Step: 0x1
Platform Settings
Pmic SlpS0 VM Support | VarStore: Setup | VarOffset: 0x75D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Settings
Power Sharing Manager | VarStore: Setup | VarOffset: 0x665 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Settings
Domain Type SPLC 1 | VarStore: Setup | VarOffset: 0x666 | Size: 0x1
Min: 0x1 | Max: 0x32 | Step: 0x1
Platform Settings
Default Power Limit 1 SPLC | VarStore: Setup | VarOffset: 0x667 | Size: 0x4
Min: 0x1 | Max: 0x2710 | Step: 0x1
Platform Settings
Default Time Window 1 SPLC | VarStore: Setup | VarOffset: 0x66B | Size: 0x4
Min: 0x1 | Max: 0x186A0 | Step: 0x1
Platform Settings
Domain Type DPLC 1 | VarStore: Setup | VarOffset: 0x66F | Size: 0x1
Min: 0x1 | Max: 0x32 | Step: 0x1
Platform Settings
Domain Preference DPLC 1 | VarStore: Setup | VarOffset: 0x670 | Size: 0x1
Min: 0x1 | Max: 0x32 | Step: 0x1
Platform Settings
Power Limit Index 1 DPLC | VarStore: Setup | VarOffset: 0x671 | Size: 0x2
Min: 0x0 | Max: 0xA | Step: 0x1
Platform Settings
Default Power Limit 1 DPLC | VarStore: Setup | VarOffset: 0x673 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x1
Platform Settings
Default Time Window 1 DPLC | VarStore: Setup | VarOffset: 0x675 | Size: 0x4
Min: 0x1 | Max: 0x186A0 | Step: 0x1
Platform Settings
Minimum Power Limit 1 DPLC | VarStore: Setup | VarOffset: 0x679 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x1
Platform Settings
Maximum Power Limit 1 DPLC | VarStore: Setup | VarOffset: 0x67B | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x1
Platform Settings
Maximum Time Window 1 DPLC | VarStore: Setup | VarOffset: 0x67D | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x1
Platform Settings
Enable FFU Support | VarStore: Setup | VarOffset: 0x6DC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Settings
HID Event Filter Driver | VarStore: Setup | VarOffset: 0x75C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Settings
Delay to wait for WWAN device to be ready before SAR reset. | VarStore: Setup | VarOffset: 0x763 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Platform Settings
System Time and Alarm Source | VarStore: Setup | VarOffset: 0x79A | Size: 0x1
ACPI Time and Alarm Device: 0x0
Legacy RTC: 0x1
Platform Settings
Enable xdpclock | VarStore: Setup | VarOffset: 0x7A4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Settings
Enable PowerMeter | VarStore: Setup | VarOffset: 0x7B2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Settings
Disable PCIE Tunneling Over USB4 | VarStore: Setup | VarOffset: 0x8EC | Size: 0x1
Disabled: 0x0
Enabled: 0x5
Platform Settings
Intel Trusted Device Setup Boot | VarStore: Setup | VarOffset: 0x79B | Size: 0x1
Enabled: 0x1
Disabled: 0x0
ACPI D3Cold settings
ACPI D3Cold Support | VarStore: Setup | VarOffset: 0x648 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
VR Ramp up delay | VarStore: Setup | VarOffset: 0x654 | Size: 0x2
Min: 0x0 | Max: 0x64 | Step: 0x10
ACPI D3Cold settings
PCIE Slot 5 Device Power-on delay in ms | VarStore: Setup | VarOffset: 0x649 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x10
ACPI D3Cold settings
Audio Delay | VarStore: Setup | VarOffset: 0x64C | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x10
ACPI D3Cold settings
SensorHub | VarStore: Setup | VarOffset: 0x652 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x10
ACPI D3Cold settings
TouchPad | VarStore: Setup | VarOffset: 0x64E | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x10
ACPI D3Cold settings
TouchPanel | VarStore: Setup | VarOffset: 0x650 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x10
ACPI D3Cold settings
P-state Capping | VarStore: Setup | VarOffset: 0x656 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
USB Port 1 | VarStore: Setup | VarOffset: 0x64A | Size: 0x1
High Speed: 0x1
Super Speed: 0x2
Disabled: 0x0
ACPI D3Cold settings
USB Port 2 | VarStore: Setup | VarOffset: 0x64B | Size: 0x1
Disabled: 0x0
High Speed: 0x1
Super Speed: 0x2
Super Speed WWAN: 0x4
ACPI D3Cold settings
ZPODD | VarStore: Setup | VarOffset: 0x658 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
WWAN | VarStore: Setup | VarOffset: 0x659 | Size: 0x1
Disabled: 0x0
D0/L1.2: 0x1
D3/L2: 0x3
ACPI D3Cold settings
Sata Port 0 | VarStore: Setup | VarOffset: 0x65A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
Sata Port 1 | VarStore: Setup | VarOffset: 0x65B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
Sata Port 2 | VarStore: Setup | VarOffset: 0x65C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
Sata Port 3 | VarStore: Setup | VarOffset: 0x65D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
Sata Port 4 | VarStore: Setup | VarOffset: 0x65E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
Sata Port 5 | VarStore: Setup | VarOffset: 0x65F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
PCIe Remapped CR1 | VarStore: Setup | VarOffset: 0x661 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
PCIe Remapped CR2 | VarStore: Setup | VarOffset: 0x662 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
PCIe Remapped CR3 | VarStore: Setup | VarOffset: 0x663 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
DTBT RTD3 Enable | VarStore: Setup | VarOffset: 0x8E3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
TBT Power-off delay in ms | VarStore: Setup | VarOffset: 0x8E4 | Size: 0x2
Min: 0x0 | Max: 0x3A98 | Step: 0x1
ACPI D3Cold settings
DTBT RTD3 CLKREQ Enable | VarStore: Setup | VarOffset: 0x8E6 | Size: 0x4
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
DTBT RTD3 CLKREQ Delay value | VarStore: Setup | VarOffset: 0x8EA | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
TCSS Platform Setting
Control Iommu Pre-boot Behavior | VarStore: Setup | VarOffset: 0x8DA | Size: 0x1
Disable IOMMU: 0x0
Enable IOMMU during boot: 0x1
TCSS Platform Setting
USBC connector manager selection | VarStore: Setup | VarOffset: 0x7A7 | Size: 0x1
Disabled: 0x0
Enable UCSI Device: 0x1
Enable UCMC Device: 0x2
TCSS Platform Setting
UCMC PD Interrupt Pin | VarStore: Setup | VarOffset: 0x958 | Size: 0x1
None Rework : H_15: 0x0
Rework Done : G_0: 0x1
TCSS Platform Setting
PD PS_ON mode selection | VarStore: Setup | VarOffset: 0x959 | Size: 0x1
Disabled: 0x0
Enable PD PS_ON: 0x1
Enable PD PS_ON Override: 0x2
TCSS Platform Setting
USBC and USBA Wake Capability | VarStore: Setup | VarOffset: 0x957 | Size: 0x1
S3: 0x3
S4: 0x4
OverClocking Performance Menu
OverClocking Feature | VarStore: CpuSetup | VarOffset: 0x19D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OverClocking Performance Menu
Per-core HT Disable | VarStore: CpuSetup | VarOffset: 0x208 | Size: 0x2
Min: 0x0 | Max: 0x1FF | Step: 0x1
OverClocking Performance Menu
Intel Speed Optimizer (ISO) | VarStore: CpuSetup | VarOffset: 0x311 | Size: 0x1
Unsupported: 0x0
Supported: 0x1
OverClocking Performance Menu
WDT Enable | VarStore: PchSetup | VarOffset: 0x24 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OverClocking Performance Menu
XTU Interface | VarStore: CpuSetup | VarOffset: 0x19E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OverClocking Performance Menu
BCLK Aware Adaptive Voltage | VarStore: CpuSetup | VarOffset: 0x1E9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OverClocking Performance Menu
Unlimited ICCMAX | VarStore: CpuSetup | VarOffset: 0x29B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OverClocking Performance Menu
PVD Ratio Threshold | VarStore: CpuSetup | VarOffset: 0x323 | Size: 0x1
Min: 0x0 | Max: 0x28 | Step: 0x1
OverClocking Performance Menu
PLL Max Banding Ratio | VarStore: CpuSetup | VarOffset: 0x3D5 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
OverClocking Performance Menu
Vmax Stress | VarStore: CpuSetup | VarOffset: 0x3D4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Processor
Core Ratio Extension Mode | VarStore: CpuSetup | VarOffset: 0x321 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Processor
Core Max OC Ratio | VarStore: CpuSetup | VarOffset: 0x19F | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Per Core Ratio Override | VarStore: CpuSetup | VarOffset: 0x290 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Processor
Core 0 Max Ratio | VarStore: CpuSetup | VarOffset: 0x291 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 1 Max Ratio | VarStore: CpuSetup | VarOffset: 0x292 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 2 Max Ratio | VarStore: CpuSetup | VarOffset: 0x293 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 3 Max Ratio | VarStore: CpuSetup | VarOffset: 0x294 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 4 Max Ratio | VarStore: CpuSetup | VarOffset: 0x295 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 5 Max Ratio | VarStore: CpuSetup | VarOffset: 0x296 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 6 Max Ratio | VarStore: CpuSetup | VarOffset: 0x297 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 7 Max Ratio | VarStore: CpuSetup | VarOffset: 0x298 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 8 Max Ratio | VarStore: CpuSetup | VarOffset: 0x299 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 9 Max Ratio | VarStore: CpuSetup | VarOffset: 0x29A | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core Voltage Mode | VarStore: CpuSetup | VarOffset: 0x1A0 | Size: 0x1
Adaptive: 0x0
Override: 0x1
Processor
Core Voltage Override | VarStore: CpuSetup | VarOffset: 0x1A1 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
Processor
Core Extra Turbo Voltage | VarStore: CpuSetup | VarOffset: 0x1A6 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
Processor
VF Offset Mode | VarStore: CpuSetup | VarOffset: 0x212 | Size: 0x1
Legacy: 0x0
Selection: 0x1
Processor
VF Configuration Scope | VarStore: CpuSetup | VarOffset: 0x270 | Size: 0x1
All-core: 0x0
Per-core: 0x1
Processor
Core Voltage Offset | VarStore: CpuSetup | VarOffset: 0x1A3 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
Offset Prefix | VarStore: CpuSetup | VarOffset: 0x1A5 | Size: 0x1
+: 0x0
-: 0x1
Processor
Core 0 Voltage Offset | VarStore: CpuSetup | VarOffset: 0x271 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
Offset Prefix | VarStore: CpuSetup | VarOffset: 0x285 | Size: 0x1
+: 0x0
-: 0x1
Processor
Core 1 Voltage Offset | VarStore: CpuSetup | VarOffset: 0x273 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
Offset Prefix | VarStore: CpuSetup | VarOffset: 0x286 | Size: 0x1
+: 0x0
-: 0x1
Processor
Core 2 Voltage Offset | VarStore: CpuSetup | VarOffset: 0x275 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
Offset Prefix | VarStore: CpuSetup | VarOffset: 0x287 | Size: 0x1
+: 0x0
-: 0x1
Processor
Core 3 Voltage Offset | VarStore: CpuSetup | VarOffset: 0x277 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
Offset Prefix | VarStore: CpuSetup | VarOffset: 0x288 | Size: 0x1
+: 0x0
-: 0x1
Processor
Core 4 Voltage Offset | VarStore: CpuSetup | VarOffset: 0x279 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
Offset Prefix | VarStore: CpuSetup | VarOffset: 0x289 | Size: 0x1
+: 0x0
-: 0x1
Processor
Core 5 Voltage Offset | VarStore: CpuSetup | VarOffset: 0x27B | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
Offset Prefix | VarStore: CpuSetup | VarOffset: 0x28A | Size: 0x1
+: 0x0
-: 0x1
Processor
Core 6 Voltage Offset | VarStore: CpuSetup | VarOffset: 0x27D | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
Offset Prefix | VarStore: CpuSetup | VarOffset: 0x28B | Size: 0x1
+: 0x0
-: 0x1
Processor
Core 7 Voltage Offset | VarStore: CpuSetup | VarOffset: 0x27F | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
Offset Prefix | VarStore: CpuSetup | VarOffset: 0x28C | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 1 Offset | VarStore: CpuSetup | VarOffset: 0x214 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 1 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x232 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 2 Offset | VarStore: CpuSetup | VarOffset: 0x216 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 2 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x233 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 3 Offset | VarStore: CpuSetup | VarOffset: 0x218 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 3 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x234 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 4 Offset | VarStore: CpuSetup | VarOffset: 0x21A | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 4 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x235 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 5 Offset | VarStore: CpuSetup | VarOffset: 0x21C | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 5 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x236 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 6 Offset | VarStore: CpuSetup | VarOffset: 0x21E | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 6 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x237 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 7 Offset | VarStore: CpuSetup | VarOffset: 0x220 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 7 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x238 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 8 Offset | VarStore: CpuSetup | VarOffset: 0x222 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 8 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x239 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 9 Offset | VarStore: CpuSetup | VarOffset: 0x224 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 9 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x23A | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 10 Offset | VarStore: CpuSetup | VarOffset: 0x226 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 10 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x23B | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 11 Offset | VarStore: CpuSetup | VarOffset: 0x228 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 11 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x23C | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 12 Offset | VarStore: CpuSetup | VarOffset: 0x22A | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 12 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x23D | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 13 Offset | VarStore: CpuSetup | VarOffset: 0x22C | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 13 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x23E | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 14 Offset | VarStore: CpuSetup | VarOffset: 0x22E | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 14 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x23F | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 15 Offset | VarStore: CpuSetup | VarOffset: 0x230 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
| VarStore: CpuSetup | VarOffset: 0x240 | Size: 0x1
+: 0x0
-: 0x1
Processor
AVX2 Ratio Offset | VarStore: CpuSetup | VarOffset: 0x1A8 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Processor
AVX2 Voltage Guardband Scale Factor | VarStore: CpuSetup | VarOffset: 0x20A | Size: 0x1
Min: 0x0 | Max: 0xC8 | Step: 0x1
Processor
AVX512 Ratio Offset | VarStore: CpuSetup | VarOffset: 0x1A9 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Processor
AVX512 Voltage Guardband Scale Factor | VarStore: CpuSetup | VarOffset: 0x20B | Size: 0x1
Min: 0x0 | Max: 0xC8 | Step: 0x1
Processor
TjMax Offset | VarStore: CpuSetup | VarOffset: 0x1CE | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Processor
TVB Ratio Clipping | VarStore: CpuSetup | VarOffset: 0x31C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Processor
TVB Voltage Optimizations | VarStore: CpuSetup | VarOffset: 0x31D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Ring
Ring Max OC Ratio | VarStore: CpuSetup | VarOffset: 0x1AA | Size: 0x1
Min: 0x0 | Max: 0x55 | Step: 0x1
Ring
Ring Voltage Mode | VarStore: CpuSetup | VarOffset: 0x1AC | Size: 0x1
Adaptive: 0x0
Override: 0x1
Ring
Ring Voltage Override | VarStore: CpuSetup | VarOffset: 0x1AD | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
Ring
Ring Extra Turbo Voltage | VarStore: CpuSetup | VarOffset: 0x1B2 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
Ring
VF Offset Mode | VarStore: CpuSetup | VarOffset: 0x29C | Size: 0x1
Legacy: 0x0
Selection: 0x1
Ring
Ring Voltage Offset | VarStore: CpuSetup | VarOffset: 0x1AF | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
Offset Prefix | VarStore: CpuSetup | VarOffset: 0x1B1 | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 1 Offset | VarStore: CpuSetup | VarOffset: 0x29E | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 1 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2BC | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 2 Offset | VarStore: CpuSetup | VarOffset: 0x2A0 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 2 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2BD | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 3 Offset | VarStore: CpuSetup | VarOffset: 0x2A2 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 3 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2BE | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 4 Offset | VarStore: CpuSetup | VarOffset: 0x2A4 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 4 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2BF | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 5 Offset | VarStore: CpuSetup | VarOffset: 0x2A6 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 5 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2C0 | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 6 Offset | VarStore: CpuSetup | VarOffset: 0x2A8 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 6 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2C1 | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 7 Offset | VarStore: CpuSetup | VarOffset: 0x2AA | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 7 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2C2 | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 8 Offset | VarStore: CpuSetup | VarOffset: 0x2AC | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 8 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2C3 | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 9 Offset | VarStore: CpuSetup | VarOffset: 0x2AE | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 9 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2C4 | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 10 Offset | VarStore: CpuSetup | VarOffset: 0x2B0 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 10 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2C5 | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 11 Offset | VarStore: CpuSetup | VarOffset: 0x2B2 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 11 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2C6 | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 12 Offset | VarStore: CpuSetup | VarOffset: 0x2B4 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 12 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2C7 | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 13 Offset | VarStore: CpuSetup | VarOffset: 0x2B6 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 13 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2C8 | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 14 Offset | VarStore: CpuSetup | VarOffset: 0x2B8 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
VF Point 14 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x2C9 | Size: 0x1
+: 0x0
-: 0x1
Ring
VF Point 15 Offset | VarStore: CpuSetup | VarOffset: 0x2BA | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Ring
| VarStore: CpuSetup | VarOffset: 0x2CA | Size: 0x1
+: 0x0
-: 0x1
Ring
Ring Down Bin | VarStore: CpuSetup | VarOffset: 0x1AB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Ring
Min Ring Ratio Limit | VarStore: CpuSetup | VarOffset: 0x1EE | Size: 0x1
Min: 0x0 | Max: 0x55 | Step: 0x1
Ring
Max Ring Ratio Limit | VarStore: CpuSetup | VarOffset: 0x1F0 | Size: 0x1
Min: 0x0 | Max: 0x55 | Step: 0x1
GT
GT OverClocking Frequency | VarStore: SaSetup | VarOffset: 0x249 | Size: 0x1
Min: 0x0 | Max: 0x2A | Step: 0x1
GT
GT Voltage Mode | VarStore: SaSetup | VarOffset: 0x24A | Size: 0x1
Adaptive: 0x0
Override: 0x1
GT
GT Voltage Override | VarStore: SaSetup | VarOffset: 0x24E | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
GT
GT Extra Turbo Voltage | VarStore: SaSetup | VarOffset: 0x250 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
GT
GT Voltage Offset | VarStore: SaSetup | VarOffset: 0x24B | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
GT
Offset Prefix | VarStore: SaSetup | VarOffset: 0x24D | Size: 0x1
+: 0x0
-: 0x1
GT
GT OverClocking Frequency | VarStore: SaSetup | VarOffset: 0x252 | Size: 0x1
Min: 0x0 | Max: 0x2A | Step: 0x1
GT
GT Voltage Mode | VarStore: SaSetup | VarOffset: 0x253 | Size: 0x1
Adaptive: 0x0
Override: 0x1
GT
GT Voltage Override | VarStore: SaSetup | VarOffset: 0x257 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
GT
GT Extra Turbo Voltage | VarStore: SaSetup | VarOffset: 0x259 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
GT
GTU Voltage Offset | VarStore: SaSetup | VarOffset: 0x254 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
GT
Offset Prefix | VarStore: SaSetup | VarOffset: 0x256 | Size: 0x1
+: 0x0
-: 0x1
Uncore
Uncore Voltage Mode | VarStore: CpuSetup | VarOffset: 0x317 | Size: 0x1
Adaptive: 0x0
Override: 0x1
Uncore
Uncore Voltage Override | VarStore: CpuSetup | VarOffset: 0x318 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
Uncore
Uncore Extra Turbo Voltage | VarStore: CpuSetup | VarOffset: 0x31A | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
Uncore
Uncore Voltage Offset | VarStore: SaSetup | VarOffset: 0x243 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Uncore
Offset Prefix | VarStore: SaSetup | VarOffset: 0x245 | Size: 0x1
+: 0x0
-: 0x1
Platform Voltage Overrides
VccCore Override Enable | VarStore: CpuSetup | VarOffset: 0x2FA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
VccCore | VarStore: CpuSetup | VarOffset: 0x2FB | Size: 0x2
Min: 0x320 | Max: 0x9F6 | Step: 0xA
Platform Voltage Overrides
VccST Override Enable | VarStore: CpuSetup | VarOffset: 0x2FD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
VccST | VarStore: CpuSetup | VarOffset: 0x2FE | Size: 0x2
Min: 0xFA | Max: 0x5DC | Step: 0xA
Platform Voltage Overrides
VccSA Override Enable | VarStore: CpuSetup | VarOffset: 0x300 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
VccSA | VarStore: CpuSetup | VarOffset: 0x301 | Size: 0x2
Min: 0xFA | Max: 0x5F0 | Step: 0xA
Platform Voltage Overrides
VccSFR_OC Override Enable | VarStore: CpuSetup | VarOffset: 0x303 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
VccSFR_OC | VarStore: CpuSetup | VarOffset: 0x304 | Size: 0x2
Min: 0x3E8 | Max: 0x9D8 | Step: 0xA
Platform Voltage Overrides
VccSFR Override Enable | VarStore: CpuSetup | VarOffset: 0x306 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
VccSFR | VarStore: CpuSetup | VarOffset: 0x307 | Size: 0x2
Min: 0x2B2 | Max: 0x802 | Step: 0xA
Platform Voltage Overrides
VccIO Override Enable | VarStore: CpuSetup | VarOffset: 0x309 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
VccIO | VarStore: CpuSetup | VarOffset: 0x30A | Size: 0x2
Min: 0x384 | Max: 0x5F0 | Step: 0x5
Platform Voltage Overrides
Core VR Loadline Override | VarStore: CpuSetup | VarOffset: 0x30C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
DC Loadline value | VarStore: CpuSetup | VarOffset: 0x30D | Size: 0x1
-100 uOhm: 0x0
0 uOhm: 0x1
100 uOhm: 0x2
700 uOhm: 0x3
900 uOhm: 0x4
1000 uOhm: 0x5
1200 uOhm: 0x6
1300 uOhm: 0x7
1400 uOhm: 0x8
1500 uOhm: 0x9
1700 uOhm: 0xA
1800 uOhm: 0xB
2100 uOhm: 0xC
Voltage PLL Trim Controls
Core PLL Voltage Offset | VarStore: CpuSetup | VarOffset: 0x1C9 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Voltage PLL Trim Controls
GT PLL Voltage Offset | VarStore: CpuSetup | VarOffset: 0x1CA | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Voltage PLL Trim Controls
Ring PLL Voltage Offset | VarStore: CpuSetup | VarOffset: 0x1CB | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Voltage PLL Trim Controls
System Agent PLL Voltage Offset | VarStore: CpuSetup | VarOffset: 0x1CC | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Voltage PLL Trim Controls
Memory Controller PLL Voltage Offset | VarStore: CpuSetup | VarOffset: 0x1CD | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
AMT Configuration
USB Provisioning of AMT | VarStore: MeSetup | VarOffset: 0x1C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CIRA Configuration
Activate Remote Assistance Process | VarStore: MeSetup | VarOffset: 0x1A
CIRA Configuration
CIRA Timeout | VarStore: MeSetup | VarOffset: 0x1B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
ASF Configuration
PET Progress | VarStore: MeSetup | VarOffset: 0x1D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ASF Configuration
WatchDog | VarStore: MeSetup | VarOffset: 0x1F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ASF Configuration
OS Timer | VarStore: MeSetup | VarOffset: 0x20 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
ASF Configuration
BIOS Timer | VarStore: MeSetup | VarOffset: 0x22 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
ASF Configuration
ASF Sensors Table | VarStore: MeSetup | VarOffset: 0x1E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Secure Erase Configuration
Secure Erase mode | VarStore: Setup | VarOffset: 0x75A | Size: 0x1
Simulated: 0x0
Real: 0x1
Secure Erase Configuration
Force Secure Erase | VarStore: Setup | VarOffset: 0x75B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OEM Flags Settings
MEBx hotkey Pressed | VarStore: MeSetup | VarOffset: 0x15
OEM Flags Settings
MEBx Selection Screen | VarStore: MeSetup | VarOffset: 0x16
OEM Flags Settings
Hide Unconfigure ME Confirmation Prompt | VarStore: MeSetup | VarOffset: 0x17
OEM Flags Settings
MEBx OEM Debug Menu Enable | VarStore: MeSetup | VarOffset: 0x18
OEM Flags Settings
Unconfigure ME | VarStore: MeSetup | VarOffset: 0x19
MEBx Resolution Settings
Non-UI Mode Resolution | VarStore: MeSetup | VarOffset: 0x24 | Size: 0x1
Auto: 0x0
80x25: 0x1
100x31: 0x2
MEBx Resolution Settings
UI Mode Resolution | VarStore: MeSetup | VarOffset: 0x25 | Size: 0x1
Auto: 0x0
80x25: 0x1
100x31: 0x2
MEBx Resolution Settings
Graphics Mode Resolution | VarStore: MeSetup | VarOffset: 0x26 | Size: 0x1
Auto: 0x0
640x480: 0x1
800x600: 0x2
1024x768: 0x3
PCH BCLK Configuration
ICC Profile | VarStore: IccAdvancedSetupDataVar | VarOffset: 0x6 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
PCH BCLK Configuration
Clock Frequency | VarStore: IccAdvancedSetupDataVar | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCH BCLK Configuration
Bclk Change Permanent | VarStore: SaSetup | VarOffset: 0x26E | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH BCLK Configuration
Bclk Change w/o Reset | VarStore: SaSetup | VarOffset: 0x26F | Size: 0x1
Real Time change: 0x0
Permanent, no warm reset: 0x1
PCH BCLK Configuration
Spread % | VarStore: IccAdvancedSetupDataVar | VarOffset: 0x2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
PCH BCLK Configuration
| VarStore: IccAdvancedSetupDataVar | VarOffset: 0x3 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x0
PCH BCLK Configuration
| VarStore: IccAdvancedSetupDataVar | VarOffset: 0x4 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x0
PCH BCLK Configuration
| VarStore: IccAdvancedSetupDataVar | VarOffset: 0x5 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x0
PCH BCLK Configuration
| VarStore: IccAdvancedSetupDataVar | VarOffset: 0x7 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x0
Thunderbolt(TM) Configuration
Discrete Thunderbolt(TM) Support | VarStore: Setup | VarOffset: 0x6E4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Thunderbolt(TM) Configuration
Wake From Thunderbolt(TM) Devices | VarStore: Setup | VarOffset: 0x6E9
Thunderbolt(TM) Configuration
Current Security Level | VarStore: Setup | VarOffset: 0x8D9 | Size: 0x1
No Security: 0x0
Disable PCIE Tunnelling for USB4: 0x5
Unknown Status: 0xFF
Thunderbolt(TM) Configuration
Native OS security for TBT | VarStore: Setup | VarOffset: 0x7A9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Discrete Thunderbolt(TM) Configuration
Thunderbolt Usb Support | VarStore: Setup | VarOffset: 0x6E7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Discrete Thunderbolt(TM) Configuration
Thunderbolt Boot Support | VarStore: Setup | VarOffset: 0x6E8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Discrete Thunderbolt(TM) Configuration
Titan Ridge Workaround for OSUP | VarStore: Setup | VarOffset: 0x70B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Discrete Thunderbolt(TM) Configuration
Tbt Dynamic AC/DC L1 | VarStore: Setup | VarOffset: 0x70F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Discrete Thunderbolt(TM) Configuration
GPIO3 Force Pwr | VarStore: Setup | VarOffset: 0x6EA
Discrete Thunderbolt(TM) Configuration
Wait time in ms after applying Force Pwr | VarStore: Setup | VarOffset: 0x6EB | Size: 0x2
Min: 0x1 | Max: 0x1388 | Step: 0x0
Discrete Thunderbolt(TM) Configuration
GPIO filter | VarStore: Setup | VarOffset: 0x6EE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Thunderbolt(TM) OS select
Windows 10 Thunderbolt support | VarStore: Setup | VarOffset: 0x70A | Size: 0x1
Enable + RTD3: 0x2
Disabled: 0x0
DTBT Controller 0 Configuration
DTBT Controller 0 | VarStore: Setup | VarOffset: 0x6F1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
DTBT Controller 0 Configuration
DTbt Root Port Type | VarStore: Setup | VarOffset: 0x6F3 | Size: 0x1
PCH Root Port: 0x1
PEG Root Port: 0x2
DTBT Controller 0 Configuration
TBT Host Router | VarStore: Setup | VarOffset: 0x6F8 | Size: 0x1
One port: 0x1
Two port: 0x2
DTBT Controller 0 Configuration
Extra Bus Reserved | VarStore: Setup | VarOffset: 0x6FA | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
DTBT Controller 0 Configuration
Reserved Memory | VarStore: Setup | VarOffset: 0x6FC | Size: 0x2
Min: 0x1 | Max: 0x1000 | Step: 0x1
DTBT Controller 0 Configuration
Memory Alignment | VarStore: Setup | VarOffset: 0x702 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
DTBT Controller 0 Configuration
Reserved PMemory | VarStore: Setup | VarOffset: 0x704 | Size: 0x2
Min: 0x1 | Max: 0x1000 | Step: 0x1
DTBT Controller 0 Configuration
PMemory Alignment | VarStore: Setup | VarOffset: 0x708 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
DTBT Controller 0 Configuration
Reserved I/O | VarStore: Setup | VarOffset: 0x700 | Size: 0x1
Min: 0x0 | Max: 0x3C | Step: 0x4
DTBT Controller 1 Configuration
DTBT Controller 1 | VarStore: Setup | VarOffset: 0x6F2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
DTBT Controller 1 Configuration
DTbt Root Port Type | VarStore: Setup | VarOffset: 0x6F4 | Size: 0x1
PCH Root Port: 0x1
PEG Root Port: 0x2
DTBT Controller 1 Configuration
TBT Host Router | VarStore: Setup | VarOffset: 0x6F9 | Size: 0x1
One port: 0x1
Two port: 0x2
DTBT Controller 1 Configuration
Extra Bus Reserved | VarStore: Setup | VarOffset: 0x6FB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
DTBT Controller 1 Configuration
Reserved Memory | VarStore: Setup | VarOffset: 0x6FE | Size: 0x2
Min: 0x1 | Max: 0x1000 | Step: 0x1
DTBT Controller 1 Configuration
Memory Alignment | VarStore: Setup | VarOffset: 0x703 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
DTBT Controller 1 Configuration
Reserved PMemory | VarStore: Setup | VarOffset: 0x706 | Size: 0x2
Min: 0x1 | Max: 0x1000 | Step: 0x1
DTBT Controller 1 Configuration
PMemory Alignment | VarStore: Setup | VarOffset: 0x709 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
DTBT Controller 1 Configuration
Reserved I/O | VarStore: Setup | VarOffset: 0x701 | Size: 0x1
Min: 0x0 | Max: 0x3C | Step: 0x4
Debug Settings
Kernel Debug Serial Port | VarStore: PchSetup | VarOffset: 0x8 | Size: 0x1
Legacy UART: 0x0
SERIALIO UART2: 0x3
Debug Settings
Kernel Debug Patch | VarStore: Setup | VarOffset: 0x7AA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Debug Settings
Platform Debug Consent | VarStore: SiSetup | VarOffset: 0x1 | Size: 0x1
Disabled: 0x0
Enabled (USB2 DbC): 0x5
Enabled (DCI OOB): 0x2
Enabled (2 Wire DCI OOB): 0x6
Enabled (USB3 DbC): 0x3
Enabled (XDP/MIPI60): 0x4
Manual: 0x7
Advanced Debug Settings
USB3 Type-C UFP2DFP Kernel/Platform Debug Support | VarStore: PchSetup | VarOffset: 0xA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
No Change: 0x2
Advanced Debug Settings
DCI Enable | VarStore: PchSetup | VarOffset: 0x686 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
USB DbC Enable Mode | VarStore: PchSetup | VarOffset: 0x687 | Size: 0x1
Disabled: 0x0
USB2: 0x1
USB3: 0x2
Both: 0x3
No Change: 0x4
Advanced Debug Settings
Enable DCI ModPHY Power Gate | VarStore: PchSetup | VarOffset: 0x688 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
PCH Trace Hub Enable Mode | VarStore: PchSetup | VarOffset: 0x65E | Size: 0x1
Disabled: 0x0
Target Debugger: 0x1
Host Debugger: 0x2
Advanced Debug Settings
PCH TH Mem Buffer Size 0 | VarStore: PchSetup | VarOffset: 0x65F | Size: 0x1
None/OS: 0x0
1MB: 0x1
8MB: 0x2
64MB: 0x3
128MB: 0x4
256MB: 0x5
512MB: 0x6
Advanced Debug Settings
PCH TH Mem Buffer Size 1 | VarStore: PchSetup | VarOffset: 0x660 | Size: 0x1
None/OS: 0x0
1MB: 0x1
8MB: 0x2
64MB: 0x3
128MB: 0x4
256MB: 0x5
512MB: 0x6
Advanced Debug Settings
CPU Trace Hub Enable Mode | VarStore: SaSetup | VarOffset: 0xD7 | Size: 0x1
Disabled: 0x0
Target Debugger: 0x1
Host Debugger: 0x2
Advanced Debug Settings
CPU TH Mem Buffer Size 0 | VarStore: SaSetup | VarOffset: 0xD8 | Size: 0x1
None/OS: 0x0
1MB: 0x1
8MB: 0x2
64MB: 0x3
128MB: 0x4
256MB: 0x5
512MB: 0x6
Advanced Debug Settings
CPU TH Mem Buffer Size 1 | VarStore: SaSetup | VarOffset: 0xD9 | Size: 0x1
None/OS: 0x0
1MB: 0x1
8MB: 0x2
64MB: 0x3
128MB: 0x4
256MB: 0x5
512MB: 0x6
Advanced Debug Settings
CPU Run Control | VarStore: CpuSetup | VarOffset: 0xF2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
No Change: 0x2
Advanced Debug Settings
CPU Run Control Lock | VarStore: CpuSetup | VarOffset: 0xF3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
USB Overcurrent Override for DbC | VarStore: PchSetup | VarOffset: 0xB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
Processor trace memory allocation | VarStore: CpuSetup | VarOffset: 0xF8 | Size: 0x1
Disabled: 0xFF
4KB: 0x0
8KB: 0x1
16KB: 0x2
32KB: 0x3
64KB: 0x4
128KB: 0x5
256KB: 0x6
512KB: 0x7
1MB: 0x8
2MB: 0x9
4MB: 0xA
8MB: 0xB
16MB: 0xC
32MB: 0xD
64MB: 0xE
128MB: 0xF
Advanced Debug Settings
Processor trace | VarStore: CpuSetup | VarOffset: 0xF9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
Processor Trace OutPut Scheme | VarStore: CpuSetup | VarOffset: 0xF7 | Size: 0x1
Single Range Output: 0x0
ToPA Output: 0x1
Advanced Debug Settings
SMM Processor Trace | VarStore: CpuSetup | VarOffset: 0x211 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
JTAG C10 Power Gate | VarStore: CpuSetup | VarOffset: 0x8 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
Advanced Debug Settings
Three Strike Counter | VarStore: CpuSetup | VarOffset: 0xFB | Size: 0x1
Disabled: 0x1
Enabled: 0x0
Advanced Debug Settings
CrashLog Feature | VarStore: Setup | VarOffset: 0x79D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
CrashLog On All Reset | VarStore: Setup | VarOffset: 0x79E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
CrashLog Clear Enable | VarStore: Setup | VarOffset: 0x79F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
PMC Debug Message Enable | VarStore: PchSetup | VarOffset: 0x689 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
Delayed Authentication Mode | VarStore: MeSetupStorage | VarOffset: 0x9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Debug Configuration
RAM | VarStore: DebugConfigData | VarOffset: 0x3
Debug Configuration
Legacy UART | VarStore: DebugConfigData | VarOffset: 0x4
Debug Configuration
USB3 | VarStore: DebugConfigData | VarOffset: 0x5
Debug Configuration
Serial IO UART | VarStore: DebugConfigData | VarOffset: 0x6
Debug Configuration
Trace Hub | VarStore: DebugConfigData | VarOffset: 0x7
Debug Configuration
MRC Serial Debug Messages | VarStore: DebugConfigData | VarOffset: 0x0 | Size: 0x1
Disabled: 0x0
Error Only: 0x1
Error & Warnings: 0x2
Load, Error, Warnings & Info: 0x3
Load, Error, Warnings, Info & Event: 0x4
Load, Error, Warnings, Info & Verbose: 0x5
Debug Configuration
Serial Debug Messages | VarStore: DebugConfigData | VarOffset: 0x1 | Size: 0x1
Disabled: 0x0
Error Only: 0x1
Error & Warnings: 0x2
Load, Error, Warnings & Info: 0x3
Load, Error, Warnings, Info & Event: 0x4
Load, Error, Warnings, Info & Verbose: 0x5
Debug Configuration
Serial Debug Message Baud Rate | VarStore: DebugConfigData | VarOffset: 0x2 | Size: 0x1
9600: 0x3
19200: 0x4
57600: 0x6
115200: 0x7
Debug Configuration
Controller Number | VarStore: DebugConfigData | VarOffset: 0x8 | Size: 0x1
Serial IO UART 0: 0x0
Serial IO UART 1: 0x1
Serial IO UART 2: 0x2
Debug Configuration
Baud Rate | VarStore: DebugConfigData | VarOffset: 0x9 | Size: 0x4
9600: 0x2580
19200: 0x4B00
57600: 0xE100
115200: 0x1C200
460800: 0x70800
921600: 0xE1000
1500000: 0x16E360
1843200: 0x1C2000
3000000: 0x2DC6C0
3686400: 0x384000
6000000: 0x5B8D80
Debug Configuration
Stop Bits | VarStore: DebugConfigData | VarOffset: 0xD | Size: 0x1
Default: 0x0
1: 0x1
1.5: 0x2
2: 0x3
Debug Configuration
Parity Bits | VarStore: DebugConfigData | VarOffset: 0xE | Size: 0x1
Default: 0x0
None: 0x1
Even: 0x2
Odd: 0x3
Debug Configuration
Flow Control | VarStore: DebugConfigData | VarOffset: 0xF
Debug Configuration
Word Length | VarStore: DebugConfigData | VarOffset: 0x10 | Size: 0x1
5 BITS: 0x5
6 BITS: 0x6
7 BITS: 0x7
8 BITS: 0x8
Serial ATA Controller 0 Settings
SATA mode | VarStore: PcieSataModVar | VarOffset: 0x0 | Size: 0x1
IDE Mode: 0x1
AHCI Mode: 0x2
RAID Mode: 0x3
Serial ATA Controller 1 Settings
SATA mode | VarStore: PcieSataModVar | VarOffset: 0x1 | Size: 0x1
IDE Mode: 0x1
AHCI Mode: 0x2
RAID Mode: 0x3
Serial ATA Controller 2 Settings
SATA mode | VarStore: PcieSataModVar | VarOffset: 0x2 | Size: 0x1
IDE Mode: 0x1
AHCI Mode: 0x2
RAID Mode: 0x3
Trusted Computing
Security Device Support | VarStore: Setup | VarOffset: 0x11 | Size: 0x1
Disable: 0x0
Enable: 0x1
Trusted Computing
Disable Block Sid | VarStore: Setup | VarOffset: 0x2C | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Trusted Computing
Security Device Support | VarStore: Setup | VarOffset: 0x11 | Size: 0x1
Disable: 0x0
Enable: 0x1
Trusted Computing
TPM State | VarStore: Setup | VarOffset: 0xC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
Pending operation | VarStore: Setup | VarOffset: 0xD | Size: 0x1
None: 0x0
TPM Clear: 0x5
Trusted Computing
Security Device Support | VarStore: Setup | VarOffset: 0x11 | Size: 0x1
Disable: 0x0
Enable: 0x1
Trusted Computing
TCM State | VarStore: Setup | VarOffset: 0xC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
Pending operation | VarStore: Setup | VarOffset: 0xD | Size: 0x1
None: 0x0
TPM Clear: 0x5
Trusted Computing
Device Select | VarStore: Setup | VarOffset: 0x1E | Size: 0x1
TPM 1.2: 0x0
TPM 2.0: 0x1
Auto: 0x2
Trusted Computing
Security Device Support | VarStore: Setup | VarOffset: 0x11 | Size: 0x1
Disable: 0x0
Enable: 0x1
Trusted Computing
SHA-1 PCR Bank | VarStore: Setup | VarOffset: 0x25 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
SHA256 PCR Bank | VarStore: Setup | VarOffset: 0x26 | Size: 0x1
Disabled: 0x0
Enabled: 0x2
Trusted Computing
SHA384 PCR Bank | VarStore: Setup | VarOffset: 0x27 | Size: 0x1
Disabled: 0x0
Enabled: 0x4
Trusted Computing
SHA512 PCR Bank | VarStore: Setup | VarOffset: 0x28 | Size: 0x1
Disabled: 0x0
Enabled: 0x8
Trusted Computing
SM3_256 PCR Bank | VarStore: Setup | VarOffset: 0x29 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
Pending operation | VarStore: Setup | VarOffset: 0xD | Size: 0x1
None: 0x0
TPM Clear: 0x1
Trusted Computing
Platform Hierarchy | VarStore: Setup | VarOffset: 0x1A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
Storage Hierarchy | VarStore: Setup | VarOffset: 0x1B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
Endorsement Hierarchy | VarStore: Setup | VarOffset: 0x1C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
TPM2.0 UEFI Spec Version | VarStore: Setup | VarOffset: 0x19 | Size: 0x1
TCG_1_2: 0x1
TCG_2: 0x2
Trusted Computing
Physical Presence Spec Version | VarStore: Setup | VarOffset: 0x2B | Size: 0x1
1.2: 0x0
1.3: 0x1
Trusted Computing
TPM 20 InterfaceType | VarStore: Setup | VarOffset: 0x1D | Size: 0x1
PTT: 0x0
External TPM2.0: 0x1
Trusted Computing
Device Select | VarStore: Setup | VarOffset: 0x1E | Size: 0x1
TPM 1.2: 0x0
TPM 2.0: 0x1
Auto: 0x2
Trusted Computing
Disable Block Sid | VarStore: Setup | VarOffset: 0x2C | Size: 0x1
Enabled: 0x1
Disabled: 0x0
ACPI Settings
Enable ACPI Auto Configuration | VarStore: Setup | VarOffset: 0x982
ACPI Settings
Enable Hibernation | VarStore: Setup | VarOffset: 0x985
ACPI Settings
ACPI Sleep State | VarStore: Setup | VarOffset: 0x983 | Size: 0x2
Suspend Disabled: 0x0
S3 (Suspend to RAM): 0x2
ACPI Settings
S3 Video Repost | VarStore: Setup | VarOffset: 0x986 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Demo Board
CRB Test | VarStore: Setup | VarOffset: 0xA00
SMART Settings
SMART Self Test | VarStore: Setup | VarOffset: 0xEF6
Super IO Configuration
Serial Port | VarStore: PNP0501_0_NV | VarOffset: 0x0
Serial Port 1 Configuration
Serial Port | VarStore: PNP0501_0_NV | VarOffset: 0x0
Serial Port 1 Configuration
Change Settings | VarStore: PNP0501_0_NV | VarOffset: 0x1 | Size: 0x1
Auto: 0x0
IO=3F8h; IRQ=4;: 0x1
IO=3F8h; IRQ=3,4,5,6,7,9,10,11,12;: 0x2
IO=2F8h; IRQ=3,4,5,6,7,9,10,11,12;: 0x3
IO=3E8h; IRQ=3,4,5,6,7,9,10,11,12;: 0x4
IO=2E8h; IRQ=3,4,5,6,7,9,10,11,12;: 0x5
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0xF10 | Size: 0x1
Unknown Device: 0x0
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0xF10 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0xF10 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
Unknown Device: 0x2
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0xF10 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
Unknown Device: 0x2
Unknown Device: 0x3
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0xF10 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
Unknown Device: 0x2
Unknown Device: 0x3
Unknown Device: 0x4
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0xF10 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
Unknown Device: 0x2
Unknown Device: 0x3
Unknown Device: 0x4
Unknown Device: 0x5
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0xF10 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
Unknown Device: 0x2
Unknown Device: 0x3
Unknown Device: 0x4
Unknown Device: 0x5
Unknown Device: 0x6
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0xF10 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
Unknown Device: 0x2
Unknown Device: 0x3
Unknown Device: 0x4
Unknown Device: 0x5
Unknown Device: 0x6
Unknown Device: 0x7
AMI Graphic Output Protocol Policy
Brightness Setting | VarStore: Setup | VarOffset: 0xF11 | Size: 0x4
Min: 0x0 | Max: 0xFFFFFFFF | Step: 0x1
Brightness Setting: 0x0
AMI Graphic Output Protocol Policy
BIST Enable | VarStore: Setup | VarOffset: 0xF15 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SIO Common Setting
Lock Legacy Resources | VarStore: SioSetupData | VarOffset: 0x0
PCI Subsystem Settings
PCI Latency Timer | VarStore: Setup | VarOffset: 0xF19 | Size: 0x1
32 PCI Bus Clocks: 0x20
64 PCI Bus Clocks: 0x40
96 PCI Bus Clocks: 0x60
128 PCI Bus Clocks: 0x80
160 PCI Bus Clocks: 0xA0
192 PCI Bus Clocks: 0xC0
224 PCI Bus Clocks: 0xE0
248 PCI Bus Clocks: 0xF8
PCI Subsystem Settings
PCI-X Latency Timer | VarStore: Setup | VarOffset: 0xF1D | Size: 0x1
32 PCI Bus Clocks: 0x20
64 PCI Bus Clocks: 0x40
96 PCI Bus Clocks: 0x60
128 PCI Bus Clocks: 0x80
160 PCI Bus Clocks: 0xA0
192 PCI Bus Clocks: 0xC0
224 PCI Bus Clocks: 0xE0
248 PCI Bus Clocks: 0xF8
PCI Subsystem Settings
VGA Palette Snoop | VarStore: Setup | VarOffset: 0xF1A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Subsystem Settings
PERR# Generation | VarStore: Setup | VarOffset: 0xF1B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Subsystem Settings
SERR# Generation | VarStore: Setup | VarOffset: 0xF1C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Subsystem Settings
Above 4G Decoding | VarStore: Setup | VarOffset: 0xF16 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Subsystem Settings
BME DMA Mitigation | VarStore: Setup | VarOffset: 0xF18 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Subsystem Settings
Don't Reset VC-TC Mapping | VarStore: Setup | VarOffset: 0xF2A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Settings
Relaxed Ordering | VarStore: Setup | VarOffset: 0xF1E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Settings
Extended Tag | VarStore: Setup | VarOffset: 0xF1F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Settings
No Snoop | VarStore: Setup | VarOffset: 0xF20 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Settings
Maximum Payload | VarStore: Setup | VarOffset: 0xF21 | Size: 0x1
Auto: 0x37
128 Bytes: 0x0
256 Bytes: 0x1
512 Bytes: 0x2
1024 Bytes: 0x3
2048 Bytes: 0x4
4096 Bytes: 0x5
PCI Express Settings
Maximum Read Request | VarStore: Setup | VarOffset: 0xF22 | Size: 0x1
Auto: 0x37
128 Bytes: 0x0
256 Bytes: 0x1
512 Bytes: 0x2
1024 Bytes: 0x3
2048 Bytes: 0x4
4096 Bytes: 0x5
PCI Express Settings
ASPM Support | VarStore: Setup | VarOffset: 0xF23 | Size: 0x1
Disabled: 0x0
Auto: 0x37
Force L0s: 0x1
PCI Express Settings
Extended Synch | VarStore: Setup | VarOffset: 0xF24 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Settings
Link Training Retry | VarStore: Setup | VarOffset: 0xF25 | Size: 0x1
Disabled: 0x0
2: 0x2
3: 0x3
5: 0x5
PCI Express Settings
Link Training Timeout (uS) | VarStore: Setup | VarOffset: 0xF26 | Size: 0x2
Min: 0xA | Max: 0x2710 | Step: 0xA
PCI Express Settings
Unpopulated Links | VarStore: Setup | VarOffset: 0xF28 | Size: 0x1
Keep Link ON: 0x0
Disable Link: 0x1
PCI Express Settings
Restore PCIE Registers | VarStore: Setup | VarOffset: 0xF29 | Size: 0x1
Enabled: 0xFF
Disabled: 0x0
PCI Express GEN 2 Settings
Completion Timeout | VarStore: Setup | VarOffset: 0xF2B | Size: 0x1
Default: 0xFF
Shorter: 0x55
Longer: 0xAA
Disabled: 0x0
PCI Express GEN 2 Settings
ARI Forwarding | VarStore: Setup | VarOffset: 0xF2C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
AtomicOp Requester Enable | VarStore: Setup | VarOffset: 0xF2D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
AtomicOp Egress Blocking | VarStore: Setup | VarOffset: 0xF2E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
IDO Request Enable | VarStore: Setup | VarOffset: 0xF2F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
IDO Completion Enable | VarStore: Setup | VarOffset: 0xF30 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
LTR Mechanism Enable | VarStore: Setup | VarOffset: 0xF31 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
End-End TLP Prefix Blocking | VarStore: Setup | VarOffset: 0xF32 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
Target Link Speed | VarStore: Setup | VarOffset: 0xF33 | Size: 0x1
Auto: 0x37
Force to 2.5 GT/s: 0x1
Force to 5.0 GT/s: 0x2
Force to 8.0 GT/s: 0x3
Force to 16.0 GT/s: 0x4
Force to 32.0 GT/s: 0x5
PCI Express GEN 2 Settings
Clock Power Management | VarStore: Setup | VarOffset: 0xF35 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
Compliance SOS | VarStore: Setup | VarOffset: 0xF36 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
Hardware Autonomous Width | VarStore: Setup | VarOffset: 0xF37 | Size: 0x1
Enabled: 0x0
Disabled: 0x1
PCI Express GEN 2 Settings
Hardware Autonomous Speed | VarStore: Setup | VarOffset: 0xF38 | Size: 0x1
Enabled: 0x0
Disabled: 0x1
PCI Hot-Plug Settings
BIOS Hot-Plug Support | VarStore: Setup | VarOffset: 0xF39 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Hot-Plug Settings
PCI Buses Padding | VarStore: Setup | VarOffset: 0xF3A | Size: 0x1
Disabled: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
PCI Hot-Plug Settings
I/O Resources Padding | VarStore: Setup | VarOffset: 0xF3B | Size: 0x1
Disabled: 0x0
4 K: 0x4
8 K: 0x8
16 K: 0x10
32 K: 0x20
PCI Hot-Plug Settings
MMIO 32 bit Resources Padding | VarStore: Setup | VarOffset: 0xF3C | Size: 0x1
Disabled: 0x0
1 M: 0x1
2 M: 0x2
4 M: 0x4
8 M: 0x8
16 M: 0x10
32 M: 0x20
64 M: 0x40
128 M: 0x80
PCI Hot-Plug Settings
PFMMIO 32 bit Resources Padding | VarStore: Setup | VarOffset: 0xF3D | Size: 0x1
Disabled: 0x0
1 M: 0x1
2 M: 0x2
4 M: 0x4
8 M: 0x8
16 M: 0x10
32 M: 0x20
64 M: 0x40
128 M: 0x80
PCI Hot-Plug Settings
PFMMIO 64 bit Resources Padding | VarStore: Setup | VarOffset: 0xF40 | Size: 0x2
Disabled: 0x0
1 M: 0x1
2 M: 0x2
4 M: 0x4
8 M: 0x8
16 M: 0x10
32 M: 0x20
64 M: 0x40
128 M: 0x80
256 M: 0x100
512 M: 0x200
1 G: 0x400
2 G: 0x800
4 G: 0x1000
8 G: 0x2000
USB Configuration
USB Support | VarStore: UsbSupport | VarOffset: 0x0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
Legacy USB Support | VarStore: UsbSupport | VarOffset: 0x1 | Size: 0x1
Enabled: 0x0
Disabled: 0x1
Auto: 0x2
USB Configuration
USB 2.0 Controller Mode | VarStore: UsbSupport | VarOffset: 0x2E | Size: 0x1
HiSpeed: 0x1
FullSpeed: 0x0
USB Configuration
XHCI Legacy Support | VarStore: UsbSupport | VarOffset: 0x2A | Size: 0x1
Enabled: 0x1
Disabled: 0x0
USB Configuration
XHCI Hand-off | VarStore: UsbSupport | VarOffset: 0x2B | Size: 0x1
Enabled: 0x1
Disabled: 0x0
USB Configuration
EHCI Hand-off | VarStore: UsbSupport | VarOffset: 0x2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB Mass Storage Driver Support | VarStore: UsbSupport | VarOffset: 0x2F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
Port 60/64 Emulation | VarStore: UsbSupport | VarOffset: 0x7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB transfer time-out | VarStore: UsbSupport | VarOffset: 0x9 | Size: 0x1
1 sec: 0x1
5 sec: 0x5
10 sec: 0xA
20 sec: 0x14
USB Configuration
Device reset time-out | VarStore: UsbSupport | VarOffset: 0x8 | Size: 0x1
10 sec: 0x0
20 sec: 0x1
30 sec: 0x2
40 sec: 0x3
USB Configuration
Device power-up delay | VarStore: UsbSupport | VarOffset: 0x2C | Size: 0x1
Auto: 0x0
Manual: 0x1
USB Configuration
Device power-up delay in seconds | VarStore: UsbSupport | VarOffset: 0x2D | Size: 0x1
Min: 0x1 | Max: 0x28 | Step: 0x1
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0xA | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0xB | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0xC | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0xD | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0xE | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0xF | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x10 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x11 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x12 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x13 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x14 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x15 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x16 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x17 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x18 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x19 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x1A | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x1B | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x1C | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x1D | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x1E | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x1F | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x20 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x21 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x22 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x23 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x24 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x25 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x26 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x27 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x28 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x29 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
APP Center Download & Install
APP Center Download & Install | VarStore: Setup | VarOffset: 0xF42 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Network Stack Configuration
Network Stack | VarStore: NetworkStackVar | VarOffset: 0x0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Network Stack Configuration
IPv4 PXE Support | VarStore: NetworkStackVar | VarOffset: 0x1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Network Stack Configuration
IPv4 HTTP Support | VarStore: NetworkStackVar | VarOffset: 0x6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Network Stack Configuration
IPv6 PXE Support | VarStore: NetworkStackVar | VarOffset: 0x2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Network Stack Configuration
IPv6 HTTP Support | VarStore: NetworkStackVar | VarOffset: 0x7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Network Stack Configuration
PXE boot wait time | VarStore: NetworkStackVar | VarOffset: 0x4 | Size: 0x1
Min: 0x0 | Max: 0x5 | Step: 0x1
Network Stack Configuration
Media detect count | VarStore: NetworkStackVar | VarOffset: 0x5 | Size: 0x1
Min: 0x1 | Max: 0x32 | Step: 0x1
RGB Fusion
LED Hue | VarStore: Setup | VarOffset: 0xF59 | Size: 0x4
Min: 0x0 | Max: 0xFFFFFF | Step: 0x1
RGB Fusion
RGB Fusion | VarStore: Setup | VarOffset: 0xF58 | Size: 0x1
Off: 0x0
Pulse Mode: 0x1
Color Cycle: 0x2
Static Mode: 0x3
Flash Mode: 0x4
Double Flash: 0x5
RGB Fusion
LED2 Hue | VarStore: Setup | VarOffset: 0xF5D | Size: 0x4
Min: 0x0 | Max: 0xFFFFFF | Step: 0x1
SATA And RST Configuration
SATA Controller(s) | VarStore: PchSetup | VarOffset: 0x49 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
SATA And RST Configuration
SATA Mode Selection | VarStore: PchSetup | VarOffset: 0x4A | Size: 0x1
AHCI: 0x0
SATA And RST Configuration
RST Control PCIe Storage Devices | VarStore: Setup | VarOffset: 0xF67 | Size: 0x1
Auto: 0x0
Manual: 0x1
SATA And RST Configuration
PCIe Storage Dev On Port 1 | VarStore: PchSetup | VarOffset: 0xBE | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 2 | VarStore: PchSetup | VarOffset: 0xBF | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 3 | VarStore: PchSetup | VarOffset: 0xC0 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 4 | VarStore: PchSetup | VarOffset: 0xC1 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 5 | VarStore: PchSetup | VarOffset: 0xC2 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 6 | VarStore: PchSetup | VarOffset: 0xC3 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 7 | VarStore: PchSetup | VarOffset: 0xC4 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 8 | VarStore: PchSetup | VarOffset: 0xC5 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 9 | VarStore: PchSetup | VarOffset: 0xC6 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 10 | VarStore: PchSetup | VarOffset: 0xC7 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 11 | VarStore: PchSetup | VarOffset: 0xC8 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 12 | VarStore: PchSetup | VarOffset: 0xC9 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 13 | VarStore: PchSetup | VarOffset: 0xCA | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 14 | VarStore: PchSetup | VarOffset: 0xCB | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 15 | VarStore: PchSetup | VarOffset: 0xCC | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 16 | VarStore: PchSetup | VarOffset: 0xCD | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 17 | VarStore: PchSetup | VarOffset: 0xCE | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 18 | VarStore: PchSetup | VarOffset: 0xCF | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 19 | VarStore: PchSetup | VarOffset: 0xD0 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 20 | VarStore: PchSetup | VarOffset: 0xD1 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 21 | VarStore: PchSetup | VarOffset: 0xD2 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 22 | VarStore: PchSetup | VarOffset: 0xD3 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 23 | VarStore: PchSetup | VarOffset: 0xD4 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 24 | VarStore: PchSetup | VarOffset: 0xD5 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
Aggressive LPM Support | VarStore: PchSetup | VarOffset: 0x94 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Port 0 | VarStore: PchSetup | VarOffset: 0x4C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Port 0 DevSlp | VarStore: PchSetup | VarOffset: 0x96 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x54 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x5C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Port 1 | VarStore: PchSetup | VarOffset: 0x4D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Port 1 DevSlp | VarStore: PchSetup | VarOffset: 0x97 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x55 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x5D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Port 2 | VarStore: PchSetup | VarOffset: 0x4E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Port 2 DevSlp | VarStore: PchSetup | VarOffset: 0x98 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x56 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x5E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Port 3 | VarStore: PchSetup | VarOffset: 0x4F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Port 3 DevSlp | VarStore: PchSetup | VarOffset: 0x99 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x57 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x5F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Chipset
VT-d | VarStore: SaSetup | VarOffset: 0xD2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Chipset
Internal Graphics | VarStore: SaSetup | VarOffset: 0x10D | Size: 0x1
Auto: 0x2
Disabled: 0x0
Enabled: 0x1
Chipset
DVMT Pre-Allocated | VarStore: SaSetup | VarOffset: 0xCE | Size: 0x1
32M: 0x1
64M: 0x2
96M: 0x3
128M: 0x4
160M: 0x5
192M: 0x6
224M: 0x7
256M: 0x8
288M: 0x9
320M: 0xA
352M: 0xB
384M: 0xC
416M: 0xD
Chipset
DVMT Total Gfx Mem | VarStore: SaSetup | VarOffset: 0xCF | Size: 0x1
128M: 0x1
256M: 0x2
MAX: 0x3
Chipset
Aperture Size | VarStore: SaSetup | VarOffset: 0x3C | Size: 0x1
128MB: 0x0
256MB: 0x1
512MB: 0x3
Chipset
Audio Controller | VarStore: PchSetup | VarOffset: 0x4D0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Chipset
Above 4G Decoding | VarStore: Setup | VarOffset: 0x46 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Chipset
Re-Size BAR Support | VarStore: Setup | VarOffset: 0xF76 | Size: 0x1
Disabled: 0x0
Auto: 0x1
Chipset
IOAPIC 24-119 Entries | VarStore: PchSetup | VarOffset: 0x601 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Chipset
Enable 8254 Clock Gate | VarStore: PchSetup | VarOffset: 0x602 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Enabled In Runtime and S3 Resume: 0x2
PCI Express Gen3 Configuration
DMI ASPM | VarStore: SaSetup | VarOffset: 0x100 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
PCI Express Gen3 Configuration
Always Attempt SW EQ | VarStore: SaSetup | VarOffset: 0x90 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Gen3 Configuration
Number of Presets to test | VarStore: SaSetup | VarOffset: 0x9B | Size: 0x1
7, 3, 5, 8: 0x0
0 - 9: 0x1
Auto: 0x2
PCI Express Gen3 Configuration
Allow PERST# GPIO Usage | VarStore: SaSetup | VarOffset: 0x92 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Gen3 Configuration
SW EQ Enable VOC | VarStore: SaSetup | VarOffset: 0x96 | Size: 0x1
Jitter Only Test Mode: 0x0
Jitter & VOC Test Mode: 0x1
Auto: 0x2
PCI Express Gen3 Configuration
Jitter Dwell Time | VarStore: SaSetup | VarOffset: 0x8E | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Gen3 Configuration
Jitter Error Target | VarStore: SaSetup | VarOffset: 0x93 | Size: 0x2
Min: 0x1 | Max: 0xFFFF | Step: 0x1
PCI Express Gen3 Configuration
VOC Dwell Time | VarStore: SaSetup | VarOffset: 0x97 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Gen3 Configuration
VOC Error Target | VarStore: SaSetup | VarOffset: 0x99 | Size: 0x2
Min: 0x1 | Max: 0xFFFF | Step: 0x1
PCI Express Gen3 Configuration
Generate BDAT PEG Margin Data | VarStore: SaSetup | VarOffset: 0x95 | Size: 0x1
Disabled: 0x0
Generate Port Jitter Data: 0x1
PCI Express Gen3 Configuration
PEG IMR | VarStore: SaSetup | VarOffset: 0xB0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Gen3 Configuration
PEG IMR Size | VarStore: SaSetup | VarOffset: 0xB1 | Size: 0x2
Min: 0x0 | Max: 0x400 | Step: 0x1
PCI Express Gen3 Configuration
RP index for IMR | VarStore: SaSetup | VarOffset: 0xB3 | Size: 0x1
Min: 0x1 | Max: 0x4 | Step: 0x1
PCI Express Gen3 Configuration
PCIe Rx CEM Test Mode | VarStore: SaSetup | VarOffset: 0x6A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Gen3 Configuration
PEG Lane number for Test | VarStore: SaSetup | VarOffset: 0x6B | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
PCI Express Gen3 Configuration
Non-Protocol Awareness | VarStore: SaSetup | VarOffset: 0x6C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Gen3 Configuration
PCIe Spread Spectrum Clocking | VarStore: SaSetup | VarOffset: 0x6D | Size: 0x1
Enabled: 0x0
Disabled: 0x1
PEG Port Configuration
Max Link Speed | VarStore: SaSetup | VarOffset: 0x5E | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PEG Port Configuration
Max Link Width | VarStore: SaSetup | VarOffset: 0x62 | Size: 0x1
Auto: 0x0
Force X1: 0x1
Force X2: 0x2
Force X4: 0x3
Force X8: 0x4
PEG Port Configuration
Gen3 Eq Phase 2 | VarStore: SaSetup | VarOffset: 0x72 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Gen3 Eq Phase 3 Method | VarStore: SaSetup | VarOffset: 0x6E | Size: 0x1
Auto: 0x0
Adaptive Hardware Equalization: 0x1
Adaptive Software Equalization: 0x2
Static Equalization: 0x3
Disabled: 0x4
PEG Port Configuration
ASPM L0s | VarStore: SaSetup | VarOffset: 0x55 | Size: 0x1
Root Port Only: 0x1
Endpoint Port Only: 0x2
Both Root and Endpoint Ports: 0x3
PEG Port Configuration
De-emphasis Control | VarStore: SaSetup | VarOffset: 0x76 | Size: 0x1
-6 dB: 0x0
-3.5 dB: 0x1
PEG Port Configuration
PEG0 Slot Power Limit Value | VarStore: SaSetup | VarOffset: 0xA4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
PEG Port Configuration
PEG0 Slot Power Limit Scale | VarStore: SaSetup | VarOffset: 0xA0 | Size: 0x1
1.0x: 0x0
0.1x: 0x1
0.01x: 0x2
0.001x: 0x3
PEG Port Configuration
PEG0 Physical Slot Number | VarStore: SaSetup | VarOffset: 0xA8 | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
PEG Port Configuration
Max Link Speed | VarStore: SaSetup | VarOffset: 0x5F | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PEG Port Configuration
Max Link Width | VarStore: SaSetup | VarOffset: 0x63 | Size: 0x1
Auto: 0x0
Force X1: 0x1
Force X2: 0x2
Force X4: 0x3
PEG Port Configuration
Gen3 Eq Phase 2 | VarStore: SaSetup | VarOffset: 0x73 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Gen3 Eq Phase 3 Method | VarStore: SaSetup | VarOffset: 0x6F | Size: 0x1
Auto: 0x0
Adaptive Hardware Equalization: 0x1
Adaptive Software Equalization: 0x2
Static Equalization: 0x3
Disabled: 0x4
PEG Port Configuration
ASPM L0s | VarStore: SaSetup | VarOffset: 0x56 | Size: 0x1
Root Port Only: 0x1
Endpoint Port Only: 0x2
Both Root and Endpoint Ports: 0x3
PEG Port Configuration
De-emphasis Control | VarStore: SaSetup | VarOffset: 0x77 | Size: 0x1
-6 dB: 0x0
-3.5 dB: 0x1
PEG Port Configuration
PEG1 Slot Power Limit Value | VarStore: SaSetup | VarOffset: 0xA5 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
PEG Port Configuration
PEG1 Slot Power Limit Scale | VarStore: SaSetup | VarOffset: 0xA1 | Size: 0x1
1.0x: 0x0
0.1x: 0x1
0.01x: 0x2
0.001x: 0x3
PEG Port Configuration
PEG1 Physical Slot Number | VarStore: SaSetup | VarOffset: 0xAA | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
PEG Port Configuration
Max Link Speed | VarStore: SaSetup | VarOffset: 0x60 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PEG Port Configuration
Max Link Width | VarStore: SaSetup | VarOffset: 0x64 | Size: 0x1
Auto: 0x0
Force X1: 0x1
Force X2: 0x2
PEG Port Configuration
Gen3 Eq Phase 2 | VarStore: SaSetup | VarOffset: 0x74 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Gen3 Eq Phase 3 Method | VarStore: SaSetup | VarOffset: 0x70 | Size: 0x1
Auto: 0x0
Adaptive Hardware Equalization: 0x1
Adaptive Software Equalization: 0x2
Static Equalization: 0x3
Disabled: 0x4
PEG Port Configuration
ASPM L0s | VarStore: SaSetup | VarOffset: 0x57 | Size: 0x1
Root Port Only: 0x1
Endpoint Port Only: 0x2
Both Root and Endpoint Ports: 0x3
PEG Port Configuration
De-emphasis Control | VarStore: SaSetup | VarOffset: 0x78 | Size: 0x1
-6 dB: 0x0
-3.5 dB: 0x1
PEG Port Configuration
PEG2 Slot Power Limit Value | VarStore: SaSetup | VarOffset: 0xA6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
PEG Port Configuration
PEG2 Slot Power Limit Scale | VarStore: SaSetup | VarOffset: 0xA2 | Size: 0x1
1.0x: 0x0
0.1x: 0x1
0.01x: 0x2
0.001x: 0x3
PEG Port Configuration
PEG2 Physical Slot Number | VarStore: SaSetup | VarOffset: 0xAC | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
PEG Port Configuration
Max Link Speed | VarStore: SaSetup | VarOffset: 0x61 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PEG Port Configuration
Max Link Width | VarStore: SaSetup | VarOffset: 0x65 | Size: 0x1
Auto: 0x0
Force X1: 0x1
Force X2: 0x2
PEG Port Configuration
Gen3 Eq Phase 2 | VarStore: SaSetup | VarOffset: 0x75 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Gen3 Eq Phase 3 Method | VarStore: SaSetup | VarOffset: 0x71 | Size: 0x1
Auto: 0x0
Adaptive Hardware Equalization: 0x1
Adaptive Software Equalization: 0x2
Static Equalization: 0x3
Disabled: 0x4
PEG Port Configuration
ASPM L0s | VarStore: SaSetup | VarOffset: 0x58 | Size: 0x1
Root Port Only: 0x1
Endpoint Port Only: 0x2
Both Root and Endpoint Ports: 0x3
PEG Port Configuration
De-emphasis Control | VarStore: SaSetup | VarOffset: 0x79 | Size: 0x1
-6 dB: 0x0
-3.5 dB: 0x1
PEG Port Configuration
PEG3 Slot Power Limit Value | VarStore: SaSetup | VarOffset: 0xA7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
PEG Port Configuration
PEG3 Slot Power Limit Scale | VarStore: SaSetup | VarOffset: 0xA3 | Size: 0x1
1.0x: 0x0
0.1x: 0x1
0.01x: 0x2
0.001x: 0x3
PEG Port Configuration
PEG3 Physical Slot Number | VarStore: SaSetup | VarOffset: 0xAE | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
Gen3 RxCTLE Control
Bundle0 | VarStore: SaSetup | VarOffset: 0x86 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle1 | VarStore: SaSetup | VarOffset: 0x87 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle2 | VarStore: SaSetup | VarOffset: 0x88 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle3 | VarStore: SaSetup | VarOffset: 0x89 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle4 | VarStore: SaSetup | VarOffset: 0x8A | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle5 | VarStore: SaSetup | VarOffset: 0x8B | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle6 | VarStore: SaSetup | VarOffset: 0x8C | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle7 | VarStore: SaSetup | VarOffset: 0x8D | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
PEG10 RxCTLE Override | VarStore: SaSetup | VarOffset: 0xB4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Gen3 RxCTLE Control
PEG11 RxCTLE Override | VarStore: SaSetup | VarOffset: 0xB5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Gen3 RxCTLE Control
PEG12 RxCTLE Override | VarStore: SaSetup | VarOffset: 0xB6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Gen3 RxCTLE Control
PEG60 RxCTLE Override | VarStore: SaSetup | VarOffset: 0xB7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Gen3 RxCTLE Control
DMI RxCTLE Override | VarStore: SaSetup | VarOffset: 0xB8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
MRC ULT Safe Config | VarStore: SaSetup | VarOffset: 0x232 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Safe Mode Support | VarStore: SaSetup | VarOffset: 0x17A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Maximum Memory Frequency | VarStore: SaSetup | VarOffset: 0x167 | Size: 0x2
Auto: 0x0
1067: 0x42B
1200: 0x4B0
1333: 0x535
1400: 0x578
1600: 0x640
1800: 0x708
1867: 0x74B
2000: 0x7D0
2133: 0x855
2200: 0x898
2400: 0x960
2600: 0xA28
2667: 0xA6B
2800: 0xAF0
2933: 0xB75
3000: 0xBB8
3200: 0xC80
3467: 0xD8B
3600: 0xE10
3733: 0xE95
4000: 0xFA0
4200: 0x1068
4267: 0x10AB
4400: 0x1130
4533: 0x11B5
4600: 0x11F8
4800: 0x12C0
5000: 0x1388
5067: 0x13CB
5200: 0x1450
5333: 0x14D5
5400: 0x1518
5600: 0x15E0
5800: 0x16A8
5867: 0x16EB
6000: 0x1770
6133: 0x17F5
6200: 0x1838
Memory Configuration
HOB Buffer Size | VarStore: SaSetup | VarOffset: 0x164 | Size: 0x1
Auto: 0x0
1B: 0x1
1KB: 0x2
Max (assuming 63KB total HOB size): 0x3
Memory Configuration
ECC Support | VarStore: SaSetup | VarOffset: 0x165 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
DDR Speed Control | VarStore: SaSetup | VarOffset: 0x188 | Size: 0x1
Auto: 0x0
Manual: 0x1
Memory Configuration
SA GV Low Freq | VarStore: SaSetup | VarOffset: 0x184 | Size: 0x2
MRC default: 0x0
1067: 0x42B
1200: 0x4B0
1333: 0x535
1400: 0x578
1600: 0x640
1800: 0x708
1867: 0x74B
2133: 0x855
2400: 0x960
2667: 0xA6B
2933: 0xB75
3200: 0xC80
3467: 0xD8B
3733: 0xE95
4000: 0xFA0
4267: 0x10AB
Memory Configuration
SA GV Mid Freq | VarStore: SaSetup | VarOffset: 0x186 | Size: 0x2
MRC default: 0x0
1067: 0x42B
1333: 0x535
1600: 0x640
1800: 0x708
1867: 0x74B
2000: 0x7D0
2133: 0x855
2400: 0x960
2667: 0xA6B
2933: 0xB75
3200: 0xC80
3467: 0xD8B
3733: 0xE95
4000: 0xFA0
4267: 0x10AB
Memory Configuration
SA GV Low Gear | VarStore: SaSetup | VarOffset: 0x189 | Size: 0x1
Gear1: 0x0
Gear2: 0x1
Memory Configuration
SA GV Mid Gear | VarStore: SaSetup | VarOffset: 0x18A | Size: 0x1
Gear1: 0x0
Gear2: 0x1
Memory Configuration
SA GV High Gear | VarStore: SaSetup | VarOffset: 0x18B | Size: 0x1
Gear1: 0x0
Gear2: 0x1
Memory Configuration
Retrain on Fast Fail | VarStore: SaSetup | VarOffset: 0x178 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
DDR4_1DPC | VarStore: SaSetup | VarOffset: 0x179 | Size: 0x1
Disabled: 0x0
Enabled on DIMM0 only: 0x1
Enabled on DIMM1 only: 0x2
Enabled: 0x3
Memory Configuration
Enable RH Prevention | VarStore: SaSetup | VarOffset: 0x233 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Row Hammer Solution | VarStore: SaSetup | VarOffset: 0x234 | Size: 0x1
Hardware RHP: 0x0
2x Refresh: 0x1
Memory Configuration
RH Activation Probability | VarStore: SaSetup | VarOffset: 0x235 | Size: 0x1
1/2^1: 0x1
1/2^2: 0x2
1/2^3: 0x3
1/2^4: 0x4
1/2^5: 0x5
1/2^6: 0x6
1/2^7: 0x7
1/2^8: 0x8
1/2^9: 0x9
1/2^10: 0xA
1/2^11: 0xB
1/2^12: 0xC
1/2^13: 0xD
1/2^14: 0xE
1/2^15: 0xF
Memory Configuration
Exit On Failure (MRC) | VarStore: SaSetup | VarOffset: 0x237 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Probeless Trace | VarStore: SaSetup | VarOffset: 0x1B7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Ch Hash Support | VarStore: SaSetup | VarOffset: 0x16E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Ch Hash Mask | VarStore: SaSetup | VarOffset: 0x16F | Size: 0x2
Min: 0x1 | Max: 0x3FFF | Step: 0x1
Memory Configuration
Ch Hash Interleaved Bit | VarStore: SaSetup | VarOffset: 0x171 | Size: 0x1
BIT6: 0x0
BIT7: 0x1
BIT8: 0x2
BIT9: 0x3
BIT10: 0x4
BIT11: 0x5
BIT12: 0x6
BIT13: 0x7
Memory Configuration
Extended Bank Hashing | VarStore: SaSetup | VarOffset: 0x172 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Per Bank Refresh | VarStore: SaSetup | VarOffset: 0x173 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Power Down Mode | VarStore: SaSetup | VarOffset: 0x181 | Size: 0x1
Auto: 0xFF
No Power Down: 0x0
APD: 0x1
PPD-DLLoff: 0x6
Memory Configuration
Pwr Down Idle Timer | VarStore: SaSetup | VarOffset: 0x182 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Configuration
Memory Scrambler | VarStore: SaSetup | VarOffset: 0x22D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Force ColdReset | VarStore: SaSetup | VarOffset: 0x22E | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Configuration
Channel A DIMM Control | VarStore: SaSetup | VarOffset: 0x22F | Size: 0x1
Enable both DIMMs: 0x0
Disable DIMM0: 0x1
Disable DIMM1: 0x2
Disable both DIMMs: 0x3
Memory Configuration
Channel B DIMM Control | VarStore: SaSetup | VarOffset: 0x230 | Size: 0x1
Enable both DIMMs: 0x0
Disable DIMM0: 0x1
Disable DIMM1: 0x2
Disable both DIMMs: 0x3
Memory Configuration
Force Single Rank | VarStore: SaSetup | VarOffset: 0x176 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Memory Remap | VarStore: SaSetup | VarOffset: 0x231 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Configuration
Time Measure | VarStore: SaSetup | VarOffset: 0x16A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Fast Boot | VarStore: SaSetup | VarOffset: 0x16B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Train On Warm boot | VarStore: SaSetup | VarOffset: 0x17E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Rank Margin Tool Per Task | VarStore: SaSetup | VarOffset: 0x16C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Training Tracing | VarStore: SaSetup | VarOffset: 0x16D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Lpddr Mem WL Set | VarStore: SaSetup | VarOffset: 0x177 | Size: 0x1
Set A: 0x0
Set B: 0x1
Memory Configuration
BDAT Memory Test Type | VarStore: SaSetup | VarOffset: 0x17B | Size: 0x1
Rank Margin Tool Rank: 0x0
Rank Margin Tool Bit: 0x1
Margin 2D: 0x2
Memory Configuration
Rank Margin Tool Loop Count | VarStore: SaSetup | VarOffset: 0x17C | Size: 0x1
Min: 0x0 | Max: 0x20 | Step: 0x1
Memory Configuration
Low Supply for LPDDR4 Data | VarStore: SaSetup | VarOffset: 0x17F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Low Supply for LPDDR4 Clock/Command/Control | VarStore: SaSetup | VarOffset: 0x180 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Memory Test on Warm Boot | VarStore: SaSetup | VarOffset: 0x17D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
System Agent (SA) Configuration
Stop Grant Configuration | VarStore: SaSetup | VarOffset: 0x105 | Size: 0x1
Auto: 0x1
Manual: 0x0
System Agent (SA) Configuration
Number of Stop Grant Cycles | VarStore: SaSetup | VarOffset: 0x106 | Size: 0x1
Min: 0x1 | Max: 0x3F | Step: 0x0
System Agent (SA) Configuration
X2APIC Opt Out | VarStore: SaSetup | VarOffset: 0xDA | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
DMA Control Guarantee | VarStore: SaSetup | VarOffset: 0xDB | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
IGD VTD Enable | VarStore: SaSetup | VarOffset: 0xDC | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
IOP VTD Enable | VarStore: SaSetup | VarOffset: 0xDD | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
CHAP Device (B0:D7:F0) | VarStore: SaSetup | VarOffset: 0xD0 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
Thermal Device (B0:D4:F0) | VarStore: SaSetup | VarOffset: 0xD1 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
Cpu CrashLog (Device 10) | VarStore: SaSetup | VarOffset: 0x14C | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
GNA Device (B0:D8:F0) | VarStore: SaSetup | VarOffset: 0xD4 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
CRID Support | VarStore: SaSetup | VarOffset: 0x23B | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
Above 4GB MMIO BIOS assignment | VarStore: SaSetup | VarOffset: 0xD3 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
eDRAM Mode | VarStore: SaSetup | VarOffset: 0xD6 | Size: 0x1
SW Mode eDRAM Off: 0x0
SW Mode eDRAM On: 0x1
eDRAM HW Mode: 0x2
Memory Overclocking Menu
Realtime Memory Timing | VarStore: SaSetup | VarOffset: 0x26D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Overclocking Menu
Memory profile | VarStore: SaSetup | VarOffset: 0x169 | Size: 0x1
Default profile: 0x0
Custom profile: 0x1
XMP profile 1: 0x2
XMP profile 2: 0x3
Memory Overclocking Menu
Realtime Memory OverClock | VarStore: SaSetup | VarOffset: 0x3C0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Overclocking Menu
Memory Reference Clock | VarStore: SaSetup | VarOffset: 0xC | Size: 0x1
133: 0x0
100: 0x1
Memory Overclocking Menu
Memory Ratio | VarStore: SaSetup | VarOffset: 0xE | Size: 0x1
Min: 0x0 | Max: 0x54 | Step: 0x1
Memory Overclocking Menu
QCLK Odd Ratio | VarStore: SaSetup | VarOffset: 0xF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Overclocking Menu
tCL | VarStore: SaSetup | VarOffset: 0x10 | Size: 0x1
Min: 0x0 | Max: 0x24 | Step: 0x1
Memory Overclocking Menu
tRCD/tRP | VarStore: SaSetup | VarOffset: 0x16 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Memory Overclocking Menu
tRAS | VarStore: SaSetup | VarOffset: 0x14 | Size: 0x2
Min: 0x0 | Max: 0x5A | Step: 0x1
Memory Overclocking Menu
tCWL | VarStore: SaSetup | VarOffset: 0x11 | Size: 0x1
Min: 0x0 | Max: 0x23 | Step: 0x1
Memory Overclocking Menu
tFAW | VarStore: SaSetup | VarOffset: 0x12 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Memory Overclocking Menu
tREFI | VarStore: SaSetup | VarOffset: 0x17 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Memory Overclocking Menu
tRFC | VarStore: SaSetup | VarOffset: 0x19 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
Memory Overclocking Menu
tRRD | VarStore: SaSetup | VarOffset: 0x1B | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Memory Overclocking Menu
tRTP | VarStore: SaSetup | VarOffset: 0x1C | Size: 0x1
Min: 0x0 | Max: 0x10 | Step: 0x1
Memory Overclocking Menu
tWR | VarStore: SaSetup | VarOffset: 0x1D | Size: 0x1
Auto: 0x0
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
18: 0x12
20: 0x14
24: 0x18
30: 0x1E
34: 0x22
40: 0x28
Memory Overclocking Menu
tWTR | VarStore: SaSetup | VarOffset: 0x1E | Size: 0x1
Min: 0x0 | Max: 0x1C | Step: 0x1
Memory Overclocking Menu
NMode | VarStore: SaSetup | VarOffset: 0x1F | Size: 0x1
Min: 0x0 | Max: 0x2 | Step: 0x1
Memory Overclocking Menu
Memory Voltage | VarStore: SaSetup | VarOffset: 0x3 | Size: 0x2
Default: 0x0
0.60 Volts: 0x258
1.10 Volts: 0x44C
1.20 Volts: 0x4B0
1.25 Volts: 0x4E2
1.30 Volts: 0x514
1.35 Volts: 0x546
1.40 Volts: 0x578
1.45 Volts: 0x5AA
1.50 Volts: 0x5DC
1.55 Volts: 0x60E
1.60 Volts: 0x640
1.65 Volts: 0x672
Memory Overclocking Menu
DllBwEn[0] | VarStore: SaSetup | VarOffset: 0x7 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Memory Overclocking Menu
DllBwEn[1] | VarStore: SaSetup | VarOffset: 0x8 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Memory Overclocking Menu
DllBwEn[2] | VarStore: SaSetup | VarOffset: 0x9 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Memory Overclocking Menu
DllBwEn[3] | VarStore: SaSetup | VarOffset: 0xA | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Graphics Configuration
Graphics Turbo IMON Current | VarStore: SaSetup | VarOffset: 0x10E | Size: 0x1
Min: 0xE | Max: 0x1F | Step: 0x1
Graphics Configuration
Skip Scaning of External Gfx Card | VarStore: SaSetup | VarOffset: 0x23A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
Primary Display | VarStore: SaSetup | VarOffset: 0x107 | Size: 0x1
Auto: 0x3
IGFX: 0x0
PEG: 0x1
PCI: 0x2
HG: 0x4
Graphics Configuration
Select PCIE Card | VarStore: SaSetup | VarOffset: 0x108 | Size: 0x1
Auto: 0x2
Elk Creek 4: 0x0
PEG Eval: 0x1
Graphics Configuration
HG Delay After Power Enable | VarStore: SaSetup | VarOffset: 0x109 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x0
Graphics Configuration
HG Delay After Hold Reset | VarStore: SaSetup | VarOffset: 0x10B | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x0
Graphics Configuration
Internal Graphics | VarStore: SaSetup | VarOffset: 0x10D | Size: 0x1
Auto: 0x2
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
GTT Size | VarStore: SaSetup | VarOffset: 0x3B | Size: 0x1
2MB: 0x1
4MB: 0x2
8MB: 0x3
Graphics Configuration
PSMI SUPPORT | VarStore: SaSetup | VarOffset: 0x3D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
PSMI Region Size | VarStore: SaSetup | VarOffset: 0x3E | Size: 0x1
32MB: 0x0
288MB: 0x1
544MB: 0x2
800MB: 0x3
1024MB: 0x4
Graphics Configuration
DVMT Total Gfx Mem | VarStore: SaSetup | VarOffset: 0xCF | Size: 0x1
128M: 0x1
256M: 0x2
MAX: 0x3
Graphics Configuration
DFD Restore | VarStore: SaSetup | VarOffset: 0x4A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
Intel Graphics Pei Display Peim | VarStore: SaSetup | VarOffset: 0x42 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
ALS Support | VarStore: SaSetup | VarOffset: 0x38 | Size: 0x1
Enabled: 0x2
Disabled: 0x0
Graphics Configuration
VDD Enable | VarStore: SaSetup | VarOffset: 0x40 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
Configure GT for use | VarStore: SaSetup | VarOffset: 0x41 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
RC1p Support | VarStore: SaSetup | VarOffset: 0x4B | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
PAVP Enable | VarStore: SaSetup | VarOffset: 0x43 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
Cdynmax Clamping Enable | VarStore: SaSetup | VarOffset: 0x45 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
Cd Clock Frequency | VarStore: SaSetup | VarOffset: 0x46 | Size: 0x1
337.5 Mhz: 0x0
450 Mhz: 0x1
540 Mhz: 0x2
675 Mhz: 0x3
192 Mhz: 0x0
312 Mhz: 0x2
324 Mhz: 0x3
552 Mhz: 0x5
648 Mhz: 0x7
307.2 Mhz: 0x1
326.4 Mhz: 0x4
556.8 Mhz: 0x6
652.8 Mhz: 0x8
Max CdClock freq based on Reference Clk: 0xFF
Graphics Configuration
Skip Full CD Clock Init | VarStore: SaSetup | VarOffset: 0x49 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
IUER Button Enable | VarStore: SaSetup | VarOffset: 0x240 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
DMI/OPI Configuration
DMI Max Link Speed | VarStore: SaSetup | VarOffset: 0xDE | Size: 0x1
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
DMI/OPI Configuration
DMI Gen3 Eq Phase 2 | VarStore: SaSetup | VarOffset: 0xE1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
DMI/OPI Configuration
DMI Gen3 Eq Phase 3 Method | VarStore: SaSetup | VarOffset: 0xE2 | Size: 0x1
Auto: 0x0
Adaptive Hardware Equalization: 0x1
Adaptive Software Equalization: 0x2
Static Equalization: 0x3
Disabled: 0x4
DMI/OPI Configuration
Program Static Phase1 Eq | VarStore: SaSetup | VarOffset: 0xE3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
DMI/OPI Configuration
DMI De-emphasis Control | VarStore: SaSetup | VarOffset: 0xE0 | Size: 0x1
-6 dB: 0x0
-3.5 dB: 0x1
DMI/OPI Configuration
DMI Gen3 ASPM | VarStore: SaSetup | VarOffset: 0x102 | Size: 0x1
Disabled: 0x0
Auto: 0x4
ASPM L0s: 0x1
ASPM L1: 0x2
ASPM L0sL1: 0x3
DMI Gen3 ASPM
DMI Gen3 ASPM Control | VarStore: SaSetup | VarOffset: 0x103 | Size: 0x1
Disabled: 0x0
Auto: 0x4
ASPM L0s: 0x1
ASPM L1: 0x2
ASPM L0sL1: 0x3
DMI Gen3 ASPM
DMI Gen3 L1 Exit Latency | VarStore: SaSetup | VarOffset: 0x104 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0xE4 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0xE5 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0xE6 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0xE7 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 4 | VarStore: SaSetup | VarOffset: 0xE8 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 5 | VarStore: SaSetup | VarOffset: 0xE9 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 6 | VarStore: SaSetup | VarOffset: 0xEA | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 7 | VarStore: SaSetup | VarOffset: 0xEB | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0xEC | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0xED | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0xEE | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0xEF | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 4 | VarStore: SaSetup | VarOffset: 0xF0 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 5 | VarStore: SaSetup | VarOffset: 0xF1 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 6 | VarStore: SaSetup | VarOffset: 0xF2 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 7 | VarStore: SaSetup | VarOffset: 0xF3 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0xF4 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0xF5 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0xF6 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0xF7 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 4 | VarStore: SaSetup | VarOffset: 0xF8 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 5 | VarStore: SaSetup | VarOffset: 0xF9 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 6 | VarStore: SaSetup | VarOffset: 0xFA | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 7 | VarStore: SaSetup | VarOffset: 0xFB | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 RxCTLE Control
Bundle0 | VarStore: SaSetup | VarOffset: 0xFC | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle1 | VarStore: SaSetup | VarOffset: 0xFD | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle2 | VarStore: SaSetup | VarOffset: 0xFE | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle3 | VarStore: SaSetup | VarOffset: 0xFF | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
PEG Port Configuration
Enable Root Port | VarStore: SaSetup | VarOffset: 0x5A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Power Down Unused Lanes | VarStore: SaSetup | VarOffset: 0x66 | Size: 0x1
Disabled: 0x0
Auto: 0x1
PEG Port Configuration
ASPM | VarStore: SaSetup | VarOffset: 0x51 | Size: 0x1
Disabled: 0x0
Auto: 0x4
ASPM L0s: 0x1
ASPM L1: 0x2
ASPM L0sL1: 0x3
PEG Port Configuration
OBFF | VarStore: SaSetup | VarOffset: 0x82 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
LTR | VarStore: SaSetup | VarOffset: 0x7E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
PEG0 Hotplug | VarStore: SaSetup | VarOffset: 0x9C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Extra Bus Reserved | VarStore: SaSetup | VarOffset: 0xB9 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PEG Port Configuration
Reseved Memory | VarStore: SaSetup | VarOffset: 0xBD | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PEG Port Configuration
Reserved I/O | VarStore: SaSetup | VarOffset: 0xC5 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PEG Port Configuration
Enable Root Port | VarStore: SaSetup | VarOffset: 0x5B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Power Down Unused Lanes | VarStore: SaSetup | VarOffset: 0x67 | Size: 0x1
Disabled: 0x0
Auto: 0x1
PEG Port Configuration
ASPM | VarStore: SaSetup | VarOffset: 0x52 | Size: 0x1
Disabled: 0x0
Auto: 0x4
ASPM L0s: 0x1
ASPM L1: 0x2
ASPM L0sL1: 0x3
PEG Port Configuration
OBFF | VarStore: SaSetup | VarOffset: 0x83 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
LTR | VarStore: SaSetup | VarOffset: 0x7F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
PEG1 Hotplug | VarStore: SaSetup | VarOffset: 0x9D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Extra Bus Reserved | VarStore: SaSetup | VarOffset: 0xBA | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PEG Port Configuration
Reseved Memory | VarStore: SaSetup | VarOffset: 0xBF | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PEG Port Configuration
Reserved I/O | VarStore: SaSetup | VarOffset: 0xC6 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PEG Port Configuration
Enable Root Port | VarStore: SaSetup | VarOffset: 0x5C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Power Down Unused Lanes | VarStore: SaSetup | VarOffset: 0x68 | Size: 0x1
Disabled: 0x0
Auto: 0x1
PEG Port Configuration
ASPM | VarStore: SaSetup | VarOffset: 0x53 | Size: 0x1
Disabled: 0x0
Auto: 0x4
ASPM L0s: 0x1
ASPM L1: 0x2
ASPM L0sL1: 0x3
PEG Port Configuration
OBFF | VarStore: SaSetup | VarOffset: 0x84 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
LTR | VarStore: SaSetup | VarOffset: 0x80 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
PEG2 Hotplug | VarStore: SaSetup | VarOffset: 0x9E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Extra Bus Reserved | VarStore: SaSetup | VarOffset: 0xBB | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PEG Port Configuration
Reseved Memory | VarStore: SaSetup | VarOffset: 0xC1 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PEG Port Configuration
Reserved I/O | VarStore: SaSetup | VarOffset: 0xC7 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PEG Port Configuration
Enable Root Port | VarStore: SaSetup | VarOffset: 0x5D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Power Down Unused Lanes | VarStore: SaSetup | VarOffset: 0x69 | Size: 0x1
Disabled: 0x0
Auto: 0x1
PEG Port Configuration
ASPM | VarStore: SaSetup | VarOffset: 0x54 | Size: 0x1
Disabled: 0x0
Auto: 0x4
ASPM L0s: 0x1
ASPM L1: 0x2
ASPM L0sL1: 0x3
PEG Port Configuration
OBFF | VarStore: SaSetup | VarOffset: 0x85 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
LTR | VarStore: SaSetup | VarOffset: 0x81 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
PEG2 Hotplug | VarStore: SaSetup | VarOffset: 0x9F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Extra Bus Reserved | VarStore: SaSetup | VarOffset: 0xBC | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PEG Port Configuration
Reseved Memory | VarStore: SaSetup | VarOffset: 0xC3 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PEG Port Configuration
Reserved I/O | VarStore: SaSetup | VarOffset: 0xC8 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PEG Port Configuration
PEG0 Max Payload size | VarStore: SaSetup | VarOffset: 0x7A | Size: 0x1
Auto: 0xFF
128: 0x0
256 TLP: 0x1
PEG Port Configuration
PEG1 Max Payload size | VarStore: SaSetup | VarOffset: 0x7B | Size: 0x1
Auto: 0xFF
128: 0x0
256 TLP: 0x1
PEG Port Configuration
PEG2 Max Payload size | VarStore: SaSetup | VarOffset: 0x7C | Size: 0x1
Auto: 0xFF
128: 0x0
256 TLP: 0x1
PEG Port Configuration
PEG3 Max Payload size | VarStore: SaSetup | VarOffset: 0x7D | Size: 0x1
Auto: 0xFF
128: 0x0
256 TLP: 0x1
PEG Port Configuration
Program PCIe ASPM after OpROM | VarStore: SaSetup | VarOffset: 0x91 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Program Static Phase1 Eq | VarStore: SaSetup | VarOffset: 0x2A1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Gen3 Root Port Preset value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0x2A2 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0x2A3 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0x2A4 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0x2A5 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 4 | VarStore: SaSetup | VarOffset: 0x2A6 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 5 | VarStore: SaSetup | VarOffset: 0x2A7 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 6 | VarStore: SaSetup | VarOffset: 0x2A8 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 7 | VarStore: SaSetup | VarOffset: 0x2A9 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 8 | VarStore: SaSetup | VarOffset: 0x2AA | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 9 | VarStore: SaSetup | VarOffset: 0x2AB | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 10 | VarStore: SaSetup | VarOffset: 0x2AC | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 11 | VarStore: SaSetup | VarOffset: 0x2AD | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 12 | VarStore: SaSetup | VarOffset: 0x2AE | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 13 | VarStore: SaSetup | VarOffset: 0x2AF | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 14 | VarStore: SaSetup | VarOffset: 0x2B0 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 15 | VarStore: SaSetup | VarOffset: 0x2B1 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0x2B2 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0x2B3 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0x2B4 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0x2B5 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 4 | VarStore: SaSetup | VarOffset: 0x2B6 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 5 | VarStore: SaSetup | VarOffset: 0x2B7 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 6 | VarStore: SaSetup | VarOffset: 0x2B8 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 7 | VarStore: SaSetup | VarOffset: 0x2B9 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 8 | VarStore: SaSetup | VarOffset: 0x2BA | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 9 | VarStore: SaSetup | VarOffset: 0x2BB | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 10 | VarStore: SaSetup | VarOffset: 0x2BC | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 11 | VarStore: SaSetup | VarOffset: 0x2BD | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 12 | VarStore: SaSetup | VarOffset: 0x2BE | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 13 | VarStore: SaSetup | VarOffset: 0x2BF | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 14 | VarStore: SaSetup | VarOffset: 0x2C0 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 15 | VarStore: SaSetup | VarOffset: 0x2C1 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0x2C2 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0x2C3 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0x2C4 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0x2C5 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 4 | VarStore: SaSetup | VarOffset: 0x2C6 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 5 | VarStore: SaSetup | VarOffset: 0x2C7 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 6 | VarStore: SaSetup | VarOffset: 0x2C8 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 7 | VarStore: SaSetup | VarOffset: 0x2C9 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 8 | VarStore: SaSetup | VarOffset: 0x2CA | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 9 | VarStore: SaSetup | VarOffset: 0x2CB | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 10 | VarStore: SaSetup | VarOffset: 0x2CC | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 11 | VarStore: SaSetup | VarOffset: 0x2CD | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 12 | VarStore: SaSetup | VarOffset: 0x2CE | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 13 | VarStore: SaSetup | VarOffset: 0x2CF | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 14 | VarStore: SaSetup | VarOffset: 0x2D0 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 15 | VarStore: SaSetup | VarOffset: 0x2D1 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0x2D2 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0x2D3 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0x2D4 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0x2D5 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 4 | VarStore: SaSetup | VarOffset: 0x2D6 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 5 | VarStore: SaSetup | VarOffset: 0x2D7 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 6 | VarStore: SaSetup | VarOffset: 0x2D8 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 7 | VarStore: SaSetup | VarOffset: 0x2D9 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 8 | VarStore: SaSetup | VarOffset: 0x2DA | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 9 | VarStore: SaSetup | VarOffset: 0x2DB | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 10 | VarStore: SaSetup | VarOffset: 0x2DC | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 11 | VarStore: SaSetup | VarOffset: 0x2DD | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 12 | VarStore: SaSetup | VarOffset: 0x2DE | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 13 | VarStore: SaSetup | VarOffset: 0x2DF | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 14 | VarStore: SaSetup | VarOffset: 0x2E0 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 15 | VarStore: SaSetup | VarOffset: 0x2E1 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 16 | VarStore: SaSetup | VarOffset: 0x2E2 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 17 | VarStore: SaSetup | VarOffset: 0x2E3 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 18 | VarStore: SaSetup | VarOffset: 0x2E4 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Root Port Preset value for each Lane
Lane 19 | VarStore: SaSetup | VarOffset: 0x2E5 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0x2E6 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0x2E7 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0x2E8 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0x2E9 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 4 | VarStore: SaSetup | VarOffset: 0x2EA | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 5 | VarStore: SaSetup | VarOffset: 0x2EB | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 6 | VarStore: SaSetup | VarOffset: 0x2EC | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 7 | VarStore: SaSetup | VarOffset: 0x2ED | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 8 | VarStore: SaSetup | VarOffset: 0x2EE | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 9 | VarStore: SaSetup | VarOffset: 0x2EF | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 10 | VarStore: SaSetup | VarOffset: 0x2F0 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 11 | VarStore: SaSetup | VarOffset: 0x2F1 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 12 | VarStore: SaSetup | VarOffset: 0x2F2 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 13 | VarStore: SaSetup | VarOffset: 0x2F3 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 14 | VarStore: SaSetup | VarOffset: 0x2F4 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 15 | VarStore: SaSetup | VarOffset: 0x2F5 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 16 | VarStore: SaSetup | VarOffset: 0x2F6 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 17 | VarStore: SaSetup | VarOffset: 0x2F7 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 18 | VarStore: SaSetup | VarOffset: 0x2F8 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Preset value for each Lane
Lane 19 | VarStore: SaSetup | VarOffset: 0x2F9 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0x2FA | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0x2FB | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0x2FC | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0x2FD | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 4 | VarStore: SaSetup | VarOffset: 0x2FE | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 5 | VarStore: SaSetup | VarOffset: 0x2FF | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 6 | VarStore: SaSetup | VarOffset: 0x300 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 7 | VarStore: SaSetup | VarOffset: 0x301 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 8 | VarStore: SaSetup | VarOffset: 0x302 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 9 | VarStore: SaSetup | VarOffset: 0x303 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 10 | VarStore: SaSetup | VarOffset: 0x304 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 11 | VarStore: SaSetup | VarOffset: 0x305 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 12 | VarStore: SaSetup | VarOffset: 0x306 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 13 | VarStore: SaSetup | VarOffset: 0x307 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 14 | VarStore: SaSetup | VarOffset: 0x308 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 15 | VarStore: SaSetup | VarOffset: 0x309 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 16 | VarStore: SaSetup | VarOffset: 0x30A | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 17 | VarStore: SaSetup | VarOffset: 0x30B | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 18 | VarStore: SaSetup | VarOffset: 0x30C | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen4 Endpoint Hint value for each Lane
Lane 19 | VarStore: SaSetup | VarOffset: 0x30D | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
LCD Control
Primary IGFX Boot Display | VarStore: SaSetup | VarOffset: 0x32 | Size: 0x1
VBIOS Default: 0x0
EFP: 0x4
LFP: 0x8
EFP3: 0x20
EFP2: 0x40
EFP4: 0x10
LCD Control
Secondary IGFX Boot Display | VarStore: SaSetup | VarOffset: 0x33 | Size: 0x1
Disabled: 0x0
EFP: 0x4
EFP3: 0x20
EFP2: 0x40
EFP4: 0x10
LCD Control
LCD Panel Type | VarStore: SaSetup | VarOffset: 0x34 | Size: 0x1
VBIOS Default: 0x0
640x480 LVDS: 0x1
800x600 LVDS: 0x2
1024x768 LVDS: 0x3
1280x1024 LVDS: 0x4
1400x1050 LVDS1: 0x5
1400x1050 LVDS2: 0x6
1600x1200 LVDS: 0x7
1280x768 LVDS: 0x8
1680x1050 LVDS: 0x9
1920x1200 LVDS: 0xA
1600x900 LVDS: 0xD
1280x800 LVDS: 0xE
1280x600 LVDS: 0xF
2048x1536 LVDS: 0x10
1366x768 LVDS: 0x11
LCD Control
Panel Scaling | VarStore: SaSetup | VarOffset: 0x35 | Size: 0x1
Auto: 0x0
Off: 0x1
Force Scaling: 0x6
LCD Control
Backlight Control | VarStore: SaSetup | VarOffset: 0x37 | Size: 0x1
PWM Inverted: 0x0
PWM Normal: 0x2
LCD Control
Active LFP | VarStore: SaSetup | VarOffset: 0x39 | Size: 0x1
No eDP: 0x0
eDP Port-A: 0x3
LCD Control
Panel Color Depth | VarStore: SaSetup | VarOffset: 0x3A | Size: 0x1
18 Bit: 0x0
24 Bit: 0x1
LCD Control
Backlight Brightness | VarStore: SaSetup | VarOffset: 0x44 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Intel(R) Ultrabook Event Support
IUER Slate Enable | VarStore: SaSetup | VarOffset: 0x241 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Ultrabook Event Support
Slate Mode boot value | VarStore: SaSetup | VarOffset: 0x23C | Size: 0x1
Slate Mode: 0x0
Laptop Mode: 0x1
Intel(R) Ultrabook Event Support
Slate Mode on S3 and S4 resume | VarStore: SaSetup | VarOffset: 0x23D | Size: 0x1
No change: 0x0
Toggle: 0x1
Intel(R) Ultrabook Event Support
IUER Dock Enable | VarStore: SaSetup | VarOffset: 0x242 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Ultrabook Event Support
Dock Mode boot value | VarStore: SaSetup | VarOffset: 0x23E | Size: 0x1
Undocked: 0x0
Docked: 0x1
Intel(R) Ultrabook Event Support
Dock Mode upon S3 and S4 resume | VarStore: SaSetup | VarOffset: 0x23F | Size: 0x1
No change: 0x0
Toggle: 0x1
GT - Power Management Control
RC6(Render Standby) | VarStore: SaSetup | VarOffset: 0x36 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT - Power Management Control
Maximum GT frequency | VarStore: SaSetup | VarOffset: 0x47 | Size: 0x1
Default Max Frequency: 0xFF
100Mhz: 0x2
150Mhz: 0x3
200Mhz: 0x4
250Mhz: 0x5
300Mhz: 0x6
350Mhz: 0x7
400Mhz: 0x8
450Mhz: 0x9
500Mhz: 0xA
550Mhz: 0xB
600Mhz: 0xC
650Mhz: 0xD
700Mhz: 0xE
750Mhz: 0xF
800Mhz: 0x10
850Mhz: 0x11
900Mhz: 0x12
950Mhz: 0x13
1000Mhz: 0x14
1050Mhz: 0x15
1100Mhz: 0x16
1150Mhz: 0x17
1200Mhz: 0x18
GT - Power Management Control
Disable Turbo GT frequency | VarStore: SaSetup | VarOffset: 0x48 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Training Algorithms
Early Command Training | VarStore: SaSetup | VarOffset: 0x1BC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
SenseAmp Offset Training | VarStore: SaSetup | VarOffset: 0x1BD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Early ReadMPR Timing Centering 2D | VarStore: SaSetup | VarOffset: 0x1BE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read MPR Training | VarStore: SaSetup | VarOffset: 0x1BF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Receive Enable Training | VarStore: SaSetup | VarOffset: 0x1C0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Jedec Write Leveling | VarStore: SaSetup | VarOffset: 0x1C1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
LPDDR4 Write DQ DQS Retraining | VarStore: SaSetup | VarOffset: 0x1E5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Early Write Time Centering 2D | VarStore: SaSetup | VarOffset: 0x1C2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Early Read Time Centering 2D | VarStore: SaSetup | VarOffset: 0x1C3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Timing Centering 1D | VarStore: SaSetup | VarOffset: 0x1C4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Voltage Centering 1D | VarStore: SaSetup | VarOffset: 0x1C5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read Timing Centering 1D | VarStore: SaSetup | VarOffset: 0x1C6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Dimm ODT Training* | VarStore: SaSetup | VarOffset: 0x1C7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Max RTT_WR | VarStore: SaSetup | VarOffset: 0x236 | Size: 0x1
ODT Off: 0x0
120 Ohms: 0x1
Memory Training Algorithms
DIMM RON Training* | VarStore: SaSetup | VarOffset: 0x1C8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Drive Strength/Equalization 2D* | VarStore: SaSetup | VarOffset: 0x1C9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Slew Rate Training* | VarStore: SaSetup | VarOffset: 0x1CA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read ODT Training* | VarStore: SaSetup | VarOffset: 0x1CB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read Equalization Training* | VarStore: SaSetup | VarOffset: 0x1CC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read Amplifier Training* | VarStore: SaSetup | VarOffset: 0x1CD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Timing Centering 2D | VarStore: SaSetup | VarOffset: 0x1CE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read Timing Centering 2D | VarStore: SaSetup | VarOffset: 0x1CF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Command Voltage Centering | VarStore: SaSetup | VarOffset: 0x1D2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Voltage Centering 2D | VarStore: SaSetup | VarOffset: 0x1D0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read Voltage Centering 2D | VarStore: SaSetup | VarOffset: 0x1D1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Late Command Training | VarStore: SaSetup | VarOffset: 0x1D3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Round Trip Latency | VarStore: SaSetup | VarOffset: 0x1D4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Turn Around Timing Training | VarStore: SaSetup | VarOffset: 0x1D5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Rank Margin Tool | VarStore: SaSetup | VarOffset: 0x1D6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Rank Margin Tool Per Bit | VarStore: SaSetup | VarOffset: 0x1D7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Margin Check Limit | VarStore: SaSetup | VarOffset: 0x1B9 | Size: 0x1
Disabled: 0x0
L1: 0x1
L2: 0x2
Both: 0x3
Memory Training Algorithms
Margin Limit Check L2 | VarStore: SaSetup | VarOffset: 0x1BA | Size: 0x2
Min: 0x1 | Max: 0x12C | Step: 0x1
Memory Training Algorithms
Memory Test | VarStore: SaSetup | VarOffset: 0x1D8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
DIMM SPD Alias Test | VarStore: SaSetup | VarOffset: 0x1D9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Receive Enable Centering 1D | VarStore: SaSetup | VarOffset: 0x1DA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Retrain Margin Check | VarStore: SaSetup | VarOffset: 0x1DB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Drive Strength Up/Dn independently | VarStore: SaSetup | VarOffset: 0x1DC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Command Slew Rate Training | VarStore: SaSetup | VarOffset: 0x1DD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Command Drive Strength and Equalization | VarStore: SaSetup | VarOffset: 0x1DE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Command Normalization | VarStore: SaSetup | VarOffset: 0x1DF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Early DQ Write Drive Strength and Equalization Training | VarStore: SaSetup | VarOffset: 0x1E0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read Voltage Centering 1D | VarStore: SaSetup | VarOffset: 0x1E1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Dimm ODT CA Training | VarStore: SaSetup | VarOffset: 0x1E2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Duty Cycle Correction | VarStore: SaSetup | VarOffset: 0x1E3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
DQ DFE Training | VarStore: SaSetup | VarOffset: 0x1E4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Configuration
Memory Thermal Management | VarStore: SaSetup | VarOffset: 0x228 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Configuration
PECI Injected Temperature | VarStore: SaSetup | VarOffset: 0x229 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Configuration
EXTTS# via TS-on-Board | VarStore: SaSetup | VarOffset: 0x22A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Configuration
EXTTS# via TS-on-DIMM | VarStore: SaSetup | VarOffset: 0x22B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Configuration
Virtual Temperature Sensor (VTS) | VarStore: SaSetup | VarOffset: 0x22C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Power and Thermal Throttling
DDR PowerDown and idle counter | VarStore: SaSetup | VarOffset: 0x1E9 | Size: 0x1
PCODE: 0x0
BIOS: 0x1
Memory Power and Thermal Throttling
For LPDDR Only: DDR PowerDown and idle counter | VarStore: SaSetup | VarOffset: 0x1EA | Size: 0x1
PCODE: 0x0
BIOS: 0x1
Memory Power and Thermal Throttling
REFRESH_2X_MODE | VarStore: SaSetup | VarOffset: 0x1EB | Size: 0x1
Disabled: 0x0
1- Enabled for WARM or HOT: 0x1
2- Enabled HOT only: 0x2
Memory Power and Thermal Throttling
LPDDR Thermal Sensor | VarStore: SaSetup | VarOffset: 0x1EC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Power and Thermal Throttling
SelfRefresh Enable | VarStore: SaSetup | VarOffset: 0x221 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Power and Thermal Throttling
SelfRefresh IdleTimer | VarStore: SaSetup | VarOffset: 0x222 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Memory Power and Thermal Throttling
Throttler CKEMin Defeature | VarStore: SaSetup | VarOffset: 0x224 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Power and Thermal Throttling
Throttler CKEMin Timer | VarStore: SaSetup | VarOffset: 0x225 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Power and Thermal Throttling
For LPDDR Only: Throttler CKEMin Defeature | VarStore: SaSetup | VarOffset: 0x226 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Power and Thermal Throttling
For LPDDR Only: Throttler CKEMin Timer | VarStore: SaSetup | VarOffset: 0x227 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Use user provided power weights, scale factor, and channel power floor values | VarStore: SaSetup | VarOffset: 0x1EE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Dram Power Meter
Energy Scale Factor | VarStore: SaSetup | VarOffset: 0x1EF | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Dram Power Meter
Idle Energy Ch0Dimm0 | VarStore: SaSetup | VarOffset: 0x20E | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
PowerDown Energy Ch0Dimm0 | VarStore: SaSetup | VarOffset: 0x210 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
Activate Energy Ch0Dimm0 | VarStore: SaSetup | VarOffset: 0x212 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Read Energy Ch0Dimm0 | VarStore: SaSetup | VarOffset: 0x214 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Write Energy Ch0Dimm0 | VarStore: SaSetup | VarOffset: 0x216 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Idle Energy Ch0Dimm1 | VarStore: SaSetup | VarOffset: 0x20D | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
PowerDown Energy Ch0Dimm1 | VarStore: SaSetup | VarOffset: 0x20F | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
Activate Energy Ch0Dimm1 | VarStore: SaSetup | VarOffset: 0x211 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Read Energy Ch0Dimm1 | VarStore: SaSetup | VarOffset: 0x213 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Write Energy Ch0Dimm1 | VarStore: SaSetup | VarOffset: 0x215 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Idle Energy Ch1Dimm0 | VarStore: SaSetup | VarOffset: 0x218 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
PowerDown Energy Ch1Dimm0 | VarStore: SaSetup | VarOffset: 0x21A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
Activate Energy Ch1Dimm0 | VarStore: SaSetup | VarOffset: 0x21C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Read Energy Ch1Dimm0 | VarStore: SaSetup | VarOffset: 0x21E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Write Energy Ch1Dimm0 | VarStore: SaSetup | VarOffset: 0x220 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Idle Energy Ch1Dimm1 | VarStore: SaSetup | VarOffset: 0x217 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
PowerDown Energy Ch1Dimm1 | VarStore: SaSetup | VarOffset: 0x219 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
Activate Energy Ch1Dimm1 | VarStore: SaSetup | VarOffset: 0x21B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Read Energy Ch1Dimm1 | VarStore: SaSetup | VarOffset: 0x21D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Write Energy Ch1Dimm1 | VarStore: SaSetup | VarOffset: 0x21F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Lock Thermal Management Registers | VarStore: SaSetup | VarOffset: 0x1ED | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Reporting
Extern Therm Status | VarStore: SaSetup | VarOffset: 0x1E6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Reporting
Warm Threshold Ch0 Dimm0 | VarStore: SaSetup | VarOffset: 0x1FD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Threshold Ch0 Dimm1 | VarStore: SaSetup | VarOffset: 0x1FE | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Threshold Ch0 Dimm0 | VarStore: SaSetup | VarOffset: 0x201 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Threshold Ch0 Dimm1 | VarStore: SaSetup | VarOffset: 0x202 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Threshold Ch1 Dimm0 | VarStore: SaSetup | VarOffset: 0x1FF | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Threshold Ch1 Dimm1 | VarStore: SaSetup | VarOffset: 0x200 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Threshold Ch1 Dimm0 | VarStore: SaSetup | VarOffset: 0x203 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Threshold Ch1 Dimm1 | VarStore: SaSetup | VarOffset: 0x204 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Budget Ch0 Dimm0 | VarStore: SaSetup | VarOffset: 0x205 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Budget Ch0 Dimm1 | VarStore: SaSetup | VarOffset: 0x206 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Budget Ch0 Dimm0 | VarStore: SaSetup | VarOffset: 0x209 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Budget Ch0 Dimm1 | VarStore: SaSetup | VarOffset: 0x20A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Budget Ch1 Dimm0 | VarStore: SaSetup | VarOffset: 0x207 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Budget Ch1 Dimm1 | VarStore: SaSetup | VarOffset: 0x208 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Budget Ch1 Dimm0 | VarStore: SaSetup | VarOffset: 0x20B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Budget Ch1 Dimm1 | VarStore: SaSetup | VarOffset: 0x20C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory RAPL
Rapl Power Floor Ch0 | VarStore: SaSetup | VarOffset: 0x1F1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory RAPL
Rapl Power Floor Ch1 | VarStore: SaSetup | VarOffset: 0x1F0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory RAPL
RAPL PL Lock | VarStore: SaSetup | VarOffset: 0x1F2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory RAPL
RAPL PL 1 enable | VarStore: SaSetup | VarOffset: 0x1FA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory RAPL
RAPL PL 1 Power | VarStore: SaSetup | VarOffset: 0x1FB | Size: 0x2
Min: 0x0 | Max: 0x3FFF | Step: 0x1
Memory RAPL
RAPL PL 1 WindowX | VarStore: SaSetup | VarOffset: 0x1F8 | Size: 0x1
Min: 0x0 | Max: 0x3 | Step: 0x1
Memory RAPL
RAPL PL 1 WindowY | VarStore: SaSetup | VarOffset: 0x1F9 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Memory RAPL
RAPL PL 2 enable | VarStore: SaSetup | VarOffset: 0x1F5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory RAPL
RAPL PL 2 Power | VarStore: SaSetup | VarOffset: 0x1F6 | Size: 0x2
Min: 0x0 | Max: 0x3FFF | Step: 0x1
Memory RAPL
RAPL PL 2 WindowX | VarStore: SaSetup | VarOffset: 0x1F3 | Size: 0x1
Min: 0x0 | Max: 0x3 | Step: 0x1
Memory RAPL
RAPL PL 2 WindowY | VarStore: SaSetup | VarOffset: 0x1F4 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
MIPI Camera Configuration
Control Logic 1 | VarStore: Setup | VarOffset: 0x88 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Control Logic 2 | VarStore: Setup | VarOffset: 0x89 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Control Logic 3 | VarStore: Setup | VarOffset: 0x8A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Control Logic 4 | VarStore: Setup | VarOffset: 0x8B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Control Logic 5 | VarStore: Setup | VarOffset: 0x8C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Control Logic 6 | VarStore: Setup | VarOffset: 0x8D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Camera1 | VarStore: Setup | VarOffset: 0x8E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Camera2 | VarStore: Setup | VarOffset: 0x8F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Camera3 | VarStore: Setup | VarOffset: 0x90 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Camera4 | VarStore: Setup | VarOffset: 0x91 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Camera5 | VarStore: Setup | VarOffset: 0x92 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Camera6 | VarStore: Setup | VarOffset: 0x93 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Link options
Sensor Model | VarStore: Setup | VarOffset: 0x181 | Size: 0x1
IMX135: 0x0
OV5693: 0x1
IMX179: 0x2
OV8858: 0x3
OV2740-IVCAM: 0x4
OV9728: 0x5
IMX188: 0x6
IMX208: 0x7
OV5670: 0x8
OV8865: 0x9
HM2051: 0xA
OV2742: 0xB
OV9234: 0xC
OV8856: 0xD
OV16860: 0xE
IMX362: 0xF
IMX488: 0x10
User Custom: 0xFF
Link options
Custom HID
Link options
Lanes Clock division | VarStore: Setup | VarOffset: 0x96 | Size: 0x1
4 4 2 2: 0x0
4 4 3 1: 0x2
4 4 4 0: 0x3
8 0 2 2: 0x4
8 0 3 1: 0x6
8 0 4 0: 0x7
Link options
CRD Version | VarStore: Setup | VarOffset: 0x1DC | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Link options
GPIO control | VarStore: Setup | VarOffset: 0x1E9 | Size: 0x1
No Control Logic: 0xFF
Control Logic 1: 0x0
Control Logic 2: 0x1
Control Logic 3: 0x2
Control Logic 4: 0x3
Control Logic 5: 0x3
Control Logic 6: 0x3
Link options
Camera position | VarStore: Setup | VarOffset: 0x194 | Size: 0x1
Front: 0x61
Back: 0x69
Link options
Flash Support | VarStore: Setup | VarOffset: 0x1EA | Size: 0x1
Driver default: 0x0
Disabled: 0x2
Enabled: 0x3
Link options
Privacy LED | VarStore: Setup | VarOffset: 0x1EB | Size: 0x1
Driver default: 0x0
ILEDA, 16mA: 0x1
ILEDB, 2mA: 0x2
ILEDB, 4mA: 0x3
ILEDB, 8mA: 0x4
ILEDB, 16mA: 0x5
Link options
Rotation | VarStore: Setup | VarOffset: 0x1EC | Size: 0x1
0: 0x0
90: 0x2
180: 0x4
270: 0x6
Link options
PMIC Position | VarStore: Setup | VarOffset: 0x1ED | Size: 0x1
Position 1: 0x0
Position 2: 0x1
Link options
Voltage Rail | VarStore: Setup | VarOffset: 0x1EE | Size: 0x1
3 voltage rail: 0x0
2 voltage rail: 0x1
Link options
PPR Value | VarStore: Setup | VarOffset: 0x1EF | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Link options
PPR Unit | VarStore: Setup | VarOffset: 0x1F0 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Link options
Camera module name
Link options
MIPI port | VarStore: Setup | VarOffset: 0x1DD | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
Link options
LaneUsed | VarStore: Setup | VarOffset: 0x1DE | Size: 0x1
x1: 0x1
x2: 0x2
x3: 0x3
x4: 0x4
x8: 0x8
Link options
MCLK | VarStore: Setup | VarOffset: 0x1E5 | Size: 0x4
Min: 0x5B8D80 | Max: 0x19BFCC0 | Step: 0x186A0
Link options
EEPROM Type | VarStore: Setup | VarOffset: 0x1DF | Size: 0x1
ROM_NONE: 0x0
ROM_OTP: 0x1
ROM_EEPROM_16K_64: 0x2
ROM_EEPROM_16K_16: 0x3
ROM_OTP_ACPI_ACPI: 0x4
ROM_ACPI: 0x5
ROM_EEPROM_BRCA016GWZ: 0x6
ROM_EEPROM_24AA32: 0x7
ROM_EEPROM_CAT24C08: 0x8
ROM_EEPROM_M24C64: 0x9
ROM_EEPROM_DW9806B: 0xA
ROM_EEPROM_CAT24C16: 0x10
ROM_EEPROM_CAT24C64: 0x11
ROM_EEPROM_24AA16: 0x12
Link options
VCM Type | VarStore: Setup | VarOffset: 0x1E0 | Size: 0x1
VCM_NONE: 0x0
VCM_AD5823: 0x1
VCM_DW9714: 0x2
VCM_AD5816: 0x3
VCM_DW9719: 0x4
VCM_DW9718: 0x5
VCM_DW9806B: 0x6
VCM_WV517S: 0x7
VCM_LC898122XA: 0x8
VCM_LC898212AXB: 0x9
VCM_RESERVED1: 0xA
VCM_RESERVED2: 0xB
VCM_AK7371: 0xF
VCM_BU64297GWZ: 0x10
Link options
Number of I2C Components | VarStore: Setup | VarOffset: 0x1B5 | Size: 0x1
Min: 0x0 | Max: 0xC | Step: 0x1
Link options
I2C Channel | VarStore: Setup | VarOffset: 0x1B6 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1B7 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1CF | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1B9 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D0 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1BB | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D1 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1BD | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D2 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1BF | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D3 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1C1 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D4 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1C3 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D5 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1C5 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D6 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1C7 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D7 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1C9 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D8 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1CB | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D9 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1CD | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1DA | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
Flash Driver Selection | VarStore: Setup | VarOffset: 0x1F1 | Size: 0x1
Disabled: 0x0
External: 0x1
Internal PMIC: 0x2
Link options
Sensor Model | VarStore: Setup | VarOffset: 0x1F2 | Size: 0x1
IMX135: 0x0
OV5693: 0x1
IMX179: 0x2
OV8858: 0x3
OV2740-IVCAM: 0x4
OV9728: 0x5
IMX188: 0x6
IMX208: 0x7
OV5670: 0x8
OV8865: 0x9
HM2051: 0xA
OV2742: 0xB
OV9234: 0xC
OV8856: 0xD
OV16860: 0xE
IMX362: 0xF
IMX488: 0x10
User Custom: 0xFF
Link options
Custom HID
Link options
Lanes Clock division | VarStore: Setup | VarOffset: 0x96 | Size: 0x1
4 4 2 2: 0x0
4 4 3 1: 0x2
4 4 4 0: 0x3
8 0 2 2: 0x4
8 0 3 1: 0x6
8 0 4 0: 0x7
Link options
CRD Version | VarStore: Setup | VarOffset: 0x24E | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Link options
GPIO control | VarStore: Setup | VarOffset: 0x25A | Size: 0x1
No Control Logic: 0xFF
Control Logic 1: 0x0
Control Logic 2: 0x1
Control Logic 3: 0x2
Control Logic 4: 0x3
Control Logic 5: 0x3
Control Logic 6: 0x3
Link options
Camera position | VarStore: Setup | VarOffset: 0x205 | Size: 0x1
Front: 0x61
Back: 0x69
Link options
Flash Support | VarStore: Setup | VarOffset: 0x25B | Size: 0x1
Driver default: 0x0
Disabled: 0x2
Enabled: 0x3
Link options
Privacy LED | VarStore: Setup | VarOffset: 0x25C | Size: 0x1
Driver default: 0x0
ILEDA, 16mA: 0x1
ILEDB, 2mA: 0x2
ILEDB, 4mA: 0x3
ILEDB, 8mA: 0x4
ILEDB, 16mA: 0x5
Link options
Rotation | VarStore: Setup | VarOffset: 0x25D | Size: 0x1
0: 0x0
90: 0x2
180: 0x4
270: 0x6
Link options
PMIC Position | VarStore: Setup | VarOffset: 0x25E | Size: 0x1
Position 1: 0x0
Position 2: 0x1
Link options
Voltage Rail | VarStore: Setup | VarOffset: 0x25F | Size: 0x1
3 voltage rail: 0x0
2 voltage rail: 0x1
Link options
PPR Value | VarStore: Setup | VarOffset: 0x260 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Link options
PPR Unit | VarStore: Setup | VarOffset: 0x261 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Link options
Camera module name
Link options
MIPI port | VarStore: Setup | VarOffset: 0x24D | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
Link options
LaneUsed | VarStore: Setup | VarOffset: 0x24F | Size: 0x1
x1: 0x1
x2: 0x2
x3: 0x3
x4: 0x4
Link options
MCLK | VarStore: Setup | VarOffset: 0x256 | Size: 0x4
Min: 0x5B8D80 | Max: 0x19BFCC0 | Step: 0x186A0
Link options
EEPROM Type | VarStore: Setup | VarOffset: 0x250 | Size: 0x1
ROM_NONE: 0x0
ROM_OTP: 0x1
ROM_EEPROM_16K_64: 0x2
ROM_EEPROM_16K_16: 0x3
ROM_OTP_ACPI_ACPI: 0x4
ROM_ACPI: 0x5
ROM_EEPROM_BRCA016GWZ: 0x6
ROM_EEPROM_24AA32: 0x7
ROM_EEPROM_CAT24C08: 0x8
ROM_EEPROM_M24C64: 0x9
ROM_EEPROM_DW9806B: 0xA
ROM_EEPROM_CAT24C16: 0x10
ROM_EEPROM_CAT24C64: 0x11
ROM_EEPROM_24AA16: 0x12
Link options
VCM Type | VarStore: Setup | VarOffset: 0x251 | Size: 0x1
VCM_NONE: 0x0
VCM_AD5823: 0x1
VCM_DW9714: 0x2
VCM_AD5816: 0x3
VCM_DW9719: 0x4
VCM_DW9718: 0x5
VCM_DW9806B: 0x6
VCM_WV517S: 0x7
VCM_LC898122XA: 0x8
VCM_LC898212AXB: 0x9
VCM_RESERVED1: 0xA
VCM_RESERVED2: 0xB
VCM_AK7371: 0xF
VCM_BU64297GWZ: 0x10
Link options
Number of I2C Components | VarStore: Setup | VarOffset: 0x226 | Size: 0x1
Min: 0x0 | Max: 0xC | Step: 0x1
Link options
I2C Channel | VarStore: Setup | VarOffset: 0x227 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Link options
I2C Address | VarStore: Setup | VarOffset: 0x228 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x240 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x22A | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x241 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x22C | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x242 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x22E | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x243 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x230 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x244 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x232 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x245 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x234 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x246 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x236 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x247 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x238 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x248 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x23A | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x249 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x23C | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x24A | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x23E | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x24B | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
Flash Driver Selection | VarStore: Setup | VarOffset: 0x262 | Size: 0x1
Disabled: 0x0
External: 0x1
Internal PMIC: 0x2
Link options
Sensor Model | VarStore: Setup | VarOffset: 0x263 | Size: 0x1
IMX135: 0x0
OV5693: 0x1
IMX179: 0x2
OV8858: 0x3
OV2740-IVCAM: 0x4
OV9728: 0x5
IMX188: 0x6
IMX208: 0x7
OV5670: 0x8
OV8865: 0x9
HM2051: 0xA
OV2742: 0xB
OV9234: 0xC
OV8856: 0xD
OV16860: 0xE
IMX362: 0xF
IMX488: 0x10
User Custom: 0xFF
Link options
Custom HID
Link options
Lanes Clock division | VarStore: Setup | VarOffset: 0x96 | Size: 0x1
4 4 2 2: 0x0
4 4 3 1: 0x2
4 4 4 0: 0x3
8 0 2 2: 0x4
8 0 3 1: 0x6
8 0 4 0: 0x7
Link options
CRD Version | VarStore: Setup | VarOffset: 0x2BE | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Link options
GPIO control | VarStore: Setup | VarOffset: 0x2CB | Size: 0x1
No Control Logic: 0xFF
Control Logic 1: 0x0
Control Logic 2: 0x1
Control Logic 3: 0x2
Control Logic 4: 0x3
Control Logic 5: 0x3
Control Logic 6: 0x3
Link options
Camera position | VarStore: Setup | VarOffset: 0x276 | Size: 0x1
Front: 0x61
Back: 0x69
Link options
Flash Support | VarStore: Setup | VarOffset: 0x2CC | Size: 0x1
Driver default: 0x0
Disabled: 0x2
Enabled: 0x3
Link options
Privacy LED | VarStore: Setup | VarOffset: 0x2CD | Size: 0x1
Driver default: 0x0
ILEDA, 16mA: 0x1
ILEDB, 2mA: 0x2
ILEDB, 4mA: 0x3
ILEDB, 8mA: 0x4
ILEDB, 16mA: 0x5
Link options
Rotation | VarStore: Setup | VarOffset: 0x2CE | Size: 0x1
0: 0x0
90: 0x2
180: 0x4
270: 0x6
Link options
PMIC Position | VarStore: Setup | VarOffset: 0x2CF | Size: 0x1
Position 1: 0x0
Position 2: 0x1
Link options
Voltage Rail | VarStore: Setup | VarOffset: 0x2D0 | Size: 0x1
3 voltage rail: 0x0
2 voltage rail: 0x1
Link options
PPR Value | VarStore: Setup | VarOffset: 0x2D1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Link options
PPR Unit | VarStore: Setup | VarOffset: 0x2D2 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Link options
Camera module name
Link options
MIPI port | VarStore: Setup | VarOffset: 0x2BF | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
Link options
LaneUsed | VarStore: Setup | VarOffset: 0x2C0 | Size: 0x1
x1: 0x1
x2: 0x2
x3: 0x3
x4: 0x4
Link options
MCLK | VarStore: Setup | VarOffset: 0x2C7 | Size: 0x4
Min: 0x5B8D80 | Max: 0x19BFCC0 | Step: 0x186A0
Link options
EEPROM Type | VarStore: Setup | VarOffset: 0x2C1 | Size: 0x1
ROM_NONE: 0x0
ROM_OTP: 0x1
ROM_EEPROM_16K_64: 0x2
ROM_EEPROM_16K_16: 0x3
ROM_OTP_ACPI_ACPI: 0x4
ROM_ACPI: 0x5
ROM_EEPROM_BRCA016GWZ: 0x6
ROM_EEPROM_24AA32: 0x7
ROM_EEPROM_CAT24C08: 0x8
ROM_EEPROM_M24C64: 0x9
ROM_EEPROM_DW9806B: 0xA
ROM_EEPROM_CAT24C16: 0x10
ROM_EEPROM_CAT24C64: 0x11
ROM_EEPROM_24AA16: 0x12
Link options
VCM Type | VarStore: Setup | VarOffset: 0x2C2 | Size: 0x1
VCM_NONE: 0x0
VCM_AD5823: 0x1
VCM_DW9714: 0x2
VCM_AD5816: 0x3
VCM_DW9719: 0x4
VCM_DW9718: 0x5
VCM_DW9806B: 0x6
VCM_WV517S: 0x7
VCM_LC898122XA: 0x8
VCM_LC898212AXB: 0x9
VCM_RESERVED1: 0xA
VCM_RESERVED2: 0xB
VCM_AK7371: 0xF
VCM_BU64297GWZ: 0x10
Link options
Number of I2C Components | VarStore: Setup | VarOffset: 0x297 | Size: 0x1
Min: 0x0 | Max: 0xC | Step: 0x1
Link options
I2C Channel | VarStore: Setup | VarOffset: 0x298 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Link options
I2C Address | VarStore: Setup | VarOffset: 0x299 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2B1 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x29B | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2B2 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x29D | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2B3 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x29F | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2B4 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x2A1 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2B5 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x2A3 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2B6 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x2A5 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2B7 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x2A7 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2B8 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x2A9 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2B9 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x2AB | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2BA | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x2AD | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2BB | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x2AF | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2BC | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
Flash Driver Selection | VarStore: Setup | VarOffset: 0x2D3 | Size: 0x1
Disabled: 0x0
External: 0x1
Internal PMIC: 0x2
Link options
Sensor Model | VarStore: Setup | VarOffset: 0x2D4 | Size: 0x1
IMX135: 0x0
OV5693: 0x1
IMX179: 0x2
OV8858: 0x3
OV2740-IVCAM: 0x4
OV9728: 0x5
IMX188: 0x6
IMX208: 0x7
OV5670: 0x8
OV8865: 0x9
HM2051: 0xA
OV2742: 0xB
OV9234: 0xC
OV8856: 0xD
OV16860: 0xE
IMX362: 0xF
IMX488: 0x10
User Custom: 0xFF
Link options
Custom HID
Link options
Lanes Clock division | VarStore: Setup | VarOffset: 0x96 | Size: 0x1
4 4 2 2: 0x0
4 4 3 1: 0x2
4 4 4 0: 0x3
8 0 2 2: 0x4
8 0 3 1: 0x6
8 0 4 0: 0x7
Link options
CRD Version | VarStore: Setup | VarOffset: 0x32F | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Link options
GPIO control | VarStore: Setup | VarOffset: 0x33C | Size: 0x1
No Control Logic: 0xFF
Control Logic 1: 0x0
Control Logic 2: 0x1
Control Logic 3: 0x2
Control Logic 4: 0x3
Control Logic 5: 0x3
Control Logic 6: 0x3
Link options
Camera position | VarStore: Setup | VarOffset: 0x2E7 | Size: 0x1
Front: 0x61
Back: 0x69
Link options
Flash Support | VarStore: Setup | VarOffset: 0x33D | Size: 0x1
Driver default: 0x0
Disabled: 0x2
Enabled: 0x3
Link options
Privacy LED | VarStore: Setup | VarOffset: 0x33E | Size: 0x1
Driver default: 0x0
ILEDA, 16mA: 0x1
ILEDB, 2mA: 0x2
ILEDB, 4mA: 0x3
ILEDB, 8mA: 0x4
ILEDB, 16mA: 0x5
Link options
Rotation | VarStore: Setup | VarOffset: 0x33F | Size: 0x1
0: 0x0
90: 0x2
180: 0x4
270: 0x6
Link options
PMIC Position | VarStore: Setup | VarOffset: 0x340 | Size: 0x1
Position 1: 0x0
Position 2: 0x1
Link options
Voltage Rail | VarStore: Setup | VarOffset: 0x341 | Size: 0x1
3 voltage rail: 0x0
2 voltage rail: 0x1
Link options
PPR Value | VarStore: Setup | VarOffset: 0x342 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Link options
PPR Unit | VarStore: Setup | VarOffset: 0x343 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Link options
Camera module name
Link options
MIPI port | VarStore: Setup | VarOffset: 0x330 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
Link options
LaneUsed | VarStore: Setup | VarOffset: 0x331 | Size: 0x1
x1: 0x1
x2: 0x2
x3: 0x3
x4: 0x4
Link options
MCLK | VarStore: Setup | VarOffset: 0x338 | Size: 0x4
Min: 0x5B8D80 | Max: 0x19BFCC0 | Step: 0x186A0
Link options
EEPROM Type | VarStore: Setup | VarOffset: 0x332 | Size: 0x1
ROM_NONE: 0x0
ROM_OTP: 0x1
ROM_EEPROM_16K_64: 0x2
ROM_EEPROM_16K_16: 0x3
ROM_OTP_ACPI_ACPI: 0x4
ROM_ACPI: 0x5
ROM_EEPROM_BRCA016GWZ: 0x6
ROM_EEPROM_24AA32: 0x7
ROM_EEPROM_CAT24C08: 0x8
ROM_EEPROM_M24C64: 0x9
ROM_EEPROM_DW9806B: 0xA
ROM_EEPROM_CAT24C16: 0x10
ROM_EEPROM_CAT24C64: 0x11
ROM_EEPROM_24AA16: 0x12
Link options
VCM Type | VarStore: Setup | VarOffset: 0x333 | Size: 0x1
VCM_NONE: 0x0
VCM_AD5823: 0x1
VCM_DW9714: 0x2
VCM_AD5816: 0x3
VCM_DW9719: 0x4
VCM_DW9718: 0x5
VCM_DW9806B: 0x6
VCM_WV517S: 0x7
VCM_LC898122XA: 0x8
VCM_LC898212AXB: 0x9
VCM_RESERVED1: 0xA
VCM_RESERVED2: 0xB
VCM_AK7371: 0xF
VCM_BU64297GWZ: 0x10
Link options
Number of I2C Components | VarStore: Setup | VarOffset: 0x308 | Size: 0x1
Min: 0x0 | Max: 0xC | Step: 0x1
Link options
I2C Channel | VarStore: Setup | VarOffset: 0x309 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Link options
I2C Address | VarStore: Setup | VarOffset: 0x30A | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x322 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x30C | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x323 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x30E | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x324 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x310 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x325 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x312 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x326 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x314 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x327 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x316 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x328 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x318 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x329 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x31A | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x32A | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x31C | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x32B | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x31E | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x32C | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x320 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x32D | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
Flash Driver Selection | VarStore: Setup | VarOffset: 0x344 | Size: 0x1
Disabled: 0x0
External: 0x1
Internal PMIC: 0x2
Link options
Sensor Model | VarStore: Setup | VarOffset: 0x345 | Size: 0x1
IMX135: 0x0
OV5693: 0x1
IMX179: 0x2
OV8858: 0x3
OV2740-IVCAM: 0x4
OV9728: 0x5
IMX188: 0x6
IMX208: 0x7
OV5670: 0x8
OV8865: 0x9
HM2051: 0xA
OV2742: 0xB
OV9234: 0xC
OV8856: 0xD
OV16860: 0xE
IMX362: 0xF
IMX488: 0x10
User Custom: 0xFF
Link options
Custom HID
Link options
Lanes Clock division | VarStore: Setup | VarOffset: 0x96 | Size: 0x1
4 4 2 2: 0x0
4 4 3 1: 0x2
4 4 4 0: 0x3
8 0 2 2: 0x4
8 0 3 1: 0x6
8 0 4 0: 0x7
Link options
CRD Version | VarStore: Setup | VarOffset: 0x3A0 | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Link options
GPIO control | VarStore: Setup | VarOffset: 0x3AD | Size: 0x1
No Control Logic: 0xFF
Control Logic 1: 0x0
Control Logic 2: 0x1
Control Logic 3: 0x2
Control Logic 4: 0x3
Control Logic 5: 0x3
Control Logic 6: 0x3
Link options
Camera position | VarStore: Setup | VarOffset: 0x358 | Size: 0x1
Front: 0x61
Back: 0x69
Link options
Flash Support | VarStore: Setup | VarOffset: 0x3AE | Size: 0x1
Driver default: 0x0
Disabled: 0x2
Enabled: 0x3
Link options
Privacy LED | VarStore: Setup | VarOffset: 0x3AF | Size: 0x1
Driver default: 0x0
ILEDA, 16mA: 0x1
ILEDB, 2mA: 0x2
ILEDB, 4mA: 0x3
ILEDB, 8mA: 0x4
ILEDB, 16mA: 0x5
Link options
Rotation | VarStore: Setup | VarOffset: 0x3B0 | Size: 0x1
0: 0x0
90: 0x2
180: 0x4
270: 0x6
Link options
PMIC Position | VarStore: Setup | VarOffset: 0x3B1 | Size: 0x1
Position 1: 0x0
Position 2: 0x1
Link options
Voltage Rail | VarStore: Setup | VarOffset: 0x3B2 | Size: 0x1
3 voltage rail: 0x0
2 voltage rail: 0x1
Link options
PPR Value | VarStore: Setup | VarOffset: 0x3B3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Link options
PPR Unit | VarStore: Setup | VarOffset: 0x3B4 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Link options
Camera module name
Link options
MIPI port | VarStore: Setup | VarOffset: 0x3A1 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
Link options
LaneUsed | VarStore: Setup | VarOffset: 0x3A2 | Size: 0x1
x1: 0x1
x2: 0x2
x3: 0x3
x4: 0x4
Link options
MCLK | VarStore: Setup | VarOffset: 0x3A9 | Size: 0x4
Min: 0x5B8D80 | Max: 0x19BFCC0 | Step: 0x186A0
Link options
EEPROM Type | VarStore: Setup | VarOffset: 0x3A3 | Size: 0x1
ROM_NONE: 0x0
ROM_OTP: 0x1
ROM_EEPROM_16K_64: 0x2
ROM_EEPROM_16K_16: 0x3
ROM_OTP_ACPI_ACPI: 0x4
ROM_ACPI: 0x5
ROM_EEPROM_BRCA016GWZ: 0x6
ROM_EEPROM_24AA32: 0x7
ROM_EEPROM_CAT24C08: 0x8
ROM_EEPROM_M24C64: 0x9
ROM_EEPROM_DW9806B: 0xA
ROM_EEPROM_CAT24C16: 0x10
ROM_EEPROM_CAT24C64: 0x11
ROM_EEPROM_24AA16: 0x12
Link options
VCM Type | VarStore: Setup | VarOffset: 0x3A4 | Size: 0x1
VCM_NONE: 0x0
VCM_AD5823: 0x1
VCM_DW9714: 0x2
VCM_AD5816: 0x3
VCM_DW9719: 0x4
VCM_DW9718: 0x5
VCM_DW9806B: 0x6
VCM_WV517S: 0x7
VCM_LC898122XA: 0x8
VCM_LC898212AXB: 0x9
VCM_RESERVED1: 0xA
VCM_RESERVED2: 0xB
VCM_AK7371: 0xF
VCM_BU64297GWZ: 0x10
Link options
Number of I2C Components | VarStore: Setup | VarOffset: 0x379 | Size: 0x1
Min: 0x0 | Max: 0xC | Step: 0x1
Link options
I2C Channel | VarStore: Setup | VarOffset: 0x37A | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Link options
I2C Address | VarStore: Setup | VarOffset: 0x37B | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x393 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x37D | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x394 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x37F | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x395 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x381 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x396 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x383 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x397 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x385 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x398 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x387 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x399 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x389 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x39A | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x38B | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x39B | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x38D | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x39C | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x38F | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x39D | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x391 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x39E | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
Flash Driver Selection | VarStore: Setup | VarOffset: 0x3B5 | Size: 0x1
Disabled: 0x0
External: 0x1
Internal PMIC: 0x2
Link options
Sensor Model | VarStore: Setup | VarOffset: 0x3B6 | Size: 0x1
IMX135: 0x0
OV5693: 0x1
IMX179: 0x2
OV8858: 0x3
OV2740-IVCAM: 0x4
OV9728: 0x5
IMX188: 0x6
IMX208: 0x7
OV5670: 0x8
OV8865: 0x9
HM2051: 0xA
OV2742: 0xB
OV9234: 0xC
OV8856: 0xD
OV16860: 0xE
IMX362: 0xF
IMX488: 0x10
User Custom: 0xFF
Link options
Custom HID
Link options
Lanes Clock division | VarStore: Setup | VarOffset: 0x96 | Size: 0x1
4 4 2 2: 0x0
4 4 3 1: 0x2
4 4 4 0: 0x3
8 0 2 2: 0x4
8 0 3 1: 0x6
8 0 4 0: 0x7
Link options
CRD Version | VarStore: Setup | VarOffset: 0x411 | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Link options
GPIO control | VarStore: Setup | VarOffset: 0x41E | Size: 0x1
No Control Logic: 0xFF
Control Logic 1: 0x0
Control Logic 2: 0x1
Control Logic 3: 0x2
Control Logic 4: 0x3
Control Logic 5: 0x3
Control Logic 6: 0x3
Link options
Camera position | VarStore: Setup | VarOffset: 0x3C9 | Size: 0x1
Front: 0x61
Back: 0x69
Link options
Flash Support | VarStore: Setup | VarOffset: 0x41F | Size: 0x1
Driver default: 0x0
Disabled: 0x2
Enabled: 0x3
Link options
Privacy LED | VarStore: Setup | VarOffset: 0x420 | Size: 0x1
Driver default: 0x0
ILEDA, 16mA: 0x1
ILEDB, 2mA: 0x2
ILEDB, 4mA: 0x3
ILEDB, 8mA: 0x4
ILEDB, 16mA: 0x5
Link options
Rotation | VarStore: Setup | VarOffset: 0x421 | Size: 0x1
0: 0x0
90: 0x2
180: 0x4
270: 0x6
Link options
PMIC Position | VarStore: Setup | VarOffset: 0x422 | Size: 0x1
Position 1: 0x0
Position 2: 0x1
Link options
Voltage Rail | VarStore: Setup | VarOffset: 0x423 | Size: 0x1
3 voltage rail: 0x0
2 voltage rail: 0x1
Link options
PPR Value | VarStore: Setup | VarOffset: 0x424 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Link options
PPR Unit | VarStore: Setup | VarOffset: 0x425 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Link options
Camera module name
Link options
MIPI port | VarStore: Setup | VarOffset: 0x412 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
Link options
LaneUsed | VarStore: Setup | VarOffset: 0x413 | Size: 0x1
x1: 0x1
x2: 0x2
x3: 0x3
x4: 0x4
Link options
MCLK | VarStore: Setup | VarOffset: 0x41A | Size: 0x4
Min: 0x5B8D80 | Max: 0x19BFCC0 | Step: 0x186A0
Link options
EEPROM Type | VarStore: Setup | VarOffset: 0x414 | Size: 0x1
ROM_NONE: 0x0
ROM_OTP: 0x1
ROM_EEPROM_16K_64: 0x2
ROM_EEPROM_16K_16: 0x3
ROM_OTP_ACPI_ACPI: 0x4
ROM_ACPI: 0x5
ROM_EEPROM_BRCA016GWZ: 0x6
ROM_EEPROM_24AA32: 0x7
ROM_EEPROM_CAT24C08: 0x8
ROM_EEPROM_M24C64: 0x9
ROM_EEPROM_DW9806B: 0xA
ROM_EEPROM_CAT24C16: 0x10
ROM_EEPROM_CAT24C64: 0x11
ROM_EEPROM_24AA16: 0x12
Link options
VCM Type | VarStore: Setup | VarOffset: 0x415 | Size: 0x1
VCM_NONE: 0x0
VCM_AD5823: 0x1
VCM_DW9714: 0x2
VCM_AD5816: 0x3
VCM_DW9719: 0x4
VCM_DW9718: 0x5
VCM_DW9806B: 0x6
VCM_WV517S: 0x7
VCM_LC898122XA: 0x8
VCM_LC898212AXB: 0x9
VCM_RESERVED1: 0xA
VCM_RESERVED2: 0xB
VCM_AK7371: 0xF
VCM_BU64297GWZ: 0x10
Link options
Number of I2C Components | VarStore: Setup | VarOffset: 0x3EA | Size: 0x1
Min: 0x0 | Max: 0xC | Step: 0x1
Link options
I2C Channel | VarStore: Setup | VarOffset: 0x3EB | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Link options
I2C Address | VarStore: Setup | VarOffset: 0x3EC | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x404 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x3EE | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x405 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x3F0 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x406 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x3F2 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x407 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x3F4 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x408 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x3F6 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x409 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x3F8 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x40A | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x3FA | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x40B | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x3FC | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x40C | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x3FE | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x40D | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x400 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x40E | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x402 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x40F | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
Flash Driver Selection | VarStore: Setup | VarOffset: 0x426 | Size: 0x1
Disabled: 0x0
External: 0x1
Internal PMIC: 0x2
Control Logic options
Control Logic Type | VarStore: Setup | VarOffset: 0x97 | Size: 0x1
Discrete: 0x1
PMIC_TPS68470: 0x2
PMIC_UP6641: 0x3
PMIC_USER0: 0xFD
PMIC_USER1: 0xFE
Control Logic options
CRD Version | VarStore: Setup | VarOffset: 0x98 | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Control Logic options
Input Clock | VarStore: Setup | VarOffset: 0x99 | Size: 0x4
20 MHz: 0x10
24 MHz: 0x20
26 MHz: 0x30
19.2 MHz: 0x40
Control Logic options
PCH Clock Source | VarStore: Setup | VarOffset: 0x9D | Size: 0x1
IMGCLKOUT_0: 0x0
IMGCLKOUT_1: 0x1
IMGCLKOUT_2: 0x2
IMGCLKOUT_3: 0x3
IMGCLKOUT_4: 0x4
Control Logic options
PMIC Flash Panel | VarStore: Setup | VarOffset: 0xA2 | Size: 0x1
Front: 0x21
Back: 0x29
Control Logic options
I2C Channel | VarStore: Setup | VarOffset: 0x9F | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Control Logic options
I2C Address | VarStore: Setup | VarOffset: 0xA0 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Control Logic options
WLED1 Type | VarStore: Setup | VarOffset: 0xA8 | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED1 Flash Max Current | VarStore: Setup | VarOffset: 0xA3 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED1 Torch Max Current | VarStore: Setup | VarOffset: 0xA4 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
WLED2 Type | VarStore: Setup | VarOffset: 0xA9 | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED2 Flash Max Current | VarStore: Setup | VarOffset: 0xA5 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED2 Torch Max Current | VarStore: Setup | VarOffset: 0xA6 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
SubPlatformId | VarStore: Setup | VarOffset: 0xA7 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Control Logic options
Number of GPIO Pins | VarStore: Setup | VarOffset: 0x9E | Size: 0x1
Min: 0x0 | Max: 0x4 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xAA | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xAE | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0xB2 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xB6 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xBA | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xAB | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xAF | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0xB3 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xB7 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xBB | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xAC | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xB0 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0xB4 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xB8 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xBC | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xAD | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xB1 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0xB5 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xB9 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xBD | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Control Logic Type | VarStore: Setup | VarOffset: 0xBE | Size: 0x1
Discrete: 0x1
PMIC_TPS68470: 0x2
PMIC_UP6641: 0x3
PMIC_USER0: 0xFD
PMIC_USER1: 0xFE
Control Logic options
CRD Version | VarStore: Setup | VarOffset: 0xBF | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Control Logic options
Input Clock | VarStore: Setup | VarOffset: 0xC0 | Size: 0x4
20 MHz: 0x10
24 MHz: 0x20
26 MHz: 0x30
19.2 MHz: 0x40
Control Logic options
PCH Clock Source | VarStore: Setup | VarOffset: 0xC4 | Size: 0x1
IMGCLKOUT_0: 0x0
IMGCLKOUT_1: 0x1
IMGCLKOUT_2: 0x2
IMGCLKOUT_3: 0x3
IMGCLKOUT_4: 0x4
Control Logic options
PMIC Flash Panel | VarStore: Setup | VarOffset: 0xC9 | Size: 0x1
Front: 0x21
Back: 0x29
Control Logic options
I2C Channel | VarStore: Setup | VarOffset: 0xC6 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Control Logic options
I2C Address | VarStore: Setup | VarOffset: 0xC7 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Control Logic options
WLED1 Type | VarStore: Setup | VarOffset: 0xCF | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED1 Flash Max Current | VarStore: Setup | VarOffset: 0xCA | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED1 Torch Max Current | VarStore: Setup | VarOffset: 0xCB | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
WLED2 Type | VarStore: Setup | VarOffset: 0xD0 | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED2 Flash Max Current | VarStore: Setup | VarOffset: 0xCC | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED2 Torch Max Current | VarStore: Setup | VarOffset: 0xCD | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
SubPlatformId | VarStore: Setup | VarOffset: 0xCE | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Control Logic options
Number of GPIO Pins | VarStore: Setup | VarOffset: 0xC5 | Size: 0x1
Min: 0x0 | Max: 0x4 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xD1 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xD5 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0xD9 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xDD | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xE1 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xD2 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xD6 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0xDA | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xDE | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xE2 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xD3 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xD7 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0xDB | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xDF | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xE3 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xD4 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xD8 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0xDC | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xE0 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xE4 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Control Logic Type | VarStore: Setup | VarOffset: 0xE5 | Size: 0x1
Discrete: 0x1
PMIC_TPS68470: 0x2
PMIC_UP6641: 0x3
PMIC_USER0: 0xFD
PMIC_USER1: 0xFE
Control Logic options
CRD Version | VarStore: Setup | VarOffset: 0xE6 | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Control Logic options
Input Clock | VarStore: Setup | VarOffset: 0xE7 | Size: 0x4
20 MHz: 0x10
24 MHz: 0x20
26 MHz: 0x30
19.2 MHz: 0x40
Control Logic options
PCH Clock Source | VarStore: Setup | VarOffset: 0xEB | Size: 0x1
IMGCLKOUT_0: 0x0
IMGCLKOUT_1: 0x1
IMGCLKOUT_2: 0x2
IMGCLKOUT_3: 0x3
IMGCLKOUT_4: 0x4
Control Logic options
PMIC Flash Panel | VarStore: Setup | VarOffset: 0xF0 | Size: 0x1
Front: 0x21
Back: 0x29
Control Logic options
I2C Channel | VarStore: Setup | VarOffset: 0xED | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Control Logic options
I2C Address | VarStore: Setup | VarOffset: 0xEE | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Control Logic options
WLED1 Type | VarStore: Setup | VarOffset: 0xF6 | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED1 Flash Max Current | VarStore: Setup | VarOffset: 0xF1 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED1 Torch Max Current | VarStore: Setup | VarOffset: 0xF2 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
WLED2 Type | VarStore: Setup | VarOffset: 0xF7 | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED2 Flash Max Current | VarStore: Setup | VarOffset: 0xF3 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED2 Torch Max Current | VarStore: Setup | VarOffset: 0xF4 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
SubPlatformId | VarStore: Setup | VarOffset: 0xF5 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Control Logic options
Number of GPIO Pins | VarStore: Setup | VarOffset: 0xEC | Size: 0x1
Min: 0x0 | Max: 0x4 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xF8 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xFC | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x100 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x104 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x108 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xF9 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xFD | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x101 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x105 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x109 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xFA | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xFE | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x102 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x106 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x10A | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xFB | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xFF | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x103 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x107 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x10B | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Control Logic Type | VarStore: Setup | VarOffset: 0x10C | Size: 0x1
Discrete: 0x1
PMIC_TPS68470: 0x2
PMIC_UP6641: 0x3
PMIC_USER0: 0xFD
PMIC_USER1: 0xFE
Control Logic options
CRD Version | VarStore: Setup | VarOffset: 0x10D | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Control Logic options
Input Clock | VarStore: Setup | VarOffset: 0x10E | Size: 0x4
20 MHz: 0x10
24 MHz: 0x20
26 MHz: 0x30
19.2 MHz: 0x40
Control Logic options
PCH Clock Source | VarStore: Setup | VarOffset: 0x112 | Size: 0x1
IMGCLKOUT_0: 0x0
IMGCLKOUT_1: 0x1
IMGCLKOUT_2: 0x2
IMGCLKOUT_3: 0x3
IMGCLKOUT_4: 0x4
Control Logic options
PMIC Flash Panel | VarStore: Setup | VarOffset: 0x117 | Size: 0x1
Front: 0x21
Back: 0x29
Control Logic options
I2C Channel | VarStore: Setup | VarOffset: 0x114 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Control Logic options
I2C Address | VarStore: Setup | VarOffset: 0x115 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Control Logic options
WLED1 Type | VarStore: Setup | VarOffset: 0x11D | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED1 Flash Max Current | VarStore: Setup | VarOffset: 0x118 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED1 Torch Max Current | VarStore: Setup | VarOffset: 0x119 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
WLED2 Type | VarStore: Setup | VarOffset: 0x11E | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED2 Flash Max Current | VarStore: Setup | VarOffset: 0x11A | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED2 Torch Max Current | VarStore: Setup | VarOffset: 0x11B | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
SubPlatformId | VarStore: Setup | VarOffset: 0x11C | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Control Logic options
Number of GPIO Pins | VarStore: Setup | VarOffset: 0x113 | Size: 0x1
Min: 0x0 | Max: 0x4 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x11F | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x123 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x127 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x12B | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x12F | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x120 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x124 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x128 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x12C | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x130 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x121 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x125 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x129 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x12D | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x131 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x122 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x126 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x12A | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x12E | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x132 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Control Logic Type | VarStore: Setup | VarOffset: 0x133 | Size: 0x1
Discrete: 0x1
PMIC_TPS68470: 0x2
PMIC_UP6641: 0x3
PMIC_USER0: 0xFD
PMIC_USER1: 0xFE
Control Logic options
CRD Version | VarStore: Setup | VarOffset: 0x134 | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Control Logic options
Input Clock | VarStore: Setup | VarOffset: 0x135 | Size: 0x4
20 MHz: 0x10
24 MHz: 0x20
26 MHz: 0x30
19.2 MHz: 0x40
Control Logic options
PCH Clock Source | VarStore: Setup | VarOffset: 0x139 | Size: 0x1
IMGCLKOUT_0: 0x0
IMGCLKOUT_1: 0x1
IMGCLKOUT_2: 0x2
IMGCLKOUT_3: 0x3
IMGCLKOUT_4: 0x4
Control Logic options
PMIC Flash Panel | VarStore: Setup | VarOffset: 0x13E | Size: 0x1
Front: 0x21
Back: 0x29
Control Logic options
I2C Channel | VarStore: Setup | VarOffset: 0x13B | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Control Logic options
I2C Address | VarStore: Setup | VarOffset: 0x13C | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Control Logic options
WLED1 Type | VarStore: Setup | VarOffset: 0x144 | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED1 Flash Max Current | VarStore: Setup | VarOffset: 0x13F | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED1 Torch Max Current | VarStore: Setup | VarOffset: 0x140 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
WLED2 Type | VarStore: Setup | VarOffset: 0x145 | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED2 Flash Max Current | VarStore: Setup | VarOffset: 0x141 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED2 Torch Max Current | VarStore: Setup | VarOffset: 0x142 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
SubPlatformId | VarStore: Setup | VarOffset: 0x143 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Control Logic options
Number of GPIO Pins | VarStore: Setup | VarOffset: 0x13A | Size: 0x1
Min: 0x0 | Max: 0x4 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x146 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x14A | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x14E | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x152 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x156 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x147 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x14B | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x14F | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x153 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x157 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x148 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x14C | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x150 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x154 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x158 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x149 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x14D | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x151 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x155 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x159 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Control Logic Type | VarStore: Setup | VarOffset: 0x15A | Size: 0x1
Discrete: 0x1
PMIC_TPS68470: 0x2
PMIC_UP6641: 0x3
PMIC_USER0: 0xFD
PMIC_USER1: 0xFE
Control Logic options
CRD Version | VarStore: Setup | VarOffset: 0x15B | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Control Logic options
Input Clock | VarStore: Setup | VarOffset: 0x15C | Size: 0x4
20 MHz: 0x10
24 MHz: 0x20
26 MHz: 0x30
19.2 MHz: 0x40
Control Logic options
PCH Clock Source | VarStore: Setup | VarOffset: 0x160 | Size: 0x1
IMGCLKOUT_0: 0x0
IMGCLKOUT_1: 0x1
IMGCLKOUT_2: 0x2
IMGCLKOUT_3: 0x3
IMGCLKOUT_4: 0x4
Control Logic options
PMIC Flash Panel | VarStore: Setup | VarOffset: 0x165 | Size: 0x1
Front: 0x21
Back: 0x29
Control Logic options
I2C Channel | VarStore: Setup | VarOffset: 0x162 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Control Logic options
I2C Address | VarStore: Setup | VarOffset: 0x163 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Control Logic options
WLED1 Type | VarStore: Setup | VarOffset: 0x16B | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED1 Flash Max Current | VarStore: Setup | VarOffset: 0x166 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED1 Torch Max Current | VarStore: Setup | VarOffset: 0x167 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
WLED2 Type | VarStore: Setup | VarOffset: 0x16C | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED2 Flash Max Current | VarStore: Setup | VarOffset: 0x168 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED2 Torch Max Current | VarStore: Setup | VarOffset: 0x169 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
SubPlatformId | VarStore: Setup | VarOffset: 0x16A | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Control Logic options
Number of GPIO Pins | VarStore: Setup | VarOffset: 0x161 | Size: 0x1
Min: 0x0 | Max: 0x4 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x16D | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x171 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x175 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x179 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x17D | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x16E | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x172 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x176 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x17A | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x17E | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x16F | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x173 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x177 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x17B | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x17F | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x170 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x174 | Size: 0x1
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Control Logic options
Function | VarStore: Setup | VarOffset: 0x178 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x17C | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x180 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Flash Options
Flash Model | VarStore: Setup | VarOffset: 0x427 | Size: 0x1
External - LM3643: 0x0
PMIC - WRC: 0x1
Flash Options
Camera module name
Flash Options
I2C Channel | VarStore: Setup | VarOffset: 0x448 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Flash Options
I2C Address | VarStore: Setup | VarOffset: 0x449 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Flash Options
Group Pad Number | VarStore: Setup | VarOffset: 0x44B | Size: 0x1
Min: 0x0 | Max: 0x58 | Step: 0x1
Flash Options
Group Number | VarStore: Setup | VarOffset: 0x44C | Size: 0x2
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Flash Options
Active Value | VarStore: Setup | VarOffset: 0x44E | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Flash Options
Initial Value | VarStore: Setup | VarOffset: 0x44F | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Flash Options
Flash Driver Operating Mode | VarStore: Setup | VarOffset: 0x450 | Size: 0x1
Don't flash or light up: 0x0
Light with ITORCH current continuously: 0x1
Flash with IFLASH current when TRIGGERed: 0x2
Flash Options
Flash Model | VarStore: Setup | VarOffset: 0x451 | Size: 0x1
External - LM3643: 0x0
PMIC - WRC: 0x1
Flash Options
Camera module name
Flash Options
I2C Channel | VarStore: Setup | VarOffset: 0x472 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Flash Options
I2C Address | VarStore: Setup | VarOffset: 0x473 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Flash Options
Group Pad Number | VarStore: Setup | VarOffset: 0x475 | Size: 0x1
Min: 0x0 | Max: 0x58 | Step: 0x1
Flash Options
Group Number | VarStore: Setup | VarOffset: 0x476 | Size: 0x2
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Flash Options
Active Value | VarStore: Setup | VarOffset: 0x478 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Flash Options
Initial Value | VarStore: Setup | VarOffset: 0x479 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Flash Options
Flash Driver Operating Mode | VarStore: Setup | VarOffset: 0x47A | Size: 0x1
Don't flash or light up: 0x0
Light with ITORCH current continuously: 0x1
Flash with IFLASH current when TRIGGERed: 0x2
Flash Options
Flash Model | VarStore: Setup | VarOffset: 0x47B | Size: 0x1
External - LM3643: 0x0
PMIC - WRC: 0x1
Flash Options
Camera module name
Flash Options
I2C Channel | VarStore: Setup | VarOffset: 0x49C | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Flash Options
I2C Address | VarStore: Setup | VarOffset: 0x49D | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Flash Options
Group Pad Number | VarStore: Setup | VarOffset: 0x49F | Size: 0x1
Min: 0x0 | Max: 0x58 | Step: 0x1
Flash Options
Group Number | VarStore: Setup | VarOffset: 0x4A0 | Size: 0x2
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Flash Options
Active Value | VarStore: Setup | VarOffset: 0x4A2 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Flash Options
Initial Value | VarStore: Setup | VarOffset: 0x4A3 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Flash Options
Flash Driver Operating Mode | VarStore: Setup | VarOffset: 0x4A4 | Size: 0x1
Don't flash or light up: 0x0
Light with ITORCH current continuously: 0x1
Flash with IFLASH current when TRIGGERed: 0x2
Flash Options
Flash Model | VarStore: Setup | VarOffset: 0x4A5 | Size: 0x1
External - LM3643: 0x0
PMIC - WRC: 0x1
Flash Options
Camera module name
Flash Options
I2C Channel | VarStore: Setup | VarOffset: 0x4C6 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Flash Options
I2C Address | VarStore: Setup | VarOffset: 0x4C7 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Flash Options
Group Pad Number | VarStore: Setup | VarOffset: 0x4C9 | Size: 0x1
Min: 0x0 | Max: 0x58 | Step: 0x1
Flash Options
Group Number | VarStore: Setup | VarOffset: 0x4CA | Size: 0x2
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Flash Options
Active Value | VarStore: Setup | VarOffset: 0x4CC | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Flash Options
Initial Value | VarStore: Setup | VarOffset: 0x4CD | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Flash Options
Flash Driver Operating Mode | VarStore: Setup | VarOffset: 0x4CE | Size: 0x1
Don't flash or light up: 0x0
Light with ITORCH current continuously: 0x1
Flash with IFLASH current when TRIGGERed: 0x2
Flash Options
Flash Model | VarStore: Setup | VarOffset: 0x4CF | Size: 0x1
External - LM3643: 0x0
PMIC - WRC: 0x1
Flash Options
Camera module name
Flash Options
I2C Channel | VarStore: Setup | VarOffset: 0x4F0 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Flash Options
I2C Address | VarStore: Setup | VarOffset: 0x4F1 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Flash Options
Group Pad Number | VarStore: Setup | VarOffset: 0x4F3 | Size: 0x1
Min: 0x0 | Max: 0x58 | Step: 0x1
Flash Options
Group Number | VarStore: Setup | VarOffset: 0x4F4 | Size: 0x2
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Flash Options
Active Value | VarStore: Setup | VarOffset: 0x4F6 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Flash Options
Initial Value | VarStore: Setup | VarOffset: 0x4F7 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Flash Options
Flash Driver Operating Mode | VarStore: Setup | VarOffset: 0x4F8 | Size: 0x1
Don't flash or light up: 0x0
Light with ITORCH current continuously: 0x1
Flash with IFLASH current when TRIGGERed: 0x2
Flash Options
Flash Model | VarStore: Setup | VarOffset: 0x4F9 | Size: 0x1
External - LM3643: 0x0
PMIC - WRC: 0x1
Flash Options
Camera module name
Flash Options
I2C Channel | VarStore: Setup | VarOffset: 0x51A | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Flash Options
I2C Address | VarStore: Setup | VarOffset: 0x51B | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Flash Options
Group Pad Number | VarStore: Setup | VarOffset: 0x51D | Size: 0x1
Min: 0x0 | Max: 0x58 | Step: 0x1
Flash Options
Group Number | VarStore: Setup | VarOffset: 0x51E | Size: 0x2
A: 0x2
B: 0x0
C: 0xB
D: 0x8
E: 0xE
F: 0xC
H: 0x7
R: 0x3
S: 0x6
T: 0x1
U: 0x9
Flash Options
Active Value | VarStore: Setup | VarOffset: 0x520 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Flash Options
Initial Value | VarStore: Setup | VarOffset: 0x521 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Flash Options
Flash Driver Operating Mode | VarStore: Setup | VarOffset: 0x522 | Size: 0x1
Don't flash or light up: 0x0
Light with ITORCH current continuously: 0x1
Flash with IFLASH current when TRIGGERed: 0x2
VMD setup menu
Enable VMD controller | VarStore: SaSetup | VarOffset: 0x14E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VMD setup menu
Enable VMD portA Support | VarStore: SaSetup | VarOffset: 0x14F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VMD setup menu
Enable VMD portB Support | VarStore: SaSetup | VarOffset: 0x150 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VMD setup menu
Enable VMD portC Support | VarStore: SaSetup | VarOffset: 0x151 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VMD setup menu
Enable VMD portD Support | VarStore: SaSetup | VarOffset: 0x152 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VMD setup menu
VMD Config Bar Size | VarStore: SaSetup | VarOffset: 0x153 | Size: 0x1
Min: 0x14 | Max: 0x1B | Step: 0x1
VMD setup menu
VMD Config Bar Attributes | VarStore: SaSetup | VarOffset: 0x154 | Size: 0x1
VMD 64bit prefetch: 0x2
VMD 32bit non prefetch: 0x0
VMD 64bit non prefetch: 0x1
VMD setup menu
VMD Mem Bar1 Size | VarStore: SaSetup | VarOffset: 0x155 | Size: 0x1
Min: 0x14 | Max: 0x27 | Step: 0x1
VMD setup menu
VMD Mem Bar1 Attributes | VarStore: SaSetup | VarOffset: 0x156 | Size: 0x1
VMD 32bit non prefetch: 0x0
VMD 64bit non prefetch: 0x1
VMD 64bit prefetch: 0x2
VMD setup menu
VMD Mem Bar2 Size | VarStore: SaSetup | VarOffset: 0x157 | Size: 0x1
Min: 0x14 | Max: 0x27 | Step: 0x1
VMD setup menu
VMD Mem Bar2 Attributes | VarStore: SaSetup | VarOffset: 0x158 | Size: 0x1
VMD 32bit non prefetch: 0x0
VMD 64bit non prefetch: 0x1
VMD 64bit prefetch: 0x2
VMD setup menu
RAID0 | VarStore: SaSetup | VarOffset: 0x15D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VMD setup menu
RAID1 | VarStore: SaSetup | VarOffset: 0x15E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VMD setup menu
RAID5 | VarStore: SaSetup | VarOffset: 0x160 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VMD setup menu
RAID10 | VarStore: SaSetup | VarOffset: 0x15F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VMD setup menu
Intel Rapid Recovery Technology | VarStore: SaSetup | VarOffset: 0x161 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VMD setup menu
RRT volumes can span internal and eSATA drives | VarStore: SaSetup | VarOffset: 0x162 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VMD setup menu
Intel(R) Optane(TM) Memory | VarStore: SaSetup | VarOffset: 0x163 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
PCI Express Clock Gating | VarStore: SaSetup | VarOffset: 0x29D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Fia Programming | VarStore: SaSetup | VarOffset: 0x29C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
PCI Express Power Gating | VarStore: SaSetup | VarOffset: 0x29E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Compliance Test Mode | VarStore: SaSetup | VarOffset: 0x29F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
PCIe function swap | VarStore: SaSetup | VarOffset: 0x2A0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Assertion on Link Down GPIOs | VarStore: SaSetup | VarOffset: 0x30E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Enable ClockReq Messaging | VarStore: SaSetup | VarOffset: 0x30F | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCI Express Configuration
PCI Express Slot Selection | VarStore: SaSetup | VarOffset: 0x310 | Size: 0x1
M2: 0x1
CEMx4 slot: 0x0
PCI Express Gen3 Eq Lanes
PCIE1 Cm | VarStore: SaSetup | VarOffset: 0x274 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE1 Cp | VarStore: SaSetup | VarOffset: 0x288 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE2 Cm | VarStore: SaSetup | VarOffset: 0x275 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE2 Cp | VarStore: SaSetup | VarOffset: 0x289 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE3 Cm | VarStore: SaSetup | VarOffset: 0x276 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE3 Cp | VarStore: SaSetup | VarOffset: 0x28A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE4 Cm | VarStore: SaSetup | VarOffset: 0x277 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE4 Cp | VarStore: SaSetup | VarOffset: 0x28B | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE5 Cm | VarStore: SaSetup | VarOffset: 0x278 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE5 Cp | VarStore: SaSetup | VarOffset: 0x28C | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE6 Cm | VarStore: SaSetup | VarOffset: 0x279 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE6 Cp | VarStore: SaSetup | VarOffset: 0x28D | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE7 Cm | VarStore: SaSetup | VarOffset: 0x27A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE7 Cp | VarStore: SaSetup | VarOffset: 0x28E | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE8 Cm | VarStore: SaSetup | VarOffset: 0x27B | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE8 Cp | VarStore: SaSetup | VarOffset: 0x28F | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE9 Cm | VarStore: SaSetup | VarOffset: 0x27C | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE9 Cp | VarStore: SaSetup | VarOffset: 0x290 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE10 Cm | VarStore: SaSetup | VarOffset: 0x27D | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE10 Cp | VarStore: SaSetup | VarOffset: 0x291 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE11 Cm | VarStore: SaSetup | VarOffset: 0x27E | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE11 Cp | VarStore: SaSetup | VarOffset: 0x292 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE12 Cm | VarStore: SaSetup | VarOffset: 0x27F | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE12 Cp | VarStore: SaSetup | VarOffset: 0x293 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE13 Cm | VarStore: SaSetup | VarOffset: 0x280 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE13 Cp | VarStore: SaSetup | VarOffset: 0x294 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE14 Cm | VarStore: SaSetup | VarOffset: 0x281 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE14 Cp | VarStore: SaSetup | VarOffset: 0x295 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE15 Cm | VarStore: SaSetup | VarOffset: 0x282 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE15 Cp | VarStore: SaSetup | VarOffset: 0x296 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE16 Cm | VarStore: SaSetup | VarOffset: 0x283 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE16 Cp | VarStore: SaSetup | VarOffset: 0x297 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE17 Cm | VarStore: SaSetup | VarOffset: 0x284 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE17 Cp | VarStore: SaSetup | VarOffset: 0x298 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE18 Cm | VarStore: SaSetup | VarOffset: 0x285 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE18 Cp | VarStore: SaSetup | VarOffset: 0x299 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE19 Cm | VarStore: SaSetup | VarOffset: 0x286 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE19 Cp | VarStore: SaSetup | VarOffset: 0x29A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE20 Cm | VarStore: SaSetup | VarOffset: 0x287 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE29 Cp | VarStore: SaSetup | VarOffset: 0x29B | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
PCI Express Root Port 1 | VarStore: SaSetup | VarOffset: 0x270 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Connection Type | VarStore: SaSetup | VarOffset: 0x315 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 1
ASPM | VarStore: SaSetup | VarOffset: 0x359 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
PCI Express Root Port 1
L1 Substates | VarStore: SaSetup | VarOffset: 0x35D | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 1
Gen3 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x351 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 1
Gen4 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x355 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 1
ACS | VarStore: SaSetup | VarOffset: 0x321 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
PTM | VarStore: SaSetup | VarOffset: 0x371 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
DPC | VarStore: SaSetup | VarOffset: 0x345 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
FOM Scoreboard Control Policy | VarStore: SaSetup | VarOffset: 0x3B8 | Size: 0x1
Auto: 0x0
Gen3: 0x1
Gen4: 0x2
Gen3/Gen4: 0x3
PCI Express Root Port 1
VC | VarStore: SaSetup | VarOffset: 0x37D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Multi-VC | VarStore: SaSetup | VarOffset: 0x381 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
EDPC | VarStore: SaSetup | VarOffset: 0x349 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
URR | VarStore: SaSetup | VarOffset: 0x329 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
FER | VarStore: SaSetup | VarOffset: 0x32D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
NFER | VarStore: SaSetup | VarOffset: 0x331 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
CER | VarStore: SaSetup | VarOffset: 0x335 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
CTO | VarStore: PchSetup | VarOffset: 0x18A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
SEFE | VarStore: SaSetup | VarOffset: 0x339 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
SENFE | VarStore: SaSetup | VarOffset: 0x33D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
SECE | VarStore: SaSetup | VarOffset: 0x341 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
PME SCI | VarStore: SaSetup | VarOffset: 0x319 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Hot Plug | VarStore: SaSetup | VarOffset: 0x311 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Advanced Error Reporting | VarStore: SaSetup | VarOffset: 0x325 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
PCIe Speed | VarStore: SaSetup | VarOffset: 0x34D | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
Gen4: 0x4
PCI Express Root Port 1
Transmitter Half Swing | VarStore: SaSetup | VarOffset: 0x31D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Detect Timeout | VarStore: SaSetup | VarOffset: 0x375 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 1
P2P Support | VarStore: SaSetup | VarOffset: 0x3BC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
LTR | VarStore: SaSetup | VarOffset: 0x389 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x391 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 1
Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x399 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 1
Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x395 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 1
Non Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x3A1 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 1
Non Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x3A9 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 1
Non Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x3A5 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 1
Force LTR Override | VarStore: SaSetup | VarOffset: 0x3B1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
LTR Lock | VarStore: SaSetup | VarOffset: 0x38D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
UPTP | VarStore: SaSetup | VarOffset: 0x361 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 1
DPTP | VarStore: SaSetup | VarOffset: 0x365 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 1
UPTP | VarStore: SaSetup | VarOffset: 0x369 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 1
DPTP | VarStore: SaSetup | VarOffset: 0x36D | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 2
PCI Express Root Port 2 | VarStore: SaSetup | VarOffset: 0x271 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Connection Type | VarStore: SaSetup | VarOffset: 0x316 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 2
ASPM | VarStore: SaSetup | VarOffset: 0x35A | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
PCI Express Root Port 2
L1 Substates | VarStore: SaSetup | VarOffset: 0x35E | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 2
Gen3 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x352 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 2
Gen4 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x356 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 2
ACS | VarStore: SaSetup | VarOffset: 0x322 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
PTM | VarStore: SaSetup | VarOffset: 0x372 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
DPC | VarStore: SaSetup | VarOffset: 0x346 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
FOM Scoreboard Control Policy | VarStore: SaSetup | VarOffset: 0x3B9 | Size: 0x1
Auto: 0x0
Gen3: 0x1
Gen4: 0x2
Gen3/Gen4: 0x3
PCI Express Root Port 2
VC | VarStore: SaSetup | VarOffset: 0x37E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Multi-VC | VarStore: SaSetup | VarOffset: 0x382 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
EDPC | VarStore: SaSetup | VarOffset: 0x34A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
URR | VarStore: SaSetup | VarOffset: 0x32A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
FER | VarStore: SaSetup | VarOffset: 0x32E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
NFER | VarStore: SaSetup | VarOffset: 0x332 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
CER | VarStore: SaSetup | VarOffset: 0x336 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
CTO | VarStore: PchSetup | VarOffset: 0x18B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
SEFE | VarStore: SaSetup | VarOffset: 0x33A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
SENFE | VarStore: SaSetup | VarOffset: 0x33E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
SECE | VarStore: SaSetup | VarOffset: 0x342 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
PME SCI | VarStore: SaSetup | VarOffset: 0x31A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Hot Plug | VarStore: SaSetup | VarOffset: 0x312 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Advanced Error Reporting | VarStore: SaSetup | VarOffset: 0x326 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
PCIe Speed | VarStore: SaSetup | VarOffset: 0x34E | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
Gen4: 0x4
PCI Express Root Port 2
Transmitter Half Swing | VarStore: SaSetup | VarOffset: 0x31E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Detect Timeout | VarStore: SaSetup | VarOffset: 0x377 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 2
P2P Support | VarStore: SaSetup | VarOffset: 0x3BD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
LTR | VarStore: SaSetup | VarOffset: 0x38A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x392 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 2
Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x39B | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 2
Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x396 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 2
Non Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x3A2 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 2
Non Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x3AB | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 2
Non Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x3A6 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 2
Force LTR Override | VarStore: SaSetup | VarOffset: 0x3B2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
LTR Lock | VarStore: SaSetup | VarOffset: 0x38E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
UPTP | VarStore: SaSetup | VarOffset: 0x362 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 2
DPTP | VarStore: SaSetup | VarOffset: 0x366 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 2
UPTP | VarStore: SaSetup | VarOffset: 0x36A | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 2
DPTP | VarStore: SaSetup | VarOffset: 0x36E | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 3
PCI Express Root Port 3 | VarStore: SaSetup | VarOffset: 0x272 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Connection Type | VarStore: SaSetup | VarOffset: 0x317 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 3
ASPM | VarStore: SaSetup | VarOffset: 0x35B | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
PCI Express Root Port 3
L1 Substates | VarStore: SaSetup | VarOffset: 0x35F | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 3
Gen3 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x353 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 3
Gen4 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x357 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 3
ACS | VarStore: SaSetup | VarOffset: 0x323 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
PTM | VarStore: SaSetup | VarOffset: 0x373 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
DPC | VarStore: SaSetup | VarOffset: 0x347 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
FOM Scoreboard Control Policy | VarStore: SaSetup | VarOffset: 0x3BA | Size: 0x1
Auto: 0x0
Gen3: 0x1
Gen4: 0x2
Gen3/Gen4: 0x3
PCI Express Root Port 3
VC | VarStore: SaSetup | VarOffset: 0x37F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Multi-VC | VarStore: SaSetup | VarOffset: 0x383 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
EDPC | VarStore: SaSetup | VarOffset: 0x34B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
URR | VarStore: SaSetup | VarOffset: 0x32B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
FER | VarStore: SaSetup | VarOffset: 0x32F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
NFER | VarStore: SaSetup | VarOffset: 0x333 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
CER | VarStore: SaSetup | VarOffset: 0x337 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
CTO | VarStore: PchSetup | VarOffset: 0x18C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
SEFE | VarStore: SaSetup | VarOffset: 0x33B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
SENFE | VarStore: SaSetup | VarOffset: 0x33F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
SECE | VarStore: SaSetup | VarOffset: 0x343 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
PME SCI | VarStore: SaSetup | VarOffset: 0x31B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Hot Plug | VarStore: SaSetup | VarOffset: 0x313 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Advanced Error Reporting | VarStore: SaSetup | VarOffset: 0x327 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
PCIe Speed | VarStore: SaSetup | VarOffset: 0x34F | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
Gen4: 0x4
PCI Express Root Port 3
Transmitter Half Swing | VarStore: SaSetup | VarOffset: 0x31F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Detect Timeout | VarStore: SaSetup | VarOffset: 0x379 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 3
P2P Support | VarStore: SaSetup | VarOffset: 0x3BE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
LTR | VarStore: SaSetup | VarOffset: 0x38B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x393 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 3
Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x39D | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 3
Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x397 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 3
Non Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x3A3 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 3
Non Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x3AD | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 3
Non Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x3A7 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 3
Force LTR Override | VarStore: SaSetup | VarOffset: 0x3B3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
LTR Lock | VarStore: SaSetup | VarOffset: 0x38F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
UPTP | VarStore: SaSetup | VarOffset: 0x363 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 3
DPTP | VarStore: SaSetup | VarOffset: 0x367 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 3
UPTP | VarStore: SaSetup | VarOffset: 0x36B | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 3
DPTP | VarStore: SaSetup | VarOffset: 0x36F | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 4
PCI Express Root Port 4 | VarStore: SaSetup | VarOffset: 0x273 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Connection Type | VarStore: SaSetup | VarOffset: 0x318 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 4
ASPM | VarStore: SaSetup | VarOffset: 0x35C | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
PCI Express Root Port 4
L1 Substates | VarStore: SaSetup | VarOffset: 0x360 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 4
Gen3 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x354 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 4
Gen4 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x358 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 4
ACS | VarStore: SaSetup | VarOffset: 0x324 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PTM | VarStore: SaSetup | VarOffset: 0x374 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
DPC | VarStore: SaSetup | VarOffset: 0x348 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
FOM Scoreboard Control Policy | VarStore: SaSetup | VarOffset: 0x3BB | Size: 0x1
Auto: 0x0
Gen3: 0x1
Gen4: 0x2
Gen3/Gen4: 0x3
PCI Express Root Port 4
VC | VarStore: SaSetup | VarOffset: 0x380 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Multi-VC | VarStore: SaSetup | VarOffset: 0x384 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
EDPC | VarStore: SaSetup | VarOffset: 0x34C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
URR | VarStore: SaSetup | VarOffset: 0x32C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
FER | VarStore: SaSetup | VarOffset: 0x330 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
NFER | VarStore: SaSetup | VarOffset: 0x334 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
CER | VarStore: SaSetup | VarOffset: 0x338 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
CTO | VarStore: PchSetup | VarOffset: 0x18D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
SEFE | VarStore: SaSetup | VarOffset: 0x33C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
SENFE | VarStore: SaSetup | VarOffset: 0x340 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
SECE | VarStore: SaSetup | VarOffset: 0x344 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PME SCI | VarStore: SaSetup | VarOffset: 0x31C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Hot Plug | VarStore: SaSetup | VarOffset: 0x314 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Advanced Error Reporting | VarStore: SaSetup | VarOffset: 0x328 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PCIe Speed | VarStore: SaSetup | VarOffset: 0x350 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
Gen4: 0x4
PCI Express Root Port 4
Transmitter Half Swing | VarStore: SaSetup | VarOffset: 0x320 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Detect Timeout | VarStore: SaSetup | VarOffset: 0x37B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 4
P2P Support | VarStore: SaSetup | VarOffset: 0x3BF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
LTR | VarStore: SaSetup | VarOffset: 0x38C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x394 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 4
Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x39F | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 4
Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x398 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 4
Non Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x3A4 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 4
Non Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x3AF | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 4
Non Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x3A8 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 4
Force LTR Override | VarStore: SaSetup | VarOffset: 0x3B4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
LTR Lock | VarStore: SaSetup | VarOffset: 0x390 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
UPTP | VarStore: SaSetup | VarOffset: 0x364 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 4
DPTP | VarStore: SaSetup | VarOffset: 0x368 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 4
UPTP | VarStore: SaSetup | VarOffset: 0x36C | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 4
DPTP | VarStore: SaSetup | VarOffset: 0x370 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
IMR Configuration
PCIe IMR | VarStore: SiSetup | VarOffset: 0x2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
IMR Configuration
PCIe IMR Size | VarStore: SiSetup | VarOffset: 0x3 | Size: 0x2
Min: 0x0 | Max: 0x400 | Step: 0x1
IMR Configuration
PCIe RP Location for IMR | VarStore: SiSetup | VarOffset: 0x5 | Size: 0x1
PCH PCIE: 0x1
SA PCIE: 0x2
IMR Configuration
RP index for IMR | VarStore: SiSetup | VarOffset: 0x6 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
PCH-IO Configuration
PCH LAN Controller | VarStore: PchSetup | VarOffset: 0x9 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
LAN Wake From DeepSx | VarStore: PchSetup | VarOffset: 0x5 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
Wake on LAN Enable | VarStore: PchSetup | VarOffset: 0xC | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
SLP_LAN# Low on DC Power | VarStore: PchSetup | VarOffset: 0xD | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
Sensor Hub Type | VarStore: Setup | VarOffset: 0x7F | Size: 0x1
None: 0x0
I2C Sensor Hub: 0x1
USB Sensor Hub: 0x2
PCH-IO Configuration
DeepSx Power Policies | VarStore: PchSetup | VarOffset: 0x4 | Size: 0x1
Disabled: 0x0
Enabled in S4-S5/Battery: 0x3
Enabled in S5/Battery: 0x1
Enabled in S4-S5: 0x4
Enabled in S5: 0x2
PCH-IO Configuration
PS_ON Enable | VarStore: PchSetup | VarOffset: 0x1E | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
Wake on WLAN and BT Enable | VarStore: PchSetup | VarOffset: 0xE | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
DeepSx Wake on WLAN and BT Enable | VarStore: PchSetup | VarOffset: 0xF | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
Disable DSX ACPRESENT PullDown | VarStore: PchSetup | VarOffset: 0x6 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
High Precision Timer | VarStore: PchSetup | VarOffset: 0x1F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
AC BACK | VarStore: PchSetup | VarOffset: 0x20 | Size: 0x1
Always On: 0x0
Always Off: 0x1
Memory: 0x2
PCH-IO Configuration
Port 80h Redirection | VarStore: PchSetup | VarOffset: 0x21 | Size: 0x1
LPC Bus: 0x0
PCIE Bus: 0x1
PCH-IO Configuration
Enhance Port 80h LPC Decoding | VarStore: PchSetup | VarOffset: 0x22 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
Compatible Revision ID | VarStore: PchSetup | VarOffset: 0x12 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
Legacy IO Low Latency | VarStore: PchSetup | VarOffset: 0x6B6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
PCH Cross Throttling | VarStore: PchSetup | VarOffset: 0x603 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
PCH Energy Reporting | VarStore: PchSetup | VarOffset: 0x10 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
LPM S0i2.0 | VarStore: PchSetup | VarOffset: 0x13 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
LPM S0i2.1 | VarStore: PchSetup | VarOffset: 0x14 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
LPM S0i2.2 | VarStore: PchSetup | VarOffset: 0x15 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
LPM S0i3.0 | VarStore: PchSetup | VarOffset: 0x16 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
LPM S0i3.1 | VarStore: PchSetup | VarOffset: 0x17 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
LPM S0i3.2 | VarStore: PchSetup | VarOffset: 0x18 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
LPM S0i3.3 | VarStore: PchSetup | VarOffset: 0x19 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
LPM S0i3.4 | VarStore: PchSetup | VarOffset: 0x1A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
IEH Mode | VarStore: PchSetup | VarOffset: 0x46F | Size: 0x1
Bypass Mode: 0x0
Enabled: 0x1
PCH-IO Configuration
Enable TCO Timer | VarStore: PchSetup | VarOffset: 0x11 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
Pcie Pll SSC | VarStore: PchSetup | VarOffset: 0x23 | Size: 0x1
Auto: 0xFF
0.0%: 0x0
0.1%: 0x1
0.2%: 0x2
0.3%: 0x3
0.4%: 0x4
0.5%: 0x5
0.6%: 0x6
0.7%: 0x7
0.8%: 0x8
0.9%: 0x9
1.0%: 0xA
1.1%: 0xB
1.2%: 0xC
1.3%: 0xD
1.4%: 0xE
1.5%: 0xF
1.6%: 0x10
1.7%: 0x11
1.8%: 0x12
1.9%: 0x13
2.0%: 0x14
Disable: 0xFE
PCH-IO Configuration
IOTG PLL SSCEN (CPU Side SSC) | VarStore: PchSetup | VarOffset: 0x6BD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
IOAPIC 24-119 Entries | VarStore: PchSetup | VarOffset: 0x601 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
Enable 8254 Clock Gate | VarStore: PchSetup | VarOffset: 0x602 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Enabled In Runtime and S3 Resume: 0x2
PCH-IO Configuration
Lock PCH Sideband Access | VarStore: PchSetup | VarOffset: 0x684 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
Flash Protection Range Registers (FPRR) | VarStore: PchSetup | VarOffset: 0x685 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
SPD Write Disable | VarStore: PchSetup | VarOffset: 0x683 | Size: 0x1
TRUE: 0x1
FALSE: 0x0
PCH-IO Configuration
LGMR | VarStore: PchSetup | VarOffset: 0x681 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
HOST_C10 reporting to Slave | VarStore: PchSetup | VarOffset: 0x682 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
OS IDLE Mode | VarStore: PchSetup | VarOffset: 0x6B5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
S0ix Auto Demotion | VarStore: PchSetup | VarOffset: 0x25 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
Latch Events C10 Exit | VarStore: PchSetup | VarOffset: 0x26 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
Hybrid Storage Detection and Configuration Mode | VarStore: PchSetup | VarOffset: 0x6BB | Size: 0x1
Dynamic Configuration for Hybrid Storage Enable: 0x1
Disabled: 0x0
PCH-IO Configuration
Extended BIOS Range Decode | VarStore: PchSetup | VarOffset: 0x6BC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
DMI Link ASPM Control | VarStore: PchSetup | VarOffset: 0x46A | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Configuration
Port8xh Decode | VarStore: PchSetup | VarOffset: 0xD6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Port8xh Decode Port# | VarStore: PchSetup | VarOffset: 0xD7 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
PCI Express Configuration
Peer Memory Write Enable | VarStore: PchSetup | VarOffset: 0xD8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Compliance Test Mode | VarStore: PchSetup | VarOffset: 0xD9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
PCIe function swap | VarStore: PchSetup | VarOffset: 0x33A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
xDCI Support | VarStore: PchSetup | VarOffset: 0x48 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB2 PHY Sus Well Power Gating | VarStore: PchSetup | VarOffset: 0x46 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB3 Link Compliance | VarStore: PchSetup | VarOffset: 0x47 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
XHCI LTR Mode | VarStore: PchSetup | VarOffset: 0x6BE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB PDO Programming | VarStore: PchSetup | VarOffset: 0x42 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB Overcurrent | VarStore: PchSetup | VarOffset: 0x43 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB Overcurrent Lock | VarStore: PchSetup | VarOffset: 0x44 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB Port Disable Override | VarStore: PchSetup | VarOffset: 0x27 | Size: 0x1
Disable Link: 0x0
Select Per-Pin: 0x1
USB Configuration
USB SS Physical Connector #0 | VarStore: PchSetup | VarOffset: 0x38 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #1 | VarStore: PchSetup | VarOffset: 0x39 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #2 | VarStore: PchSetup | VarOffset: 0x3A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #3 | VarStore: PchSetup | VarOffset: 0x3B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #4 | VarStore: PchSetup | VarOffset: 0x3C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #5 | VarStore: PchSetup | VarOffset: 0x3D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #6 | VarStore: PchSetup | VarOffset: 0x3E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #7 | VarStore: PchSetup | VarOffset: 0x3F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #8 | VarStore: PchSetup | VarOffset: 0x40 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #9 | VarStore: PchSetup | VarOffset: 0x41 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #0 | VarStore: PchSetup | VarOffset: 0x28 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #1 | VarStore: PchSetup | VarOffset: 0x29 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #2 | VarStore: PchSetup | VarOffset: 0x2A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #3 | VarStore: PchSetup | VarOffset: 0x2B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #4 | VarStore: PchSetup | VarOffset: 0x2C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #5 | VarStore: PchSetup | VarOffset: 0x2D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #6 | VarStore: PchSetup | VarOffset: 0x2E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #7 | VarStore: PchSetup | VarOffset: 0x2F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #8 | VarStore: PchSetup | VarOffset: 0x30 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #9 | VarStore: PchSetup | VarOffset: 0x31 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #10 | VarStore: PchSetup | VarOffset: 0x32 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #11 | VarStore: PchSetup | VarOffset: 0x33 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #12 | VarStore: PchSetup | VarOffset: 0x34 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #13 | VarStore: PchSetup | VarOffset: 0x35 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB Sensor Hub | VarStore: Setup | VarOffset: 0x84 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
SATA And RST Configuration
SATA Controller(s) | VarStore: PchSetup | VarOffset: 0x49 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
SATA And RST Configuration
SATA Mode Selection | VarStore: PchSetup | VarOffset: 0x4A | Size: 0x1
AHCI: 0x0
SATA And RST Configuration
Sata Interrupt Selection | VarStore: PchSetup | VarOffset: 0x4B | Size: 0x1
Msix: 0x0
Msi: 0x1
Legacy: 0x2
SATA And RST Configuration
PCIe Storage Dev On Port 1 | VarStore: PchSetup | VarOffset: 0xBE | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 2 | VarStore: PchSetup | VarOffset: 0xBF | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 3 | VarStore: PchSetup | VarOffset: 0xC0 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 4 | VarStore: PchSetup | VarOffset: 0xC1 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 5 | VarStore: PchSetup | VarOffset: 0xC2 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 6 | VarStore: PchSetup | VarOffset: 0xC3 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 7 | VarStore: PchSetup | VarOffset: 0xC4 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 8 | VarStore: PchSetup | VarOffset: 0xC5 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 9 | VarStore: PchSetup | VarOffset: 0xC6 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 10 | VarStore: PchSetup | VarOffset: 0xC7 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 11 | VarStore: PchSetup | VarOffset: 0xC8 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 12 | VarStore: PchSetup | VarOffset: 0xC9 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 13 | VarStore: PchSetup | VarOffset: 0xCA | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 14 | VarStore: PchSetup | VarOffset: 0xCB | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 15 | VarStore: PchSetup | VarOffset: 0xCC | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 16 | VarStore: PchSetup | VarOffset: 0xCD | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 17 | VarStore: PchSetup | VarOffset: 0xCE | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 18 | VarStore: PchSetup | VarOffset: 0xCF | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 19 | VarStore: PchSetup | VarOffset: 0xD0 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 20 | VarStore: PchSetup | VarOffset: 0xD1 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 21 | VarStore: PchSetup | VarOffset: 0xD2 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 22 | VarStore: PchSetup | VarOffset: 0xD3 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 23 | VarStore: PchSetup | VarOffset: 0xD4 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 24 | VarStore: PchSetup | VarOffset: 0xD5 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
SATA Test Mode | VarStore: PchSetup | VarOffset: 0x95 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
SATA And RST Configuration
RAID Device ID | VarStore: PchSetup | VarOffset: 0x93 | Size: 0x1
Client: 0x0
Alternate: 0x1
Server: 0x2
SATA And RST Configuration
Aggressive LPM Support | VarStore: PchSetup | VarOffset: 0x94 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Port 0 | VarStore: PchSetup | VarOffset: 0x4C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x54 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x6C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x5C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x64 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x74 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
Topology | VarStore: PchSetup | VarOffset: 0x7C | Size: 0x1
Unknown: 0x0
ISATA: 0x1
Direct Connect: 0x2
Flex: 0x3
M2: 0x4
SATA And RST Configuration
SATA Port 0 DevSlp | VarStore: PchSetup | VarOffset: 0x96 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0x9E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xA6 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xB6 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 1 | VarStore: PchSetup | VarOffset: 0x4D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x55 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x6D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x5D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x65 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x75 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
Topology | VarStore: PchSetup | VarOffset: 0x7D | Size: 0x1
Unknown: 0x0
ISATA: 0x1
Direct Connect: 0x2
Flex: 0x3
M2: 0x4
SATA And RST Configuration
SATA Port 1 DevSlp | VarStore: PchSetup | VarOffset: 0x97 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0x9F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xA8 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xB7 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 2 | VarStore: PchSetup | VarOffset: 0x4E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x56 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x6E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x5E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x66 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x76 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
Topology | VarStore: PchSetup | VarOffset: 0x7E | Size: 0x1
Unknown: 0x0
ISATA: 0x1
Direct Connect: 0x2
Flex: 0x3
M2: 0x4
SATA And RST Configuration
SATA Port 2 DevSlp | VarStore: PchSetup | VarOffset: 0x98 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0xA0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xAA | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xB8 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 3 | VarStore: PchSetup | VarOffset: 0x4F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x57 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x6F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x5F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x67 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x77 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
Topology | VarStore: PchSetup | VarOffset: 0x7F | Size: 0x1
Unknown: 0x0
ISATA: 0x1
Direct Connect: 0x2
Flex: 0x3
M2: 0x4
SATA And RST Configuration
SATA Port 3 DevSlp | VarStore: PchSetup | VarOffset: 0x99 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0xA1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xAC | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xB9 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 4 | VarStore: PchSetup | VarOffset: 0x50 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x58 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x70 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x60 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x68 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x78 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
Topology | VarStore: PchSetup | VarOffset: 0x80 | Size: 0x1
Unknown: 0x0
ISATA: 0x1
Direct Connect: 0x2
Flex: 0x3
M2: 0x4
SATA And RST Configuration
SATA Port 4 DevSlp | VarStore: PchSetup | VarOffset: 0x9A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0xA2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xAE | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xBA | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 5 | VarStore: PchSetup | VarOffset: 0x51 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x59 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x71 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x61 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x69 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x79 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
Topology | VarStore: PchSetup | VarOffset: 0x81 | Size: 0x1
Unknown: 0x0
ISATA: 0x1
Direct Connect: 0x2
Flex: 0x3
M2: 0x4
SATA And RST Configuration
SATA Port 5 DevSlp | VarStore: PchSetup | VarOffset: 0x9B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0xA3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xB0 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xBB | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 6 | VarStore: PchSetup | VarOffset: 0x52 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x5A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x72 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x62 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x6A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x7A | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
Topology | VarStore: PchSetup | VarOffset: 0x82 | Size: 0x1
Unknown: 0x0
ISATA: 0x1
Direct Connect: 0x2
Flex: 0x3
M2: 0x4
SATA And RST Configuration
SATA Port 6 DevSlp | VarStore: PchSetup | VarOffset: 0x9C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0xA4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xB2 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xBC | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 0 | VarStore: PchSetup | VarOffset: 0x53 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x5B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x73 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x63 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x6B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x7B | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
Topology | VarStore: PchSetup | VarOffset: 0x83 | Size: 0x1
Unknown: 0x0
ISATA: 0x1
Direct Connect: 0x2
Flex: 0x3
M2: 0x4
SATA And RST Configuration
SATA Port 7 DevSlp | VarStore: PchSetup | VarOffset: 0x9D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0xA5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xB4 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xBD | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
Software Feature Mask Configuration
HDD Unlock | VarStore: PchSetup | VarOffset: 0x8A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
LED Locate | VarStore: PchSetup | VarOffset: 0x8B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
RAID0 | VarStore: PchSetup | VarOffset: 0x84 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
RAID1 | VarStore: PchSetup | VarOffset: 0x85 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
RAID10 | VarStore: PchSetup | VarOffset: 0x86 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
RAID5 | VarStore: PchSetup | VarOffset: 0x87 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
Intel Rapid Recovery Technology | VarStore: PchSetup | VarOffset: 0x88 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
OROM UI and BANNER | VarStore: PchSetup | VarOffset: 0x89 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
IRRT Only on eSATA | VarStore: PchSetup | VarOffset: 0x8C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
Smart Response Technology | VarStore: PchSetup | VarOffset: 0x8D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
OROM UI Normal Delay | VarStore: PchSetup | VarOffset: 0x8E | Size: 0x1
2 secs: 0x0
4 secs: 0x1
6 secs: 0x2
8 secs: 0x3
Software Feature Mask Configuration
RST Force Form | VarStore: PchSetup | VarOffset: 0x8F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
System Acceleration with Intel(R) Optane(TM) Memory | VarStore: PchSetup | VarOffset: 0x91 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
CPU Attached Storage | VarStore: PchSetup | VarOffset: 0x92 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCIe EQ settings
PCIe EQ override | VarStore: PchSetup | VarOffset: 0x33B
PCIe EQ settings
PCIe EQ method | VarStore: PchSetup | VarOffset: 0x33C | Size: 0x1
PCIe hardware EQ: 0x0
PCIe fixed EQ: 0x1
PCIe EQ settings
PCIe EQ mode | VarStore: PchSetup | VarOffset: 0x33D | Size: 0x1
Use presets during EQ: 0x0
Use coefficients during EQ: 0x1
PCIe EQ settings
EQ PH1 downstream port transmitter preset | VarStore: PchSetup | VarOffset: 0x33F | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCIe EQ settings
EQ PH1 upstream port transmitter preset | VarStore: PchSetup | VarOffset: 0x340 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCIe EQ settings
Enable EQ phase 2 local transmitter override | VarStore: PchSetup | VarOffset: 0x33E
PCIe EQ settings
EQ Phase 2 local transmitter override preset | VarStore: PchSetup | VarOffset: 0x361 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCIe EQ settings
Number of presets or coefficients used during phase 3 | VarStore: PchSetup | VarOffset: 0x341 | Size: 0x1
Min: 0x0 | Max: 0xB | Step: 0x1
PCIe EQ settings
Preset 0 | VarStore: PchSetup | VarOffset: 0x356 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Preset 1 | VarStore: PchSetup | VarOffset: 0x357 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Preset 2 | VarStore: PchSetup | VarOffset: 0x358 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Preset 3 | VarStore: PchSetup | VarOffset: 0x359 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Preset 4 | VarStore: PchSetup | VarOffset: 0x35A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Preset 5 | VarStore: PchSetup | VarOffset: 0x35B | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Preset 6 | VarStore: PchSetup | VarOffset: 0x35C | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Preset 7 | VarStore: PchSetup | VarOffset: 0x35D | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Preset 8 | VarStore: PchSetup | VarOffset: 0x35E | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Preset 9 | VarStore: PchSetup | VarOffset: 0x35F | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Preset 10 | VarStore: PchSetup | VarOffset: 0x360 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Pre-cursor coefficient 0 | VarStore: PchSetup | VarOffset: 0x342 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Post-cursor coefficient 0 | VarStore: PchSetup | VarOffset: 0x34C | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Pre-cursor coefficient 1 | VarStore: PchSetup | VarOffset: 0x343 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Post-cursor coefficient 1 | VarStore: PchSetup | VarOffset: 0x34D | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Pre-cursor coefficient 2 | VarStore: PchSetup | VarOffset: 0x344 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Post-cursor coefficient 2 | VarStore: PchSetup | VarOffset: 0x34E | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Pre-cursor coefficient 3 | VarStore: PchSetup | VarOffset: 0x345 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Post-cursor coefficient 3 | VarStore: PchSetup | VarOffset: 0x34F | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Pre-cursor coefficient 4 | VarStore: PchSetup | VarOffset: 0x346 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Post-cursor coefficient 4 | VarStore: PchSetup | VarOffset: 0x350 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Pre-cursor coefficient 5 | VarStore: PchSetup | VarOffset: 0x347 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Post-cursor coefficient 5 | VarStore: PchSetup | VarOffset: 0x351 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Pre-cursor coefficient 6 | VarStore: PchSetup | VarOffset: 0x348 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Post-cursor coefficient 6 | VarStore: PchSetup | VarOffset: 0x352 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Pre-cursor coefficient 7 | VarStore: PchSetup | VarOffset: 0x349 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Post-cursor coefficient 7 | VarStore: PchSetup | VarOffset: 0x353 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Pre-cursor coefficient 8 | VarStore: PchSetup | VarOffset: 0x34A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Post-cursor coefficient 8 | VarStore: PchSetup | VarOffset: 0x354 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Pre-cursor coefficient 9 | VarStore: PchSetup | VarOffset: 0x34B | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCIe EQ settings
Post-cursor coefficient 9 | VarStore: PchSetup | VarOffset: 0x355 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
PCI Express Root Port 1 | VarStore: PchSetup | VarOffset: 0xFA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Connection Type | VarStore: PchSetup | VarOffset: 0x2F2 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 1
ASPM | VarStore: PchSetup | VarOffset: 0x112 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 1
L1 Substates | VarStore: PchSetup | VarOffset: 0x27A | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 1
ACS | VarStore: PchSetup | VarOffset: 0x292 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
PTM | VarStore: PchSetup | VarOffset: 0x2AA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
DPC | VarStore: PchSetup | VarOffset: 0x2C2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
EDPC | VarStore: PchSetup | VarOffset: 0x2DA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
URR | VarStore: PchSetup | VarOffset: 0x12A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
FER | VarStore: PchSetup | VarOffset: 0x142 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
NFER | VarStore: PchSetup | VarOffset: 0x15A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
CER | VarStore: PchSetup | VarOffset: 0x172 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
SEFE | VarStore: PchSetup | VarOffset: 0x1BA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
SENFE | VarStore: PchSetup | VarOffset: 0x1D2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
SECE | VarStore: PchSetup | VarOffset: 0x1EA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
PME SCI | VarStore: PchSetup | VarOffset: 0x202 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Hot Plug | VarStore: PchSetup | VarOffset: 0x21A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x232 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
PCIe Speed | VarStore: PchSetup | VarOffset: 0x24A | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 1
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x262 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Detect Timeout | VarStore: PchSetup | VarOffset: 0x30A | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 1
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x470 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 1
Reserved Memory | VarStore: PchSetup | VarOffset: 0x488 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 1
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4B8 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 1
LTR | VarStore: PchSetup | VarOffset: 0x362 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x392 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 1
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x3F2 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 1
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3AA | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 1
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3C2 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 1
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x422 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 1
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3DA | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 1
Force LTR Override | VarStore: PchSetup | VarOffset: 0x452 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
LTR Lock | VarStore: PchSetup | VarOffset: 0x37A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
PCI Express Root Port 2 | VarStore: PchSetup | VarOffset: 0xFB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Connection Type | VarStore: PchSetup | VarOffset: 0x2F3 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 2
ASPM | VarStore: PchSetup | VarOffset: 0x113 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 2
L1 Substates | VarStore: PchSetup | VarOffset: 0x27B | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 2
ACS | VarStore: PchSetup | VarOffset: 0x293 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
PTM | VarStore: PchSetup | VarOffset: 0x2AB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
DPC | VarStore: PchSetup | VarOffset: 0x2C3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
EDPC | VarStore: PchSetup | VarOffset: 0x2DB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
URR | VarStore: PchSetup | VarOffset: 0x12B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
FER | VarStore: PchSetup | VarOffset: 0x143 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
NFER | VarStore: PchSetup | VarOffset: 0x15B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
CER | VarStore: PchSetup | VarOffset: 0x173 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
SEFE | VarStore: PchSetup | VarOffset: 0x1BB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
SENFE | VarStore: PchSetup | VarOffset: 0x1D3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
SECE | VarStore: PchSetup | VarOffset: 0x1EB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
PME SCI | VarStore: PchSetup | VarOffset: 0x203 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Hot Plug | VarStore: PchSetup | VarOffset: 0x21B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x233 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
PCIe Speed | VarStore: PchSetup | VarOffset: 0x24B | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 2
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x263 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Detect Timeout | VarStore: PchSetup | VarOffset: 0x30C | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 2
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x471 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 2
Reserved Memory | VarStore: PchSetup | VarOffset: 0x48A | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 2
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4B9 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 2
LTR | VarStore: PchSetup | VarOffset: 0x363 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x393 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 2
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x3F4 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 2
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3AB | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 2
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3C3 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 2
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x424 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 2
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3DB | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 2
Force LTR Override | VarStore: PchSetup | VarOffset: 0x453 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
LTR Lock | VarStore: PchSetup | VarOffset: 0x37B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
PCI Express Root Port 3 | VarStore: PchSetup | VarOffset: 0xFC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Connection Type | VarStore: PchSetup | VarOffset: 0x2F4 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 3
ASPM | VarStore: PchSetup | VarOffset: 0x114 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 3
L1 Substates | VarStore: PchSetup | VarOffset: 0x27C | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 3
ACS | VarStore: PchSetup | VarOffset: 0x294 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
PTM | VarStore: PchSetup | VarOffset: 0x2AC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
DPC | VarStore: PchSetup | VarOffset: 0x2C4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
EDPC | VarStore: PchSetup | VarOffset: 0x2DC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
URR | VarStore: PchSetup | VarOffset: 0x12C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
FER | VarStore: PchSetup | VarOffset: 0x144 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
NFER | VarStore: PchSetup | VarOffset: 0x15C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
CER | VarStore: PchSetup | VarOffset: 0x174 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
SEFE | VarStore: PchSetup | VarOffset: 0x1BC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
SENFE | VarStore: PchSetup | VarOffset: 0x1D4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
SECE | VarStore: PchSetup | VarOffset: 0x1EC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
PME SCI | VarStore: PchSetup | VarOffset: 0x204 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Hot Plug | VarStore: PchSetup | VarOffset: 0x21C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x234 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
PCIe Speed | VarStore: PchSetup | VarOffset: 0x24C | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 3
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x264 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Detect Timeout | VarStore: PchSetup | VarOffset: 0x30E | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 3
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x472 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 3
Reserved Memory | VarStore: PchSetup | VarOffset: 0x48C | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 3
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4BA | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 3
LTR | VarStore: PchSetup | VarOffset: 0x364 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x394 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 3
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x3F6 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 3
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3AC | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 3
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3C4 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 3
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x426 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 3
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3DC | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 3
Force LTR Override | VarStore: PchSetup | VarOffset: 0x454 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
LTR Lock | VarStore: PchSetup | VarOffset: 0x37C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PCI Express Root Port 4 | VarStore: PchSetup | VarOffset: 0xFD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Connection Type | VarStore: PchSetup | VarOffset: 0x2F5 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 4
ASPM | VarStore: PchSetup | VarOffset: 0x115 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 4
L1 Substates | VarStore: PchSetup | VarOffset: 0x27D | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 4
ACS | VarStore: PchSetup | VarOffset: 0x295 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PTM | VarStore: PchSetup | VarOffset: 0x2AD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
DPC | VarStore: PchSetup | VarOffset: 0x2C5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
EDPC | VarStore: PchSetup | VarOffset: 0x2DD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
URR | VarStore: PchSetup | VarOffset: 0x12D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
FER | VarStore: PchSetup | VarOffset: 0x145 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
NFER | VarStore: PchSetup | VarOffset: 0x15D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
CER | VarStore: PchSetup | VarOffset: 0x175 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
SEFE | VarStore: PchSetup | VarOffset: 0x1BD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
SENFE | VarStore: PchSetup | VarOffset: 0x1D5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
SECE | VarStore: PchSetup | VarOffset: 0x1ED | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PME SCI | VarStore: PchSetup | VarOffset: 0x205 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Hot Plug | VarStore: PchSetup | VarOffset: 0x21D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x235 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PCIe Speed | VarStore: PchSetup | VarOffset: 0x24D | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 4
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x265 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Detect Timeout | VarStore: PchSetup | VarOffset: 0x310 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 4
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x473 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 4
Reserved Memory | VarStore: PchSetup | VarOffset: 0x48E | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 4
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4BB | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 4
LTR | VarStore: PchSetup | VarOffset: 0x365 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x395 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 4
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x3F8 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 4
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3AD | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 4
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3C5 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 4
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x428 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 4
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3DD | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 4
Force LTR Override | VarStore: PchSetup | VarOffset: 0x455 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
LTR Lock | VarStore: PchSetup | VarOffset: 0x37D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
PCI Express Root Port 5 | VarStore: PchSetup | VarOffset: 0xFE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
Connection Type | VarStore: PchSetup | VarOffset: 0x2F6 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 5
ASPM | VarStore: PchSetup | VarOffset: 0x116 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 5
L1 Substates | VarStore: PchSetup | VarOffset: 0x27E | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 5
ACS | VarStore: PchSetup | VarOffset: 0x296 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
PTM | VarStore: PchSetup | VarOffset: 0x2AE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
DPC | VarStore: PchSetup | VarOffset: 0x2C6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
EDPC | VarStore: PchSetup | VarOffset: 0x2DE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
URR | VarStore: PchSetup | VarOffset: 0x12E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
FER | VarStore: PchSetup | VarOffset: 0x146 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
NFER | VarStore: PchSetup | VarOffset: 0x15E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
CER | VarStore: PchSetup | VarOffset: 0x176 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
SEFE | VarStore: PchSetup | VarOffset: 0x1BE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
SENFE | VarStore: PchSetup | VarOffset: 0x1D6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
SECE | VarStore: PchSetup | VarOffset: 0x1EE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
PME SCI | VarStore: PchSetup | VarOffset: 0x206 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
Hot Plug | VarStore: PchSetup | VarOffset: 0x21E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x236 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
PCIe Speed | VarStore: PchSetup | VarOffset: 0x24E | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 5
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x266 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
Detect Timeout | VarStore: PchSetup | VarOffset: 0x312 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 5
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x474 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 5
Reserved Memory | VarStore: PchSetup | VarOffset: 0x490 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 5
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4BC | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 5
LTR | VarStore: PchSetup | VarOffset: 0x366 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x396 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 5
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x3FA | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 5
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3AE | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 5
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3C6 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 5
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x42A | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 5
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3DE | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 5
Force LTR Override | VarStore: PchSetup | VarOffset: 0x456 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
LTR Lock | VarStore: PchSetup | VarOffset: 0x37E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
PCI Express Root Port 6 | VarStore: PchSetup | VarOffset: 0xFF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
Connection Type | VarStore: PchSetup | VarOffset: 0x2F7 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 6
ASPM | VarStore: PchSetup | VarOffset: 0x117 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 6
L1 Substates | VarStore: PchSetup | VarOffset: 0x27F | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 6
ACS | VarStore: PchSetup | VarOffset: 0x297 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
PTM | VarStore: PchSetup | VarOffset: 0x2AF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
DPC | VarStore: PchSetup | VarOffset: 0x2C7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
EDPC | VarStore: PchSetup | VarOffset: 0x2DF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
URR | VarStore: PchSetup | VarOffset: 0x12F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
FER | VarStore: PchSetup | VarOffset: 0x147 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
NFER | VarStore: PchSetup | VarOffset: 0x15F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
CER | VarStore: PchSetup | VarOffset: 0x177 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
SEFE | VarStore: PchSetup | VarOffset: 0x1BF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
SENFE | VarStore: PchSetup | VarOffset: 0x1D7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
SECE | VarStore: PchSetup | VarOffset: 0x1EF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
PME SCI | VarStore: PchSetup | VarOffset: 0x207 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
Hot Plug | VarStore: PchSetup | VarOffset: 0x21F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x237 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
PCIe Speed | VarStore: PchSetup | VarOffset: 0x24F | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 6
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x267 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
Detect Timeout | VarStore: PchSetup | VarOffset: 0x314 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 6
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x475 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 6
Reserved Memory | VarStore: PchSetup | VarOffset: 0x492 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 6
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4BD | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 6
LTR | VarStore: PchSetup | VarOffset: 0x367 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x397 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 6
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x3FC | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 6
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3AF | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 6
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3C7 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 6
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x42C | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 6
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3DF | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 6
Force LTR Override | VarStore: PchSetup | VarOffset: 0x457 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
LTR Lock | VarStore: PchSetup | VarOffset: 0x37F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
PCI Express Root Port 7 | VarStore: PchSetup | VarOffset: 0x100 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
Connection Type | VarStore: PchSetup | VarOffset: 0x2F8 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 7
ASPM | VarStore: PchSetup | VarOffset: 0x118 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 7
L1 Substates | VarStore: PchSetup | VarOffset: 0x280 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 7
ACS | VarStore: PchSetup | VarOffset: 0x298 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
PTM | VarStore: PchSetup | VarOffset: 0x2B0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
DPC | VarStore: PchSetup | VarOffset: 0x2C8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
EDPC | VarStore: PchSetup | VarOffset: 0x2E0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
URR | VarStore: PchSetup | VarOffset: 0x130 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
FER | VarStore: PchSetup | VarOffset: 0x148 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
NFER | VarStore: PchSetup | VarOffset: 0x160 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
CER | VarStore: PchSetup | VarOffset: 0x178 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
SEFE | VarStore: PchSetup | VarOffset: 0x1C0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
SENFE | VarStore: PchSetup | VarOffset: 0x1D8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
SECE | VarStore: PchSetup | VarOffset: 0x1F0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
PME SCI | VarStore: PchSetup | VarOffset: 0x208 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
Hot Plug | VarStore: PchSetup | VarOffset: 0x220 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x238 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
PCIe Speed | VarStore: PchSetup | VarOffset: 0x250 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 7
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x268 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
Detect Timeout | VarStore: PchSetup | VarOffset: 0x316 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 7
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x476 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 7
Reserved Memory | VarStore: PchSetup | VarOffset: 0x494 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 7
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4BE | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 7
LTR | VarStore: PchSetup | VarOffset: 0x368 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x398 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 7
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x3FE | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 7
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3B0 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 7
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3C8 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 7
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x42E | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 7
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3E0 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 7
Force LTR Override | VarStore: PchSetup | VarOffset: 0x458 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
LTR Lock | VarStore: PchSetup | VarOffset: 0x380 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
PCI Express Root Port 8 | VarStore: PchSetup | VarOffset: 0x101 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
Connection Type | VarStore: PchSetup | VarOffset: 0x2F9 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 8
ASPM | VarStore: PchSetup | VarOffset: 0x119 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 8
L1 Substates | VarStore: PchSetup | VarOffset: 0x281 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 8
ACS | VarStore: PchSetup | VarOffset: 0x299 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
PTM | VarStore: PchSetup | VarOffset: 0x2B1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
DPC | VarStore: PchSetup | VarOffset: 0x2C9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
EDPC | VarStore: PchSetup | VarOffset: 0x2E1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
URR | VarStore: PchSetup | VarOffset: 0x131 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
FER | VarStore: PchSetup | VarOffset: 0x149 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
NFER | VarStore: PchSetup | VarOffset: 0x161 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
CER | VarStore: PchSetup | VarOffset: 0x179 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
SEFE | VarStore: PchSetup | VarOffset: 0x1C1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
SENFE | VarStore: PchSetup | VarOffset: 0x1D9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
SECE | VarStore: PchSetup | VarOffset: 0x1F1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
PME SCI | VarStore: PchSetup | VarOffset: 0x209 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
Hot Plug | VarStore: PchSetup | VarOffset: 0x221 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x239 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
PCIe Speed | VarStore: PchSetup | VarOffset: 0x251 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 8
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x269 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
Detect Timeout | VarStore: PchSetup | VarOffset: 0x318 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 8
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x477 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 8
Reserved Memory | VarStore: PchSetup | VarOffset: 0x496 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 8
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4BF | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 8
LTR | VarStore: PchSetup | VarOffset: 0x369 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x399 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 8
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x400 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 8
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3B1 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 8
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3C9 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 8
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x430 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 8
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3E1 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 8
Force LTR Override | VarStore: PchSetup | VarOffset: 0x459 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 8
LTR Lock | VarStore: PchSetup | VarOffset: 0x381 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
PCI Express Root Port 9 | VarStore: PchSetup | VarOffset: 0x102 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
Connection Type | VarStore: PchSetup | VarOffset: 0x2FA | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 9
ASPM | VarStore: PchSetup | VarOffset: 0x11A | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 9
L1 Substates | VarStore: PchSetup | VarOffset: 0x282 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 9
ACS | VarStore: PchSetup | VarOffset: 0x29A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
PTM | VarStore: PchSetup | VarOffset: 0x2B2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
DPC | VarStore: PchSetup | VarOffset: 0x2CA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
EDPC | VarStore: PchSetup | VarOffset: 0x2E2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
URR | VarStore: PchSetup | VarOffset: 0x132 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
FER | VarStore: PchSetup | VarOffset: 0x14A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
NFER | VarStore: PchSetup | VarOffset: 0x162 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
CER | VarStore: PchSetup | VarOffset: 0x17A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
SEFE | VarStore: PchSetup | VarOffset: 0x1C2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
SENFE | VarStore: PchSetup | VarOffset: 0x1DA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
SECE | VarStore: PchSetup | VarOffset: 0x1F2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
PME SCI | VarStore: PchSetup | VarOffset: 0x20A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
Hot Plug | VarStore: PchSetup | VarOffset: 0x222 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x23A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
PCIe Speed | VarStore: PchSetup | VarOffset: 0x252 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 9
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x26A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
Detect Timeout | VarStore: PchSetup | VarOffset: 0x31A | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 9
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x478 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 9
Reserved Memory | VarStore: PchSetup | VarOffset: 0x498 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 9
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4C0 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 9
LTR | VarStore: PchSetup | VarOffset: 0x36A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x39A | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 9
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x402 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 9
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3B2 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 9
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3CA | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 9
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x432 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 9
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3E2 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 9
Force LTR Override | VarStore: PchSetup | VarOffset: 0x45A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
LTR Lock | VarStore: PchSetup | VarOffset: 0x382 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
PCI Express Root Port 10 | VarStore: PchSetup | VarOffset: 0x103 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
Connection Type | VarStore: PchSetup | VarOffset: 0x2FB | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 10
ASPM | VarStore: PchSetup | VarOffset: 0x11B | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 10
L1 Substates | VarStore: PchSetup | VarOffset: 0x283 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 10
ACS | VarStore: PchSetup | VarOffset: 0x29B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
PTM | VarStore: PchSetup | VarOffset: 0x2B3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
DPC | VarStore: PchSetup | VarOffset: 0x2CB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
EDPC | VarStore: PchSetup | VarOffset: 0x2E3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
URR | VarStore: PchSetup | VarOffset: 0x133 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
FER | VarStore: PchSetup | VarOffset: 0x14B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
NFER | VarStore: PchSetup | VarOffset: 0x163 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
CER | VarStore: PchSetup | VarOffset: 0x17B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
SEFE | VarStore: PchSetup | VarOffset: 0x1C3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
SENFE | VarStore: PchSetup | VarOffset: 0x1DB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
SECE | VarStore: PchSetup | VarOffset: 0x1F3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
PME SCI | VarStore: PchSetup | VarOffset: 0x20B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
Hot Plug | VarStore: PchSetup | VarOffset: 0x223 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x23B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
PCIe Speed | VarStore: PchSetup | VarOffset: 0x253 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 10
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x26B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
Detect Timeout | VarStore: PchSetup | VarOffset: 0x31C | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 10
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x479 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 10
Reserved Memory | VarStore: PchSetup | VarOffset: 0x49A | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 10
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4C1 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 10
LTR | VarStore: PchSetup | VarOffset: 0x36B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x39B | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 10
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x404 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 10
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3B3 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 10
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3CB | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 10
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x434 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 10
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3E3 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 10
Force LTR Override | VarStore: PchSetup | VarOffset: 0x45B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
LTR Lock | VarStore: PchSetup | VarOffset: 0x383 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
PCI Express Root Port 11 | VarStore: PchSetup | VarOffset: 0x104 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
Connection Type | VarStore: PchSetup | VarOffset: 0x2FC | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 11
ASPM | VarStore: PchSetup | VarOffset: 0x11C | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 11
L1 Substates | VarStore: PchSetup | VarOffset: 0x284 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 11
ACS | VarStore: PchSetup | VarOffset: 0x29C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
PTM | VarStore: PchSetup | VarOffset: 0x2B4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
DPC | VarStore: PchSetup | VarOffset: 0x2CC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
EDPC | VarStore: PchSetup | VarOffset: 0x2E4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
URR | VarStore: PchSetup | VarOffset: 0x134 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
FER | VarStore: PchSetup | VarOffset: 0x14C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
NFER | VarStore: PchSetup | VarOffset: 0x164 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
CER | VarStore: PchSetup | VarOffset: 0x17C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
SEFE | VarStore: PchSetup | VarOffset: 0x1C4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
SENFE | VarStore: PchSetup | VarOffset: 0x1DC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
SECE | VarStore: PchSetup | VarOffset: 0x1F4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
PME SCI | VarStore: PchSetup | VarOffset: 0x20C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
Hot Plug | VarStore: PchSetup | VarOffset: 0x224 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x23C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
PCIe Speed | VarStore: PchSetup | VarOffset: 0x254 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 11
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x26C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
Detect Timeout | VarStore: PchSetup | VarOffset: 0x31E | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 11
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x47A | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 11
Reserved Memory | VarStore: PchSetup | VarOffset: 0x49C | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 11
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4C2 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 11
LTR | VarStore: PchSetup | VarOffset: 0x36C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x39C | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 11
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x406 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 11
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3B4 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 11
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3CC | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 11
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x436 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 11
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3E4 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 11
Force LTR Override | VarStore: PchSetup | VarOffset: 0x45C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
LTR Lock | VarStore: PchSetup | VarOffset: 0x384 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
PCI Express Root Port 12 | VarStore: PchSetup | VarOffset: 0x105 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
Connection Type | VarStore: PchSetup | VarOffset: 0x2FD | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 12
ASPM | VarStore: PchSetup | VarOffset: 0x11D | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 12
L1 Substates | VarStore: PchSetup | VarOffset: 0x285 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 12
ACS | VarStore: PchSetup | VarOffset: 0x29D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
PTM | VarStore: PchSetup | VarOffset: 0x2B5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
DPC | VarStore: PchSetup | VarOffset: 0x2CD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
EDPC | VarStore: PchSetup | VarOffset: 0x2E5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
URR | VarStore: PchSetup | VarOffset: 0x135 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
FER | VarStore: PchSetup | VarOffset: 0x14D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
NFER | VarStore: PchSetup | VarOffset: 0x165 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
CER | VarStore: PchSetup | VarOffset: 0x17D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
SEFE | VarStore: PchSetup | VarOffset: 0x1C5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
SENFE | VarStore: PchSetup | VarOffset: 0x1DD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
SECE | VarStore: PchSetup | VarOffset: 0x1F5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
PME SCI | VarStore: PchSetup | VarOffset: 0x20D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
Hot Plug | VarStore: PchSetup | VarOffset: 0x225 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x23D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
PCIe Speed | VarStore: PchSetup | VarOffset: 0x255 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 12
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x26D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
Detect Timeout | VarStore: PchSetup | VarOffset: 0x320 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 12
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x47B | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 12
Reserved Memory | VarStore: PchSetup | VarOffset: 0x49E | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 12
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4C3 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 12
LTR | VarStore: PchSetup | VarOffset: 0x36D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x39D | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 12
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x408 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 12
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3B5 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 12
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3CD | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 12
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x438 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 12
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3E5 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 12
Force LTR Override | VarStore: PchSetup | VarOffset: 0x45D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
LTR Lock | VarStore: PchSetup | VarOffset: 0x385 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
PCI Express Root Port 13 | VarStore: PchSetup | VarOffset: 0x106 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
Connection Type | VarStore: PchSetup | VarOffset: 0x2FE | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 13
ASPM | VarStore: PchSetup | VarOffset: 0x11E | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 13
L1 Substates | VarStore: PchSetup | VarOffset: 0x286 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 13
ACS | VarStore: PchSetup | VarOffset: 0x29E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
PTM | VarStore: PchSetup | VarOffset: 0x2B6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
DPC | VarStore: PchSetup | VarOffset: 0x2CE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
EDPC | VarStore: PchSetup | VarOffset: 0x2E6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
URR | VarStore: PchSetup | VarOffset: 0x136 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
FER | VarStore: PchSetup | VarOffset: 0x14E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
NFER | VarStore: PchSetup | VarOffset: 0x166 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
CER | VarStore: PchSetup | VarOffset: 0x17E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
SEFE | VarStore: PchSetup | VarOffset: 0x1C6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
SENFE | VarStore: PchSetup | VarOffset: 0x1DE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
SECE | VarStore: PchSetup | VarOffset: 0x1F6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
PME SCI | VarStore: PchSetup | VarOffset: 0x20E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
Hot Plug | VarStore: PchSetup | VarOffset: 0x226 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x23E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
PCIe Speed | VarStore: PchSetup | VarOffset: 0x256 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 13
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x26E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
Detect Timeout | VarStore: PchSetup | VarOffset: 0x322 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 13
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x47C | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 13
Reserved Memory | VarStore: PchSetup | VarOffset: 0x4A0 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 13
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4C4 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 13
LTR | VarStore: PchSetup | VarOffset: 0x36E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x39E | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 13
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x40A | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 13
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3B6 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 13
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3CE | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 13
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x43A | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 13
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3E6 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 13
Force LTR Override | VarStore: PchSetup | VarOffset: 0x45E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
LTR Lock | VarStore: PchSetup | VarOffset: 0x386 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
PCI Express Root Port 14 | VarStore: PchSetup | VarOffset: 0x107 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
Connection Type | VarStore: PchSetup | VarOffset: 0x2FF | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 14
ASPM | VarStore: PchSetup | VarOffset: 0x11F | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 14
L1 Substates | VarStore: PchSetup | VarOffset: 0x287 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 14
ACS | VarStore: PchSetup | VarOffset: 0x29F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
PTM | VarStore: PchSetup | VarOffset: 0x2B7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
DPC | VarStore: PchSetup | VarOffset: 0x2CF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
EDPC | VarStore: PchSetup | VarOffset: 0x2E7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
URR | VarStore: PchSetup | VarOffset: 0x137 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
FER | VarStore: PchSetup | VarOffset: 0x14F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
NFER | VarStore: PchSetup | VarOffset: 0x167 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
CER | VarStore: PchSetup | VarOffset: 0x17F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
SEFE | VarStore: PchSetup | VarOffset: 0x1C7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
SENFE | VarStore: PchSetup | VarOffset: 0x1DF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
SECE | VarStore: PchSetup | VarOffset: 0x1F7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
PME SCI | VarStore: PchSetup | VarOffset: 0x20F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
Hot Plug | VarStore: PchSetup | VarOffset: 0x227 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x23F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
PCIe Speed | VarStore: PchSetup | VarOffset: 0x257 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 14
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x26F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
Detect Timeout | VarStore: PchSetup | VarOffset: 0x324 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 14
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x47D | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 14
Reserved Memory | VarStore: PchSetup | VarOffset: 0x4A2 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 14
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4C5 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 14
LTR | VarStore: PchSetup | VarOffset: 0x36F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x39F | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 14
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x40C | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 14
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3B7 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 14
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3CF | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 14
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x43C | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 14
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3E7 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 14
Force LTR Override | VarStore: PchSetup | VarOffset: 0x45F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
LTR Lock | VarStore: PchSetup | VarOffset: 0x387 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
PCI Express Root Port 15 | VarStore: PchSetup | VarOffset: 0x108 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
Connection Type | VarStore: PchSetup | VarOffset: 0x300 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 15
ASPM | VarStore: PchSetup | VarOffset: 0x120 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 15
L1 Substates | VarStore: PchSetup | VarOffset: 0x288 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 15
ACS | VarStore: PchSetup | VarOffset: 0x2A0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
PTM | VarStore: PchSetup | VarOffset: 0x2B8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
DPC | VarStore: PchSetup | VarOffset: 0x2D0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
EDPC | VarStore: PchSetup | VarOffset: 0x2E8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
URR | VarStore: PchSetup | VarOffset: 0x138 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
FER | VarStore: PchSetup | VarOffset: 0x150 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
NFER | VarStore: PchSetup | VarOffset: 0x168 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
CER | VarStore: PchSetup | VarOffset: 0x180 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
SEFE | VarStore: PchSetup | VarOffset: 0x1C8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
SENFE | VarStore: PchSetup | VarOffset: 0x1E0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
SECE | VarStore: PchSetup | VarOffset: 0x1F8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
PME SCI | VarStore: PchSetup | VarOffset: 0x210 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
Hot Plug | VarStore: PchSetup | VarOffset: 0x228 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x240 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
PCIe Speed | VarStore: PchSetup | VarOffset: 0x258 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 15
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x270 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
Detect Timeout | VarStore: PchSetup | VarOffset: 0x326 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 15
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x47E | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 15
Reserved Memory | VarStore: PchSetup | VarOffset: 0x4A4 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 15
Reserved I/O | VarStore: PchSetup | VarOffset: 0x4C6 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 15
LTR | VarStore: PchSetup | VarOffset: 0x370 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3A0 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 15
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x40E | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 15
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3B8 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 15
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x3D0 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 15
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x43E | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 15
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x3E8 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 15
Force LTR Override | VarStore: PchSetup | VarOffset: 0x460 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
LTR Lock | VarStore: PchSetup | VarOffset: 0x388 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
PCI Express Root Port 16 | VarStore: PchSetup | VarOffset: 0x109 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
Connection Type | VarStore: PchSetup | VarOffset: 0x301 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 16
ASPM | VarStore: PchSetup | VarOffset: 0x121 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 16
L1 Substates | VarStore: PchSetup | VarOffset: 0x289 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 16
ACS | VarStore: PchSetup | VarOffset: 0x2A1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
PTM | VarStore: PchSetup | VarOffset: 0x2B9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
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