Makefile template for C

Makefile

PROJECT_NAME := TEMPLATE

CC ?= gcc
CFLAGS := -Wall -Wextra

OUT_PATH := ${PWD}/out
BIN_PATH := ${OUT_PATH}/bin
OBJ_PATH := ${OUT_PATH}/obj
SRC_PATH := ${PWD}/src

TARGET := ${BIN_PATH}/${PROJECT_NAME}
ifeq (${OS},Windows_NT)
	TARGET := $(addsuffix .exe,${TARGET})
endif

# https://stackoverflow.com/a/18258352
rwildcard=$(foreach d,$(wildcard $(1:=/*)),$(call rwildcard,$d,$2) $(filter $(subst *,%,$2),$d))

SRC_FILES := $(call rwildcard,${SRC_PATH}/,*.c)
OBJ_FILES := $(patsubst ${SRC_PATH}/%.c,${OBJ_PATH}/%.o,${SRC_FILES})

.PHONY: all clean

all: ${OBJ_FILES}
	@mkdir -p $(dir ${TARGET})
	@${CC} ${CFLAGS} -o ${TARGET} ${OBJ_FILES}

clean:
	@rm -rf ${OUT_PATH}

${OBJ_FILES}: ${OBJ_PATH}/%.o : ${SRC_PATH}/%.c
	@mkdir -p $(dir $@)
	@${CC} ${CFLAGS} -c -o $@ $<

All you really need to do is change PROJECT_NAME to what your project is. Nothing else.

The convention that this Makefile assumes is that all your code exists in a src/ directory.