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2007 IC Contest Cell-Based 大學 / 研究所初賽 - 題目 : Image Display Controller
Raw
lcd_ctrl.v
//############################################################################
// 2007 IC Contest preliminary round
// Topic : Image Display Controller
// Author : HsuChiChen ([email protected])
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Date : 2024.03.16
// Version : v1.0
// File Name : lcd_ctrl.v
// Module Name : lcd_ctrl
//############################################################################
// LCD controller module
// In TSMC 0.13um technology, latency is 1540 cycles, cycle time is 6ns, total cell area 25535 um^2
module LCD_CTRL(clk, reset, datain, cmd, cmd_valid, dataout, output_valid, busy);
// input ports
input clk;
input reset;
input [7:0] datain;
input [2:0] cmd;
input cmd_valid;
// output ports
output reg [7:0] dataout;
output reg output_valid;
output reg busy;
//==============================================//
// Parameter and Integer //
//==============================================//
parameter IDLE = 0,
CMD_IN = 1,
OUTPUT = 2,
LOAD = 3;
//==============================================//
// Wire and Register Declaration //
//==============================================//
reg [1:0] current_state, next_state; // 2-bit state
reg [5:0] counter; // 6-bit counter
reg [2:0] x_start, y_start; // x and y start position
reg [2:0] x_current, y_current; // pseudo-reg for x and y current position
reg [7:0] data_reg [0:63]; // 8*8 data register
reg [2:0] cmd_reg; // store command
reg zome_out; // zoom out or not
//==============================================//
// Update Current State //
//==============================================//
always @(posedge clk or posedge reset) begin
if(reset) current_state <= IDLE;
else current_state <= next_state;
end
//==============================================//
// Calculate Next State //
//==============================================//
always @(*) begin
case(current_state)
// wait for command
IDLE: begin
if(cmd_valid) next_state = CMD_IN;
else next_state = IDLE;
end
// read command
CMD_IN: begin
if(cmd_reg == 1) next_state = LOAD;
else next_state = OUTPUT;
end
// load data
LOAD: begin
if(counter == 63) next_state = OUTPUT;
else next_state = LOAD;
end
// output data
OUTPUT: begin
if(counter == 15) next_state = IDLE;
else next_state = OUTPUT;
end
default: next_state = IDLE;
endcase
end
//==============================================//
// Counter //
//==============================================//
always @(posedge clk or posedge reset) begin
if(reset) counter <= 0;
else if(next_state == LOAD || current_state == OUTPUT) counter <= counter + 1;
else counter <= 0;
end
//==============================================//
// Read Data from Data in //
//==============================================//
always @(posedge clk) begin
if(next_state == LOAD || current_state == LOAD) begin
data_reg[counter] <= datain;
end
end
//==============================================//
// Read command //
//==============================================//
always @(posedge clk) begin
if(cmd_valid) cmd_reg <= cmd;
end
//==============================================//
// X and Y Start Position //
//==============================================//
always @(posedge clk) begin
if(current_state == CMD_IN) begin
case(cmd_reg)
// Reflash
// No change
// Load Data
1: begin
x_start <= 0;
y_start <= 0;
zome_out <= 1; // zoom out
end
// Zoom In
2: begin
x_start <= 2;
y_start <= 2;
zome_out <= 0; // do not zoom out
end
// Zoom Out
3: begin
x_start <= 0;
y_start <= 0;
zome_out <= 1; // zoom out
end
// Shift Right
4: begin
if(zome_out == 1 || y_start == 4) begin
// No change in zoom out mode or y_start is upper bound
end else begin
x_start <= x_start;
y_start <= y_start + 1;
end
end
// Shift Left
5: begin
if(zome_out == 1 || y_start == 0) begin
// No change in zoom out mode or y_start is lower bound
end else begin
x_start <= x_start;
y_start <= y_start - 1;
end
end
// Shift Up
6: begin
if(zome_out == 1 || x_start == 0) begin
// No change in zoom out mode or x_start is lower bound
end else begin
x_start <= x_start - 1;
y_start <= y_start;
end
end
// Shift Down
7: begin
if(zome_out == 1 || x_start == 4) begin
// No change in zoom out mode or x_start is upper bound
end else begin
x_start <= x_start + 1;
y_start <= y_start;
end
end
endcase
end
end
//==============================================//
// X and Y Current Position //
//==============================================//
always @(*) begin
x_current = x_start + (counter / 4) * (zome_out + 1);
y_current = y_start + (counter % 4) * (zome_out + 1);
end
//==============================================//
// Output Logic //
//==============================================//
// output valid
always @(posedge clk or posedge reset) begin
if(reset) output_valid <= 0;
else if(current_state == OUTPUT) output_valid <= 1;
else output_valid <= 0;
end
// output data
always @(posedge clk or posedge reset) begin
if (reset) dataout <= 0;
else if(current_state == OUTPUT) dataout <= data_reg[x_current*8 + y_current]; // 8*8 data register
end
// busy
always @(posedge clk or posedge reset) begin
if(reset) busy <= 0;
else if(cmd_valid == 1) busy <= 1; // busy when command is valid
else if(current_state == IDLE) busy <= 0; // not busy when in IDLE state
end
endmodule
Raw
syn.log
# Read all Files
read_verilog lcd_ctrl.v
Loading db file '/home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db'
Loading db file '/home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/fast.db'
Loading db file '/usr/cad/synopsys/synthesis/2022.12/libraries/syn/dw_foundation.sldb'
Loading db file '/usr/cad/synopsys/synthesis/2022.12/libraries/syn/gtech.db'
Loading db file '/usr/cad/synopsys/synthesis/2022.12/libraries/syn/standard.sldb'
Loading link library 'slow'
Loading link library 'fast'
Loading link library 'gtech'
Loading verilog file '/home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl.v'
Detecting input file type automatically (-rtl or -netlist).
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl.v
Statistics for case statements in always block at line 55 in file
'/home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl.v'
===============================================
| Line | full/ parallel |
===============================================
| 56 | auto/auto |
===============================================
Statistics for case statements in always block at line 109 in file
'/home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl.v'
===============================================
| Line | full/ parallel |
===============================================
| 111 | no/auto |
===============================================
Inferred memory devices in process
in routine LCD_CTRL line 47 in file
'/home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| current_state_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine LCD_CTRL line 84 in file
'/home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| counter_reg | Flip-flop | 6 | Y | N | Y | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine LCD_CTRL line 93 in file
'/home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| data_reg_reg | Flip-flop | 512 | Y | N | N | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine LCD_CTRL line 102 in file
'/home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| cmd_reg_reg | Flip-flop | 3 | Y | N | N | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine LCD_CTRL line 109 in file
'/home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| x_start_reg | Flip-flop | 3 | Y | N | N | N | N | N | N |
| y_start_reg | Flip-flop | 3 | Y | N | N | N | N | N | N |
| zome_out_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine LCD_CTRL line 191 in file
'/home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| output_valid_reg | Flip-flop | 1 | N | N | Y | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine LCD_CTRL line 198 in file
'/home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| dataout_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine LCD_CTRL line 204 in file
'/home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| busy_reg | Flip-flop | 1 | N | N | Y | N | N | N | N |
===============================================================================
Statistics for MUX_OPs
======================================================
| block name/line | Inputs | Outputs | # sel inputs |
======================================================
| LCD_CTRL/200 | 64 | 8 | 6 |
======================================================
Presto compilation completed successfully.
Current design is now '/home/M12/chenneil90121/ic_contest_mock2/LCD_CTRL.db:LCD_CTRL'
Loaded 1 design.
Current design is 'LCD_CTRL'.
LCD_CTRL
current_design LCD_CTRL
Current design is 'LCD_CTRL'.
{LCD_CTRL}
link
Linking design 'LCD_CTRL'
Using the following designs and libraries:
--------------------------------------------------------------------------
LCD_CTRL /home/M12/chenneil90121/ic_contest_mock2/LCD_CTRL.db
slow (library) /home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db
fast (library) /home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/fast.db
dw_foundation.sldb (library) /usr/cad/synopsys/synthesis/2022.12/libraries/syn/dw_foundation.sldb
1
# Setting Clock Constraits
source -echo -verbose lcd_ctrl.sdc
# operating conditions and boundary conditions #
current_design LCD_CTRL
Current design is 'LCD_CTRL'.
{LCD_CTRL}
set cycle 6; #clock period defined by designer
6
set t_in 3; #input delay defined by designer
3
set t_out 1; #output delay defined by designer
1
create_clock -period $cycle [get_ports clk]
1
set_dont_touch_network [get_clocks clk]
1
set_clock_uncertainty -setup 0.1 [get_clocks clk]
1
set_clock_latency 0.5 [get_clocks clk]
1
set_input_delay $t_in -clock clk [all_inputs]
1
set_output_delay $t_out -clock clk [all_outputs]
1
set_load -pin_load 1 [all_outputs]
1
set_drive 1 [all_inputs]
1
set_operating_conditions -min_library fast -min fast -max_library slow -max slow
Using operating conditions 'slow' found in library 'slow'.
Using operating conditions 'fast' found in library 'fast'.
1
set_wire_load_model -name tsmc13_wl10 -library slow
1
1
# Synthesis all design
compile -map_effort high -area_effort high
Information: Checking out the license 'DesignWare'. (SEC-104)
Information: Evaluating DesignWare library utilization. (UISN-27)
============================================================================
| DesignWare Building Block Library | Version | Available |
============================================================================
| Basic DW Building Blocks | U-2022.12-DWBB_202212.0 | * |
| Licensed DW Building Blocks | U-2022.12-DWBB_202212.0 | * |
============================================================================
====================================================================================================
| Flow Information |
----------------------------------------------------------------------------------------------------
| Flow | Design Compiler NXT |
====================================================================================================
| Design Information | Value |
====================================================================================================
| Number of Scenarios | 0 |
| Leaf Cell Count | 799 |
| Number of User Hierarchies | 0 |
| Sequential Cell Count | 540 |
| Macro Count | 0 |
| Number of Power Domains | 0 |
| Number of Path Groups | 2 |
| Number of VT Class | 0 |
| Number of Clocks | 1 |
| Number of Dont Touch Cells | 67 |
| Number of Dont Touch Nets | 1 |
| Number of Size Only Cells | 0 |
| Design with UPF Data | false |
====================================================================================================
Information: There are 6 potential problems in your design. Please run 'check_design' for more information. (LINT-99)
Warning: Operating condition slow set on design LCD_CTRL has different process,
voltage and temperatures parameters than the parameters at which target library
fast is characterized. Delays may be inaccurate as a result. (OPT-998)
Beginning Pass 1 Mapping
------------------------
Processing 'LCD_CTRL'
Updating timing information
Information: Updating design information... (UID-85)
Beginning Implementation Selection
----------------------------------
Processing 'LCD_CTRL_DW01_inc_0_DW01_inc_3'
Building model 'DW01_NAND2'
Processing 'DW01_NAND2'
Building model 'DW01_add_width3' (rpl)
Processing 'DW01_add_width3'
Building model 'DW01_add_width6' (rpl)
Processing 'DW01_add_width6'
Processing 'DW01_add_width3_DW01_add_0'
Mapping 'LCD_CTRL_DW_mult_uns_0'
Mapping 'DW_mult_uns'
Information: Added key list 'DesignWare' to design 'dp_cluster_1_2'. (DDB-72)
Processing 'LCD_CTRL_DW01_add_0_DW01_add_1'
Processing 'DW01_add_width3_DW01_add_2'
Information: Added key list 'DesignWare' to design 'LCD_CTRL'. (DDB-72)
Beginning Mapping Optimizations (High effort)
-------------------------------
Loading db file '/home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/fast.db'
TOTAL
ELAPSED WORST NEG SETUP DESIGN
TIME AREA SLACK COST RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:05 54060.5 0.00 0.0 7479.7
0:00:05 54060.5 0.00 0.0 7479.7
0:00:05 54060.5 0.00 0.0 7479.7
0:00:05 54060.5 0.00 0.0 7479.7
0:00:05 54060.5 0.00 0.0 7479.7
0:00:06 25842.9 1.40 544.6 7451.8
0:00:07 26005.9 1.08 446.2 7451.8
0:00:07 25946.5 0.99 482.2 7451.8
0:00:07 26019.4 0.63 274.9 7451.8
0:00:07 26056.8 0.52 223.1 7451.8
0:00:07 26146.7 0.73 220.6 7451.8
0:00:07 26179.0 0.48 217.9 7451.8
0:00:08 26196.0 0.37 157.2 7451.8
0:00:08 26168.8 0.37 151.3 7451.8
0:00:08 26190.9 0.37 148.3 7451.8
0:00:08 26202.8 0.34 135.1 7451.8
0:00:08 26229.9 0.32 123.3 7451.8
0:00:08 26257.1 0.21 72.7 7451.8
0:00:08 26260.5 0.21 69.4 7451.8
0:00:08 26265.6 0.21 64.3 7451.8
0:00:08 26269.0 0.21 60.9 7451.8
0:00:08 26272.4 0.21 57.6 7451.8
0:00:08 26274.1 0.21 55.9 7451.8
0:00:08 26279.1 0.21 50.8 7451.8
0:00:08 26279.1 0.21 50.8 7451.8
0:00:08 26279.1 0.21 50.8 7451.8
0:00:08 26364.0 0.40 52.0 1519.7
0:00:08 26408.1 0.21 50.4 1502.4
0:00:08 26435.3 0.21 50.4 22.6
0:00:08 26438.7 0.21 50.4 11.2
0:00:08 26482.8 0.21 49.6 0.0
0:00:08 26482.8 0.21 49.6 0.0
0:00:08 26482.8 0.21 49.6 0.0
0:00:08 26482.8 0.21 49.6 0.0
0:00:08 26533.8 0.16 11.6 0.0 data_reg_reg[39][7]/D
0:00:09 26562.6 0.00 0.0 0.0
Beginning Delay Optimization Phase
----------------------------------
TOTAL
ELAPSED WORST NEG SETUP DESIGN
TIME AREA SLACK COST RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:09 26562.6 0.00 0.0 0.0
0:00:09 26562.6 0.00 0.0 0.0
0:00:09 26515.1 0.00 0.0 940.9
Beginning Design Rule Fixing (max_transition) (max_capacitance)
----------------------------
TOTAL
ELAPSED WORST NEG SETUP DESIGN
TIME AREA SLACK COST RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:09 26515.1 0.00 0.0 940.9
0:00:09 26530.4 0.00 0.0 0.0
Beginning Area-Recovery Phase (cleanup)
-----------------------------
TOTAL
ELAPSED WORST NEG SETUP DESIGN
TIME AREA SLACK COST RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:09 26530.4 0.00 0.0 0.0
0:00:09 26530.4 0.00 0.0 0.0
0:00:09 26252.0 0.00 0.0 0.0
0:00:09 26056.8 0.05 0.1 0.0
0:00:09 25898.9 0.00 0.0 0.0
0:00:09 25837.8 0.00 0.0 0.0
0:00:09 25776.7 0.00 0.0 0.0
0:00:09 25776.7 0.00 0.0 0.0
0:00:09 25776.7 0.00 0.0 0.0
0:00:09 25564.5 0.10 0.3 0.0
0:00:09 25561.1 0.10 0.3 0.0
0:00:09 25561.1 0.10 0.3 0.0
0:00:09 25561.1 0.10 0.3 0.0
0:00:09 25561.1 0.10 0.3 0.0
0:00:09 25561.1 0.10 0.3 0.0
0:00:09 25561.1 0.10 0.3 0.0
0:00:09 25566.2 0.00 0.0 0.0
Loading db file '/home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db'
Note: Symbol # after min delay cost means estimated hold TNS across all active scenarios
Optimization Complete
---------------------
1
compile -map_effort high -area_effort high -inc
====================================================================================================
| Flow Information |
----------------------------------------------------------------------------------------------------
| Flow | Design Compiler NXT |
====================================================================================================
| Design Information | Value |
====================================================================================================
| Number of Scenarios | 0 |
| Leaf Cell Count | 1732 |
| Number of User Hierarchies | 0 |
| Sequential Cell Count | 540 |
| Macro Count | 0 |
| Number of Power Domains | 0 |
| Number of Path Groups | 2 |
| Number of VT Class | 0 |
| Number of Clocks | 1 |
| Number of Dont Touch Cells | 0 |
| Number of Dont Touch Nets | 1 |
| Number of Size Only Cells | 0 |
| Design with UPF Data | false |
====================================================================================================
Warning: Operating condition slow set on design LCD_CTRL has different process,
voltage and temperatures parameters than the parameters at which target library
fast is characterized. Delays may be inaccurate as a result. (OPT-998)
Beginning Pass 1 Mapping (Incremental)
------------------------
Updating timing information
Information: Updating design information... (UID-85)
Beginning Mapping Optimizations (High effort) (Incremental)
-------------------------------
Beginning Incremental Implementation Selection
----------------------------------------------
Beginning Delay Optimization Phase
----------------------------------
TOTAL
ELAPSED WORST NEG SETUP DESIGN
TIME AREA SLACK COST RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:01 25566.2 0.00 0.0 0.0
0:00:01 25566.2 0.00 0.0 0.0
0:00:02 25440.6 0.00 0.0 6370.2
Beginning Design Rule Fixing (max_transition) (max_capacitance)
----------------------------
TOTAL
ELAPSED WORST NEG SETUP DESIGN
TIME AREA SLACK COST RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:02 25440.6 0.00 0.0 6370.2
0:00:02 25535.7 0.00 0.0 0.0
Loading db file '/home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/fast.db'
Loading db file '/home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db'
Note: Symbol # after min delay cost means estimated hold TNS across all active scenarios
Optimization Complete
---------------------
1
write -format ddc -hierarchy -output "lcd_ctrl.ddc"
Writing ddc file 'lcd_ctrl.ddc'.
1
write_sdf lcd_ctrl.sdf
Information: Annotated 'cell' delays are assumed to include load delay. (UID-282)
Information: Writing timing information to file '/home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl.sdf'. (WT-3)
Information: Updating design information... (UID-85)
1
write_file -format verilog -hierarchy -output lcd_ctrl_syn.v
Writing verilog file '/home/M12/chenneil90121/ic_contest_mock2/lcd_ctrl_syn.v'.
1
report_area > area.log
report_timing > timing.log
report_qor > lcd_ctrl.qor
report_area -designware -hierarchy
****************************************
Report : area
Design : LCD_CTRL
Version: U-2022.12
Date : Sat Mar 16 14:55:25 2024
****************************************
Library(s) Used:
slow (File: /home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db)
Number of ports: 24
Number of nets: 1770
Number of cells: 1734
Number of combinational cells: 1193
Number of sequential cells: 540
Number of macros/black boxes: 0
Number of buf/inv: 162
Number of references: 83
Combinational area: 11537.227515
Buf/Inv area: 1161.021621
Noncombinational area: 13998.458017
Macro/Black Box area: 0.000000
Net Interconnect area: 242574.579620
Total cell area: 25535.685532
Total area: 268110.265152
Hierarchical area distribution
------------------------------
Global cell area Local cell area
------------------- ------------------------------
Hierarchical cell Absolute Percent Combi- Noncombi- Black-
Total Total national national boxes Design
-------------------------------- ---------- ------- ---------- ---------- ------ ---------
LCD_CTRL 25535.6855 100.0 11537.2275 13998.4580 0.0000 LCD_CTRL
-------------------------------- ---------- ------- ---------- ---------- ------ ---------
Total 11537.2275 13998.4580 0.0000
Area of detected synthetic parts
--------------------------------
No DW parts to report!
Estimated area of ungrouped synthetic parts
-------------------------------------------
Estimated Perc. of
Module Implem. Count Area cell area
----------- ------- ----- ---------- ---------
DW01_add rpl 2 115.3884 0.5%
DW01_dec rpl 2 47.5618 0.2%
DW01_inc rpl 4 182.6162 0.7%
DW_mult_uns apparch 2 56.5721 0.2%
----------- ------- ----- ---------- ---------
Total: 10 402.1385 1.6%
Total synthetic cell area: 402.1385 1.6% (estimated)
1
report_timing
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : LCD_CTRL
Version: U-2022.12
Date : Sat Mar 16 14:55:25 2024
****************************************
Operating Conditions: slow Library: slow
Wire Load Model Mode: top
Startpoint: cmd_valid (input port clocked by clk)
Endpoint: data_reg_reg[32][0]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
LCD_CTRL tsmc13_wl10 slow
Point Incr Path
-----------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.50 0.50
input external delay 3.00 3.50 r
cmd_valid (in) 0.07 3.57 r
U971/Y (AOI33X2) 0.15 3.72 f
U730/Y (AND2X2) 0.35 4.07 f
U891/Y (OR2X8) 0.19 4.26 f
U708/Y (NAND2X6) 0.09 4.36 r
U848/Y (AND2X4) 0.20 4.56 r
U990/Y (AND3X2) 0.52 5.08 r
U796/Y (NAND2XL) 0.29 5.37 f
U795/Y (BUFX4) 0.41 5.78 f
U1337/Y (OAI2BB2XL) 0.35 6.13 f
data_reg_reg[32][0]/D (DFFQXL) 0.00 6.13 f
data arrival time 6.13
clock clk (rise edge) 6.00 6.00
clock network delay (ideal) 0.50 6.50
clock uncertainty -0.10 6.40
data_reg_reg[32][0]/CK (DFFQXL) 0.00 6.40 r
library setup time -0.27 6.13
data required time 6.13
-----------------------------------------------------------
data required time 6.13
data arrival time -6.13
-----------------------------------------------------------
slack (MET) 0.00
1
exit
Memory usage for this session 202 Mbytes.
Memory usage for this session including child processes 202 Mbytes.
CPU usage for this session 19 seconds ( 0.01 hours ).
Elapsed time for this session 20 seconds ( 0.01 hours ).
Thank you...
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