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2019 IC Contest Cell-Based 研究所決賽 - 題目 : IoT Data Filtering (未優化版本)
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| //############################################################################ | |
| // 2019 IC Contest graduate group final round | |
| // Topic : IoT Data Filtering | |
| // Author : HsuChiChen ([email protected]) | |
| //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | |
| // Date : 2024.03.23 | |
| // Version : v1.0 | |
| // File Name : IOTDF.v | |
| // Module Name : IOTDF | |
| //############################################################################ | |
| // In TSMC 0.13um technology, latency is 10764 cycles, cycle time is 2.5ns, total cell area 85088 um^2 | |
| // latency is sum of TB1 + TB2 + TB3 + TB4 + TB5 + TB6 + TB7 = 1539 + 1539 + 1539 + 1536 + 1539 + 153 6+ 1536 = 10764 cycles | |
| // latency is minimum value because busy is always 0 | |
| module IOTDF( clk, rst, in_en, iot_in, fn_sel, busy, valid, iot_out); | |
| //==============================================// | |
| // Input & Output Declaration // | |
| //==============================================// | |
| // Input Ports | |
| input clk; | |
| input rst; | |
| input in_en; | |
| input [7:0] iot_in; | |
| input [2:0] fn_sel; | |
| // Output Ports | |
| output busy; | |
| output reg valid; | |
| output reg [127:0] iot_out; | |
| //==============================================// | |
| // Parameter and Integer // | |
| //==============================================// | |
| // 7 functions for data filtering | |
| parameter MAX = 3'b001; // Max(N) | |
| parameter MIN = 3'b010; // Min(N) | |
| parameter AVG = 3'b011; // Avg(N) | |
| parameter EXTRACT = 3'b100; // Extract (low < data < high) | |
| parameter EXCLUDE = 3'b101; // Exclude (data<low , high<data) | |
| parameter PEAK_MAX = 3'b110; // PeakMax (the data is greater than any previously output values) | |
| parameter PEAK_MIN = 3'b111; // PeakMin (the data is smaller than any previously output values) | |
| // In max or min mode | |
| parameter MIN_VALUE = 128'h0000_0000_0000_0000_0000_0000_0000_0000; | |
| parameter MIN_VALUE_PLUS1 = 128'h0000_0000_0000_0000_0000_0000_0000_0001; | |
| parameter MAX_VALUE = 128'hFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF; | |
| parameter MAX_VALUE_MINUS1 = 128'hFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFE; | |
| // In extract mode | |
| parameter EXTRACT_LOW = 128'h6FFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF; | |
| parameter EXTRACT_HIGH = 128'hAFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF; | |
| // In exclude mode | |
| parameter EXCLUDE_LOW = 128'h7FFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF; | |
| parameter EXCLUDE_HIGH = 128'hBFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF; | |
| //==============================================// | |
| // reg declaration // | |
| //==============================================// | |
| // 16 byte * 8 data * 12 round = 1536 < 2^11 | |
| // 4-bit counter_byte counter[3:0] for iot_in , max value is 15 | |
| // 3-bit counter_data counter[6:4] for iot_data, max value is 7 | |
| // 4-bit counter_round counter[10:7] for round, max value is 12 | |
| reg [10:0] counter; | |
| reg [10:0] counter_delay; | |
| reg [10:0] counter_delay2; | |
| // 128-bit data register | |
| reg [127:0] iot_data; | |
| reg [127:0] iot_data_delay; | |
| // max, min, sum value | |
| reg [127:0] max; | |
| reg [127:0] min; | |
| reg [130:0] sum; // max 127*8 = 1016, more 3 bits | |
| // whether the data is in the range of extract or exclude | |
| reg extract_flag; | |
| reg exclude_flag; | |
| // peak max, peak min | |
| reg [127:0] peak_max; | |
| reg [127:0] peak_min; | |
| // whether the data is peak max or peak min | |
| wire peak_max_flag; | |
| wire peak_min_flag; | |
| //==============================================// | |
| // Delayed Signal Declaration // | |
| //==============================================// | |
| always @(posedge clk) begin | |
| // add dummy mux to avoid timing violation | |
| if(in_en) begin | |
| counter_delay <= counter; | |
| counter_delay2 <= counter_delay; | |
| end | |
| end | |
| always @(posedge clk) begin | |
| // add dummy mux to avoid timing violation | |
| if(fn_sel == EXTRACT || fn_sel == EXCLUDE) begin | |
| iot_data_delay <= iot_data; | |
| end | |
| end | |
| //==============================================// | |
| // counter for iot_in // | |
| //==============================================// | |
| always @(posedge clk or posedge rst) begin | |
| if(rst) begin | |
| counter <= 0; | |
| end else if(in_en) begin | |
| if (counter == 1535) counter <= 0; | |
| else counter <= counter + 1; | |
| end | |
| end | |
| //==============================================// | |
| // Read iot_in data // | |
| //==============================================// | |
| always @(posedge clk or posedge rst) begin | |
| if(rst) begin | |
| iot_data <= 0; | |
| end else if(in_en) begin | |
| iot_data[7:0] <= iot_in; | |
| // shift register | |
| iot_data[127:8] <= iot_data[119:0]; | |
| end | |
| end | |
| //==============================================// | |
| // Updat Max Value and Min Value // | |
| //==============================================// | |
| // update max value | |
| always @(posedge clk or posedge rst) begin | |
| if(rst) begin | |
| max <= MIN_VALUE_PLUS1; | |
| // input enable | |
| end else if(in_en) begin | |
| // In max mode | |
| if(fn_sel == MAX || fn_sel == PEAK_MAX) begin | |
| // read iot_data every 16 cycles | |
| if (counter_delay[3:0] == 15) begin | |
| // update max value in the first round or iot_data > max | |
| if(counter_delay[6:4] == 0 || iot_data > max) max <= iot_data; | |
| end | |
| // Other modes will reset max | |
| end else begin | |
| max <= MIN_VALUE_PLUS1; | |
| end | |
| end | |
| end | |
| // update min value | |
| always @(posedge clk or posedge rst) begin | |
| if(rst) begin | |
| min <= MAX_VALUE; | |
| // input enable | |
| end else if(in_en) begin | |
| // In min mode | |
| if(fn_sel == MIN || fn_sel == PEAK_MIN) begin | |
| // read iot_data every 16 cycles | |
| if (counter_delay[3:0] == 15) begin | |
| // update min value in the first round or iot_data < min | |
| if(counter_delay[6:4] == 0 || iot_data < min) min <= iot_data; | |
| end | |
| // Other modes will reset min | |
| end else begin | |
| min <= MAX_VALUE; | |
| end | |
| end | |
| end | |
| //==============================================// | |
| // Calculate Sum // | |
| //==============================================// | |
| always @(posedge clk or posedge rst) begin | |
| if(rst) begin | |
| sum <= 0; | |
| end else begin | |
| // end else if(in_en) begin | |
| // In avg mode | |
| // if(fn_sel == AVG) begin | |
| // read iot_data every 16 cycles | |
| if (counter_delay[3:0] == 15) begin | |
| if(counter_delay[6:4] == 0) begin | |
| sum <= iot_data; // initial sum | |
| end else begin | |
| sum <= sum + iot_data; | |
| end | |
| end | |
| // Other modes will reset sum | |
| // end else begin | |
| // sum <= 0; | |
| // end | |
| end | |
| end | |
| //==============================================// | |
| // Flag for Extract and Exclude // | |
| //==============================================// | |
| always @(posedge clk) begin | |
| extract_flag <= (EXTRACT_LOW < iot_data) && (iot_data < EXTRACT_HIGH); | |
| exclude_flag <= (iot_data < EXCLUDE_LOW) || (EXCLUDE_HIGH < iot_data); | |
| end | |
| //==============================================// | |
| // Update Peak Max and Peak Min Value // | |
| //==============================================// | |
| // update peak max value | |
| always @(posedge clk or posedge rst) begin | |
| if(rst) begin | |
| peak_max <= MIN_VALUE; | |
| end else if(in_en) begin | |
| // In peak max mode | |
| if(fn_sel == PEAK_MAX) begin | |
| // check each round (ie 16 cycles * 8 data = 128 cycles) | |
| if (counter_delay2[6:0] == 127) begin | |
| // update peak max value | |
| if(max > peak_max) peak_max <= max; | |
| end | |
| // Other modes will reset peak max | |
| end else begin | |
| peak_max <= MIN_VALUE; | |
| end | |
| end | |
| end | |
| // update peak min value | |
| always @(posedge clk or posedge rst) begin | |
| if(rst) begin | |
| peak_min <= MAX_VALUE_MINUS1; | |
| end else if(in_en) begin | |
| // In peak min mode | |
| if(fn_sel == PEAK_MIN) begin | |
| // check each round (ie 16 cycles * 8 data = 128 cycles) | |
| if (counter_delay2[6:0] == 127) begin | |
| // update peak min value | |
| if(min < peak_min) peak_min <= min; | |
| end | |
| // Other modes will reset peak min | |
| end else begin | |
| peak_min <= MAX_VALUE_MINUS1; | |
| end | |
| end | |
| end | |
| // Whether the data is peak max or peak min | |
| assign peak_max_flag = max > peak_max; | |
| assign peak_min_flag = min < peak_min; | |
| //==============================================// | |
| // Output Block // | |
| //==============================================// | |
| // busy always 0 | |
| assign busy = 0; | |
| // valid | |
| always @(posedge clk or posedge rst) begin | |
| if(rst) begin | |
| valid <= 0; | |
| end else if(in_en) begin | |
| case(fn_sel) | |
| // In max mode | |
| MAX: begin | |
| // output max value every round (ie 16 cycles * 8 data = 128 cycles) | |
| if (counter_delay2[6:0] == 127) begin | |
| valid <= 1; | |
| end else begin | |
| valid <= 0; | |
| end | |
| end | |
| // In min mode | |
| MIN: begin | |
| // output min value every round (ie 16 cycles * 8 data = 128 cycles) | |
| if (counter_delay2[6:0] == 127) begin | |
| valid <= 1; | |
| end else begin | |
| valid <= 0; | |
| end | |
| end | |
| // In avg mode | |
| AVG: begin | |
| // output avg value every round (ie 16 cycles * 8 data = 128 cycles) | |
| if (counter_delay2[6:0] == 127) begin | |
| valid <= 1; | |
| end else begin | |
| valid <= 0; | |
| end | |
| end | |
| // In extract mode | |
| EXTRACT: begin | |
| // output extract value every iot_data (ie 16 cycles) | |
| if (counter_delay2[3:0] == 15) begin | |
| valid <= extract_flag; | |
| end else begin | |
| valid <= 0; | |
| end | |
| end | |
| // In exclude mode | |
| EXCLUDE: begin | |
| // output exclude value every iot_data (ie 16 cycles) | |
| if (counter_delay2[3:0] == 15) begin | |
| valid <= exclude_flag; | |
| end else begin | |
| valid <= 0; | |
| end | |
| end | |
| // In peak max mode | |
| PEAK_MAX: begin | |
| // output peak max value every round (ie 16 cycles * 8 data = 128 cycles) | |
| if (counter_delay2[6:0] == 127) begin | |
| valid <= peak_max_flag; | |
| end else begin | |
| valid <= 0; | |
| end | |
| end | |
| // In peak min mode | |
| PEAK_MIN: begin | |
| // output peak min value every round (ie 16 cycles * 8 data = 128 cycles) | |
| if (counter_delay2[6:0] == 127) begin | |
| valid <= peak_min_flag; | |
| end else begin | |
| valid <= 0; | |
| end | |
| end | |
| // Other modes | |
| default: begin | |
| valid <= 0; | |
| end | |
| endcase | |
| end | |
| end | |
| // iot_out | |
| always @(posedge clk or posedge rst) begin | |
| if(rst) begin | |
| iot_out <= 0; | |
| end else if(in_en) begin | |
| case(fn_sel) | |
| // In max mode | |
| MAX: begin | |
| // output max value every round (ie 16 cycles * 8 data = 128 cycles) | |
| if (counter_delay2[6:0] == 127) begin | |
| iot_out <= max; | |
| end | |
| end | |
| // In min mode | |
| MIN: begin | |
| // output min value every round (ie 16 cycles * 8 data = 128 cycles) | |
| if (counter_delay2[6:0] == 127) begin | |
| iot_out <= min; | |
| end | |
| end | |
| // In avg mode | |
| AVG: begin | |
| // output avg value every round (ie 16 cycles * 8 data = 128 cycles) | |
| if (counter_delay2[6:0] == 127) begin | |
| iot_out <= sum >> 3; // avg = sum / 8 | |
| end | |
| end | |
| // In extract mode | |
| EXTRACT: begin | |
| // output extract value every iot_data (ie 16 cycles) | |
| if (counter_delay2[3:0] == 15) begin | |
| iot_out <= iot_data_delay; | |
| end | |
| end | |
| // In exclude mode | |
| EXCLUDE: begin | |
| // output exclude value every iot_data (ie 16 cycles) | |
| if (counter_delay2[3:0] == 15) begin | |
| iot_out <= iot_data_delay; | |
| end | |
| end | |
| // In peak max mode | |
| PEAK_MAX: begin | |
| // output peak max value every round (ie 16 cycles * 8 data = 128 cycles) | |
| if (counter_delay2[6:0] == 127) begin | |
| iot_out <= max; | |
| end | |
| end | |
| // In peak min mode | |
| PEAK_MIN: begin | |
| // output peak min value every round (ie 16 cycles * 8 data = 128 cycles) | |
| if (counter_delay2[6:0] == 127) begin | |
| iot_out <= min; | |
| end | |
| end | |
| // Other modes | |
| default: begin | |
| iot_out <= 1'b0; | |
| end | |
| endcase | |
| end | |
| end | |
| endmodule |
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| # Read all Files | |
| read_verilog IOTDF.v | |
| Loading db file '/home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db' | |
| Loading db file '/usr/cad/synopsys/synthesis/2022.12/libraries/syn/dw_foundation.sldb' | |
| Loading db file '/usr/cad/synopsys/synthesis/2022.12/libraries/syn/gtech.db' | |
| Loading db file '/usr/cad/synopsys/synthesis/2022.12/libraries/syn/standard.sldb' | |
| Loading link library 'slow' | |
| Loading link library 'gtech' | |
| Loading verilog file '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v' | |
| Detecting input file type automatically (-rtl or -netlist). | |
| Reading with Presto HDL Compiler (equivalent to -rtl option). | |
| Running PRESTO HDLC | |
| Compiling source file /home/M12/chenneil90121/ic_contest_mock3/IOTDF.v | |
| Statistics for case statements in always block at line 256 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v' | |
| =============================================== | |
| | Line | full/ parallel | | |
| =============================================== | |
| | 260 | auto/auto | | |
| =============================================== | |
| Statistics for case statements in always block at line 333 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v' | |
| =============================================== | |
| | Line | full/ parallel | | |
| =============================================== | |
| | 337 | auto/auto | | |
| =============================================== | |
| Inferred memory devices in process | |
| in routine IOTDF line 90 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'. | |
| =============================================================================== | |
| | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | | |
| =============================================================================== | |
| | counter_delay_reg | Flip-flop | 7 | Y | N | N | N | N | N | N | | |
| | counter_delay2_reg | Flip-flop | 7 | Y | N | N | N | N | N | N | | |
| =============================================================================== | |
| Inferred memory devices in process | |
| in routine IOTDF line 97 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'. | |
| =============================================================================== | |
| | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | | |
| =============================================================================== | |
| | iot_data_delay_reg | Flip-flop | 128 | Y | N | N | N | N | N | N | | |
| =============================================================================== | |
| Inferred memory devices in process | |
| in routine IOTDF line 106 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'. | |
| =============================================================================== | |
| | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | | |
| =============================================================================== | |
| | counter_reg | Flip-flop | 11 | Y | N | Y | N | N | N | N | | |
| =============================================================================== | |
| Inferred memory devices in process | |
| in routine IOTDF line 118 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'. | |
| =============================================================================== | |
| | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | | |
| =============================================================================== | |
| | iot_data_reg | Flip-flop | 128 | Y | N | Y | N | N | N | N | | |
| =============================================================================== | |
| Inferred memory devices in process | |
| in routine IOTDF line 132 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'. | |
| =============================================================================== | |
| | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | | |
| =============================================================================== | |
| | max_reg | Flip-flop | 127 | Y | N | Y | N | N | N | N | | |
| | max_reg | Flip-flop | 1 | N | N | N | Y | N | N | N | | |
| =============================================================================== | |
| Inferred memory devices in process | |
| in routine IOTDF line 152 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'. | |
| =============================================================================== | |
| | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | | |
| =============================================================================== | |
| | min_reg | Flip-flop | 128 | Y | N | N | Y | N | N | N | | |
| =============================================================================== | |
| Inferred memory devices in process | |
| in routine IOTDF line 174 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'. | |
| =============================================================================== | |
| | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | | |
| =============================================================================== | |
| | sum_reg | Flip-flop | 131 | Y | N | Y | N | N | N | N | | |
| =============================================================================== | |
| Inferred memory devices in process | |
| in routine IOTDF line 199 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'. | |
| =============================================================================== | |
| | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | | |
| =============================================================================== | |
| | exclude_flag_reg | Flip-flop | 1 | N | N | N | N | N | N | N | | |
| | extract_flag_reg | Flip-flop | 1 | N | N | N | N | N | N | N | | |
| =============================================================================== | |
| Inferred memory devices in process | |
| in routine IOTDF line 208 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'. | |
| =============================================================================== | |
| | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | | |
| =============================================================================== | |
| | peak_max_reg | Flip-flop | 128 | Y | N | Y | N | N | N | N | | |
| =============================================================================== | |
| Inferred memory devices in process | |
| in routine IOTDF line 227 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'. | |
| =============================================================================== | |
| | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | | |
| =============================================================================== | |
| | peak_min_reg | Flip-flop | 127 | Y | N | N | Y | N | N | N | | |
| | peak_min_reg | Flip-flop | 1 | N | N | Y | N | N | N | N | | |
| =============================================================================== | |
| Inferred memory devices in process | |
| in routine IOTDF line 256 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'. | |
| =============================================================================== | |
| | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | | |
| =============================================================================== | |
| | valid_reg | Flip-flop | 1 | N | N | Y | N | N | N | N | | |
| =============================================================================== | |
| Inferred memory devices in process | |
| in routine IOTDF line 333 in file | |
| '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.v'. | |
| =============================================================================== | |
| | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | | |
| =============================================================================== | |
| | iot_out_reg | Flip-flop | 128 | Y | N | Y | N | N | N | N | | |
| =============================================================================== | |
| Presto compilation completed successfully. | |
| Current design is now '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.db:IOTDF' | |
| Loaded 1 design. | |
| Current design is 'IOTDF'. | |
| IOTDF | |
| current_design IOTDF | |
| Current design is 'IOTDF'. | |
| {IOTDF} | |
| link | |
| Linking design 'IOTDF' | |
| Using the following designs and libraries: | |
| -------------------------------------------------------------------------- | |
| IOTDF /home/M12/chenneil90121/ic_contest_mock3/IOTDF.db | |
| slow (library) /home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db | |
| dw_foundation.sldb (library) /usr/cad/synopsys/synthesis/2022.12/libraries/syn/dw_foundation.sldb | |
| 1 | |
| # Setting Clock Constraits | |
| source -echo -verbose IOTDF_DC.sdc | |
| # operating conditions and boundary conditions # | |
| create_clock -name clk -period 2.5 [get_ports clk] ;#Modify period by yourself | |
| 1 | |
| set_dont_touch_network [all_clocks] | |
| 1 | |
| set_fix_hold [all_clocks] | |
| 1 | |
| set_clock_uncertainty 0.1 [all_clocks] | |
| 1 | |
| set_clock_latency 1.0 [all_clocks] | |
| 1 | |
| set_ideal_network [get_ports clk] | |
| 1 | |
| #Don't touch the basic env setting as below | |
| set_input_delay -max 1.0 -clock clk [remove_from_collection [all_inputs] {clk}] | |
| 1 | |
| set_input_delay -min 0.0 -clock clk [remove_from_collection [all_inputs] {clk}] | |
| 1 | |
| set_output_delay -max 1.0 -clock clk [all_outputs] | |
| 1 | |
| set_output_delay -min 0.0 -clock clk [all_outputs] | |
| 1 | |
| set_load 0.01 [all_outputs] | |
| 1 | |
| set_drive 0.1 [all_inputs] | |
| 1 | |
| set_operating_conditions -max_library slow -max slow | |
| Using operating conditions 'slow' found in library 'slow'. | |
| 1 | |
| set_max_fanout 10 [all_inputs] | |
| 1 | |
| 1 | |
| # Synthesis all design | |
| compile -map_effort high -area_effort high | |
| Information: Checking out the license 'DesignWare'. (SEC-104) | |
| Information: Evaluating DesignWare library utilization. (UISN-27) | |
| ============================================================================ | |
| | DesignWare Building Block Library | Version | Available | | |
| ============================================================================ | |
| | Basic DW Building Blocks | U-2022.12-DWBB_202212.0 | * | | |
| | Licensed DW Building Blocks | U-2022.12-DWBB_202212.0 | * | | |
| ============================================================================ | |
| ==================================================================================================== | |
| | Flow Information | | |
| ---------------------------------------------------------------------------------------------------- | |
| | Flow | Design Compiler NXT | | |
| ==================================================================================================== | |
| | Design Information | Value | | |
| ==================================================================================================== | |
| | Number of Scenarios | 0 | | |
| | Leaf Cell Count | 1318 | | |
| | Number of User Hierarchies | 0 | | |
| | Sequential Cell Count | 1055 | | |
| | Macro Count | 0 | | |
| | Number of Power Domains | 0 | | |
| | Number of Path Groups | 2 | | |
| | Number of VT Class | 0 | | |
| | Number of Clocks | 1 | | |
| | Number of Dont Touch Cells | 62 | | |
| | Number of Dont Touch Nets | 1 | | |
| | Number of Size Only Cells | 0 | | |
| | Design with UPF Data | false | | |
| ==================================================================================================== | |
| Information: There are 7 potential problems in your design. Please run 'check_design' for more information. (LINT-99) | |
| Beginning Pass 1 Mapping | |
| ------------------------ | |
| Processing 'IOTDF' | |
| Updating timing information | |
| Information: Updating design information... (UID-85) | |
| Beginning Implementation Selection | |
| ---------------------------------- | |
| Mapping 'IOTDF_DW_cmp_0' | |
| Mapping 'IOTDF_DW_cmp_1' | |
| Mapping 'IOTDF_DW_cmp_2' | |
| Mapping 'IOTDF_DW_cmp_3' | |
| Mapping 'IOTDF_DW_cmp_4' | |
| Mapping 'IOTDF_DW_cmp_5' | |
| Processing 'IOTDF_DW01_inc_0' | |
| Mapping 'IOTDF_DW_cmp_6' | |
| Mapping 'IOTDF_DW_cmp_7' | |
| Building model 'DW01_NAND2' | |
| Processing 'DW01_NAND2' | |
| Building model 'DW01_add_width131' (rpl) | |
| Processing 'DW01_add_width131' | |
| Processing 'IOTDF_DW01_add_0' | |
| Mapping 'IOTDF_DW_mult_uns_0' | |
| Beginning Mapping Optimizations (High effort) | |
| ------------------------------- | |
| Information: Added key list 'DesignWare' to design 'IOTDF'. (DDB-72) | |
| Mapping Optimization (Phase 1) | |
| TOTAL | |
| ELAPSED WORST NEG SETUP DESIGN MIN DELAY | |
| TIME AREA SLACK COST RULE COST ENDPOINT COST | |
| --------- --------- --------- --------- --------- ------------------------- ----------- | |
| 0:00:16 172574.7 0.22 60.8 0.0 *cell*28665/U131/Y 0.00 | |
| 0:00:16 172574.7 0.22 60.8 0.0 *cell*28665/U131/Y 0.00 | |
| 0:00:17 172284.4 0.10 51.0 0.0 *cell*28665/*cell*28737/Y 0.00 | |
| 0:00:17 171894.0 0.09 49.9 0.0 *cell*28665/U3/Y 0.00 | |
| 0:00:17 171739.5 0.09 50.0 0.0 *cell*28665/*cell*28982/Y 0.00 | |
| 0:00:17 171702.2 0.09 50.2 0.0 *cell*28665/U264/Y 0.00 | |
| 0:00:18 171525.7 0.09 49.9 0.0 *cell*28665/U256/Y 0.00 | |
| 0:00:18 171340.6 0.09 49.5 0.0 *cell*28665/U245/Y 0.00 | |
| 0:00:18 171187.9 0.09 49.6 0.0 *cell*28665/U198/Y 0.00 | |
| 0:00:18 171013.0 0.09 49.7 0.0 *cell*28665/U251/Y 0.00 | |
| 0:00:18 170685.4 0.09 49.5 0.0 *cell*28665/*cell*29271/Y 0.00 | |
| 0:00:18 170529.3 0.09 49.8 0.0 *cell*28665/U148/Y 0.00 | |
| 0:00:19 175782.7 0.21 57.3 0.0 *cell*29395/U668/Y 0.00 | |
| 0:00:19 174227.9 0.11 51.8 0.0 *cell*29395/U1579/Y 0.00 | |
| 0:00:19 173717.0 0.10 49.4 0.0 *cell*29395/U1480/Y 0.00 | |
| 0:00:19 173294.4 0.10 47.2 0.0 *cell*29395/U1160/Y 0.00 | |
| 0:00:19 173111.0 0.10 46.4 0.0 *cell*29395/U965/Y 0.00 | |
| 0:00:19 172751.2 0.10 46.4 0.0 *cell*29395/*cell*29753/Y 0.00 | |
| 0:00:19 172540.7 0.10 49.8 0.0 *cell*29395/*cell*29705/Y 0.00 | |
| 0:00:19 172416.8 0.10 49.6 0.0 *cell*29395/*cell*29813/Y 0.00 | |
| 0:00:20 172362.5 0.10 49.4 0.0 *cell*29395/U370/Y 0.00 | |
| 0:00:20 171821.0 0.10 49.3 0.0 *cell*29395/U951/Y 0.00 | |
| 0:00:20 171468.0 0.10 49.8 0.0 *cell*29395/*cell*29967/Y 0.00 | |
| 0:00:20 171006.3 0.10 50.5 0.0 *cell*29395/*cell*30015/Y 0.00 | |
| 0:00:20 170692.2 0.10 49.3 0.0 *cell*29395/*cell*29728/Y 0.00 | |
| 0:00:20 170395.2 0.10 49.2 0.0 *cell*29395/*cell*30133/Y 0.00 | |
| 0:00:20 170067.6 0.10 49.2 0.0 *cell*29395/U1623/Y 0.00 | |
| 0:00:20 169760.4 0.10 49.2 0.0 *cell*29395/U1569/Y 0.00 | |
| 0:00:20 169672.1 0.10 50.6 0.0 *cell*29395/U1622/Y 0.00 | |
| 0:00:20 169361.5 0.10 50.4 0.0 *cell*29395/*cell*29686/Y 0.00 | |
| 0:00:20 169015.2 0.10 50.3 0.0 *cell*29395/*cell*29747/Y 0.00 | |
| 0:00:21 168850.6 0.10 50.2 0.0 *cell*29395/*cell*30386/Y 0.00 | |
| 0:00:21 168590.9 0.10 50.2 0.0 *cell*29395/*cell*30442/Y 0.00 | |
| 0:00:21 168399.1 0.10 50.1 0.0 *cell*29395/*cell*30459/Y 0.00 | |
| 0:00:21 168175.0 0.10 50.1 0.0 *cell*29395/*cell*30560/Y 0.00 | |
| 0:00:21 168037.5 0.09 50.9 0.0 *cell*29395/*cell*30538/Y 0.00 | |
| 0:00:21 167821.9 0.09 50.5 0.0 *cell*29395/U430/Y 0.00 | |
| 0:00:21 167433.2 0.09 50.3 0.0 *cell*29395/*cell*30044/Y 0.00 | |
| 0:00:21 166915.5 0.09 50.3 0.0 *cell*29395/*cell*30754/Y 0.00 | |
| 0:00:21 166696.6 0.09 50.3 0.0 *cell*29395/*cell*30797/Y 0.00 | |
| 0:00:21 166306.2 0.09 50.3 0.0 *cell*29395/*cell*30473/Y 0.00 | |
| 0:00:21 165931.0 0.09 50.2 0.0 *cell*29395/*cell*30164/Y 0.00 | |
| 0:00:22 165645.9 0.09 50.2 0.0 *cell*29395/*cell*30966/Y 0.00 | |
| 0:00:22 165313.2 0.09 50.2 0.0 *cell*29395/*cell*29655/Y 0.00 | |
| 0:00:22 165107.8 0.09 50.2 0.0 *cell*29395/*cell*31066/Y 0.00 | |
| 0:00:22 164924.5 0.09 50.2 0.0 *cell*29395/*cell*30544/Y 0.00 | |
| 0:00:22 164747.9 0.09 50.2 0.0 *cell*29395/*cell*30956/Y 0.00 | |
| 0:00:22 164512.0 0.09 50.1 0.0 *cell*29395/*cell*31178/Y 0.00 | |
| 0:00:22 164308.3 0.09 50.1 0.0 *cell*29395/*cell*30743/Y 0.00 | |
| 0:00:22 164102.9 0.09 50.1 0.0 *cell*29395/U717/Y 0.00 | |
| 0:00:22 163440.9 0.09 50.1 0.0 *cell*29395/*cell*31329/Y 0.00 | |
| 0:00:22 163228.8 0.09 50.1 0.0 *cell*29395/*cell*30967/Y 0.00 | |
| 0:00:22 163077.7 0.09 50.1 0.0 *cell*29395/*cell*31431/Y 0.00 | |
| 0:00:22 162746.7 0.09 50.1 0.0 *cell*29395/*cell*31472/Y 0.00 | |
| 0:00:23 162475.1 0.09 50.0 0.0 *cell*29395/*cell*31500/Y 0.00 | |
| 0:00:23 162269.7 0.09 50.0 0.0 *cell*29395/*cell*31365/Y 0.00 | |
| 0:00:23 161979.5 0.09 50.0 0.0 *cell*29395/*cell*31575/Y 0.00 | |
| 0:00:23 161758.8 0.09 49.1 0.0 *cell*29395/*cell*31582/Y 0.00 | |
| 0:00:23 161584.0 0.09 49.1 0.0 *cell*29395/*cell*31645/Y 0.00 | |
| 0:00:23 161390.5 0.09 49.1 0.0 *cell*29395/*cell*31710/Y 0.00 | |
| 0:00:23 161314.1 0.09 49.1 0.0 *cell*29395/*cell*30433/Y 0.00 | |
| 0:00:23 161069.7 0.09 47.6 0.0 *cell*29395/*cell*31780/Y 0.00 | |
| 0:00:23 160820.2 0.09 47.6 0.0 *cell*29395/*cell*31669/Y 0.00 | |
| 0:00:23 160628.4 0.09 47.6 0.0 *cell*29395/*cell*31835/Y 0.00 | |
| 0:00:23 160511.2 0.09 47.6 0.0 *cell*29395/*cell*29852/Y 0.00 | |
| 0:00:23 160404.3 0.09 47.6 0.0 *cell*29395/*cell*29926/Y 0.00 | |
| 0:00:24 160180.2 0.09 47.6 0.0 *cell*29395/*cell*31993/Y 0.00 | |
| 0:00:24 159942.6 0.09 47.6 0.0 *cell*29395/*cell*29666/Y 0.00 | |
| 0:00:24 159796.6 0.09 46.8 0.0 *cell*29395/*cell*32066/Y 0.00 | |
| 0:00:24 159553.9 0.09 46.8 0.0 *cell*29395/*cell*32095/Y 0.00 | |
| 0:00:24 159309.5 0.09 46.8 0.0 *cell*29395/*cell*32127/Y 0.00 | |
| 0:00:24 159127.9 0.09 46.8 0.0 *cell*29395/U109/Y 0.00 | |
| 0:00:24 158931.0 0.09 46.8 0.0 *cell*29395/*cell*32195/Y 0.00 | |
| 0:00:24 158781.6 0.09 46.8 0.0 *cell*29395/*cell*32236/Y 0.00 | |
| 0:00:24 158717.1 0.09 46.8 0.0 *cell*29395/*cell*32211/Y 0.00 | |
| 0:00:24 158506.6 0.09 46.8 0.0 *cell*29395/U838/Y 0.00 | |
| 0:00:24 158447.2 0.09 46.8 0.0 *cell*29395/*cell*31140/Y 0.00 | |
| 0:00:24 158255.4 0.09 46.8 0.0 *cell*29395/U435/Y 0.00 | |
| 0:00:25 158021.1 0.09 46.8 0.0 *cell*29395/U917/Y 0.00 | |
| 0:00:25 157861.6 0.09 44.4 0.0 *cell*29395/*cell*31793/Y 0.00 | |
| 0:00:25 157551.0 0.09 44.3 0.0 *cell*29395/*cell*32507/Y 0.00 | |
| 0:00:25 157382.9 0.09 44.3 0.0 *cell*29395/*cell*32512/Y 0.00 | |
| 0:00:25 157140.2 0.09 44.3 0.0 *cell*29395/*cell*32558/Y 0.00 | |
| 0:00:25 156929.7 0.09 44.3 0.0 *cell*29395/U581/Y 0.00 | |
| 0:00:25 156805.8 0.09 44.3 0.0 *cell*29395/*cell*32515/Y 0.00 | |
| 0:00:25 156622.5 0.09 44.2 0.0 *cell*29395/*cell*30909/Y 0.00 | |
| 0:00:25 156478.2 0.09 44.2 0.0 *cell*29395/*cell*31541/Y 0.00 | |
| 0:00:25 156376.4 0.09 44.2 0.0 *cell*29395/U1549/Y 0.00 | |
| 0:00:25 156182.9 0.09 43.7 0.0 *cell*29395/*cell*32428/Y 0.00 | |
| 0:00:25 156091.2 0.09 43.7 0.0 *cell*29395/*cell*31415/Y 0.00 | |
| 0:00:25 155986.0 0.09 43.7 0.0 *cell*29395/*cell*31436/Y 0.00 | |
| 0:00:26 155868.8 0.09 42.6 0.0 *cell*29395/*cell*30089/Y 0.00 | |
| 0:00:26 155789.1 0.09 42.6 0.0 *cell*29395/*cell*31060/Y 0.00 | |
| 0:00:26 155678.7 0.09 42.6 0.0 *cell*29395/*cell*30992/Y 0.00 | |
| 0:00:26 155570.1 0.09 42.6 0.0 *cell*29395/*cell*30063/Y 0.00 | |
| 0:00:26 155520.9 0.09 42.6 0.0 *cell*29395/*cell*32831/Y 0.00 | |
| 0:00:26 155366.4 0.09 42.6 0.0 *cell*29395/*cell*32898/Y 0.00 | |
| 0:00:26 155291.7 0.09 42.6 0.0 *cell*29395/*cell*32838/Y 0.00 | |
| 0:00:26 155208.6 0.09 42.6 0.0 *cell*29395/*cell*31767/Y 0.00 | |
| 0:00:26 155091.4 0.09 40.9 0.0 *cell*29395/*cell*32916/Y 0.00 | |
| 0:00:26 155010.0 0.09 40.9 0.0 *cell*29395/*cell*31685/Y 0.00 | |
| 0:00:26 154918.3 0.09 40.9 0.0 *cell*29395/*cell*32996/Y 0.00 | |
| 0:00:26 154857.2 0.09 40.9 0.0 *cell*29395/*cell*29699/Y 0.00 | |
| 0:00:26 154801.2 0.09 40.9 0.0 *cell*29395/U183/Y 0.00 | |
| 0:00:27 154758.7 0.09 41.4 0.0 *cell*29395/*cell*29759/Y 0.00 | |
| 0:00:27 154656.9 0.09 40.9 0.0 *cell*29395/*cell*31311/Y 0.00 | |
| 0:00:27 154645.0 0.09 40.7 0.0 *cell*29395/*cell*30594/Y 0.00 | |
| 0:00:27 154621.3 0.09 40.7 0.0 *cell*29395/*cell*31598/Y 0.00 | |
| 0:00:27 154558.5 0.09 40.7 0.0 0.00 | |
| 0:00:29 153523.0 0.09 39.6 1679.0 0.00 | |
| 0:00:29 153523.0 0.09 39.6 1679.0 0.00 | |
| 0:00:29 153523.0 0.09 39.6 1679.0 0.00 | |
| 0:00:29 153523.0 0.09 39.6 1679.0 0.00 | |
| 0:00:33 79490.9 0.99 580.0 444.8 0.00 | |
| 0:00:35 78194.1 0.84 497.8 444.0 0.00 | |
| 0:00:36 78111.0 0.90 514.3 444.0 0.00 | |
| 0:00:36 78112.6 0.77 460.4 444.0 0.00 | |
| 0:00:37 78049.8 0.75 467.4 444.0 0.00 | |
| 0:00:37 78097.4 0.77 408.0 444.0 0.00 | |
| 0:00:38 78088.9 0.72 393.7 444.0 0.00 | |
| 0:00:38 78114.3 0.75 392.6 444.0 0.00 | |
| 0:00:38 78114.3 0.74 369.6 444.0 0.00 | |
| 0:00:38 78143.2 0.96 396.9 444.0 0.00 | |
| 0:00:39 78134.7 0.71 365.9 444.0 0.00 | |
| 0:00:39 78170.4 0.61 349.2 444.0 0.00 | |
| 0:00:39 78177.2 0.60 348.5 443.3 0.00 | |
| 0:00:39 78178.8 0.59 347.8 443.3 0.00 | |
| 0:00:39 78178.8 0.59 347.5 443.3 0.00 | |
| 0:00:39 78183.9 0.59 347.1 443.3 0.00 | |
| 0:00:39 78189.0 0.58 346.1 443.3 0.00 | |
| 0:00:39 78207.7 0.58 332.6 443.3 0.00 | |
| 0:00:39 78202.6 0.57 331.0 443.3 0.00 | |
| 0:00:39 78202.6 0.57 331.0 443.3 0.00 | |
| 0:00:39 78202.6 0.57 331.0 443.3 0.00 | |
| 0:00:39 78202.6 0.57 331.0 443.3 0.00 | |
| 0:00:39 78202.6 0.57 331.0 443.3 0.00 | |
| 0:00:39 78202.6 0.57 331.0 443.3 0.00 | |
| 0:00:39 78681.3 0.50 311.8 529.0 max_reg[88]/D 0.00 | |
| 0:00:40 78942.7 0.46 289.9 558.7 sum_reg[110]/D 0.00 | |
| 0:00:40 79056.4 0.44 282.3 566.2 sum_reg[110]/D 0.00 | |
| 0:00:40 79149.8 0.42 273.8 569.9 peak_min_reg[33]/D 0.00 | |
| 0:00:40 79255.0 0.40 243.4 569.9 min_reg[35]/D 0.00 | |
| 0:00:41 79502.8 0.38 231.6 573.3 peak_max_reg[26]/D 0.00 | |
| 0:00:41 79570.7 0.36 226.6 573.3 min_reg[15]/D 0.00 | |
| 0:00:41 79653.9 0.35 223.3 573.3 min_reg[15]/D 0.00 | |
| 0:00:41 79665.8 0.35 222.1 573.3 sum_reg[79]/D 0.00 | |
| 0:00:41 79725.2 0.35 219.7 576.7 peak_max_reg[104]/D 0.00 | |
| 0:00:41 79788.0 0.34 219.0 580.1 min_reg[52]/D 0.00 | |
| 0:00:41 79835.5 0.34 212.1 583.4 min_reg[15]/D 0.00 | |
| 0:00:42 79928.9 0.32 195.1 583.4 peak_max_reg[26]/D 0.00 | |
| 0:00:42 79993.4 0.31 192.1 586.8 max_reg[30]/D 0.00 | |
| 0:00:42 80051.1 0.30 191.7 586.8 sum_reg[79]/D 0.00 | |
| 0:00:42 80095.2 0.29 187.4 586.8 min_reg[52]/D 0.00 | |
| 0:00:42 80248.0 0.29 175.2 586.8 min_reg[52]/D 0.00 | |
| 0:00:42 80319.3 0.27 162.5 590.2 max_reg[22]/D 0.00 | |
| 0:00:42 80344.7 0.27 162.1 590.2 max_reg[22]/D 0.00 | |
| 0:00:43 80377.0 0.26 150.8 590.2 iot_out_reg[101]/D 0.00 | |
| 0:00:43 80545.0 0.25 150.2 590.2 iot_out_reg[84]/D 0.00 | |
| 0:00:43 80704.6 0.25 149.5 590.2 iot_out_reg[107]/D 0.00 | |
| 0:00:43 80840.4 0.25 149.0 590.2 iot_out_reg[0]/D 0.00 | |
| 0:00:43 80933.7 0.25 148.6 590.2 iot_out_reg[11]/D 0.00 | |
| 0:00:43 81049.2 0.25 148.1 590.2 iot_out_reg[21]/D 0.00 | |
| 0:00:43 81176.5 0.25 148.1 590.2 iot_out_reg[27]/D 0.00 | |
| 0:00:43 81247.7 0.25 147.7 590.2 min_reg[15]/D 0.00 | |
| 0:00:43 81400.5 0.24 146.9 590.2 iot_out_reg[46]/D 0.00 | |
| 0:00:44 81560.1 0.24 146.0 590.2 iot_out_reg[54]/D 0.00 | |
| 0:00:44 81575.3 0.24 142.4 590.2 iot_out_reg[56]/D 0.00 | |
| 0:00:44 81692.5 0.24 144.3 590.2 iot_out_reg[63]/D 0.00 | |
| 0:00:44 81807.9 0.24 143.5 590.2 iot_out_reg[69]/D 0.00 | |
| 0:00:44 81962.4 0.24 142.9 590.2 iot_out_reg[82]/D 0.00 | |
| 0:00:44 82113.4 0.24 142.4 590.2 iot_out_reg[92]/D 0.00 | |
| 0:00:44 82269.6 0.23 141.8 590.2 iot_out_reg[9]/D 0.00 | |
| 0:00:44 82342.6 0.23 141.4 590.2 sum_reg[79]/D 0.00 | |
| 0:00:45 82451.2 0.23 141.2 590.2 iot_out_reg[2]/D 0.00 | |
| 0:00:45 82617.5 0.23 140.4 590.2 iot_out_reg[112]/D 0.00 | |
| 0:00:45 82722.8 0.23 134.2 590.2 iot_out_reg[115]/D 0.00 | |
| 0:00:45 82873.9 0.22 131.7 590.2 sum_reg[79]/D 0.00 | |
| 0:00:45 82909.5 0.22 132.1 590.2 sum_reg[41]/D 0.00 | |
| 0:00:45 82912.9 0.20 126.1 590.2 max_reg[22]/D 0.00 | |
| 0:00:45 82945.1 0.20 122.8 590.2 sum_reg[76]/D 0.00 | |
| 0:00:45 82980.8 0.20 119.7 590.2 max_reg[22]/D 0.00 | |
| 0:00:46 83026.6 0.19 118.6 594.0 min_reg[125]/D 0.00 | |
| 0:00:46 83108.1 0.19 114.7 594.0 min_reg[125]/D 0.00 | |
| 0:00:46 83194.7 0.18 116.5 621.3 sum_reg[36]/D 0.00 | |
| 0:00:46 83284.6 0.18 115.4 621.9 sum_reg[58]/D 0.00 | |
| 0:00:48 83715.8 0.18 101.3 742.2 0.00 | |
| 0:00:48 83863.4 0.17 95.9 788.9 0.00 | |
| 0:00:48 83866.8 0.16 89.4 761.6 0.00 | |
| 0:00:48 83924.5 0.16 87.9 761.6 0.00 | |
| 0:00:48 84036.6 0.16 85.4 761.6 0.00 | |
| 0:00:49 84060.3 0.16 84.1 761.6 0.00 | |
| 0:00:49 84060.3 0.15 76.7 761.6 0.00 | |
| 0:00:49 84119.7 0.15 75.6 762.9 0.00 | |
| 0:00:49 84192.7 0.14 73.0 762.9 0.00 | |
| 0:00:49 84225.0 0.14 71.9 762.9 0.00 | |
| 0:00:49 84258.9 0.13 68.1 762.9 0.00 | |
| 0:00:49 84299.7 0.13 62.5 762.9 0.00 | |
| 0:00:49 84318.3 0.12 58.7 762.9 0.00 | |
| 0:00:50 84265.7 0.12 55.1 762.9 0.00 | |
| 0:00:50 84343.8 0.11 46.4 762.9 0.00 | |
| 0:00:50 84365.9 0.11 45.4 762.9 0.00 | |
| 0:00:50 84415.1 0.11 41.4 763.4 0.00 | |
| 0:00:50 84420.2 0.11 40.8 763.4 0.00 | |
| 0:00:50 84471.1 0.11 40.1 766.7 0.00 | |
| 0:00:50 84498.3 0.11 39.8 766.7 0.00 | |
| 0:00:50 84525.4 0.11 39.4 766.7 0.00 | |
| 0:00:50 84576.3 0.11 38.5 766.7 0.00 | |
| 0:00:50 84583.1 0.11 37.9 766.7 0.00 | |
| Beginning Delay Optimization Phase | |
| ---------------------------------- | |
| TOTAL | |
| ELAPSED WORST NEG SETUP DESIGN MIN DELAY | |
| TIME AREA SLACK COST RULE COST ENDPOINT COST | |
| --------- --------- --------- --------- --------- ------------------------- ----------- | |
| 0:00:50 84583.1 0.11 37.9 766.7 0.00 | |
| 0:00:50 84595.0 0.10 37.4 766.7 peak_min_reg[119]/D 0.00 | |
| 0:00:51 84634.1 0.10 36.5 766.7 min_reg[125]/D 0.00 | |
| 0:00:51 84685.0 0.09 35.6 773.4 min_reg[125]/D 0.00 | |
| 0:00:51 84705.4 0.09 34.9 773.4 min_reg[119]/D 0.00 | |
| 0:00:51 84734.2 0.09 34.7 773.4 min_reg[125]/D 0.00 | |
| 0:00:51 84802.1 0.09 33.6 773.4 min_reg[127]/D 0.00 | |
| 0:00:51 84851.3 0.09 33.1 773.4 min_reg[115]/D 0.00 | |
| 0:00:51 84863.2 0.09 32.3 773.4 min_reg[93]/D 0.00 | |
| 0:00:52 84887.0 0.09 31.8 773.4 sum_reg[74]/D 0.00 | |
| 0:00:52 84902.2 0.09 32.3 776.7 sum_reg[74]/D 0.00 | |
| 0:00:52 84922.6 0.08 30.6 780.0 min_reg[105]/D 0.00 | |
| 0:00:52 84932.8 0.08 30.5 780.0 min_reg[65]/D 0.00 | |
| 0:00:52 85027.9 0.08 30.0 780.0 min_reg[16]/D 0.00 | |
| 0:00:52 85049.9 0.08 29.3 782.5 sum_reg[98]/D 0.00 | |
| 0:00:52 85068.6 0.08 28.5 789.7 sum_reg[86]/D 0.00 | |
| 0:00:52 85099.1 0.08 28.3 789.7 min_reg[40]/D 0.00 | |
| 0:00:52 85223.1 0.07 27.0 793.5 sum_reg[122]/D 0.00 | |
| 0:00:52 85257.0 0.07 26.2 796.8 sum_reg[113]/D 0.00 | |
| 0:00:53 85280.8 0.07 25.7 796.8 sum_reg[101]/D 0.00 | |
| 0:00:53 85321.5 0.07 21.6 796.8 sum_reg[105]/D 0.00 | |
| 0:00:53 85367.3 0.07 21.1 800.2 min_reg[9]/D 0.00 | |
| 0:00:53 85442.0 0.06 19.8 807.3 min_reg[94]/D 0.00 | |
| 0:00:53 85498.0 0.06 17.9 810.6 peak_min_reg[86]/D 0.00 | |
| 0:00:53 85516.7 0.06 17.3 811.2 sum_reg[74]/D 0.00 | |
| 0:00:53 85560.8 0.05 16.0 811.7 sum_reg[76]/D 0.00 | |
| 0:00:53 85586.3 0.05 15.7 811.7 sum_reg[95]/D 0.00 | |
| 0:00:53 85601.6 0.05 14.7 811.7 min_reg[8]/D 0.00 | |
| 0:00:54 85571.0 0.05 12.9 811.7 sum_reg[83]/D 0.00 | |
| 0:00:54 85594.8 0.04 11.9 813.0 sum_reg[49]/D 0.00 | |
| 0:00:54 85598.2 0.04 11.8 813.0 max_reg[37]/D 0.00 | |
| 0:00:54 85606.7 0.04 6.7 813.0 peak_max_reg[44]/D 0.00 | |
| 0:00:54 85640.6 0.04 5.9 813.0 min_reg[15]/D 0.00 | |
| 0:00:54 85732.3 0.04 5.7 813.0 max_reg[122]/D 0.00 | |
| 0:00:54 85701.7 0.03 4.7 813.0 max_reg[21]/D 0.00 | |
| 0:00:54 85720.4 0.03 4.5 813.0 sum_reg[60]/D 0.00 | |
| 0:00:55 85786.6 0.03 4.2 813.0 min_reg[30]/D 0.00 | |
| 0:00:55 85800.2 0.03 3.1 811.9 min_reg[39]/D 0.00 | |
| 0:00:55 85817.1 0.03 2.8 809.8 sum_reg[82]/D 0.00 | |
| 0:00:55 85839.2 0.02 2.1 809.8 sum_reg[67]/D 0.00 | |
| 0:00:55 85847.7 0.02 1.7 809.8 min_reg[125]/D 0.00 | |
| 0:00:55 85856.2 0.02 1.6 809.8 min_reg[125]/D 0.00 | |
| 0:00:56 85893.5 0.02 1.4 809.2 peak_min_reg[117]/D 0.00 | |
| 0:00:56 85925.8 0.01 1.3 809.2 sum_reg[79]/D 0.00 | |
| 0:00:56 85932.6 0.01 1.2 809.2 max_reg[40]/D 0.00 | |
| 0:00:56 85951.2 0.01 1.1 810.4 max_reg[52]/D 0.00 | |
| 0:00:56 85924.1 0.01 1.0 810.4 sum_reg[88]/D 0.00 | |
| 0:00:56 85919.0 0.01 0.8 810.4 max_reg[40]/D 0.00 | |
| 0:00:56 85932.6 0.01 0.7 810.4 min_reg[105]/D 0.00 | |
| 0:00:56 85956.3 0.01 0.6 809.9 sum_reg[88]/D 0.00 | |
| 0:00:57 85973.3 0.01 0.5 809.9 peak_min_reg[117]/D 0.00 | |
| 0:00:57 85988.6 0.01 0.4 809.9 max_reg[52]/D 0.00 | |
| 0:00:57 86007.3 0.01 0.4 809.9 sum_reg[130]/D 0.00 | |
| 0:00:57 86000.5 0.01 0.3 809.9 iot_out_reg[99]/D 0.00 | |
| 0:00:57 86005.6 0.00 0.1 809.9 min_reg[105]/D 0.00 | |
| 0:00:57 86017.4 0.00 0.1 809.9 peak_min_reg[125]/D 0.00 | |
| 0:00:57 86036.1 0.00 0.1 809.9 min_reg[15]/D 0.00 | |
| 0:00:57 86058.2 0.00 0.0 809.9 min_reg[64]/D 0.00 | |
| 0:00:58 86071.8 0.00 0.0 809.9 sum_reg[88]/D 0.00 | |
| 0:00:58 86073.5 0.00 0.0 809.9 0.00 | |
| 0:00:58 86042.9 0.00 0.0 816.9 0.00 | |
| 0:01:00 85857.9 0.00 0.0 830.5 0.00 | |
| 0:01:00 85849.4 0.00 0.0 835.0 0.00 | |
| Beginning Design Rule Fixing (max_transition) (max_capacitance) | |
| ---------------------------- | |
| TOTAL | |
| ELAPSED WORST NEG SETUP DESIGN MIN DELAY | |
| TIME AREA SLACK COST RULE COST ENDPOINT COST | |
| --------- --------- --------- --------- --------- ------------------------- ----------- | |
| 0:01:00 85849.4 0.00 0.0 835.0 0.00 | |
| 0:01:00 85861.3 0.00 0.0 0.0 0.00 | |
| Beginning Area-Recovery Phase (cleanup) | |
| ----------------------------- | |
| TOTAL | |
| ELAPSED WORST NEG SETUP DESIGN MIN DELAY | |
| TIME AREA SLACK COST RULE COST ENDPOINT COST | |
| --------- --------- --------- --------- --------- ------------------------- ----------- | |
| 0:01:00 85861.3 0.00 0.0 0.0 0.00 | |
| 0:01:00 85861.3 0.00 0.0 0.0 0.00 | |
| 0:01:01 84506.8 0.03 3.9 0.0 0.00 | |
| 0:01:01 84289.5 0.03 4.8 0.0 0.00 | |
| 0:01:01 84146.9 0.03 4.8 0.0 0.00 | |
| 0:01:01 84062.0 0.03 4.6 0.0 0.00 | |
| 0:01:02 84004.3 0.03 4.6 0.0 0.00 | |
| 0:01:02 84004.3 0.03 4.6 0.0 0.00 | |
| 0:01:02 84051.9 0.00 0.3 0.0 0.00 | |
| 0:01:02 84056.9 0.00 0.2 0.0 0.00 | |
| 0:01:02 84070.5 0.00 0.1 0.0 0.00 | |
| 0:01:03 84067.1 0.00 0.1 0.0 0.00 | |
| 0:01:03 84226.7 0.00 0.0 0.0 0.00 | |
| 0:01:03 84233.5 0.00 0.0 0.0 0.00 | |
| 0:01:03 82266.2 0.41 123.9 0.0 0.00 | |
| 0:01:03 82072.7 0.45 140.6 0.0 0.00 | |
| 0:01:03 82059.1 0.45 140.6 0.0 0.00 | |
| 0:01:03 82059.1 0.45 140.6 0.0 0.00 | |
| 0:01:03 82059.1 0.45 140.6 0.0 0.00 | |
| 0:01:03 82059.1 0.45 140.6 0.0 0.00 | |
| 0:01:03 82059.1 0.45 140.6 0.0 0.00 | |
| 0:01:03 82059.1 0.45 140.6 0.0 0.00 | |
| 0:01:04 82108.3 0.17 63.4 0.0 iot_out_reg[44]/D 0.00 | |
| 0:01:05 82127.0 0.10 33.5 0.0 max_reg[29]/D 0.00 | |
| 0:01:05 82181.3 0.05 12.6 0.0 peak_max_reg[35]/D 0.00 | |
| 0:01:05 82262.8 0.03 5.3 0.0 peak_min_reg[15]/D 0.00 | |
| 0:01:06 82313.7 0.02 2.0 0.0 0.00 | |
| 0:01:06 82344.3 0.01 1.5 0.0 0.00 | |
| 0:01:06 82361.2 0.01 1.4 0.0 0.00 | |
| 0:01:06 82427.4 0.01 1.2 0.0 0.00 | |
| 0:01:06 82515.7 0.01 1.0 0.0 0.00 | |
| 0:01:06 82527.6 0.00 0.9 0.0 0.00 | |
| 0:01:06 82614.2 0.00 0.7 0.0 0.00 | |
| 0:01:07 82639.6 0.00 0.4 0.0 0.00 | |
| 0:01:07 82797.5 0.00 0.3 0.0 0.00 | |
| 0:01:07 82892.5 0.00 0.1 0.0 0.00 | |
| 0:01:07 82921.4 0.00 0.0 0.0 0.00 | |
| 0:01:07 82935.0 0.00 0.0 0.0 0.00 | |
| 0:01:07 82935.0 0.00 0.0 0.0 0.00 | |
| Loading db file '/home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db' | |
| Note: Symbol # after min delay cost means estimated hold TNS across all active scenarios | |
| Optimization Complete | |
| --------------------- | |
| Warning: Design 'IOTDF' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) | |
| Net 'clk': 1055 load(s), 1 driver(s) | |
| 1 | |
| compile -map_effort high -area_effort high -inc | |
| ==================================================================================================== | |
| | Flow Information | | |
| ---------------------------------------------------------------------------------------------------- | |
| | Flow | Design Compiler NXT | | |
| ==================================================================================================== | |
| | Design Information | Value | | |
| ==================================================================================================== | |
| | Number of Scenarios | 0 | | |
| | Leaf Cell Count | 8022 | | |
| | Number of User Hierarchies | 7 | | |
| | Sequential Cell Count | 1055 | | |
| | Macro Count | 0 | | |
| | Number of Power Domains | 0 | | |
| | Number of Path Groups | 2 | | |
| | Number of VT Class | 0 | | |
| | Number of Clocks | 1 | | |
| | Number of Dont Touch Cells | 0 | | |
| | Number of Dont Touch Nets | 1 | | |
| | Number of Size Only Cells | 0 | | |
| | Design with UPF Data | false | | |
| ==================================================================================================== | |
| Information: There are 44 potential problems in your design. Please run 'check_design' for more information. (LINT-99) | |
| Beginning Pass 1 Mapping (Incremental) | |
| ------------------------ | |
| Updating timing information | |
| Information: Updating design information... (UID-85) | |
| Beginning Mapping Optimizations (High effort) (Incremental) | |
| ------------------------------- | |
| Beginning Incremental Implementation Selection | |
| ---------------------------------------------- | |
| Mapping 'IOTDF_DW01_add_0' | |
| Mapping 'IOTDF_DW_cmp_0' | |
| Mapping 'IOTDF_DW_cmp_1' | |
| Mapping 'IOTDF_DW_cmp_2' | |
| Mapping 'IOTDF_DW_cmp_3' | |
| Mapping 'IOTDF_DW_mult_uns_1_0' | |
| Selecting implementations | |
| Building model 'DW01_NAND2' | |
| Building model 'DW01_inc_width11' (rpl) | |
| Beginning Delay Optimization Phase | |
| ---------------------------------- | |
| TOTAL | |
| ELAPSED WORST NEG SETUP DESIGN MIN DELAY | |
| TIME AREA SLACK COST RULE COST ENDPOINT COST | |
| --------- --------- --------- --------- --------- ------------------------- ----------- | |
| 0:00:04 82935.0 0.00 0.0 0.0 0.00 | |
| 0:00:04 85318.1 0.00 0.0 0.0 0.00 | |
| 0:00:05 85089.0 0.00 0.0 0.0 0.00 | |
| 0:00:05 85089.0 0.00 0.0 0.0 0.00 | |
| Loading db file '/home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db' | |
| Note: Symbol # after min delay cost means estimated hold TNS across all active scenarios | |
| Optimization Complete | |
| --------------------- | |
| Warning: Design 'IOTDF' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) | |
| Net 'clk': 1055 load(s), 1 driver(s) | |
| 1 | |
| write -format ddc -hierarchy -output "IOTDF.ddc" | |
| Writing ddc file 'IOTDF.ddc'. | |
| 1 | |
| write_sdf IOTDF.sdf | |
| Information: Annotated 'cell' delays are assumed to include load delay. (UID-282) | |
| Information: Writing timing information to file '/home/M12/chenneil90121/ic_contest_mock3/IOTDF.sdf'. (WT-3) | |
| Information: Updating design information... (UID-85) | |
| Warning: Design 'IOTDF' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) | |
| 1 | |
| write_file -format verilog -hierarchy -output IOTDF_syn.v | |
| Writing verilog file '/home/M12/chenneil90121/ic_contest_mock3/IOTDF_syn.v'. | |
| Warning: Verilog writer has added 1 nets to module IOTDF using SYNOPSYS_UNCONNECTED_ as prefix. Please use the change_names command to make the correct changes before invoking the verilog writer. (VO-11) | |
| Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4) | |
| 1 | |
| report_area > area.log | |
| report_timing > timing.log | |
| report_qor > IOTDF.qor | |
| report_area -designware -hierarchy | |
| **************************************** | |
| Report : area | |
| Design : IOTDF | |
| Version: U-2022.12 | |
| Date : Sat Mar 23 17:22:39 2024 | |
| **************************************** | |
| Library(s) Used: | |
| slow (File: /home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/slow.db) | |
| Number of ports: 1869 | |
| Number of nets: 10330 | |
| Number of cells: 7950 | |
| Number of combinational cells: 6877 | |
| Number of sequential cells: 1055 | |
| Number of macros/black boxes: 0 | |
| Number of buf/inv: 1427 | |
| Number of references: 113 | |
| Combinational area: 49058.254370 | |
| Buf/Inv area: 8363.089830 | |
| Noncombinational area: 36030.709703 | |
| Macro/Black Box area: 0.000000 | |
| Net Interconnect area: undefined (No wire load specified) | |
| Total cell area: 85088.964074 | |
| Total area: undefined | |
| Hierarchical area distribution | |
| ------------------------------ | |
| Global cell area Local cell area | |
| ------------------- ------------------------------ | |
| Hierarchical cell Absolute Percent Combi- Noncombi- Black- | |
| Total Total national national boxes Design | |
| -------------------------------- ---------- ------- ---------- ---------- ------ ------------------- | |
| IOTDF 85088.9641 100.0 23821.3114 36030.7097 0.0000 IOTDF | |
| add_111 183.3192 0.2 183.3192 0.0000 0.0000 IOTDF_DW01_inc_0 | |
| add_186_aco 10097.8325 11.9 10097.8325 0.0000 0.0000 IOTDF_DW01_add_1 | |
| gt_142 3410.0766 4.0 3410.0766 0.0000 0.0000 IOTDF_DW_cmp_J2_0 | |
| lt_162 3651.1074 4.3 3651.1074 0.0000 0.0000 IOTDF_DW_cmp_8 | |
| mult_add_186_aco 1162.7190 1.4 1162.7190 0.0000 0.0000 IOTDF_DW_mult_uns_1 | |
| r415 3338.7857 3.9 3338.7857 0.0000 0.0000 IOTDF_DW_cmp_J3_0 | |
| r416 3393.1026 4.0 3393.1026 0.0000 0.0000 IOTDF_DW_cmp_J4_0 | |
| -------------------------------- ---------- ------- ---------- ---------- ------ ------------------- | |
| Total 49058.2544 36030.7097 0.0000 | |
| Area of detected synthetic parts | |
| -------------------------------- | |
| Perc. of | |
| Module Implem. Count Area cell area | |
| ----------- ------- ----- ----------- --------- | |
| DW01_add pparch 1 10097.8457 11.9% | |
| DW01_inc rpl 1 183.3192 0.2% | |
| DW_cmp pparch 4 13793.1067 16.2% | |
| DW_mult_uns pparch 1 1162.7186 1.4% | |
| ----------- ------- ----- ----------- --------- | |
| Total: 7 25236.9902 29.7% | |
| Estimated area of ungrouped synthetic parts | |
| ------------------------------------------- | |
| Estimated Perc. of | |
| Module Implem. Count Area cell area | |
| ------ ------- ----- ---------- --------- | |
| DW_cmp apparch 4 663.3935 0.8% | |
| ------ ------- ----- ---------- --------- | |
| Total: 4 663.3935 0.8% | |
| Total synthetic cell area: 25900.3838 30.4% (estimated) | |
| 1 | |
| report_timing | |
| **************************************** | |
| Report : timing | |
| -path full | |
| -delay max | |
| -max_paths 1 | |
| Design : IOTDF | |
| Version: U-2022.12 | |
| Date : Sat Mar 23 17:22:39 2024 | |
| **************************************** | |
| # A fanout number of 1000 was used for high fanout net computations. | |
| Operating Conditions: slow Library: slow | |
| Wire Load Model Mode: top | |
| Startpoint: counter_delay_reg[4] | |
| (rising edge-triggered flip-flop clocked by clk) | |
| Endpoint: sum_reg[128] | |
| (rising edge-triggered flip-flop clocked by clk) | |
| Path Group: clk | |
| Path Type: max | |
| Point Incr Path | |
| -------------------------------------------------------------------------- | |
| clock clk (rise edge) 0.00 0.00 | |
| clock network delay (ideal) 1.00 1.00 | |
| counter_delay_reg[4]/CK (DFFHQX4) 0.00 # 1.00 r | |
| counter_delay_reg[4]/Q (DFFHQX4) 0.17 1.17 r | |
| U2878/Y (OR2X8) 0.10 1.27 r | |
| U2902/Y (OR2X8) 0.14 1.41 r | |
| mult_add_186_aco/b (IOTDF_DW_mult_uns_1) 0.00 1.41 r | |
| mult_add_186_aco/U313/Y (INVX12) 0.09 1.50 f | |
| mult_add_186_aco/U526/Y (NOR2X1) 0.12 1.62 r | |
| mult_add_186_aco/product[120] (IOTDF_DW_mult_uns_1) 0.00 1.62 r | |
| add_186_aco/A[120] (IOTDF_DW01_add_1) 0.00 1.62 r | |
| add_186_aco/U2752/Y (NAND2X1) 0.09 1.71 f | |
| add_186_aco/U1836/Y (OAI21XL) 0.33 2.04 r | |
| add_186_aco/U2753/Y (AOI21X1) 0.16 2.19 f | |
| add_186_aco/U2844/Y (OAI21XL) 0.22 2.41 r | |
| add_186_aco/U3113/Y (AOI21X1) 0.07 2.48 f | |
| add_186_aco/U2987/Y (OAI21XL) 0.09 2.57 r | |
| add_186_aco/U3014/Y (AOI21XL) 0.07 2.64 f | |
| add_186_aco/U2098/Y (OAI21XL) 0.11 2.75 r | |
| add_186_aco/U2033/Y (INVX1) 0.07 2.82 f | |
| add_186_aco/U2034/Y (CLKINVX2) 0.06 2.88 r | |
| add_186_aco/U3220/Y (XNOR2X1) 0.14 3.03 f | |
| add_186_aco/SUM[128] (IOTDF_DW01_add_1) 0.00 3.03 f | |
| U3944/Y (CLKMX2X2) 0.17 3.20 f | |
| sum_reg[128]/D (DFFRX1) 0.00 3.20 f | |
| data arrival time 3.20 | |
| clock clk (rise edge) 2.50 2.50 | |
| clock network delay (ideal) 1.00 3.50 | |
| clock uncertainty -0.10 3.40 | |
| sum_reg[128]/CK (DFFRX1) 0.00 3.40 r | |
| library setup time -0.20 3.20 | |
| data required time 3.20 | |
| -------------------------------------------------------------------------- | |
| data required time 3.20 | |
| data arrival time -3.20 | |
| -------------------------------------------------------------------------- | |
| slack (MET) 0.00 | |
| 1 | |
| exit | |
| Memory usage for this session 219 Mbytes. | |
| Memory usage for this session including child processes 383 Mbytes. | |
| CPU usage for this session 116 seconds ( 0.03 hours ). | |
| Elapsed time for this session 81 seconds ( 0.02 hours ). | |
| Thank you... | |
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