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BCM3380 Source Code
Raw
3380_intr.h
/*
<:copyright-gpl
Copyright 2007 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
#ifndef __3380_INTR_H
#define __3380_INTR_H
#ifdef __cplusplus
extern "C" {
#endif
#define INTERRUPT_ID_SOFTWARE_0 0
#define INTERRUPT_ID_SOFTWARE_1 1
/*=====================================================================*/
/* BCM3380 Timer Interrupt Level Assignments */
/*=====================================================================*/
#define MIPS_TIMER_INT 7
/*=====================================================================*/
/* Peripheral ISR Table Offset */
/*=====================================================================*/
#define INTERNAL_ISR_TABLE_OFFSET 8
/*=====================================================================*/
/* Logical Peripheral Interrupt IDs */
/*=====================================================================*/
#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0)
#define INTERRUPT_ID_SPI (INTERNAL_ISR_TABLE_OFFSET + 1)
#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2)
#define INTERRUPT_ID_UART1 (INTERNAL_ISR_TABLE_OFFSET + 3)
#define INTERRUPT_ID_SIMCARD0 (INTERNAL_ISR_TABLE_OFFSET + 4)
#define INTERRUPT_ID_SIMCARD1 (INTERNAL_ISR_TABLE_OFFSET + 5)
#define INTERRUPT_ID_I2C (INTERNAL_ISR_TABLE_OFFSET + 6)
#define INTERRUPT_ID_HS_SPI (INTERNAL_ISR_TABLE_OFFSET + 7)
#define INTERRUPT_ID_RING_OSC (INTERNAL_ISR_TABLE_OFFSET + 8)
#define INTERRUPT_ID_PERIPH_ERR (INTERNAL_ISR_TABLE_OFFSET + 9)
#define INTERRUPT_ID_RESERVED_10 (INTERNAL_ISR_TABLE_OFFSET + 10)
#define INTERRUPT_ID_RESERVED_11 (INTERNAL_ISR_TABLE_OFFSET + 11)
#define INTERRUPT_ID_RESERVED_12 (INTERNAL_ISR_TABLE_OFFSET + 12)
#define INTERRUPT_ID_RESERVED_13 (INTERNAL_ISR_TABLE_OFFSET + 13)
#define INTERRUPT_ID_RESERVED_14 (INTERNAL_ISR_TABLE_OFFSET + 14)
#define INTERRUPT_ID_PCIE_RC (INTERNAL_ISR_TABLE_OFFSET + 15)
#define INTERRUPT_ID_PCIE_EP_LNK_RST (INTERNAL_ISR_TABLE_OFFSET + 16)
#define INTERRUPT_ID_BRG_UBUS0 (INTERNAL_ISR_TABLE_OFFSET + 17)
#define INTERRUPT_ID_BRG_UBUS1 (INTERNAL_ISR_TABLE_OFFSET + 18)
#define INTERRUPT_ID_FPM (INTERNAL_ISR_TABLE_OFFSET + 19)
#define INTERRUPT_ID_USB0 (INTERNAL_ISR_TABLE_OFFSET + 20)
#define INTERRUPT_ID_USB1 (INTERNAL_ISR_TABLE_OFFSET + 21)
#define INTERRUPT_ID_APM (INTERNAL_ISR_TABLE_OFFSET + 22)
#define INTERRUPT_ID_APM_DMA (INTERNAL_ISR_TABLE_OFFSET + 23)
#define INTERRUPT_ID_UNI_IRQ2 (INTERNAL_ISR_TABLE_OFFSET + 24)
#define INTERRUPT_ID_UNI_IRQ (INTERNAL_ISR_TABLE_OFFSET + 25)
#define INTERRUPT_ID_GPHY_IRQB (INTERNAL_ISR_TABLE_OFFSET + 26)
#define INTERRUPT_ID_DAVIC (INTERNAL_ISR_TABLE_OFFSET + 27)
#define INTERRUPT_ID_OB (INTERNAL_ISR_TABLE_OFFSET + 28)
#define INTERRUPT_ID_RESERVED_29 (INTERNAL_ISR_TABLE_OFFSET + 29)
#define INTERRUPT_ID_RESERVED_30 (INTERNAL_ISR_TABLE_OFFSET + 30)
#define INTERRUPT_ID_EXT_IRQ (INTERNAL_ISR_TABLE_OFFSET + 31)
#define INTERRUPT_ID_MEP_IRQ (INTERNAL_ISR_TABLE_OFFSET + 2 + 32)
#define INTERRUPT_ID_MSP_IRQ (INTERNAL_ISR_TABLE_OFFSET + 3 + 32)
#define INTERRUPT_ID_MSP_SW_IRQ (INTERNAL_ISR_TABLE_OFFSET + 5 + 32)
#define INTERRUPT_ID_LAST INTERRUPT_ID_MSP_SW_IRQ
#define INTERRUPT_ID_MPI INTERRUPT_ID_EXT_IRQ
#ifdef __cplusplus
}
#endif
#endif /* __BCM3380_H */
Raw
3380_map_part.h
//****************************************************************************
//
// Copyright(c) 2007-2008 Broadcom Corporation
//
// This program is the proprietary software of Broadcom Corporation and/or
// its licensors, and may only be used, duplicated, modified or distributed
// pursuant to the terms and conditions of a separate, written license
// agreement executed between you and Broadcom (an "Authorized License").
// Except as set forth in an Authorized License, Broadcom grants no license
// (express or implied), right to use, or waiver of any kind with respect to
// the Software, and Broadcom expressly reserves all rights in and to the
// Software and all intellectual property rights therein. IF YOU HAVE NO
// AUTHORIZED LICENSE, THEN YOU HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY WAY,
// AND SHOULD IMMEDIATELY NOTIFY BROADCOM AND DISCONTINUE ALL USE OF THE
// SOFTWARE.
//
// Except as expressly set forth in the Authorized License,
//
// 1. This program, including its structure, sequence and organization,
// constitutes the valuable trade secrets of Broadcom, and you shall use all
// reasonable efforts to protect the confidentiality thereof, and to use this
// information only in connection with your use of Broadcom integrated circuit
// products.
//
// 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED
// "AS IS" AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, REPRESENTATIONS
// OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
// RESPECT TO THE SOFTWARE. BROADCOM SPECIFICALLY DISCLAIMS ANY AND ALL
// IMPLIED WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR
// A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET
// ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. YOU ASSUME
// THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE.
//
// 3. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM
// OR ITS LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL, SPECIAL,
// INDIRECT, OR EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR IN ANY WAY
// RELATING TO YOUR USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF BROADCOM
// HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN
// EXCESS OF THE AMOUNT ACTUALLY PAID FOR THE SOFTWARE ITSELF OR U.S. $1,
// WHICHEVER IS GREATER. THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY
// FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.
//
//****************************************************************************
// $Id$
//
// Filename: 3380_map.h
// Author: Russell Enderby
// Creation Date: June 13, 2008
//
//****************************************************************************
// Description:
// This file defines addresses of major hardware components of 3380
//
//****************************************************************************
#ifndef __BCM3380_MAP_PART_H
#define __BCM3380_MAP_PART_H
#include "bcmtypes.h"
#ifdef __cplusplus
extern "C" {
#endif
// ------------------- Physical Memory Map -----------------------------------
#define PHYS_DRAM_BASE 0x00000000 // Dynamic RAM Base
// matches isb_decoder.v
#define INTC_BASE 0xb4e00000 // interrupts controller registers
#define UART_BASE 0xb4e00200 // uart registers
#define UART_BASE1 0xb4e00220 // uart registers
#define SPIM_BASE 0xb4e02000 // serial port interface registers
// IntControlRegs TimerControl bits
#define SOFT_RESET 1
#define CP0_CMT_TPID (1<<31)
// macro to convert logical data addresses to physical
// DMA hardware must see physical address
#define LtoP( x ) ( (uint32)x & 0x1fffffff )
#define PtoL( x ) ( LtoP(x) | 0xa0000000 )
// Interrupt Controller mask and status group
typedef struct
{
uint32 iMask;
uint32 iStatus;
} IntMaskStatus;
#define IRQ_BITS 32
// Interrupt Controller
typedef struct IntControl
{
uint32 RevID; // (00) // Revision ID Register
uint32 ClkCtrlLow; // (04) // Clock Control Register LOW
uint32 ClkCtrlHigh; // (08) // Clock Control Register HI
uint32 ClkCtrlUBus; // (0c) // UBUS Clock Control Register
uint32 TimerControl; // (10) // Timer Control Register
IntMaskStatus DocsisIrq[3]; // (14..28) // Docsis Interrupt Mask/Status Registers
uint32 IntPeriphIrqStatus; // (2c) // Internal Periph IRQ Status Register
IntMaskStatus PeriphIrq[4]; // (30..4c) // Internal Periph IRQ Mask/Status Registers
IntMaskStatus IopIrq[2]; // (50..5c) // IOP Interrupt Mask/Status Registers
uint32 DocsisIrqSense; // (60) // Docsis Interrupt Sense Register (0 = hi, 1 = lo)
uint32 PeriphIrqSense; // (64) // Periph Interrupt Sense Register (0 = hi, 1 = lo)
uint32 IopIrqSense; // (68) // IOP Interrupt Sense Register (0 = hi, 1 = lo)
uint32 Ext0IrqControl; // (6c) // External Interrupt Configuration Register 0
uint32 DiagControl; // (70) // Diagnostic and MBIST Control Register
uint32 Ext1IrqControl; // (74) // External Interrupt Configuration Register 1
uint32 IrqOutMask; // (78) // Interrupt Out Mask Register
uint32 DiagSelectControl; // (7c) // Diagnostic Select Control Register
uint32 DiagReadBack; // (80) // Diagnostic Readback Register
uint32 DiagReadBackHi; // (84) // Diagnostic High Readback Register
uint32 DiagMiscControl; // (88) // Miscellaneous Control Register
uint32 SoftResetBLow; // (8c) // Soft ResetB Register Lo
uint32 SoftResetBHigh; // (90) // Soft ResetB Register Hi
uint32 SoftReset; // (94) // Soft Reset Register
uint32 ExtIrqMuxSelect0; // (98) // External IRQ Mux Select Register
} IntControl;
#define PERF ((volatile IntControl * const) INTC_BASE)
#if defined(CONFIG_BCM_LOT1)
#define IrqStatus PeriphIrq[3].iStatus
#define IrqMask PeriphIrq[3].iMask
#else
#define IrqStatus PeriphIrq[2].iStatus
#define IrqMask PeriphIrq[2].iMask
#endif
#define pll_control TimerControl
typedef struct Uart
{
byte unused0;
byte control;
#define BRGEN (1<<7)
#define TXEN (1<<6)
#define RXEN (1<<5)
#define LOOPBK (1<<4)
#define TXPARITYEN (1<<3)
#define TXPARITYEVEN (1<<2)
#define RXPARITYEN (1<<1)
#define RXPARITYEVEN (1<<0)
byte config;
#define XMITBREAK 0x40
#define BITS5SYM 0x00
#define BITS6SYM 0x10
#define BITS7SYM 0x20
#define BITS8SYM 0x30
// 4 low bits are STOP bits/char in 1/8 bit-time intervals. Zero
// represents 1/8 stop bit interval. Fifteen represents 2 stop bits.
#define ONESTOP 0x07
#define TWOSTOP 0x0f
byte fifoctl;
#define RSTTXFIFOS 0x80
#define RSTRXFIFOS 0x40
#define RSTTXDN 0x20
// 5-bit TimeoutCnt is in low bits of this register.
// This count represents the number of character
// idle times before setting receive Irq when below threshold
// When we divide SysClk/2/(1+baudword) we should get 32*bit-rate
uint32 baudword;
// Read-only fifo depth
byte txf_levl;
byte rxf_levl;
// Upper 4-bits are TxThresh, Lower are RxThresh. Irq can be asserted
// when rxf_level > RxThresh and/or txf_level < TxThresh
byte fifocfg;
// Set value of DTR & RTS if bits are enabled to GPIO_o
byte prog_out;
#define UART_DTR_OUT 0x01
#define UART_RTS_OUT 0x02
byte unused1;
// Low 4-bits, set corr bit to 1 to detect irq on rising AND falling
// edges for corresponding GPIO_if enabled (edge insensitive)
byte DeltaIPEdgeNoSense;
// Upper 4 bits: 1 for posedge sense, 0 for negedge sense if
// not configured for edge insensitive (see above)
// Lower 4 bits: Mask to enable change detection IRQ for corresponding
// GPIO_i
byte DeltaIPConfig_Mask;
// Upper 4 bits show which bits have changed (may set IRQ).
// read automatically clears bit
// Lower 4 bits are actual status
byte DeltaIP_SyncIP;
uint16 intMask;
uint16 intStatus;
#define TXCHARDONE (1<<15)
#define RXBRK (1<<14)
#define RXPARERR (1<<13)
#define RXFRAMERR (1<<12)
#define RXFIFONE (1<<11)
#define RXFIFOTHOLD (1<<10)
#define RXFIFOFULL (1<< 9)
#define RXTIMEOUT (1<< 8)
#define RXOVFERR (1<< 7)
#define RXUNDERR (1<< 6)
#define TXFIFOEMT (1<< 5)
#define TXREADLATCH (1<< 4)
#define TXFIFOTHOLD (1<< 3)
#define TXOVFERR (1<< 2)
#define TXUNDERR (1<< 1)
#define DELTAIP (1<< 0)
uint16 unused2;
// Write to TX, Read from RX. Bits 11:8 are BRK,PAR,FRM errors
uint16 Data;
} Uart;
#define UART0 ((volatile Uart * const) UART_BASE)
/*
** Spi Controller
*/
/* TBD. Taken from 6358_map.h. Need to verify for BCM6368. */
typedef struct SpiControl {
uint16 spiMsgCtl; /* (0x0) control byte */
#define FULL_DUPLEX_RW 0
#define HALF_DUPLEX_W 1
#define HALF_DUPLEX_R 2
#define SPI_MSG_TYPE_SHIFT 14
#define SPI_BYTE_CNT_SHIFT 0
byte spiMsgData[0x21e]; /* (0x02 - 0x21f) msg data */
byte unused0[0x1e0];
byte spiRxDataFifo[0x220]; /* (0x400 - 0x61f) rx data */
byte unused1[0xe0];
uint16 spiCmd; /* (0x700): SPI command */
#define SPI_CMD_NOOP 0
#define SPI_CMD_SOFT_RESET 1
#define SPI_CMD_HARD_RESET 2
#define SPI_CMD_START_IMMEDIATE 3
#define SPI_CMD_COMMAND_SHIFT 0
#define SPI_CMD_COMMAND_MASK 0x000f
#define SPI_CMD_DEVICE_ID_SHIFT 4
#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
#define SPI_CMD_ONE_BYTE_SHIFT 11
#define SPI_CMD_ONE_WIRE_SHIFT 12
#define SPI_DEV_ID_0 0
#define SPI_DEV_ID_1 1
#define SPI_DEV_ID_2 2
#define SPI_DEV_ID_3 3
byte spiIntStatus; /* (0x702): SPI interrupt status */
byte spiMaskIntStatus; /* (0x703): SPI masked interrupt status */
byte spiIntMask; /* (0x704): SPI interrupt mask */
#define SPI_INTR_CMD_DONE 0x01
#define SPI_INTR_RX_OVERFLOW 0x02
#define SPI_INTR_INTR_TX_UNDERFLOW 0x04
#define SPI_INTR_TX_OVERFLOW 0x08
#define SPI_INTR_RX_UNDERFLOW 0x10
#define SPI_INTR_CLEAR_ALL 0x1f
byte spiStatus; /* (0x705): SPI status */
#define SPI_RX_EMPTY 0x02
#define SPI_CMD_BUSY 0x04
#define SPI_SERIAL_BUSY 0x08
byte spiClkCfg; /* (0x706): SPI clock configuration */
#define SPI_CLK_0_391MHZ 1
#define SPI_CLK_0_781MHZ 2 /* default */
#define SPI_CLK_1_563MHZ 3
#define SPI_CLK_3_125MHZ 4
#define SPI_CLK_6_250MHZ 5
#define SPI_CLK_12_50MHZ 6
#define SPI_CLK_MASK 0x07
#define SPI_SSOFFTIME_MASK 0x38
#define SPI_SSOFFTIME_SHIFT 3
#define SPI_BYTE_SWAP 0x80
byte spiFillByte; /* (0x707): SPI fill byte */
byte unused2;
byte spiMsgTail; /* (0x709): msgtail */
byte unused3;
byte spiRxTail; /* (0x70B): rxtail */
} SpiControl;
#define SPI ((volatile SpiControl * const) SPIM_BASE)
#ifdef __cplusplus
}
#endif
#endif
Raw
bcm3380.h
// ****************************************************************************
//
// Copyright (c) 2008 Broadcom Corporation
//
// This program is the proprietary software of Broadcom Corporation and/or
// its licensors, and may only be used, duplicated, modified or distributed
// pursuant to the terms and conditions of a separate, written license
// agreement executed between you and Broadcom (an "Authorized License").
// Except as set forth in an Authorized License, Broadcom grants no license
// (express or implied), right to use, or waiver of any kind with respect to
// the Software, and Broadcom expressly reserves all rights in and to the
// Software and all intellectual property rights therein. IF YOU HAVE NO
// AUTHORIZED LICENSE, THEN YOU HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY WAY,
// AND SHOULD IMMEDIATELY NOTIFY BROADCOM AND DISCONTINUE ALL USE OF THE
// SOFTWARE.
//
// Except as expressly set forth in the Authorized License,
//
// 1. This program, including its structure, sequence and organization,
// constitutes the valuable trade secrets of Broadcom, and you shall use all
// reasonable efforts to protect the confidentiality thereof, and to use this
// information only in connection with your use of Broadcom integrated circuit
// products.
//
// 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED
// "AS IS" AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, REPRESENTATIONS
// OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
// RESPECT TO THE SOFTWARE. BROADCOM SPECIFICALLY DISCLAIMS ANY AND ALL
// IMPLIED WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR
// A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET
// ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. YOU ASSUME
// THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE.
//
// 3. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM
// OR ITS LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL, SPECIAL,
// INDIRECT, OR EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR IN ANY WAY
// RELATING TO YOUR USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF BROADCOM
// HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN
// EXCESS OF THE AMOUNT ACTUALLY PAID FOR THE SOFTWARE ITSELF OR U.S. $1,
// WHICHEVER IS GREATER. THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY
// FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.
//
// ****************************************************************************
//
// Filename: bcm3380.h
// Generated by: RDB Utility
// Creation Date: 8/7/2008
// Command Line:
// ****************************************************************************
//
// IMPORTANT: DO NOT MODIFY, THIS IS AN AUTOGENERATED FILE.
// Please modify the source .rdb file instead if you need to change this file.
// Contact Jeff Bauch if you need more information.
//
// ****************************************************************************
#ifndef BCM3380_H__
#define BCM3380_H__
#include "bridge_blockdef.h"
#include "unimac.h"
#include "usmac30_blockdef.h"
#include "ddr_top_blockdef.h"
#include "fap_blockdef.h"
#include "ds_top.h"
#include "davic_blockdef.h"
#include "periph_blockdef.h"
#include "legacy_mac_blockdef.h"
#include "tc_blockdef.h"
#include "crypto_blockdef.h"
#include "pico_imem_blockdef.h"
#include "hs_spim_blockdef.h"
#include "utp_blockdef.h"
#include "us_regs.h"
#include "apm_blockdef.h"
#include "bmu_blockdef.h"
#include "pcie_blockdef.h"
#include "dtp_blockdef.h"
#include "usb_otg_blockdef.h"
#include "spim_blockdef.h"
#include "oob_blockdef.h"
#include "downstream_blockdef.h"
#include "fpm_blockdef.h"
#include "segdma_blockdef.h"
typedef struct {
union {
struct {
uint8 Pad0[0x12000000];
DdrTop DdrBlock;
} ;
struct {
uint8 Pad1[0x12010000];
Fpm FpmBlock;
} ;
struct {
uint8 Pad2[0x12020000];
LegacyMac1 LegacyMacBlock;
} ;
struct {
uint8 Pad3[0x12030000];
SegdmaBlockSegdmaBlock SegdmaBlock;
} ;
struct {
uint8 Pad4[0x12034000];
TcTop TcBlock0;
} ;
struct {
uint8 Pad5[0x12035000];
TcTop TcBlock1;
} ;
struct {
uint8 Pad6[0x12036000];
TcTop TcBlock2;
} ;
struct {
uint8 Pad7[0x12037000];
TcTop TcBlock3;
} ;
struct {
uint8 Pad8[0x12038000];
Usmac30BlockUsmac301 Usmac30Block;
} ;
struct {
uint8 Pad9[0x1203c000];
Us UsBlock;
} ;
struct {
uint8 Pad10[0x12040000];
CryptoBlockCryptoBlock CryptoBlock;
} ;
struct {
uint8 Pad11[0x12070000];
Bridge BridgeBlock;
} ;
struct {
uint8 Pad12[0x12100000];
Unimac UnimacBlock0;
} ;
struct {
uint8 Pad13[0x12110000];
Unimac UnimacBlock1;
} ;
struct {
uint8 Pad14[0x12120000];
Davic DavicBlock;
} ;
struct {
uint8 Pad15[0x14000000];
UtpBlockUtpBlock UtpBlock;
} ;
struct {
uint8 Pad16[0x14200000];
DtpBlockDtpBlock DtpBlock;
} ;
struct {
uint8 Pad17[0x14400000];
FapBlockFapBlock FapBlock;
} ;
struct {
uint8 Pad18[0x14600000];
FapBlockFapBlock MepBlock;
} ;
struct {
uint8 Pad19[0x14c00000];
Dsmac30 Dsmac30Block;
} ;
struct {
uint8 Pad20[0x14c10000];
DsTop DsTopBlock;
} ;
struct {
uint8 Pad21[0x14c30000];
OobTop OobTopBlock;
} ;
struct {
uint8 Pad22[0x14e00000];
Periph PeriphBlock;
} ;
struct {
uint8 Pad23[0x14e00400];
SpiMaster SpiMasterBlock;
} ;
struct {
uint8 Pad24[0x15000000];
UsbOtgSingle UsbOtgBlock0;
} ;
struct {
uint8 Pad25[0x15200000];
UsbOtgSingle UsbOtgBlock1;
} ;
struct {
uint8 Pad26[0x15400000];
Apm ApmBlock;
} ;
struct {
uint8 Pad27[0x15401000];
Bmu BmuBlock;
} ;
struct {
uint8 Pad28[0x15410000];
PicoImem PicoImemBlock;
} ;
struct {
uint8 Pad29[0x15800000];
FapBlockFapBlock MspBlock;
} ;
};
} Bcm3380A0;
#endif
Raw
IntControl.h
// ****************************************************************************
//
// Copyright (c) 2008 Broadcom Corporation
//
// This program is the proprietary software of Broadcom Corporation and/or
// its licensors, and may only be used, duplicated, modified or distributed
// pursuant to the terms and conditions of a separate, written license
// agreement executed between you and Broadcom (an "Authorized License").
// Except as set forth in an Authorized License, Broadcom grants no license
// (express or implied), right to use, or waiver of any kind with respect to
// the Software, and Broadcom expressly reserves all rights in and to the
// Software and all intellectual property rights therein. IF YOU HAVE NO
// AUTHORIZED LICENSE, THEN YOU HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY WAY,
// AND SHOULD IMMEDIATELY NOTIFY BROADCOM AND DISCONTINUE ALL USE OF THE
// SOFTWARE.
//
// Except as expressly set forth in the Authorized License,
//
// 1. This program, including its structure, sequence and organization,
// constitutes the valuable trade secrets of Broadcom, and you shall use all
// reasonable efforts to protect the confidentiality thereof, and to use this
// information only in connection with your use of Broadcom integrated circuit
// products.
//
// 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED
// "AS IS" AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, REPRESENTATIONS
// OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
// RESPECT TO THE SOFTWARE. BROADCOM SPECIFICALLY DISCLAIMS ANY AND ALL
// IMPLIED WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR
// A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET
// ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. YOU ASSUME
// THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE.
//
// 3. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM
// OR ITS LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL, SPECIAL,
// INDIRECT, OR EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR IN ANY WAY
// RELATING TO YOUR USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF BROADCOM
// HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN
// EXCESS OF THE AMOUNT ACTUALLY PAID FOR THE SOFTWARE ITSELF OR U.S. $1,
// WHICHEVER IS GREATER. THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY
// FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.
//
// ****************************************************************************
//
// Filename: IntControl.h
// Generated by: RDB Utility
// Creation Date: 8/7/2008
// Command Line:
// ****************************************************************************
//
// IMPORTANT: DO NOT MODIFY, THIS IS AN AUTOGENERATED FILE.
// Please modify the source .rdb file instead if you need to change this file.
// Contact Jeff Bauch if you need more information.
//
// ****************************************************************************
#ifndef INTCONTROL_H__
#define INTCONTROL_H__
typedef union {
struct {
uint32 Reserved :9;
uint32 DsTunerIrq :1;
uint32 DsIrq :1;
uint32 D3macIrq :1;
uint32 D3macDsaIrq :1;
uint32 D3macDsbIrq :1;
uint32 D3macTokaIrq :1;
uint32 D3macTokbIrq :1;
uint32 Reserved2 :5;
uint32 UsIrq :1;
uint32 DlmacMacIrq :1;
uint32 Tc0Irq :1;
uint32 Tc1Irq :1;
uint32 Tc2Irq :1;
uint32 Tc3Irq :1;
uint32 CryptoIrq :1;
uint32 SegHostIrq :1;
uint32 SegUtpIrq :1;
uint32 U3macMacIrqa :1;
uint32 U3macMacIrqb :1;
} Bits;
uint32 Reg32;
} IntControlDocsisIrqMask;
typedef union {
struct {
uint32 Reserved :9;
uint32 DsTunerIrq :1;
uint32 DsIrq :1;
uint32 D3macIrq :1;
uint32 D3macDsaIrq :1;
uint32 D3macDsbIrq :1;
uint32 D3macTokaIrq :1;
uint32 D3macTokbIrq :1;
uint32 Reserved2 :5;
uint32 UsIrq :1;
uint32 DlmacMacIrq :1;
uint32 Tc0Irq :1;
uint32 Tc1Irq :1;
uint32 Tc2Irq :1;
uint32 Tc3Irq :1;
uint32 CryptoIrq :1;
uint32 SegHostIrq :1;
uint32 SegUtpIrq :1;
uint32 U3macMacIrqa :1;
uint32 U3macMacIrqb :1;
} Bits;
uint32 Reg32;
} IntControlDocsisIrqSense;
typedef union {
struct {
uint32 Reserved :9;
uint32 DsTunerIrq :1;
uint32 DsIrq :1;
uint32 D3macIrq :1;
uint32 D3macDsaIrq :1;
uint32 D3macDsbIrq :1;
uint32 D3macTokaIrq :1;
uint32 D3macTokbIrq :1;
uint32 Reserved2 :5;
uint32 UsIrq :1;
uint32 DlmacMacIrq :1;
uint32 Tc0Irq :1;
uint32 Tc1Irq :1;
uint32 Tc2Irq :1;
uint32 Tc3Irq :1;
uint32 CryptoIrq :1;
uint32 SegHostIrq :1;
uint32 SegUtpIrq :1;
uint32 U3macMacIrqa :1;
uint32 U3macMacIrqb :1;
} Bits;
uint32 Reg32;
} IntControlDocsisIrqStatus;
typedef union {
struct {
uint32 Reserved :2;
uint32 ExtIrqLevelSense :6;
uint32 EdgeInsensitive :6;
uint32 ExtIrqMask :6;
uint32 ExtIrqStatus :6;
uint32 ExtIrqSense :6;
} Bits;
uint32 Reg32;
} IntControlExtIrqControl;
typedef union {
struct {
uint32 Reserved :2;
uint32 ExtIrq5Sel :5;
uint32 ExtIrq4Sel :5;
uint32 ExtIrq3Sel :5;
uint32 ExtIrq2Sel :5;
uint32 ExtIrq1Sel :5;
uint32 ExtIrq0Sel :5;
} Bits;
uint32 Reg32;
} IntControlExtIrqMuxSel0;
typedef union {
struct {
uint32 Reserved :24;
uint32 RbusErrorIrq :1;
uint32 BridgeTimeoutErrorIrq :1;
uint32 ReqoutPlenErrorIrq :1;
uint32 Ubus2rbusRepoutErrorIrq :1;
uint32 BridgeUbusErrorIrq :1;
uint32 DevtimeoutIrq :1;
uint32 ErrorPortXactionIrq :1;
uint32 BadBootLocIrq :1;
} Bits;
uint32 Reg32;
} IntControlIntPeriphIrqStatus;
typedef union {
struct {
uint32 Reserved :27;
uint32 Fapirq :1;
uint32 Mspirq :1;
uint32 Mepirq :1;
uint32 Dtpirq :1;
uint32 Utpirq :1;
} Bits;
uint32 Reg32;
} IntControlIopIrqMask;
typedef union {
struct {
uint32 Reserved :27;
uint32 DtpIrq :1;
uint32 Fapirq :1;
uint32 Mspirq :1;
uint32 Mepirq :1;
uint32 Utpirq :1;
} Bits;
uint32 Reg32;
} IntControlIopIrqSense;
typedef union {
struct {
uint32 Reserved :27;
uint32 Fapirq :1;
uint32 Mspirq :1;
uint32 Mepirq :1;
uint32 DtpIrq :1;
uint32 Utpirq :1;
} Bits;
uint32 Reg32;
} IntControlIopIrqStatus;
typedef union {
struct {
uint32 PcieEpIrqMask7 :1;
uint32 PcieEpIrqMask6 :1;
uint32 PcieEpIrqMask5 :1;
uint32 PcieEpIrqMask4 :1;
uint32 PcieEpIrqMask3 :1;
uint32 PcieEpIrqMask2 :1;
uint32 PcieEpIrqMask1 :1;
uint32 PcieEpIrqMask0 :1;
uint32 UbuscaptureIrqMask7 :1;
uint32 UbuscaptureIrqMask6 :1;
uint32 UbuscaptureIrqMask5 :1;
uint32 UbuscaptureIrqMask4 :1;
uint32 UbuscaptureIrqMask3 :1;
uint32 UbuscaptureIrqMask2 :1;
uint32 UbuscaptureIrqMask1 :1;
uint32 UbuscaptureIrqMask0 :1;
uint32 TestbusIrqMask7 :1;
uint32 TestbusIrqMask6 :1;
uint32 TestbusIrqMask5 :1;
uint32 TestbusIrqMask4 :1;
uint32 TestbusIrqMask3 :1;
uint32 TestbusIrqMask2 :1;
uint32 TestbusIrqMask1 :1;
uint32 TestbusIrqMask0 :1;
uint32 SysirqIrqMask7 :1;
uint32 SysirqIrqMask6 :1;
uint32 SysirqIrqMask5 :1;
uint32 SysirqIrqMask4 :1;
uint32 SysirqIrqMask3 :1;
uint32 SysirqIrqMask2 :1;
uint32 SysirqIrqMask1 :1;
uint32 SysirqIrqMask0 :1;
} Bits;
uint32 Reg32;
} IntControlIrqOutMask;
typedef union {
struct {
uint32 ExtIrq :1;
uint32 Reserved :2;
uint32 ObObIrq :1;
uint32 DavicIrq :1;
uint32 GphyIrqb :1;
uint32 UniIrq :1;
uint32 UniIrq2 :1;
uint32 ApmIudmaIrq :1;
uint32 ApmIrq :1;
uint32 UsbIrq1 :1;
uint32 UsbIrq0 :1;
uint32 FpmIrq :1;
uint32 BridgeUbus1StatIrq :1;
uint32 BridgeUbus0StatIrq :1;
uint32 PcieEpLinkRst :1;
uint32 PcieRcIrq :1;
uint32 Reserved2 :5;
uint32 PeriphErrorDetect :1;
uint32 RingOscIrq :1;
uint32 HsSpiIrq :1;
uint32 I2cIrq :1;
uint32 Simcard1Irq :1;
uint32 Simcard0Irq :1;
uint32 Uart1irq :1;
uint32 Uart0irq :1;
uint32 LsSpiIrq :1;
uint32 Timrirq :1;
} Bits;
uint32 Reg32;
} IntControlPeriphIrqMask;
typedef union {
struct {
uint32 ExtIrq :1;
uint32 Reserved :2;
uint32 ObObIrq :1;
uint32 DavicIrq :1;
uint32 GphyIrqb :1;
uint32 UniIrq :1;
uint32 UniIrq2 :1;
uint32 ApmIudmaIrq :1;
uint32 ApmIrq :1;
uint32 UsbIrq1 :1;
uint32 UsbIrq0 :1;
uint32 FpmIrq :1;
uint32 BridgeUbus1StatIrq :1;
uint32 BridgeUbus0StatIrq :1;
uint32 PcieEpLinkRst :1;
uint32 PcieRcIrq :1;
uint32 Reserved2 :5;
uint32 PeriphErrorDetect :1;
uint32 RingOscIrq :1;
uint32 HsSpiIrq :1;
uint32 I2cIrq :1;
uint32 Simcard1Irq :1;
uint32 Simcard0Irq :1;
uint32 Uart1irq :1;
uint32 Uart0irq :1;
uint32 LsSpiIrq :1;
uint32 Timrirq :1;
} Bits;
uint32 Reg32;
} IntControlPeriphIrqSense;
typedef union {
struct {
uint32 ExtIrq :1;
uint32 Reserved :2;
uint32 ObObIrq :1;
uint32 DavicIrq :1;
uint32 GphyIrqb :1;
uint32 UniIrq :1;
uint32 UniIrq2 :1;
uint32 ApmIudmaIrq :1;
uint32 ApmIrq :1;
uint32 UsbIrq1 :1;
uint32 UsbIrq0 :1;
uint32 FpmIrq :1;
uint32 BridgeUbus1StatIrq :1;
uint32 BridgeUbus0StatIrq :1;
uint32 PcieEpLinkRst :1;
uint32 PcieRcIrq :1;
uint32 Reserved2 :5;
uint32 PeriphErrorDetect :1;
uint32 RingOscIrq :1;
uint32 HsSpiIrq :1;
uint32 I2cIrq :1;
uint32 Simcard1Irq :1;
uint32 Simcard0Irq :1;
uint32 Uart1irq :1;
uint32 Uart0irq :1;
uint32 LsSpiIrq :1;
uint32 Timrirq :1;
} Bits;
uint32 Reg32;
} IntControlPeriphIrqStatus;
typedef union {
struct {
uint32 Chipid :16;
uint32 Revid :16;
} Bits;
uint32 Reg32;
} IntControlRevId;
typedef union {
struct {
uint32 Reserved :16;
uint32 GphyClkEn :1;
uint32 Usb1ClkEn :1;
uint32 UsbClkEn :1;
uint32 DsTunerClkEn :1;
uint32 ObClkEn :1;
uint32 UsTopClkEn :1;
uint32 Ds7ClkEn :1;
uint32 Ds6ClkEn :1;
uint32 Ds5AClkEn :1;
uint32 Ds4BClkEn :1;
uint32 Ds3ClkEn :1;
uint32 Ds2ClkEn :1;
uint32 Ds1ClkEn :1;
uint32 Ds0ClkEn :1;
uint32 GphyPllClkEn :1;
uint32 PciePllClkEn :1;
} Bits;
uint32 Reg32;
} IntControlClkControlHi;
typedef union {
struct {
uint32 AudioBClkEn :1;
uint32 AudioAClkEn :1;
uint32 AudioComClkEn :1;
uint32 NtpClkEn :1;
uint32 PcmClkEn :1;
uint32 BmuClkEn :1;
uint32 ApmClkEn :1;
uint32 ApmPllClkEn :1;
uint32 MipsClkEn :1;
uint32 BrgRbusClkEn :1;
uint32 DavicClkEn :1;
uint32 Unimac1ClkEn :1;
uint32 Unimac0ClkEn :1;
uint32 SpimGlessClkEn :1;
uint32 SpimClkEn :1;
uint32 PcieClkEn :1;
uint32 Tc3ClkEn :1;
uint32 Tc2ClkEn :1;
uint32 Tc1ClkEn :1;
uint32 Tc0ClkEn :1;
uint32 SegdmaClkEn :1;
uint32 Usmac30ClkEn :1;
uint32 Usmac20ClkEn :1;
uint32 D3dsmacClkEn :1;
uint32 MspClkEn :1;
uint32 MepClkEn :1;
uint32 FapClkEn :1;
uint32 UtpClkEn :1;
uint32 DtpClkEn :1;
uint32 CryptoClkEn :1;
uint32 FpmClkEn :1;
uint32 DdrClkEn :1;
} Bits;
uint32 Reg32;
} IntControlClkControlLo;
typedef union {
struct {
uint32 Reserved :7;
uint32 DiagMbistCntl :25;
} Bits;
uint32 Reg32;
} IntControlDiagControl;
typedef union {
struct {
uint32 Reserved :30;
uint32 DsphyByp :1;
uint32 Reserved2 :1;
} Bits;
uint32 Reg32;
} IntControlDiagMiscControl;
typedef union {
struct {
uint32 Reserved :24;
uint32 DiagReadBackHi :8;
} Bits;
uint32 Reg32;
} IntControlDiagReadBackHi;
typedef union {
struct {
uint32 SpiOverride :1;
uint32 Reserved :2;
uint32 UbusObservabilityEn :1;
uint32 DiagHiClkEn :1;
uint32 DiagHiEn :1;
uint32 DiagLoClkEn :1;
uint32 DiagLoEn :1;
uint32 Reserved2 :2;
uint32 DiagClkPhsSel :6;
uint32 DiagHiSel :8;
uint32 DiagLoSel :8;
} Bits;
uint32 Reg32;
} IntControlDiagSelControl;
typedef union {
struct {
uint32 Reserved :31;
uint32 SoftRstDdr :1;
} Bits;
uint32 Reg32;
} IntControlSoftReset;
typedef union {
struct {
uint32 Reserved :24;
uint32 SoftRstTc3 :1;
uint32 SoftRstTc2 :1;
uint32 SoftRstTc1 :1;
uint32 SoftRstTc0 :1;
uint32 SoftRstPerst :1;
uint32 SoftRstD3legmac :1;
uint32 SoftRstHsSpiPll :1;
uint32 SoftRstHsSpi :1;
} Bits;
uint32 Reg32;
} IntControlSoftResetBHi;
typedef union {
struct {
uint32 SoftRstCrypto :1;
uint32 SoftRstPcieCore :1;
uint32 SoftRstDavIudma :1;
uint32 SoftRstDac :1;
uint32 SoftRstHvgb :1;
uint32 SoftRstHvga :1;
uint32 SoftRstSeg :1;
uint32 SoftRstMsp :1;
uint32 SoftRstMep :1;
uint32 SoftRstFap :1;
uint32 SoftRstDtp :1;
uint32 SoftRstUtp :1;
uint32 SoftRstD3mac :1;
uint32 SoftRstU3log :1;
uint32 SoftRstU3reg :1;
uint32 SoftRstU3mac :1;
uint32 SoftRstBmu :1;
uint32 SoftRstHvg :1;
uint32 SoftRstPcm :1;
uint32 SoftRstApm :1;
uint32 SoftRstAudio :1;
uint32 SoftRstRsvd1 :1;
uint32 SoftRstUnimac1 :1;
uint32 SoftRstUnimac0 :1;
uint32 SoftRstDs :1;
uint32 SoftRstGphy :1;
uint32 SoftRstFpm :1;
uint32 SoftRstRsvd0 :1;
uint32 SoftRstPcie :1;
uint32 SoftRstUsb :1;
uint32 SoftRstAcp :1;
uint32 SoftRstSpi :1;
} Bits;
uint32 Reg32;
} IntControlSoftResetBLo;
typedef union {
struct {
uint32 Reserved :31;
uint32 SoftRst :1;
} Bits;
uint32 Reg32;
} IntControlTimerControl;
typedef union {
struct {
uint32 Reserved :9;
uint32 TestbusUbusClkEn :1;
uint32 BrgUbusClkEn :1;
uint32 DavicUbusClkEn :1;
uint32 UsbotgUbusClkEn :1;
uint32 Unimac1UbusClkEn :1;
uint32 Unimac0UbusClkEn :1;
uint32 FapUbusClkEn :1;
uint32 MspUbusClkEn :1;
uint32 MepUbusClkEn :1;
uint32 DtpUbusClkEn :1;
uint32 UtpcryptoUbusClkEn :1;
uint32 ApmUbusClkEn :1;
uint32 FpmUbusClkEn :1;
uint32 Usmac30UbusClkEn :1;
uint32 D3dsmacUbusClkEn :1;
uint32 SegmacUbusClkEn :1;
uint32 MipsUbusClkEn :1;
uint32 PcieUbusClkEn :1;
uint32 DdrUbusClkEn :1;
uint32 Brg10UbusClkEn :1;
uint32 Brg01UbusClkEn :1;
uint32 Arb1UbusClkEn :1;
uint32 Arb0UbusClkEn :1;
} Bits;
uint32 Reg32;
} IntControlUbusClkControl;
#define INTC_BASE 0xb4e00000
typedef struct {
IntControlRevId Revid; // 0
IntControlClkControlLo ClkcontrolLo; // 4
IntControlClkControlHi ClkcontrolHi; // 8
IntControlUbusClkControl ClkcontrolUbus; // c
IntControlTimerControl TimerControl; // 10
IntControlDocsisIrqMask DocsisIrqmask0; // 14
IntControlDocsisIrqStatus DocsisIrqstatus0; // 18
IntControlDocsisIrqMask DocsisIrqmask1; // 1c
IntControlDocsisIrqStatus DocsisIrqstatus1; // 20
IntControlDocsisIrqMask DocsisIrqmask2; // 24
IntControlDocsisIrqStatus DocsisIrqstatus2; // 28
IntControlIntPeriphIrqStatus IntPeriphIrqstatus; // 2c
IntControlPeriphIrqMask PeriphIrqmask0; // 30
IntControlPeriphIrqStatus PeriphIrqstatus0; // 34
IntControlPeriphIrqMask PeriphIrqmask1; // 38
IntControlPeriphIrqStatus PeriphIrqstatus1; // 3c
IntControlPeriphIrqMask PeriphIrqmask2; // 40
IntControlPeriphIrqStatus PeriphIrqstatus2; // 44
IntControlPeriphIrqMask PeriphIrqmask3; // 48
IntControlPeriphIrqStatus PeriphIrqstatus3; // 4c
IntControlIopIrqMask Iopirqmask0; // 50
IntControlIopIrqStatus Iopirqstatus0; // 54
IntControlIopIrqMask Iopirqmask1; // 58
IntControlIopIrqStatus Iopirqstatus1; // 5c
IntControlDocsisIrqSense DocsisIrqSense; // 60
IntControlPeriphIrqSense PeriphIrqSense; // 64
IntControlIopIrqSense IopirqSense; // 68
IntControlExtIrqControl Ext0irqcontrol; // 6c
IntControlDiagControl Diagcontrol; // 70
IntControlExtIrqControl Ext1irqcontrol; // 74
IntControlIrqOutMask IrqOutMask; // 78
IntControlDiagSelControl Diagselcontrol; // 7c
uint32 Diagreadback; // 80
IntControlDiagReadBackHi Diagreadbackhi; // 84
IntControlDiagMiscControl Diagmisccontrol; // 88
IntControlSoftResetBLo SoftresetbLo; // 8c
IntControlSoftResetBHi SoftresetbHi; // 90
IntControlSoftReset Softreset; // 94
IntControlExtIrqMuxSel0 Extirqmuxsel0; // 98
} IntControlRegs;
#endif
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