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@SKGleba
Created January 23, 2022 00:39
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Snuffleupagus interface for f00d
/*
* Copyright (C) 2021-2022 skgleba
*
* This software may be modified and distributed under the terms
* of the MIT license.
*/
#define READAS_REG 0xE0020040 // readas32 device
#define RAS_DEV_S 0 // default secure
#define RAS_MODE_WRITE 0b1 // write mode
#define RAS_DEV_UNK 0b10 // masks DRAM and DRAM regs, from arm bus
#define RAS_DEV_NS 0b100 // non-secure
// below options only apply to write mode and some offsets in read mode
#define RAS_B0 0b1000
#define RAS_B1 0b10000 // or RAS_NOALIGN in incompatible read offsets
#define RAS_B2 0b100000
#define RAS_B3 0b1000000
#define RAS_32 (RAS_B0 | RAS_B1 | RAS_B2 | RAS_B3)
typedef struct {
unsigned int addr;
unsigned int resp;
unsigned int mode;
} __attribute__((packed)) e002_readas32;
static volatile e002_readas32* const READAS32 = (void*)READAS_REG;
static u32_t readAs(u32_t addr, u32_t mode) {
READAS32->addr = addr;
READAS32->resp = 0xDEADBABE;
READAS32->mode = mode;
while (READAS32->resp == 0xDEADBABE) {} // wait until RAS replies
return READAS32->resp;
}
static void writeAs(u32_t addr, u32_t data, u32_t mode) {
READAS32->addr = addr;
READAS32->resp = data;
READAS32->mode = mode | RAS_MODE_WRITE;
}
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