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Hazard3 Closely-coupled Accelerators

This document describes the Hazard3 closely-coupled accelerator interface (CCA) and the associated the Xh3cca RISC-V extension. The purpose of the CCA interface is:

• Higher write throughput into core-local accelerators
• Support for I/O stalls that do not block debug and IRQs (impossible on AHB)
• Access to accelerators without generating addresses first (reduced register pressure)
• Access to accelerators without address-dependent protection checks (improved control-path timing)
• Atomic (non-tearing) reads of 64-bit buses
• Compatibility with vendor coprocessors designed for Cortex-M systems

Wren6991

#ifdef HAZARD3
#include "tb_cxxrtl_io.h"
#define printf tb_printf
#else
#include <stdio.h>
#endif
#include <stdint.h>

int __attribute__((noinline)) test(int x) {
	int count = 0;

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yosys -p 'read_verilog -DFPGA hazard3_core.v hazard3_cpu_1port.v hazard3_cpu_2port.v arith/hazard3_alu.v arith/hazard3_shift_barrel.v arith/hazard3_priority_encode.v arith/hazard3_muldiv_seq.v arith/hazard3_mul_fast.v hazard3_frontend.v hazard3_instr_decompress.v hazard3_decode.v hazard3_csr.v hazard3_regfile_1w2r.v; hierarchy -top hazard3_cpu_2port; synth_ice40'

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/*****************************************************************************\
|                        Copyright (C) 2021 Luke Wren                         |
|                     SPDX-License-Identifier: Apache-2.0                     |
\*****************************************************************************/

// Hazard3 CPU configuration parameters

// To configure Hazard3 you can either edit this file, or set parameters on
// your top-level instantiation, it's up to you. These parameters are all
// plumbed through Hazard3's internal hierarchy to the appropriate places.

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/*****************************************************************************\
|                        Copyright (C) 2021 Luke Wren                         |
|                     SPDX-License-Identifier: Apache-2.0                     |
\*****************************************************************************/

// Hazard3 CPU configuration parameters

// To configure Hazard3 you can either edit this file, or set parameters on
// your top-level instantiation, it's up to you. These parameters are all
// plumbed through Hazard3's internal hierarchy to the appropriate places.

Wren6991

// Custom CSRs
#define meie0 0xbe0 // External interrupt enable
#define meip0 0xfe0 // External interrupt pending
#define mlei  0xfe4 // Lowest external interrupt, left shifted by 2.

_external_irq_vector:
	// Begin critical section
	addi sp, sp, -16
	sw a0, 0(sp)

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#define OPCODE_AMO  0x2f

#define FUNCT5_AMOSWAP 0x01
#define FUNCT5_AMOADD  0x00
#define FUNCT5_AMOXOR  0x04
#define FUNCT5_AMOAND  0x0c
#define FUNCT5_AMOOR   0x08
#define FUNCT5_AMOMIN  0x10
#define FUNCT5_AMOMAX  0x14
#define FUNCT5_AMOMINU 0x18

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RISCBoy Audio Processing Unit (APU)

Goals:

• Resource budget: 100 LUTs (excluding system interface and digital DACs), two BRAMs
• 48 kHz 8 bit stereo output when running at 36 MHz
• Provide similar capability to an original Gameboy with default microcode
• Be rather more capable with user-supplied microcode
• Easy to use as a dumb wave-out ring buffer interface
• Fun to program

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module priority_select #(
	parameter N = 16 // any positive integer
) (
	input  wire [N-1:0] req,
	output wire [N-1:0] gnt
);

generate
if (N == 1) begin: base_case0
	assign gnt = req;

Wren6991

read_verilog hazard5_alu.v hazard5_shift_barrel.v
write_cxxrtl foo.cpp