reg.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity reg is
  port (
	    clk     : in std_logic;
		i_port  : in  std_logic_vector(7 downto 0);
        o_port       : out  std_logic_vector(7 downto 0)
end entity reg;
	  
architecture arch of reg is
begin
	process(clk) is
	  begin
	  if rising_edge(clk) then
	      o_port <= i_port;
	 end if;
	 end process;
end architecture arch;