PC98 sleigh testing

pc98.sleigh

# V20 format - 29 bits
# TYPE 0
# 0  1. 2. 3. 4. 5. 6. 7. 8. 9. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
# Source  1     |  Destination1| Source2.  |Dst2 |F |W |E | 0 0 | Alu Op.      | Tmp | R
# RMMAAAAA00EWFNNCCCCDDDDDSSSSS
# TYPE 1
# Source  1     |  Destination1| Source2.  |Dst2 |F |W |E | 0 1 | Cndition  | val 0~15  
# NNNNCCCC10EWFNNCCCCDDDDDSSSSS
# TYPE 2 
# Source  1     |  Destination1| Source2.  |Dst2 |F |W |E | 1| INT CTL   | EXT CTL| SR
# RRXXXIIII1EWFNNCCCCDDDDDSSSSS


define endian=little;

?? > define alignment=2;

define space IVT 
    type=ram_space
    size=1024
    default 
?? >    wordsize=2
;

define space register type=register_space size=2;
define register offset=0 size=2
    [AX CX DX BX SP BP SI DI PSW];
# PSW = program status word , v20 flags register (not io mapped)
define register offset=0 size=1
    [AL AH CL CH DL DH BL BH];

define token movw_reg_reg(16)
    opc = (6,15)
    dr16 = (3,5)
    sr16 = (0,2)
;
attach variables [ dr16 sr16 ] [ ax cx dx bx ];
define token movb_reg_reg(16)
    opc = (6,15)
    dr8 = (3,5)
    sr8 = (0,2)
;
attach variables [ dr8 sr8 ] [ al ah cl ch dl dh bl bh];
# 8 bit MOV Rn,Rm - 10001010.11nnnmmm
:MOV dr8, sr8 is opc=0b1000101011 & dr8 & sr8 {
    dr8 = sr8;
}
# 16 bit MOV Rn,Rm - 10001011.11nnnmmm
:MOV dr16, sr16 is opc=0b1000101111 & dr16 & sr16 {
    dr16 = sr16;
}