M1's /usr/share/kpep/a14.plist

14.plist.json

/* plutil -convert json -o - /usr/share/kpep/a14.plist */
{"name":"a14","system":{"cpu":{"config_counters":1020,"marketing_name":"Apple A14","fixed_counters":3,"aliases":{"Instructions":"FIXED_INSTRUCTIONS","MispredictedBranches":"BRANCH_MISPREDICT","Branches":"INST_BRANCH","FPInstructions":"INST_NEON_OR_FP","TLBInstructionMisses":"ITLB_MISS","MMUFaults":"MMU_MISS","ALUInstructions":"INST_INTEGER","L1DataCacheStoreMisses":"DCACHE_STORE_MISS","Cycles":"FIXED_CYCLES","TLBDataMisses":"DTLB_MISS","L1DataCacheLoadMisses":"DCACHE_LOAD_MISS","L1DataCacheAccesses":"INST_LDST"},"events":{"MEMORY_ORDER_VIOLATION":{"counters_mask":224,"number":196,"description":"Incorrect speculation between store and dependent load"},"ATOMIC_OR_EXCLUSIVE_SUCCESS":{"number":179,"description":"Atomic or exclusive instruction successfully completed"},"ICACHE_MISS":{"number":211,"description":"Instruction cache demand misses"},"INST_ALL":{"counters_mask":128,"number":140,"description":"All Instructions"},"INST_LDST":{"counters_mask":128,"number":155,"description":"Load\/store instructions"},"DCACHE_STORE_MISS":{"counters_mask":224,"number":192,"description":"Stores that miss in the L1 Data Cache"},"INST_FUNCTION_CALLS":{"counters_mask":224,"number":142,"description":"Function call instructions"},"INST_ISSUE":{"number":82,"description":"Instruction issued from scheduler"},"INST_FETCH_RESTART":{"number":222,"description":"Instruction fetch pipeline flush"},"ITLB_MISS":{"number":212,"description":"Instruction TLB misses"},"DTLB_MISS":{"counters_mask":224,"number":193,"description":"Data TLB misses"},"FIXED_INSTRUCTIONS":{"counters_mask":2,"fallback":"INST_ALL","fixed_counter":1},"PIPELINE_REDIRECT":{"number":132,"description":"Pipeline redirect caused by misspeculation not covered by other events"},"SCHEDULER_REWIND":{"number":117,"description":"Counts cycles lost in rewinding due to misspeculation"},"CYCLE":{"number":2,"description":"Counts cycles"},"INST_BARRIER":{"counters_mask":224,"number":156,"description":"Barrier instructions (DMB, DSB, ISB, etc)"},"INST_INTEGER":{"counters_mask":128,"number":151,"description":"Non-branch, non-load-store integer instructions"},"INST_BRANCH":{"counters_mask":224,"number":141,"description":"Branch Instructions"},"FIXED_CYCLES":{"counters_mask":1,"fallback":"CYCLE","fixed_counter":0},"ATOMIC_OR_EXCLUSIVE_FAIL":{"number":180,"description":"Atomic or exclusive instruction failed (due to contention)"},"DCACHE_LOAD_MISS":{"counters_mask":224,"number":191,"description":"Loads that miss in the L1 Data Cache"},"INST_FUNCTION_RETURNS":{"counters_mask":224,"number":143,"description":"Function return instructions"},"MMU_MISS":{"number":13,"description":"Translation request miss in MMU"},"BRANCH_MISPREDICT":{"counters_mask":224,"number":203,"description":"Branch mispredict"},"DISPATCH_STALL":{"number":112,"description":"Counts cycles when dispatch is stalled"},"SCHEDULER_STALL":{"number":118,"description":"Counts cycles when the scheduler is stalled"},"INST_NEON_OR_FP":{"counters_mask":128,"number":154,"description":"Non-load-store neon or FP instructions"},"INTERRUPT_PENDING":{"number":108,"description":"Counts cycles when an Interrupt is pending because it is masked"}},"architecture":"arm64","power_counters":224}},"version":[1,0]}