This gist shows an example for why an "accept" as an optional feature would be nice to have in the airhdl generated register files. It would connect to a register file which implements a memory field. Read is just included for completeness. A testbench for how I would imagine the output of the register file to look is also included.

random_delay_write.sv

module tb;

    logic clk_axi;
    initial begin
        clk_axi = 1'd0;
        forever begin
            clk_axi <= !clk_axi;
            #(800ps/2.0);        
        end
    end

    logic rstn_axi;
    initial begin
        rstn_axi= 1'd0;
        #102ns;
        @(posedge clk_axi);
        rstn_axi= 1'd1;
    end
    
    logic ex_we,ex_accept;
    logic [7:0] ex_addr;
    logic [31:0] ex_data;
    example_mem example_mem(.clk(clk_axi), .rstn(rstn_axi), .we(ex_we), .waccept(ex_accept), .waddress(ex_addr), .wdata(ex_data), .rdata(), .raddress());
    initial begin
        ex_we = 1'd0;
        ex_addr = 'd0;
        ex_data = 'd0;
        wait(rstn_axi);

        @(posedge clk_axi);
        for (int i = 0; i< 256; i++) begin
            #100ps;
            ex_addr = i;
            ex_data = $urandom();
            ex_we = 1'd1;
            @(posedge clk_axi);
            while (!ex_accept) @(posedge clk_axi);
            ex_we = 1'd0;
            @(posedge clk_axi);
        end
    end
endmodule

module example_mem(
    input logic clk,
    input logic rstn,
    input logic we,
    output logic waccept,
    input logic [7:0] waddress,
    input logic [31:0] wdata,
    output logic [31:0] rdata,
    input logic [7:0] raddress
);
    logic [255:0][31:0] mem;
    logic unsigned [7:0] delay_cnt;
    always_ff @(posedge clk) begin
        if (!rstn) delay_cnt <= 'd0;
        else if (we && delay_cnt == 0) delay_cnt <= $urandom() % 20; //Example: It takes a random number of cycles (less than 20) to actually write data 
        else if (delay_cnt >0) delay_cnt <= delay_cnt - 'd1;
    end
    assign waccept = (delay_cnt == 'd1);
    always_ff @(posedge clk) begin
        if (delay_cnt == 'd1) mem[waddress] <= wdata;
    end
    
    assign rdata = mem[raddress];
endmodule;