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ciniml / regslice.sv

Created February 14, 2025 04:31

axi4 stream register slice

	`default_nettype none
	module register_slice #(
	parameter int WIDTH_BITS = 8
	)(
	input wire clock, // クロック
	input wire reset, // リセット (正論理)
	input wire input_valid, // 入力VALID
	output logic input_ready, // 入力READY
	input wire [WIDTH_BITS-1:0] input_data, // 入力データ

ciniml / disable_chip_wdt.c

Created August 6, 2024 13:47

Disable Chip WDT for ESP32-C3/S3

	#include "hal/wdt_hal.h"

	static void disable_chip_wdt(void) {
	wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
	wdt_hal_write_protect_disable(&rtc_wdt_ctx);
	wdt_hal_disable(&rtc_wdt_ctx);
	wdt_hal_write_protect_enable(&rtc_wdt_ctx);
	}

ciniml / wisecoco_1280x400_edid.txt

Created May 25, 2024 16:32

Wisecoco 1280x400 HDMI display EDID

	$ edid-decode /sys/class/drm/card1-HDMI-A-2/edid
	edid-decode (hex):

	00 ff ff ff ff ff ff 00 67 13 66 66 00 00 00 00
	1e 20 01 04 82 00 00 78 ee de 50 a3 54 4c 99 26
	0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
	01 01 01 01 01 01 e4 10 90 82 10 00 50 50 32 1e
	e4 05 0a c0 00 00 00 18 e4 10 90 82 10 00 50 50
	32 1e e4 05 0a c0 00 00 00 18 e4 10 90 82 10 00
	50 50 32 1e e4 05 0a c0 00 00 00 18 00 00 00 fc

ciniml / scs0009_test.py

Created May 21, 2024 17:37

SCS0009 test

	import time
	import serial
	import struct
	from typing import Tuple

	s = serial.Serial('COM19', 1000000)
	def read_packet(servo_id: int, reg_address: int, reg_length: int) -> Tuple[bytes, int]:
	packet = [0xff, 0xff, servo_id, 0x04, 0x02, reg_address, reg_length]
	packet.append(0xff - (sum(packet[2:]) & 0xff)) # checksum
	response_length = 2 + 1 + 1 + 1 + reg_length + 1 # header, servo_id, packet_length, command, content, checksum

ciniml / pin_table.md

Created November 21, 2022 06:37

RMII TangNano9K pin table

名称	ピン	信号名	TN9K	FPGAピン
TX1	1	rmii_txd[1]	J5 1	38
NC	2
TX-EN	3	rmii_txen	J5 2	37
TX0	4	rmii_txd[0]	J5 3	36
RX0	5	rmii_rxd[0]	J5 4	39
RX1	6	rmii_rxd[1]	J5 5	25
REFCLK	7	rmii_txclk	J5 6	26
CRS	8	rmii_crs_dv	J5 7	27

ciniml / 99-gowin-gwu2x.rules

Created April 16, 2022 18:38

GWU2X GOWIN USB Dongle udev rule

SUBSYSTEMS=="usb", ATTRS{idVendor}=="33aa", ATTRS{idProduct}=="0120", GROUP="plugdev", MODE="0660"

ciniml / Panel_M5HDMI_FS.h

Last active March 27, 2022 02:07

AtomDisplay Precompiled FPGA bistream for M5GFX

This file has been truncated, but you can view the full file.

	static constexpr const unsigned char fs_bitstream_rle[] = {
	0x16, 0xff, 0x00, 0x03, 0xa5, 0xc3, 0x06, 0x03, 0x00, 0x00, 0x05, 0x11, 0x00, 0x48, 0x1b, 0x10,
	0x07, 0x00, 0x00, 0x02, 0x51, 0x00, 0x06, 0xff, 0x01, 0x0b, 0x03, 0x00, 0x00, 0x02, 0xd2, 0x00,
	0x02, 0xff, 0x04, 0x00, 0x01, 0x12, 0x03, 0x00, 0x00, 0x05, 0x3b, 0x80, 0x04, 0xc8, 0xf0, 0x1a,
	0x00, 0x00, 0x05, 0xc0, 0x34, 0x10, 0x00, 0x80, 0x12, 0x00, 0x00, 0x02, 0x03, 0x01, 0x05, 0x00,
	0x00, 0x05, 0xc0, 0x34, 0x10, 0x00, 0x80, 0x02, 0x00, 0x00, 0x03, 0x14, 0x03, 0x01, 0x1c, 0x00,
	0x00, 0x04, 0x03, 0x41, 0x00, 0x08, 0x13, 0x00, 0x00, 0x04, 0x34, 0x10, 0x00, 0x80, 0x02, 0x00,
	0x00, 0x05, 0x0c, 0x03, 0x41, 0x00, 0x08, 0x13, 0x00, 0x00, 0x04, 0x34, 0x10, 0x00, 0x80, 0x03,
	0x00, 0x00, 0x04, 0x03, 0x41, 0x00, 0x08, 0x04, 0x00, 0x00, 0x04, 0x34, 0x10, 0x00, 0x80, 0x19,

ciniml / pin_table_gen.py

Last active January 16, 2022 05:56

pin_table_gen.py

ciniml / code.py

Created June 7, 2021 20:32

Measure voltage, current and power with Circuit Python on RPi Pico

ciniml / M5Paper.ino

Created November 28, 2020 22:06

M5Paper Storage Benchmark