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April 5, 2025 09:55
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Core Ultra 7 265K
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| Intel(R) Core(TM) Ultra 7 265K |
ServiceProcessoris bound to E-core
Processor [Intel(R) Core(TM) Ultra 7 265K]
|- Architecture [Arrow Lake]
|- Vendor ID [GenuineIntel]
|- Microcode [0x00000117]
|- Signature [ 06_C6]
|- Stepping [ 2]
|- Online CPU [ 20/ 20]
|- Base Clock [ 99.447]
|- Frequency (MHz) Ratio
Min 795.58 < 8 >
Max 3878.45 < 39 >
|- Factory [100.000]
3900 [ 39 ]
|- Performance
TGT 994.92 < 10 >
|- HWP
Min 795.58 < 8 >
Max 6366.45 < 64 >
TGT AUTO < 0 >
|- Turbo Boost [ UNLOCK]
1C 4574.58 < 46 >
2C 4574.58 < 46 >
3C 4574.58 < 46 >
4C 4574.58 < 46 >
5C 4574.58 < 46 >
6C 4574.58 < 46 >
7C 4574.58 < 46 >
8C 4574.58 < 46 >
|- Hybrid [ UNLOCK]
1C 4575.08 < 46 >
2C 4575.08 < 46 >
3C 4575.08 < 46 >
4C 4575.08 < 46 >
5C 4575.08 < 46 >
6C 4575.08 < 46 >
7C 4575.08 < 46 >
8C 4575.08 < 46 >
|- Uncore [ UNLOCK]
Min 795.67 < 8 >
Max 3779.42 < 38 >
|- TDP Level [ 0:3 ]
|- Programmable [ UNLOCK]
|- Configuration [ LOCK]
|- Turbo Activation [ UNLOCK]
Nominal 3878.45 [ 39 ]
Turbo AUTO < 0 >
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AMX-BF16 [N] AMX-TILE [N] AMX-INT8 [N] AMX-FP16 [N]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [Y] AVX-VNN-INT8 [Y] AVX-NE-CONV [Y]
|- AVX-IFMA [Y] CMPccXADD [Y] MOVDIRI [Y] MOVDIR64B [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- ENQCMD [N] GFNI [Y] OSPKE [Y] WAITPKG [Y]
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [Y] SYSCALL [Y] RDPID [Y] SGX [N]
|- VAES [Y] VPCLMULQDQ [Y] PREFETCH/W [Y] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast Short REP CMPSB|SCASB FSRC [Missing]
|- Fast Short REP MOVSB FSRM [Capable]
|- Fast Short REP STOSB FSRS [Capable]
|- Fast Zero-length REP MOVSB FZRM [Missing]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA [Capable]
|- Flexible Return and Event Delivery FRED [Missing]
|- Hardware Feedback Interface HFI [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hyper-Threading Technology HTT [Capable]
|- History Reset HRESET [Capable]
|- Hybrid part processor HYBRID [Capable]
|- Instruction Based Sampling IBS [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- Linear Address Space Separation LASS [Capable]
|- Linear Address Masking LAM [Capable]
|- Load Kernel GS segment register LKGS [Missing]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Platform Configuration PCONFIG [Missing]
|- Process Context Identifiers PCID [Capable]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Write Data to a Processor Trace Packet PTWRITE [Capable]
|- PREFETCHIT0/1 Instructions PREFETCHI [Missing]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Capable]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Thread Director TD [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Capable]
|- Extended xAPIC Support x2APIC [ x2APIC]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [ Enable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [ Enable]
|- Arch - Buffer Overwriting MD-CLEAR [Capable]
|- Arch - No Rogue Data Cache Load RDCL_NO [ Enable]
|- Arch - Enhanced IBRS IBRS_ALL [ Enable]
|- Arch - Return Stack Buffer Alternate RSBA [Capable]
|- Arch - No Speculative Store Bypass SSB_NO [Capable]
|- Arch - No Microarchitectural Data Sampling MDS_NO [ Enable]
|- Arch - No TSX Asynchronous Abort TAA_NO [ Enable]
|- Arch - No Page Size Change MCE PSCHANGE_MC_NO [ Enable]
|- Arch - STLB QoS STLB [ Enable]
|- Arch - Functional Safety Island FuSa [ Enable]
|- Arch - RSM in CPL0 only RSM [ Enable]
|- Arch - Split Locked Access Exception SPLA [ Enable]
|- Arch - Snoop Filter QoS Mask SNOOP_FILTER [ Enable]
|- Arch - No Fast Predictive Store Forwarding PSFD [Capable]
|- Arch - Data Operand Independent Timing Mode DOITM [Capable]
|- Arch - Not affected by SBDR or SSDP SBDR_SSDP_NO [ Enable]
|- Arch - No Fill Buffer Stale Data Propagator FBSDP_NO [ Enable]
|- Arch - No Primary Stale Data Propagator PSDP_NO [ Enable]
|- Arch - Overwrite Fill Buffer values FB_CLEAR [Capable]
|- Arch - Special Register Buffer Data Sampling SRBDS [ Unable]
|- RDRAND and RDSEED mitigation RNGDS [ Unable]
|- Restricted Transactional Memory RTM [ Unable]
|- Verify Segment for Writing instruction VERW [ Unable]
|- Arch - Restricted RSB Alternate RRSBA [ Enable]
|- Arch - No Branch Target Injection BHI_NO [ Enable]
|- Arch - Legacy xAPIC Disable XAPIC_DIS [ Enable]
|- Arch - No Post-Barrier Return Stack Buffer PBRSB_NO [ Enable]
|- Arch - No Gather Data Sampling GDS_NO [ Enable]
|- Arch - No Register File Data Sampling RFDS_NO [ Enable]
|- Arch - IPRED disabled for CPL3 IPRED_DIS_U [Capable]
|- Arch - IPRED disabled for CPL0/1/2 IPRED_DIS_S [Capable]
|- Arch - RRSBA disabled for CPL3 RRSBA_DIS_U [Capable]
|- Arch - RRSBA disabled for CPL0/1/2 RRSBA_DIS_S [Capable]
|- Arch - Data Dependent Prefetcher CPL3 DDPD_U_DIS [Capable]
|- Arch - BHI disabled for CPL0/1/2 BHI_DIS_S [Capable]
|- No MXCSR Configuration Dependent Timing MCDT_NO [Capable]
|- No MONITOR/UMONITOR mitigation UMON_MITG_NO [Capable]
|- Overclocking
|- Overclocking Utilized UTILIZED [ Enable]
|- Undervolt Protection UVP [ Enable]
|- Overclocking Secure Status UNLOCKED [Capable]
Security Features
|- CPUID Key Locker KL [Missing]
|- AES Key Locker instructions AESKLE [Missing]
|- CET Shadow Stack features CET-SS [Capable]
|- CET Indirect Branch Tracking CET-IBT [Capable]
|- CET Supervisor Shadow Stack CET-SSS [Capable]
|- AES Wide Key Locker instructions WIDE_KL [Missing]
|- Software Guard SGX1 Extensions SGX1 [Missing]
|- Software Guard SGX2 Extensions SGX2 [Missing]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- L1 IP Prefetcher L1 HW IP < ON>
|- L1 Next Page Prefetcher L1 NPP < ON>
|- L1 Scrubbing L1 Scrubbing <OFF>
|- Cache Prefetchers
|- L2 Prefetcher L2 HW < ON>
|- L2 Adjacent Cache Line Prefetcher L2 HW CL < ON>
|- L2 Adaptive Multipath Probability L2 AMP <OFF>
|- L2 Next Line Prefetcher L2 NLP <OFF>
|- LLC Streamer LLC < ON>
|- System Management Mode SMM-Dual [ ON]
|- Hyper-Threading HTT [OFF]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost Max 3.0 TURBO < ON>
|- Energy Efficiency Optimization EEO <OFF>
|- Race To Halt Optimization R2H <OFF>
|- Watchdog Timer TCO <OFF>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [ ON]
|- Version [ 8.6]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
|- Volume Management Device VMD [ ON]
|- Gaussian & Neural Accelerator GNA [ ON]
|- Digital Content Protection HDCP [ ON]
|- Image Processing Unit IPU [OFF]
|- Vision Processing Unit VPU [ ON]
|- Overclocking OC [ ON]
Performance Monitoring
|- Version PM [ 6]
|- Counters: General Fixed
| { 8, 0, 0 } x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E < ON>
|- C1 Auto Demotion C1A < ON>
|- C3 Auto Demotion C3A <OFF>
|- C1 UnDemotion C1U < ON>
|- C3 UnDemotion C3U <OFF>
|- C6 Core Demotion CC6 <OFF>
|- C6 Module Demotion MC6 <OFF>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-States
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT < C0>
|- I/O MWAIT Redirection IOMWAIT <Disable>
|- Max C-State Inclusion RANGE < C8>
|- Core C-States
|- C-States Base Address BAR [ 0x1814]
|- ACPI Processor C-States _CST [ 3]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 0 2 0 1 0 1
|- Monitor-Mwait Extensions EMX [Capable]
|- Interrupt Break-Event IBE [Capable]
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
|- Top-down slots Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 1]
|- Performance Present Capabilities _PPC [ 0]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax < 0:105 C>
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Energy Policy HWP EPP < 64>
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 125 W]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package < Enable>
|- Power Limit PL1 < 125 W>
|- Time Window TW1 < 56 s>
|- Power Limit PL2 < 159 W>
|- Time Window TW2 < 2 ms>
|- Thermal Design Power Core <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Uncore <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power DRAM <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Platform <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 28 s>
|- Power Limit PL2 < 0 W>
|- Time Window TW2 < 976 us>
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Package Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000061035]
|- Window second [ 0.000976562]
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID Hybrid ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 P 3 0 0 65536 16 49152 12 3145728 12 31457280 10
001: 0 8 P 3 4 0 65536 16 49152 12 3145728 12 31457280 10
002: 0 32 P 3 16 0 65536 16 49152 12 3145728 12 31457280 10
003: 0 40 P 3 20 0 65536 16 49152 12 3145728 12 31457280 10
004: 0 48 P 3 24 0 65536 16 49152 12 3145728 12 31457280 10
005: 0 56 P 3 28 0 65536 16 49152 12 3145728 12 31457280 10
006: 0 80 P 3 40 0 65536 16 49152 12 3145728 12 31457280 10
007: 0 88 P 3 44 0 65536 16 49152 12 3145728 12 31457280 10
008: 0 24 E 3 12 0 65536 8 32768 8 4194304 16 31457280 10
009: 0 26 E 3 13 0 65536 8 32768 8 4194304 16 31457280 10
010: 0 28 E 3 14 0 65536 8 32768 8 4194304 16 31457280 10
011: 0 30 E 3 15 0 65536 8 32768 8 4194304 16 31457280 10
012: 0 64 E 3 32 0 65536 8 32768 8 4194304 16 31457280 10
013: 0 66 E 3 33 0 65536 8 32768 8 4194304 16 31457280 10
014: 0 68 E 3 34 0 65536 8 32768 8 4194304 16 31457280 10
015: 0 70 E 3 35 0 65536 8 32768 8 4194304 16 31457280 10
016: 0 72 E 3 36 0 65536 8 32768 8 4194304 16 31457280 10
017: 0 74 E 3 37 0 65536 8 32768 8 4194304 16 31457280 10
018: 0 76 E 3 38 0 65536 8 32768 8 4194304 16 31457280 10
019: 0 78 E 3 39 0 65536 8 32768 8 4194304 16 31457280 10
CPU Freq(MHz) VID Vcore TMP(C) Accumulator Energy(J) Power(W)
000 2.95 5986 0.7307 36 000000000000000000 0.000000000 0.000000000
001 0.73 6211 0.7582 38 000000000000000000 0.000000000 0.000000000
002 16.96 6293 0.7682 36 000000000000000000 0.000000000 0.000000000
003 14.94 6150 0.7507 36 000000000000000000 0.000000000 0.000000000
004 1.05 6170 0.7532 38 000000000000000000 0.000000000 0.000000000
005 0.93 6170 0.7532 36 000000000000000000 0.000000000 0.000000000
006 2.64 6191 0.7557 38 000000000000000000 0.000000000 0.000000000
007 1.01 6088 0.7432 36 000000000000000000 0.000000000 0.000000000
008 0.85 5304 0.6475 36 000000000000000000 0.000000000 0.000000000
009 1.82 5304 0.6475 36 000000000000000000 0.000000000 0.000000000
010 11.61 5304 0.6475 36 000000000000000000 0.000000000 0.000000000
011 7.94 5304 0.6475 36 000000000000000000 0.000000000 0.000000000
012 1.04 5243 0.6400 36 000000000000000000 0.000000000 0.000000000
013 1.05 5243 0.6400 36 000000000000000000 0.000000000 0.000000000
014 0.81 5243 0.6400 36 000000000000000000 0.000000000 0.000000000
015 2.47 5243 0.6400 36 000000000000000000 0.000000000 0.000000000
016 2.63 5243 0.6400 36 000000000000000000 0.000000000 0.000000000
017 4.81 5243 0.6400 36 000000000000000000 0.000000000 0.000000000
018 4.20 5243 0.6400 36 000000000000000000 0.000000000 0.000000000
019 4.81 5243 0.6400 36 000000000000000000 0.000000000 0.000000000
Package[0] Cores Uncore Memory Platform
Energy(J): 10.727478027 2.002746582 0.021301270 0.000000000 0.000000000
Power(W) : 10.727478027 2.002746582 0.021301270 0.000000000 0.000000000
CPU Freq(MHz) Accumulator Min Energy(J) Max Min Power(W) Max
000 3.87 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
001 2.18 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
002 27.79 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
003 5.67 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
004 0.88 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
005 1.01 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
006 1.72 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
007 1.97 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
008 0.91 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
009 0.44 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
010 5.85 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
011 2.63 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
012 0.67 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
013 5.58 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
014 0.82 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
015 2.11 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
016 1.22 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
017 2.51 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
018 2.69 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
019 4.80 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
Energy(J) Package[0] Cores Uncore Memory
10.67 10.8 13.82 1.90 2.0 4.84 0.02 0.0 0.38 0.00 0.0 0.00
Power(W)
10.67 10.8 13.82 1.90 2.0 4.84 0.02 0.0 0.38 0.00 0.0 0.00
CPU Freq(MHz) Ratio Turbo C0(%) C1(%) C3(%) C6(%) C7(%) Min TMP:TS Max
000 3.52 ( 0.04) 0.09 0.51 0.05 0.00 0.11 99.19 36 / 38:67 / 38
001 2.25 ( 0.02) 0.06 0.19 0.12 0.00 0.39 99.26 36 / 38:67 / 38
002 18.21 ( 0.18) 0.47 1.64 0.53 0.00 4.75 92.93 36 / 36:69 / 38
003 16.13 ( 0.16) 0.42 1.63 0.25 0.00 0.82 97.19 36 / 36:69 / 36
004 1.65 ( 0.02) 0.04 0.13 0.09 0.00 0.40 99.35 38 / 38:67 / 38
005 0.60 ( 0.01) 0.02 0.04 0.06 0.00 0.11 99.79 36 / 36:69 / 38
006 2.08 ( 0.02) 0.05 0.16 0.14 0.00 0.23 99.44 38 / 38:67 / 38
007 1.64 ( 0.02) 0.04 0.10 0.11 0.00 0.28 99.48 36 / 38:67 / 38
008 1.82 ( 0.02) 0.05 0.23 0.12 0.00 99.59 0.00 36 / 36:69 / 36
009 0.82 ( 0.01) 0.02 0.10 0.06 0.00 99.80 0.00 36 / 36:69 / 36
010 10.52 ( 0.11) 0.27 1.17 20.50 0.00 78.18 0.00 36 / 36:69 / 36
011 5.81 ( 0.06) 0.15 0.64 22.96 0.00 76.17 0.00 36 / 36:69 / 36
012 4.05 ( 0.04) 0.10 0.50 1.62 0.00 97.67 0.00 36 / 36:69 / 36
013 4.75 ( 0.05) 0.12 0.48 14.35 0.00 84.98 0.00 36 / 36:69 / 36
014 1.68 ( 0.02) 0.04 0.21 0.11 0.00 99.62 0.00 36 / 36:69 / 36
015 2.61 ( 0.03) 0.07 0.29 0.10 0.00 99.54 0.00 36 / 36:69 / 36
016 0.71 ( 0.01) 0.02 0.09 0.13 0.00 99.74 0.00 34 / 34:71 / 36
017 2.67 ( 0.03) 0.07 0.33 0.08 0.00 99.48 0.00 34 / 34:71 / 36
018 6.46 ( 0.06) 0.17 0.76 7.24 0.00 91.68 0.00 34 / 34:71 / 36
019 3.76 ( 0.04) 0.10 0.40 55.39 0.00 44.09 0.00 36 / 36:69 / 38
Averages: Turbo C0(%) C1(%) C3(%) C6(%) C7(%) TjMax: Pkg:
0.12 0.48 6.20 0.00 53.88 39.33 105 C 38 C
Cycles State(%)
PC02 0 0.00
PC03 0 0.00
PC04 0 0.00
PC06 0 0.00
PC07 0 0.00
PC08 0 0.00
PC09 0 0.00
PC10 0 0.00
MC6 3835734974 79.29
PTSC 3877907976
UNCORE 0
CPU IPS IPC CPI
000 0.005109/s 0.500153/c 1.999387/i
001 0.000142/s 0.116870/c 8.556501/i
002 0.003870/s 0.312866/c 3.196252/i
003 0.001447/s 0.165716/c 6.034405/i
004 0.000201/s 0.128268/c 7.796176/i
005 0.000794/s 0.226688/c 4.411357/i
006 0.000111/s 0.112312/c 8.903757/i
007 0.000108/s 0.096854/c 10.324845/i
008 0.000757/s 0.361229/c 2.768326/i
009 0.004403/s 0.473347/c 2.112614/i
010 0.000626/s 0.097308/c 10.276629/i
011 0.004249/s 0.864358/c 1.156929/i
012 0.003535/s 0.622937/c 1.605298/i
013 0.000185/s 0.120250/c 8.316039/i
014 0.000824/s 0.286546/c 3.489846/i
015 0.002230/s 0.448917/c 2.227583/i
016 0.003495/s 0.681067/c 1.468285/i
017 0.003482/s 0.401862/c 2.488418/i
018 0.000432/s 0.082453/c 12.128154/i
019 0.003520/s 0.598363/c 1.671225/i
ServiceProcessoris bound to P-core
Processor [Intel(R) Core(TM) Ultra 7 265K]
|- Architecture [Arrow Lake]
|- Vendor ID [GenuineIntel]
|- Microcode [0x00000117]
|- Signature [ 06_C6]
|- Stepping [ 2]
|- Online CPU [ 20/ 20]
|- Base Clock [ 99.445]
|- Frequency (MHz) Ratio
Min 795.56 < 8 >
Max 3878.37 < 39 >
|- Factory [100.000]
3900 [ 39 ]
|- Performance
TGT 994.45 < 10 >
|- HWP
Min 795.59 < 8 >
Max 6364.49 < 64 >
TGT AUTO < 0 >
|- Turbo Boost [ UNLOCK]
1C 5469.49 < 55 >
2C 5469.49 < 55 >
3C 5171.16 < 52 >
4C 5171.16 < 52 >
5C 5171.16 < 52 >
6C 5171.16 < 52 >
7C 5171.16 < 52 >
8C 5171.16 < 52 >
|- Hybrid [ UNLOCK]
1C 4574.79 < 46 >
2C 4574.79 < 46 >
3C 4574.79 < 46 >
4C 4574.79 < 46 >
5C 4574.79 < 46 >
6C 4574.79 < 46 >
7C 4574.79 < 46 >
8C 4574.79 < 46 >
|- Uncore [ UNLOCK]
Min 795.61 < 8 >
Max 3779.17 < 38 >
|- TDP Level [ 0:3 ]
|- Programmable [ UNLOCK]
|- Configuration [ LOCK]
|- Turbo Activation [ UNLOCK]
Nominal 3878.37 [ 39 ]
Turbo AUTO < 0 >
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AMX-BF16 [N] AMX-TILE [N] AMX-INT8 [N] AMX-FP16 [N]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [Y] AVX-VNN-INT8 [Y] AVX-NE-CONV [Y]
|- AVX-IFMA [Y] CMPccXADD [Y] MOVDIRI [Y] MOVDIR64B [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- ENQCMD [N] GFNI [Y] OSPKE [Y] WAITPKG [Y]
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [Y] SYSCALL [Y] RDPID [Y] SGX [N]
|- VAES [Y] VPCLMULQDQ [Y] PREFETCH/W [Y] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast Short REP CMPSB|SCASB FSRC [Missing]
|- Fast Short REP MOVSB FSRM [Capable]
|- Fast Short REP STOSB FSRS [Capable]
|- Fast Zero-length REP MOVSB FZRM [Missing]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA [Capable]
|- Flexible Return and Event Delivery FRED [Missing]
|- Hardware Feedback Interface HFI [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hyper-Threading Technology HTT [Capable]
|- History Reset HRESET [Capable]
|- Hybrid part processor HYBRID [Capable]
|- Instruction Based Sampling IBS [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- Linear Address Space Separation LASS [Capable]
|- Linear Address Masking LAM [Capable]
|- Load Kernel GS segment register LKGS [Missing]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Platform Configuration PCONFIG [Missing]
|- Process Context Identifiers PCID [Capable]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Write Data to a Processor Trace Packet PTWRITE [Capable]
|- PREFETCHIT0/1 Instructions PREFETCHI [Missing]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Capable]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Thread Director TD [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Capable]
|- Extended xAPIC Support x2APIC [ x2APIC]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [ Enable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [ Enable]
|- Arch - Buffer Overwriting MD-CLEAR [Capable]
|- Arch - No Rogue Data Cache Load RDCL_NO [ Enable]
|- Arch - Enhanced IBRS IBRS_ALL [ Enable]
|- Arch - Return Stack Buffer Alternate RSBA [Capable]
|- Arch - No Speculative Store Bypass SSB_NO [Capable]
|- Arch - No Microarchitectural Data Sampling MDS_NO [ Enable]
|- Arch - No TSX Asynchronous Abort TAA_NO [ Enable]
|- Arch - No Page Size Change MCE PSCHANGE_MC_NO [ Enable]
|- Arch - STLB QoS STLB [ Enable]
|- Arch - Functional Safety Island FuSa [ Enable]
|- Arch - RSM in CPL0 only RSM [ Enable]
|- Arch - Split Locked Access Exception SPLA [ Enable]
|- Arch - Snoop Filter QoS Mask SNOOP_FILTER [ Enable]
|- Arch - No Fast Predictive Store Forwarding PSFD [Capable]
|- Arch - Data Operand Independent Timing Mode DOITM [Capable]
|- Arch - Not affected by SBDR or SSDP SBDR_SSDP_NO [ Enable]
|- Arch - No Fill Buffer Stale Data Propagator FBSDP_NO [ Enable]
|- Arch - No Primary Stale Data Propagator PSDP_NO [ Enable]
|- Arch - Overwrite Fill Buffer values FB_CLEAR [Capable]
|- Arch - Special Register Buffer Data Sampling SRBDS [ Unable]
|- RDRAND and RDSEED mitigation RNGDS [ Unable]
|- Restricted Transactional Memory RTM [ Unable]
|- Verify Segment for Writing instruction VERW [ Unable]
|- Arch - Restricted RSB Alternate RRSBA [ Enable]
|- Arch - No Branch Target Injection BHI_NO [ Enable]
|- Arch - Legacy xAPIC Disable XAPIC_DIS [ Enable]
|- Arch - No Post-Barrier Return Stack Buffer PBRSB_NO [ Enable]
|- Arch - No Gather Data Sampling GDS_NO [ Enable]
|- Arch - No Register File Data Sampling RFDS_NO [ Enable]
|- Arch - IPRED disabled for CPL3 IPRED_DIS_U [Capable]
|- Arch - IPRED disabled for CPL0/1/2 IPRED_DIS_S [Capable]
|- Arch - RRSBA disabled for CPL3 RRSBA_DIS_U [Capable]
|- Arch - RRSBA disabled for CPL0/1/2 RRSBA_DIS_S [Capable]
|- Arch - Data Dependent Prefetcher CPL3 DDPD_U_DIS [Capable]
|- Arch - BHI disabled for CPL0/1/2 BHI_DIS_S [Capable]
|- No MXCSR Configuration Dependent Timing MCDT_NO [Capable]
|- No MONITOR/UMONITOR mitigation UMON_MITG_NO [Capable]
|- Overclocking
|- Overclocking Utilized UTILIZED [ Enable]
|- Undervolt Protection UVP [ Enable]
|- Overclocking Secure Status UNLOCKED [Capable]
Security Features
|- CPUID Key Locker KL [Missing]
|- AES Key Locker instructions AESKLE [Missing]
|- CET Shadow Stack features CET-SS [Capable]
|- CET Indirect Branch Tracking CET-IBT [Capable]
|- CET Supervisor Shadow Stack CET-SSS [Capable]
|- AES Wide Key Locker instructions WIDE_KL [Missing]
|- Software Guard SGX1 Extensions SGX1 [Missing]
|- Software Guard SGX2 Extensions SGX2 [Missing]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- L1 IP Prefetcher L1 HW IP < ON>
|- L1 Next Page Prefetcher L1 NPP < ON>
|- L1 Scrubbing L1 Scrubbing <OFF>
|- Cache Prefetchers
|- L2 Prefetcher L2 HW < ON>
|- L2 Adjacent Cache Line Prefetcher L2 HW CL < ON>
|- L2 Adaptive Multipath Probability L2 AMP <OFF>
|- L2 Next Line Prefetcher L2 NLP <OFF>
|- LLC Streamer LLC < ON>
|- System Management Mode SMM-Dual [ ON]
|- Hyper-Threading HTT [OFF]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost Max 3.0 TURBO < ON>
|- Energy Efficiency Optimization EEO <OFF>
|- Race To Halt Optimization R2H <OFF>
|- Watchdog Timer TCO <OFF>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [ ON]
|- Version [ 8.6]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
|- Volume Management Device VMD [ ON]
|- Gaussian & Neural Accelerator GNA [ ON]
|- Digital Content Protection HDCP [ ON]
|- Image Processing Unit IPU [OFF]
|- Vision Processing Unit VPU [ ON]
|- Overclocking OC [ ON]
Performance Monitoring
|- Version PM [ 6]
|- Counters: General Fixed
| { 8, 0, 0 } x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E < ON>
|- C1 Auto Demotion C1A < ON>
|- C3 Auto Demotion C3A <OFF>
|- C1 UnDemotion C1U < ON>
|- C3 UnDemotion C3U <OFF>
|- C6 Core Demotion CC6 <OFF>
|- C6 Module Demotion MC6 <OFF>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-States
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT < C0>
|- I/O MWAIT Redirection IOMWAIT <Disable>
|- Max C-State Inclusion RANGE < C8>
|- Core C-States
|- C-States Base Address BAR [ 0x1814]
|- ACPI Processor C-States _CST [ 3]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 0 2 0 1 0 1
|- Monitor-Mwait Extensions EMX [Capable]
|- Interrupt Break-Event IBE [Capable]
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
|- Top-down slots Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 1]
|- Performance Present Capabilities _PPC [ 0]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax < 0:105 C>
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Energy Policy HWP EPP < 64>
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 125 W]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package < Enable>
|- Power Limit PL1 < 125 W>
|- Time Window TW1 < 56 s>
|- Power Limit PL2 < 159 W>
|- Time Window TW2 < 2 ms>
|- Thermal Design Power Core <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Uncore <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power DRAM <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Platform <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 28 s>
|- Power Limit PL2 < 0 W>
|- Time Window TW2 < 976 us>
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Package Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000061035]
|- Window second [ 0.000976562]
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID Hybrid ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 P 3 0 0 65536 16 49152 12 3145728 12 31457280 10
001: 0 8 P 3 4 0 65536 16 49152 12 3145728 12 31457280 10
002: 0 32 P 3 16 0 65536 16 49152 12 3145728 12 31457280 10
003: 0 40 P 3 20 0 65536 16 49152 12 3145728 12 31457280 10
004: 0 48 P 3 24 0 65536 16 49152 12 3145728 12 31457280 10
005: 0 56 P 3 28 0 65536 16 49152 12 3145728 12 31457280 10
006: 0 80 P 3 40 0 65536 16 49152 12 3145728 12 31457280 10
007: 0 88 P 3 44 0 65536 16 49152 12 3145728 12 31457280 10
008: 0 24 E 3 12 0 65536 8 32768 8 4194304 16 31457280 10
009: 0 26 E 3 13 0 65536 8 32768 8 4194304 16 31457280 10
010: 0 28 E 3 14 0 65536 8 32768 8 4194304 16 31457280 10
011: 0 30 E 3 15 0 65536 8 32768 8 4194304 16 31457280 10
012: 0 64 E 3 32 0 65536 8 32768 8 4194304 16 31457280 10
013: 0 66 E 3 33 0 65536 8 32768 8 4194304 16 31457280 10
014: 0 68 E 3 34 0 65536 8 32768 8 4194304 16 31457280 10
015: 0 70 E 3 35 0 65536 8 32768 8 4194304 16 31457280 10
016: 0 72 E 3 36 0 65536 8 32768 8 4194304 16 31457280 10
017: 0 74 E 3 37 0 65536 8 32768 8 4194304 16 31457280 10
018: 0 76 E 3 38 0 65536 8 32768 8 4194304 16 31457280 10
019: 0 78 E 3 39 0 65536 8 32768 8 4194304 16 31457280 10
CPU Freq(MHz) VID Vcore TMP(C) Accumulator Energy(J) Power(W)
000 4.61 5965 0.7281 36 000000000000000000 0.000000000 0.000000000
001 8.80 6211 0.7582 36 000000000000000000 0.000000000 0.000000000
002 17.85 6273 0.7657 36 000000000000000000 0.000000000 0.000000000
003 3.05 6150 0.7507 36 000000000000000000 0.000000000 0.000000000
004 16.41 6150 0.7507 36 000000000000000000 0.000000000 0.000000000
005 3.41 6170 0.7532 34 000000000000000000 0.000000000 0.000000000
006 2.60 6191 0.7557 36 000000000000000000 0.000000000 0.000000000
007 3.31 6109 0.7457 34 000000000000000000 0.000000000 0.000000000
008 1.68 5304 0.6475 34 000000000000000000 0.000000000 0.000000000
009 5.12 5304 0.6475 34 000000000000000000 0.000000000 0.000000000
010 0.83 5304 0.6475 34 000000000000000000 0.000000000 0.000000000
011 1.66 5304 0.6475 34 000000000000000000 0.000000000 0.000000000
012 2.65 5263 0.6425 36 000000000000000000 0.000000000 0.000000000
013 2.57 5263 0.6425 36 000000000000000000 0.000000000 0.000000000
014 1.68 5263 0.6425 36 000000000000000000 0.000000000 0.000000000
015 1.09 5263 0.6425 36 000000000000000000 0.000000000 0.000000000
016 0.50 5263 0.6425 36 000000000000000000 0.000000000 0.000000000
017 1.52 5263 0.6425 36 000000000000000000 0.000000000 0.000000000
018 6.20 5263 0.6425 34 000000000000000000 0.000000000 0.000000000
019 7.33 5263 0.6425 34 000000000000000000 0.000000000 0.000000000
Package[0] Cores Uncore Memory Platform
Energy(J): 10.738769531 2.033264160 0.068298340 0.000000000 0.000000000
Power(W) : 10.738769531 2.033264160 0.068298340 0.000000000 0.000000000
CPU Freq(MHz) Accumulator Min Energy(J) Max Min Power(W) Max
000 40.58 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
001 18.98 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
002 41.83 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
003 8.71 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
004 3.22 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
005 13.36 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
006 6.07 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
007 8.74 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
008 0.80 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
009 5.44 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
010 0.53 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
011 1.50 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
012 2.69 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
013 0.65 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
014 0.51 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
015 10.72 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
016 0.52 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
017 1.31 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
018 10.25 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
019 12.49 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
Energy(J) Package[0] Cores Uncore Memory
10.59 10.7 41.28 1.93 2.1 31.82 0.01 0.1 0.44 0.00 0.0 0.00
Power(W)
10.59 10.7 41.28 1.93 2.1 31.82 0.01 0.1 0.44 0.00 0.0 0.00
CPU Freq(MHz) Ratio Turbo C0(%) C1(%) C3(%) C6(%) C7(%) Min TMP:TS Max
000 31.34 ( 0.32) 0.81 2.92 0.21 0.00 2.35 94.24 36 / 36:69 / 38
001 20.32 ( 0.20) 0.52 1.56 0.51 0.00 14.39 83.25 36 / 36:69 / 38
002 32.19 ( 0.32) 0.83 2.57 0.31 0.00 2.71 94.19 34 / 36:69 / 58
003 5.30 ( 0.05) 0.14 0.52 0.08 0.00 0.39 98.92 36 / 36:69 / 38
004 1.88 ( 0.02) 0.05 0.11 0.02 0.00 0.17 99.66 36 / 36:69 / 40
005 8.42 ( 0.08) 0.22 0.99 0.06 0.00 0.76 98.07 34 / 36:69 / 38
006 4.73 ( 0.05) 0.12 0.54 0.19 0.00 0.27 98.93 36 / 36:69 / 38
007 5.48 ( 0.06) 0.14 0.62 0.08 0.00 0.98 98.22 34 / 36:69 / 50
008 1.21 ( 0.01) 0.03 0.15 0.00 0.00 99.80 0.00 34 / 34:71 / 38
009 1.94 ( 0.02) 0.05 0.24 0.00 0.00 99.65 0.00 34 / 34:71 / 38
010 0.60 ( 0.01) 0.02 0.08 0.00 0.00 99.89 0.00 34 / 34:71 / 38
011 1.75 ( 0.02) 0.05 0.21 8.72 0.00 91.00 0.00 34 / 34:71 / 38
012 0.88 ( 0.01) 0.02 0.11 0.00 0.00 99.86 0.00 34 / 34:71 / 38
013 0.69 ( 0.01) 0.02 0.09 0.00 0.00 99.88 0.00 34 / 34:71 / 38
014 0.81 ( 0.01) 0.02 0.10 0.00 0.00 99.85 0.00 34 / 34:71 / 38
015 2.97 ( 0.03) 0.08 0.37 0.06 0.00 99.43 0.00 34 / 34:71 / 38
016 1.82 ( 0.02) 0.05 0.23 0.03 0.00 99.58 0.00 34 / 34:71 / 38
017 2.82 ( 0.03) 0.07 0.35 0.00 0.00 99.49 0.00 34 / 36:69 / 38
018 10.67 ( 0.11) 0.28 1.23 32.33 0.00 66.16 0.00 34 / 36:69 / 38
019 11.97 ( 0.12) 0.31 1.44 20.78 0.00 77.39 0.00 34 / 36:69 / 38
Averages: Turbo C0(%) C1(%) C3(%) C6(%) C7(%) TjMax: Pkg:
0.19 0.72 3.17 0.00 57.70 38.27 105 C 38 C
Cycles State(%)
PC02 0 0.00
PC03 0 0.00
PC04 0 0.00
PC06 0 0.00
PC07 0 0.00
PC08 0 0.00
PC09 0 0.00
PC10 0 0.00
MC6 0 0.00
PTSC 3880121412
UNCORE 0
CPU IPS IPC CPI
000 0.014114/s 0.451490/c 2.214889/i
001 0.002126/s 0.164557/c 6.076924/i
002 0.006710/s 0.230146/c 4.345077/i
003 0.000918/s 0.158317/c 6.316423/i
004 0.000108/s 0.110585/c 9.042815/i
005 0.000045/s 0.111190/c 8.993607/i
006 0.000804/s 0.170005/c 5.882170/i
007 0.000068/s 0.142026/c 7.040959/i
008 0.000053/s 0.067530/c 14.808296/i
009 0.000061/s 0.062035/c 16.120002/i
010 0.000061/s 0.075954/c 13.165882/i
011 0.000064/s 0.073445/c 13.615669/i
012 0.000639/s 0.233269/c 4.286901/i
013 0.000066/s 0.071527/c 13.980783/i
014 0.000049/s 0.068835/c 14.527515/i
015 0.000048/s 0.079965/c 12.505516/i
016 0.000045/s 0.071007/c 14.083032/i
017 0.000385/s 0.082771/c 12.081571/i
018 0.001100/s 0.107060/c 9.340532/i
019 0.001055/s 0.081716/c 12.237441/i
SOC OC 102 MHz
Intel ARL-S [AE0D]
Controller #0 Dual Channel
Bus Rate 3000 MHz Bus Speed 3060 MHz DDR5 Speed 6120 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 30 40 40 40 76 8 16 32 90 23 128 28 23 2T
#1 30 40 40 40 76 8 16 32 90 23 128 28 23 2T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 16 8 16 16 22 22 22 22 67 44 13 13
#1 16 8 17 17 22 22 22 22 67 44 13 13
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 61 8 17 17 5968 480 884 23 16 2 0
#1 61 8 17 17 5968 480 884 23 16 2 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 131072 1024 32768
Controller #1 Dual Channel
Bus Rate 3000 MHz Bus Speed 3060 MHz DDR5 Speed 6120 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 30 40 40 40 76 8 16 32 90 23 128 28 23 2T
#1 30 40 40 40 76 8 16 32 90 23 128 28 23 2T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 16 8 16 16 22 22 22 22 67 44 13 13
#1 16 8 16 16 22 22 22 22 67 44 13 13
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 61 8 17 17 5968 480 884 23 16 2 0
#1 61 8 17 17 5968 480 884 23 16 2 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 131072 1024 32768
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Thank you @valery-kirichenko for its great contribution