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Intel Core i7-6700 [Skylake/S]
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| CoreFreq version 1.50.2 |
System Information
Processor [Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz]
|- Architecture [Skylake/S]
|- Vendor ID [GenuineIntel]
|- Microcode [ 186]
|- Signature [ 06_5E]
|- Stepping [ 3]
|- Online CPU [ 8/8 ]
|- Base Clock [100.24]
|- Frequency (MHz) Ratio
Min 801.89 [ 8 ]
Max 3408.01 [ 34 ]
|- Factory [100.00]
3400 [ 34 ]
|- Performance
|- OSPM
TGT 4009.43 < 40 >
|- HWP
Min 100.24 < 1 >
Max 4009.43 < 40 >
TGT 4009.43 < 40 >
|- Turbo Boost [UNLOCK]
1C 4009.43 < 40 >
2C 3909.19 < 39 >
3C 3808.96 < 38 >
4C 3708.72 < 37 >
|- Uncore [UNLOCK]
Min 801.89 < 8 >
Max 4009.43 < 40 >
|- TDP Level [ 0:3 ]
|- Programmable [UNLOCK]
|- Configuration [ LOCK]
|- Turbo Activation [UNLOCK]
Nominal 3408.01 [ 34 ]
Instruction Set Extensions
|- 3DNow!/Ext [N,N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX-512 [N] BMI1/BMI2 [Y/Y] CLFSH [Y] CMOV [Y]
|- CMPXCH8 [Y] CMPXCH16 [Y] F16C [Y] FPU [Y]
|- FXSR [Y] LAHF/SAHF [Y] MMX/Ext [Y/N] MONITOR [Y]
|- MOVBE [Y] MPX [Y] PCLMULDQ [Y] POPCNT [Y]
|- RDRAND [Y] RDSEED [Y] RDTSCP [Y] SEP [Y]
|- SGX [Y] SSE [Y] SSE2 [Y] SSE3 [Y]
|- SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y] SYSCALL [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Present]
|- Advanced Configuration & Power Interface ACPI [Present]
|- Advanced Programmable Interrupt Controller APIC [Present]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Present]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Present]
|- CPL Qualified Debug Store DS-CPL [Present]
|- 64-Bit Debug Store DTES64 [Present]
|- Fast-String Operation Fast-Strings [Present]
|- Fused Multiply Add FMA|FMA4 [Present]
|- Hardware Lock Elision HLE [Present]
|- Long Mode 64 bits IA64|LM [Present]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Present]
|- Model Specific Registers MSR [Present]
|- Memory Type Range Registers MTRR [Present]
|- OS-Enabled Ext. State Management OSXSAVE [Present]
|- Physical Address Extension PAE [Present]
|- Page Attribute Table PAT [Present]
|- Pending Break Enable PBE [Present]
|- Process Context Identifiers PCID [Present]
|- Perfmon and Debug Capability PDCM [Present]
|- Page Global Enable PGE [Present]
|- Page Size Extension PSE [Present]
|- 36-bit Page Size Extension PSE36 [Present]
|- Processor Serial Number PSN [Missing]
|- Restricted Transactional Memory RTM [Present]
|- Safer Mode Extensions SMX [Present]
|- Self-Snoop SS [Present]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Present]
|- Virtual Mode Extension VME [Present]
|- Virtual Machine Extensions VMX [Present]
|- Extended xAPIC Support x2APIC [ xAPIC]
|- Execution Disable Bit Support XD-Bit [Present]
|- XSAVE/XSTOR States XSAVE [Present]
|- xTPR Update Control xTPR [Present]
Technologies
|- System Management Mode SMM-Dual [ ON]
|- Hyper-Threading HTT [ ON]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost TURBO < ON>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [ ON]
|- Hypervisor [OFF]
Performance Monitoring
|- Version PM [ 4]
|- Counters: General Fixed
| 4 x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E <OFF>
|- C1 Auto Demotion C1A < ON>
|- C3 Auto Demotion C3A < ON>
|- C1 UnDemotion C1U < ON>
|- C3 UnDemotion C3U < ON>
|- Frequency ID control FID [OFF]
|- Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware-Controlled Performance States HWP < ON>
|- Capabilities (MHz) Ratio
Lowest 100.24 [ 1 ]
Efficient 801.89 [ 8 ]
Guaranteed 3408.01 [ 34 ]
Highest 4009.43 [ 40 ]
|- Hardware Duty Cycling HDC [ ON]
|- Package C-State
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT [ 8]
|- I/O MWAIT Redirection IOMWAIT [Disable]
|- Max C-State Inclusion RANGE [ 8]
|- MWAIT States: C0 C1 C2 C3 C4 C5 C6 C7
| 0 2 1 2 4 1 0 0
|- Core Cycles [Present]
|- Instructions Retired [Present]
|- Reference Cycles [Present]
|- Last Level Cache References [Present]
|- Last Level Cache Misses [Present]
|- Branch Instructions Retired [Present]
|- Branch Mispredicts Retired [Present]
Power & Thermal
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint < 8>
|- Energy Policy HWP EPP < 128>
|- Junction Temperature TjMax [ 0:100]
|- Digital Thermal Sensor DTS [Present]
|- Power Limit Notification PLN [Present]
|- Package Thermal Management PTM [Present]
|- Thermal Monitor 1 TM1|TTP [ Enable]
|- Thermal Monitor 2 TM2|HTC [Present]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000061035]
|- Window second [ 0.000976562]
Topology
CPU Pkg Apic Core Thread Caches (w)rite-Back (i)nclusive
# ID ID ID ID L1-Inst Way L1-Data Way L2 Way L3 Way
00: BSP 0 0 0 32768 8 32768 8 262144 4 8388608 16 i
01: 0 2 1 0 32768 8 32768 8 262144 4 8388608 16 i
02: 0 4 2 0 32768 8 32768 8 262144 4 8388608 16 i
03: 0 6 3 0 32768 8 32768 8 262144 4 8388608 16 i
04: 0 1 0 1 32768 8 32768 8 262144 4 8388608 16 i
05: 0 3 1 1 32768 8 32768 8 262144 4 8388608 16 i
06: 0 5 2 1 32768 8 32768 8 262144 4 8388608 16 i
07: 0 7 3 1 32768 8 32768 8 262144 4 8388608 16 i
Memory Controller
Sunrise Point [191F]
Controller #0 Dual Channel
Bus Rate 8000 MT/s Bus Speed 8019 MT/s DRAM Speed 2133 MHz
Cha CL RCD RP RAS RRD RFC WR RTPr WTPr FAW B2B CWL Rate
#0 15 15 15 35 0 374 0 8 34 0 0 13 2N
#1 15 15 15 35 0 374 0 8 34 0 0 13 2N
ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW ECC
#0 0 0 0 0 0 0 0 0 0 0 0 0 0
#1 0 0 0 0 0 0 0 0 0 0 0 0 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 65536 1024 16384
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 65536 1024 16384
Power and Voltage
Idle
Turbo Single Core
Turbo All Cores
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Hardware-Controlled Performance States (HWP)