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April 27, 2025 09:37
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Ryzen 7 PRO 8840HS
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| AMD Ryzen 7 PRO 8840HS w/ Radeon 780M Graph |
Author
cyring
commented
Apr 27, 2025
Processor [AMD Ryzen 7 PRO 8840HS w/ Radeon 780M Graphics]
|- Architecture [Zen4/Hawk Point]
|- Vendor ID [AuthenticAMD]
|- Microcode [0x0a705206]
|- Signature [ AF_75]
|- Stepping [ 2]
|- Online CPU [ 16/ 16]
|- Base Clock [ 99.817]
|- Frequency (MHz) Ratio
Min 1597.07 < 16 >
Max 3293.96 < 33 >
|- Factory [100.000]
3300 [ 33 ]
|- Performance
TGT 3293.96 < 33 >
|- Boost [ LOCK]
XFR 5090.67 [ 51 ]
CPB 5090.67 [ 51 ]
|- P-State
P1 2195.98 < 22 >
P2 1597.07 < 16 >
|- Uncore [ LOCK]
CLK 1397.44 [ 14 ]
MEM 2794.88 [ 28 ]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX512-F [Y] AVX512-DQ [Y] AVX512-IFMA [Y] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [Y] AVX512-BW [Y] AVX512-VL [Y]
|- AVX512-VBMI [Y] AVX512-VBMI2 [Y] AVX512-VNNI [Y] AVX512-ALG [Y]
|- AVX512-VPOP [Y] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [Y] AVX-VNNI-VEX [N] AVX-FP128 [N] AVX-FP256 [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [Y] UMIP [Y]
|- VAES [Y] VPCLMULQDQ [Y] PREFETCH/W [Y] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- Advanced Virtual Interrupt Controller AVIC [Missing]
|- APIC Timer Invariance ARAT [Capable]
|- LOCK prefix to read CR8 AltMov [Capable]
|- Clear Zero Instruction CLZERO [Capable]
|- Core Multi-Processing CMP Legacy [Capable]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Collaborative Processor Performance Control CPPC [Capable]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast Short REP CMPSB|SCASB FSRC [Capable]
|- Fast Short REP MOVSB FSRM [Capable]
|- Fast Short REP STOSB FSRS [Capable]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA4 [Missing]
|- Fused Multiply Add FMA [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hyper-Threading Technology HTT [Capable]
|- Hardware P-state control HwP [Capable]
|- Instruction Based Sampling IBS [Capable]
|- Instruction INVLPGB INVLPGB [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Memory Bandwidth Enforcement MBE [Capable]
|- Machine-Check Architecture MCA [Capable]
|- Instruction MCOMMIT MCOMMIT [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- OS Visible Work-around OSVW [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- PREFETCHIT0/1 Instructions PREFETCHI [Missing]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Capable]
|- Read Processor Register at User level RDPRU [Capable]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Trailing Bit Manipulation TBM [Missing]
|- Translation Cache Extension TCE [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Missing]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Capable]
|- Extended xAPIC Support x2APIC [ xAPIC]
|- AVIC controller for x2APIC x2AVIC [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Missing]
|- Extended Operation Support XOP [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Capable]
|- IBRS Always-On preferred by processor [ Unable]
|- IBRS preferred over software solution [Capable]
|- IBRS provides same speculation limits [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Selective Branch Predictor Barrier SBPB [ Unable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- SSBD use VIRT_SPEC_CTRL register [ Unable]
|- SSBD not needed on this processor [ Unable]
|- No Speculative Return Stack Overflow SRSO_NO [ Unable]
|- No SRSO at the User-Kernel boundary [ Unable]
|- No Branch Type Confusion BTC_NO [ Unable]
|- BTC on Non-Branch instruction BTC-NOBR [ Unable]
|- Limited Early Redirect Window AGENPICK [ Unable]
|- Arch - No Fast Predictive Store Forwarding PSFD [Capable]
|- Arch - Enhanced Predictive Store Forwarding EPSF [Capable]
|- Arch - Cross Processor Information Leak XPROC_LEAK [ Unable]
Security Features
|- CET Shadow Stack features CET-SS [Capable]
|- Secure Init and Jump with Attestation SKINIT [Capable]
|- Secure Encrypted Virtualization SEV [Missing]
|- SEV - Encrypted State SEV-ES [Missing]
|- SEV - Secure Nested Paging SEV-SNP [Missing]
|- Guest Mode Execute Trap GMET [Capable]
|- Supervisor Shadow Stack SSS [Capable]
|- VM Permission Levels VMPL [Missing]
|- VMPL Supervisor Shadow Stack VMPL-SSS [Missing]
|- Secure Memory Encryption SME [Capable]
|- Transparent SME TSME [ Enable]
|- Secure Multi-Key Memory Encryption SME-MK [Missing]
|- DRAM Data Scrambling Scrambler [ Enable]
Technologies
|- Instruction Cache Unit
|- L1 IP Prefetcher L1 HW IP < ON>
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- Cache Prefetchers
|- L2 Prefetcher L2 HW < ON>
|- L1 Stride Prefetcher L1 Stride < ON>
|- L1 Region Prefetcher L1 Region < ON>
|- L1 Burst Prefetch Mode L1 Burst < ON>
|- L2 Stream HW Prefetcher L2 Stream < ON>
|- L2 Up/Down Prefetcher L2 Up/Down < ON>
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [ ON]
|- Core C-States CCx [ ON]
|- Core Performance Boost CPB < ON>
|- Watchdog Timer WDT < ON>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [ ON]
|- Version [ 0.1]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 2]
|- Counters: General Fixed
| { 6, 6, 4 } x 48 bits 3 x 64 bits
|- Enhanced Halt State C1E <OFF>
|- C2 UnDemotion C2U < ON>
|- C3 UnDemotion C3U < ON>
|- Core C6 State CC6 < ON>
|- Package C6 State PC6 < ON>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Core C-States
|- C-States Base Address BAR [ 0x413 ]
|- ACPI Processor C-States _CST [ 3]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 1 1 0 0 0 0 0 0
|- Monitor-Mwait Extensions EMX [Capable]
|- Interrupt Break-Event IBE [Capable]
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Global Time Stamp Counter [Missing]
|- Data Fabric Performance Counter [Capable]
|- Core Performance Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 3]
|- Performance Present Capabilities _PPC [ 0]
|- Continuous Performance Control _CPC [Missing]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax [ 49:100 C]
|- CPPC Energy Preference EPP [Capable]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TTP [ Enable]
|- Thermal Monitor 2 HTC [ Enable]
|- Thermal Design Power TDP [Missing]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 0 ns]
|- Thermal Design Power Core [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Uncore [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power DRAM [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Platform [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 0 ns]
|- Package Power Tracking PPT [Missing]
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- Package Thermal Point
|- Thermal Monitor Trip Limit [ 125 C]
|- HTC Temperature Limit Limit [ 127 C]
|- HTC Temperature Hysteresis Threshold [ 2 C]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000015259]
|- Window second [ 0.000976562]
Linux:
|- Release [6.14.2-arch1-1]
|- Version [#1 SMP PREEMPT_DYNAMIC Thu, 10 Apr 2025 18:43:59 +0000]
|- Machine [x86_64]
Memory:
|- Total RAM 28364796 KB
|- Shared RAM 1008928 KB
|- Free RAM 26540536 KB
|- Buffer RAM 668 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < corefreq_tsc>
CPU-Freq driver [ corefreqk-perf]
Governor [ corefreq-policy]
CPU-Idle driver [ corefreqk-idle]
|- Idle Limit < C6>
|- State POLL C1 C2 C3 C4 C5 C6
|- CPUIDLE ZEN-C1 ZEN-C2 ZEN-C3 ZEN-C4 ZEN-C5 ZEN-C6
|- Power -1 0 0 0 0 0 0
|- Latency 0 1 20 40 60 80 100
|- Residency 0 2 40 80 120 160 200
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID ID ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 32 8 32 8 1024 8 i 16384 16w
001: 0 1 0 1 32 8 32 8 1024 8 i 16384 16w
002: 0 2 1 0 32 8 32 8 1024 8 i 16384 16w
003: 0 3 1 1 32 8 32 8 1024 8 i 16384 16w
004: 0 4 2 0 32 8 32 8 1024 8 i 16384 16w
005: 0 5 2 1 32 8 32 8 1024 8 i 16384 16w
006: 0 6 3 0 32 8 32 8 1024 8 i 16384 16w
007: 0 7 3 1 32 8 32 8 1024 8 i 16384 16w
008: 0 8 4 0 32 8 32 8 1024 8 i 16384 16w
009: 0 9 4 1 32 8 32 8 1024 8 i 16384 16w
010: 0 10 5 0 32 8 32 8 1024 8 i 16384 16w
011: 0 11 5 1 32 8 32 8 1024 8 i 16384 16w
012: 0 12 6 0 32 8 32 8 1024 8 i 16384 16w
013: 0 13 6 1 32 8 32 8 1024 8 i 16384 16w
014: 0 14 7 0 32 8 32 8 1024 8 i 16384 16w
015: 0 15 7 1 32 8 32 8 1024 8 i 16384 16w
[ 0] LENOVO
[ 1] R2LET30W (1.11 )
[ 2] 11/11/2024
[ 3] LENOVO
[ 4] 21MECTO1WW
[ 5] ThinkPad P14s Gen 5 AMD
[ 6] P---6---
[ 7] LENOVO_MT_21ME_BU_Think_FM_ThinkPad P14s Gen 5 AMD
[ 8] ThinkPad P14s Gen 5 AMD
[ 9] LENOVO
[10] 21MECTO1WW
[11] SDK0K17763 WIN
[12] L---4---1--
[13] Number Of Devices:2\Maximum Capacity:67108864 kilobytes
[14]
[15] DIMM 0\P0 CHANNEL B
[16]
[17]
[18]
[19] Hynix
[20]
[21]
[22]
[23] HMCG88AGBSA092N
[24]
[25]
Zen UMC [14F0]
Controller #0 Dual Channel
Bus Rate 2800 MHz Bus Speed 2794 MHz DDR5 Speed 5588 MT/s
Cha CL RCDr RCDw RP RAS RC RRDs RRDl FAW WTRs WTRl WR clRR clWW
#0 46 45 45 45 90 135 8 14 32 7 28 84 7 21
#1 46 45 45 45 90 135 8 14 32 7 28 84 7 21
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 44 21 22 6 1 12 12 1 14 14 0 0 0 0
#1 44 21 21 6 1 12 12 1 14 14 0 0 0 0
REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt Ban Page CKE CMD GDM ECC
#0 10892 447 447 364 0 0 ON OFF R0W0 0 6 1T ON 0
#1 10892 447 447 364 0 0 ON OFF R0W0 0 6 1T ON 0
MRD:PDA MOD:PDA WRMPR STAG PDM RDDATA WRD WRL RDL XS XP CPDED
#0 40 0 40 0 24 7 0:F:0 34 6 0 56 852 21 14
#1 40 0 40 0 24 7 0:F:0 34 6 0 56 852 21 14
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768
#1
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768
#1
Voltage
Idle
All Cores
Single Core
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