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May 19, 2025 07:34
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Dual EPYC Genoa
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| AMD Eng Sample |
Author
cyring
commented
May 19, 2025
Processor [AMD Eng Sample: XXX-XXXXXXXXX-XX]
|- PPIN# [ 8X1XcX7XeX0X0X]
|- Architecture [EPYC/Genoa]
|- Vendor ID [AuthenticAMD]
|- Firmware [ 71.119.0-5]
|- Microcode [0x0a101020]
|- Signature [ AF_11]
|- Stepping [ 0]
|- Online CPU [128/128]
|- Base Clock [102.002]
|- Frequency (MHz) Ratio
Min 1530.03 < 15 >
Max 2550.04 < 25 >
|- Factory [100.000]
2500 [ 25 ]
|- Performance
TGT 1530.03 < 15 >
|- Boost [ LOCK]
XFR 3570.06 [ 35 ]
CPB 3570.06 [ 35 ]
|- P-State
P1 2040.04 < 20 >
P2 1530.03 < 15 >
|- Uncore [ LOCK]
CLK 2448.04 [ 24 ]
MEM 2448.04 [ 24 ]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX512-F [Y] AVX512-DQ [Y] AVX512-IFMA [Y] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [Y] AVX512-BW [Y] AVX512-VL [Y]
|- AVX512-VBMI [Y] AVX512-VBMI2 [Y] AVX512-VNNI [Y] AVX512-ALG [Y]
|- AVX512-VPOP [Y] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [Y] AVX-VNNI-VEX [N] AVX-FP128 [N] AVX-FP256 [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [Y] UMIP [Y]
|- VAES [Y] VPCLMULQDQ [Y] PREFETCH/W [Y] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- Advanced Virtual Interrupt Controller AVIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- LOCK prefix to read CR8 AltMov [Capable]
|- Clear Zero Instruction CLZERO [Capable]
|- Core Multi-Processing CMP Legacy [Capable]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Collaborative Processor Performance Control CPPC [Capable]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast Short REP CMPSB|SCASB FSRC [Capable]
|- Fast Short REP MOVSB FSRM [Capable]
|- Fast Short REP STOSB FSRS [Capable]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA4 [Missing]
|- Fused Multiply Add FMA [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hyper-Threading Technology HTT [Capable]
|- Hardware P-state control HwP [Capable]
|- Instruction Based Sampling IBS [Capable]
|- Instruction INVLPGB INVLPGB [Capable]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Memory Bandwidth Enforcement MBE [Capable]
|- Machine-Check Architecture MCA [Capable]
|- Instruction MCOMMIT MCOMMIT [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- OS Visible Work-around OSVW [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Capable]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- PREFETCHIT0/1 Instructions PREFETCHI [Missing]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Capable]
|- Read Processor Register at User level RDPRU [Capable]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Trailing Bit Manipulation TBM [Missing]
|- Translation Cache Extension TCE [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Missing]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Capable]
|- Extended xAPIC Support x2APIC [ x2APIC]
|- AVIC controller for x2APIC x2AVIC [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Missing]
|- Extended Operation Support XOP [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Capable]
|- IBRS Always-On preferred by processor [ Unable]
|- IBRS preferred over software solution [Capable]
|- IBRS provides same speculation limits [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Selective Branch Predictor Barrier SBPB [ Unable]
|- Single Thread Indirect Branch Predictor STIBP [ Enable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- SSBD use VIRT_SPEC_CTRL register [ Unable]
|- SSBD not needed on this processor [ Unable]
|- No Speculative Return Stack Overflow SRSO_NO [ Unable]
|- No SRSO at the User-Kernel boundary [ Unable]
|- No Branch Type Confusion BTC_NO [Capable]
|- BTC on Non-Branch instruction BTC-NOBR [ Unable]
|- Limited Early Redirect Window AGENPICK [ Unable]
|- Arch - No Fast Predictive Store Forwarding PSFD [Capable]
|- Arch - Enhanced Predictive Store Forwarding EPSF [Capable]
|- Arch - Cross Processor Information Leak XPROC_LEAK [ Unable]
Security Features
|- CET Shadow Stack features CET-SS [Capable]
|- Secure Init and Jump with Attestation SKINIT [Capable]
|- Secure Encrypted Virtualization SEV [Capable]
|- SEV - Encrypted State SEV-ES [Capable]
|- SEV - Secure Nested Paging SEV-SNP [Capable]
|- Guest Mode Execute Trap GMET [Capable]
|- Supervisor Shadow Stack SSS [Capable]
|- VM Permission Levels VMPL [Capable]
|- VMPL Supervisor Shadow Stack VMPL-SSS [Capable]
|- Secure Memory Encryption SME [Capable]
|- Transparent SME TSME [ Enable]
|- Secure Multi-Key Memory Encryption SME-MK [Capable]
|- DRAM Data Scrambling Scrambler [ Enable]
Technologies
|- Instruction Cache Unit
|- L1 IP Prefetcher L1 HW IP < ON>
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- Cache Prefetchers
|- L2 Prefetcher L2 HW < ON>
|- L1 Stride Prefetcher L1 Stride < ON>
|- L1 Region Prefetcher L1 Region < ON>
|- L1 Burst Prefetch Mode L1 Burst < ON>
|- L2 Stream HW Prefetcher L2 Stream < ON>
|- L2 Up/Down Prefetcher L2 Up/Down < ON>
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [ ON]
|- Core C-States CCx [ ON]
|- Core Performance Boost CPB < ON>
|- Watchdog Timer WDT < ON>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [ ON]
|- Version [ 0.1]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 2]
|- Counters: General Fixed
| { 6, 6, 16 } x 48 bits 3 x 64 bits
|- Enhanced Halt State C1E <OFF>
|- C2 UnDemotion C2U < ON>
|- C3 UnDemotion C3U < ON>
|- Core C6 State CC6 < ON>
|- Package C6 State PC6 < ON>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Core C-States
|- C-States Base Address BAR [ 0x813 ]
|- ACPI Processor C-States _CST [ 2]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 1 1 0 0 0 0 0 0
|- Monitor-Mwait Extensions EMX [Capable]
|- Interrupt Break-Event IBE [Capable]
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Global Time Stamp Counter [Missing]
|- Data Fabric Performance Counter [Capable]
|- Core Performance Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 3]
|- Performance Present Capabilities _PPC [ 0]
|- Continuous Performance Control _CPC [Missing]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax [ 49: 95 C]
|- CPPC Energy Preference EPP [Capable]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TTP [ Enable]
|- Thermal Monitor 2 HTC [ Enable]
|- Thermal Design Power TDP [Missing]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package < Enable>
|- Power Limit PL1 < 210 W>
|- Time Window TW1 < 0 ns>
|- Power Limit PL2 < 240 W>
|- Time Window TW2 < 0 ns>
|- Thermal Design Power Core [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Uncore [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power DRAM [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Platform [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 0 ns]
|- Package Power Tracking PPT [Missing]
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- Package Thermal Point
|- Thermal Monitor Trip Limit [ 115 C]
|- HTC Temperature Limit Limit [ 0 C]
|- HTC Temperature Hysteresis Threshold [ 0 C]
|- Units
|- Power watt [ Missing]
|- Energy joule [ 0.000015259]
|- Window second [ 0.000976562]
Linux:
|- Release [6.8.0-59-generic]
|- Version [#61-Ubuntu SMP PREEMPT_DYNAMIC Fri Apr 11 23:16:11 UTC 2025]
|- Machine [x86_64]
Memory:
|- Total RAM 792249128 KB
|- Shared RAM 44800 KB
|- Free RAM 787432760 KB
|- Buffer RAM 157788 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < tsc>
CPU-Freq driver [ acpi-cpufreq]
Governor [ schedutil]
CPU-Idle driver [ acpi_idle]
|- Idle Limit [ C2]
|- State POLL C1 C2
|- CPUIDLE ACPI FF ACPI IO
|- Power -1 0 0
|- Latency 0 1 800
|- Residency 0 2 1600 CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID CCD CCX ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 0 0 32 8 32 8 1024 8 i 131072 16w
001: 0 2 0 0 1 0 32 8 32 8 1024 8 i 131072 16w
002: 0 4 0 0 2 0 32 8 32 8 1024 8 i 131072 16w
003: 0 6 0 0 3 0 32 8 32 8 1024 8 i 131072 16w
004: 0 8 0 0 4 0 32 8 32 8 1024 8 i 131072 16w
005: 0 10 0 0 5 0 32 8 32 8 1024 8 i 131072 16w
006: 0 12 0 0 6 0 32 8 32 8 1024 8 i 131072 16w
007: 0 14 0 0 7 0 32 8 32 8 1024 8 i 131072 16w
008: 0 32 1 2 16 0 32 8 32 8 1024 8 i 131072 16w
009: 0 34 1 2 17 0 32 8 32 8 1024 8 i 131072 16w
010: 0 36 1 2 18 0 32 8 32 8 1024 8 i 131072 16w
011: 0 38 1 2 19 0 32 8 32 8 1024 8 i 131072 16w
012: 0 40 1 2 20 0 32 8 32 8 1024 8 i 131072 16w
013: 0 42 1 2 21 0 32 8 32 8 1024 8 i 131072 16w
014: 0 44 1 2 22 0 32 8 32 8 1024 8 i 131072 16w
015: 0 46 1 2 23 0 32 8 32 8 1024 8 i 131072 16w
016: 0 48 1 3 24 0 32 8 32 8 1024 8 i 131072 16w
017: 0 50 1 3 25 0 32 8 32 8 1024 8 i 131072 16w
018: 0 52 1 3 26 0 32 8 32 8 1024 8 i 131072 16w
019: 0 54 1 3 27 0 32 8 32 8 1024 8 i 131072 16w
020: 0 56 1 3 28 0 32 8 32 8 1024 8 i 131072 16w
021: 0 58 1 3 29 0 32 8 32 8 1024 8 i 131072 16w
022: 0 60 1 3 30 0 32 8 32 8 1024 8 i 131072 16w
023: 0 62 1 3 31 0 32 8 32 8 1024 8 i 131072 16w
024: 0 16 0 1 8 0 32 8 32 8 1024 8 i 131072 16w
025: 0 18 0 1 9 0 32 8 32 8 1024 8 i 131072 16w
026: 0 20 0 1 10 0 32 8 32 8 1024 8 i 131072 16w
027: 0 22 0 1 11 0 32 8 32 8 1024 8 i 131072 16w
028: 0 24 0 1 12 0 32 8 32 8 1024 8 i 131072 16w
029: 0 26 0 1 13 0 32 8 32 8 1024 8 i 131072 16w
030: 0 28 0 1 14 0 32 8 32 8 1024 8 i 131072 16w
031: 0 30 0 1 15 0 32 8 32 8 1024 8 i 131072 16w
032: 1 64 2 0 0 0 32 8 32 8 1024 8 i 131072 16w
033: 1 66 2 0 1 0 32 8 32 8 1024 8 i 131072 16w
034: 1 68 2 0 2 0 32 8 32 8 1024 8 i 131072 16w
035: 1 70 2 0 3 0 32 8 32 8 1024 8 i 131072 16w
036: 1 72 2 0 4 0 32 8 32 8 1024 8 i 131072 16w
037: 1 74 2 0 5 0 32 8 32 8 1024 8 i 131072 16w
038: 1 76 2 0 6 0 32 8 32 8 1024 8 i 131072 16w
039: 1 78 2 0 7 0 32 8 32 8 1024 8 i 131072 16w
040: 1 96 3 2 16 0 32 8 32 8 1024 8 i 131072 16w
041: 1 98 3 2 17 0 32 8 32 8 1024 8 i 131072 16w
042: 1 100 3 2 18 0 32 8 32 8 1024 8 i 131072 16w
043: 1 102 3 2 19 0 32 8 32 8 1024 8 i 131072 16w
044: 1 104 3 2 20 0 32 8 32 8 1024 8 i 131072 16w
045: 1 106 3 2 21 0 32 8 32 8 1024 8 i 131072 16w
046: 1 108 3 2 22 0 32 8 32 8 1024 8 i 131072 16w
047: 1 110 3 2 23 0 32 8 32 8 1024 8 i 131072 16w
048: 1 112 3 3 24 0 32 8 32 8 1024 8 i 131072 16w
049: 1 114 3 3 25 0 32 8 32 8 1024 8 i 131072 16w
050: 1 116 3 3 26 0 32 8 32 8 1024 8 i 131072 16w
051: 1 118 3 3 27 0 32 8 32 8 1024 8 i 131072 16w
052: 1 120 3 3 28 0 32 8 32 8 1024 8 i 131072 16w
053: 1 122 3 3 29 0 32 8 32 8 1024 8 i 131072 16w
054: 1 124 3 3 30 0 32 8 32 8 1024 8 i 131072 16w
055: 1 126 3 3 31 0 32 8 32 8 1024 8 i 131072 16w
056: 1 80 2 1 8 0 32 8 32 8 1024 8 i 131072 16w
057: 1 82 2 1 9 0 32 8 32 8 1024 8 i 131072 16w
058: 1 84 2 1 10 0 32 8 32 8 1024 8 i 131072 16w
059: 1 86 2 1 11 0 32 8 32 8 1024 8 i 131072 16w
060: 1 88 2 1 12 0 32 8 32 8 1024 8 i 131072 16w
061: 1 90 2 1 13 0 32 8 32 8 1024 8 i 131072 16w
062: 1 92 2 1 14 0 32 8 32 8 1024 8 i 131072 16w
063: 1 94 2 1 15 0 32 8 32 8 1024 8 i 131072 16w
064: 0 1 0 0 0 1 32 8 32 8 1024 8 i 131072 16w
065: 0 3 0 0 1 1 32 8 32 8 1024 8 i 131072 16w
066: 0 5 0 0 2 1 32 8 32 8 1024 8 i 131072 16w
067: 0 7 0 0 3 1 32 8 32 8 1024 8 i 131072 16w
068: 0 9 0 0 4 1 32 8 32 8 1024 8 i 131072 16w
069: 0 11 0 0 5 1 32 8 32 8 1024 8 i 131072 16w
070: 0 13 0 0 6 1 32 8 32 8 1024 8 i 131072 16w
071: 0 15 0 0 7 1 32 8 32 8 1024 8 i 131072 16w
072: 0 33 1 2 16 1 32 8 32 8 1024 8 i 131072 16w
073: 0 35 1 2 17 1 32 8 32 8 1024 8 i 131072 16w
074: 0 37 1 2 18 1 32 8 32 8 1024 8 i 131072 16w
075: 0 39 1 2 19 1 32 8 32 8 1024 8 i 131072 16w
076: 0 41 1 2 20 1 32 8 32 8 1024 8 i 131072 16w
077: 0 43 1 2 21 1 32 8 32 8 1024 8 i 131072 16w
078: 0 45 1 2 22 1 32 8 32 8 1024 8 i 131072 16w
079: 0 47 1 2 23 1 32 8 32 8 1024 8 i 131072 16w
080: 0 49 1 3 24 1 32 8 32 8 1024 8 i 131072 16w
081: 0 51 1 3 25 1 32 8 32 8 1024 8 i 131072 16w
082: 0 53 1 3 26 1 32 8 32 8 1024 8 i 131072 16w
083: 0 55 1 3 27 1 32 8 32 8 1024 8 i 131072 16w
084: 0 57 1 3 28 1 32 8 32 8 1024 8 i 131072 16w
085: 0 59 1 3 29 1 32 8 32 8 1024 8 i 131072 16w
086: 0 61 1 3 30 1 32 8 32 8 1024 8 i 131072 16w
087: 0 63 1 3 31 1 32 8 32 8 1024 8 i 131072 16w
088: 0 17 0 1 8 1 32 8 32 8 1024 8 i 131072 16w
089: 0 19 0 1 9 1 32 8 32 8 1024 8 i 131072 16w
090: 0 21 0 1 10 1 32 8 32 8 1024 8 i 131072 16w
091: 0 23 0 1 11 1 32 8 32 8 1024 8 i 131072 16w
092: 0 25 0 1 12 1 32 8 32 8 1024 8 i 131072 16w
093: 0 27 0 1 13 1 32 8 32 8 1024 8 i 131072 16w
094: 0 29 0 1 14 1 32 8 32 8 1024 8 i 131072 16w
095: 0 31 0 1 15 1 32 8 32 8 1024 8 i 131072 16w
096: 1 65 2 0 0 1 32 8 32 8 1024 8 i 131072 16w
097: 1 67 2 0 1 1 32 8 32 8 1024 8 i 131072 16w
098: 1 69 2 0 2 1 32 8 32 8 1024 8 i 131072 16w
099: 1 71 2 0 3 1 32 8 32 8 1024 8 i 131072 16w
100: 1 73 2 0 4 1 32 8 32 8 1024 8 i 131072 16w
101: 1 75 2 0 5 1 32 8 32 8 1024 8 i 131072 16w
102: 1 77 2 0 6 1 32 8 32 8 1024 8 i 131072 16w
103: 1 79 2 0 7 1 32 8 32 8 1024 8 i 131072 16w
104: 1 97 3 2 16 1 32 8 32 8 1024 8 i 131072 16w
105: 1 99 3 2 17 1 32 8 32 8 1024 8 i 131072 16w
106: 1 101 3 2 18 1 32 8 32 8 1024 8 i 131072 16w
107: 1 103 3 2 19 1 32 8 32 8 1024 8 i 131072 16w
108: 1 105 3 2 20 1 32 8 32 8 1024 8 i 131072 16w
109: 1 107 3 2 21 1 32 8 32 8 1024 8 i 131072 16w
110: 1 109 3 2 22 1 32 8 32 8 1024 8 i 131072 16w
111: 1 111 3 2 23 1 32 8 32 8 1024 8 i 131072 16w
112: 1 113 3 3 24 1 32 8 32 8 1024 8 i 131072 16w
113: 1 115 3 3 25 1 32 8 32 8 1024 8 i 131072 16w
114: 1 117 3 3 26 1 32 8 32 8 1024 8 i 131072 16w
115: 1 119 3 3 27 1 32 8 32 8 1024 8 i 131072 16w
116: 1 121 3 3 28 1 32 8 32 8 1024 8 i 131072 16w
117: 1 123 3 3 29 1 32 8 32 8 1024 8 i 131072 16w
118: 1 125 3 3 30 1 32 8 32 8 1024 8 i 131072 16w
119: 1 127 3 3 31 1 32 8 32 8 1024 8 i 131072 16w
120: 1 81 2 1 8 1 32 8 32 8 1024 8 i 131072 16w
121: 1 83 2 1 9 1 32 8 32 8 1024 8 i 131072 16w
122: 1 85 2 1 10 1 32 8 32 8 1024 8 i 131072 16w
123: 1 87 2 1 11 1 32 8 32 8 1024 8 i 131072 16w
124: 1 89 2 1 12 1 32 8 32 8 1024 8 i 131072 16w
125: 1 91 2 1 13 1 32 8 32 8 1024 8 i 131072 16w
126: 1 93 2 1 14 1 32 8 32 8 1024 8 i 131072 16w
127: 1 95 2 1 15 1 32 8 32 8 1024 8 i 131072 16w
Zen UMC [14AD]
Controller #0 Twelve Channel
Bus Rate 2400 MHz Bus Speed 2448 MHz REG DDR5 Speed 4896 MT/s
Cha CL RCDr RCDw RP RAS RC RRDs RRDl FAW WTRs WTRl WR clRR clWW
#0 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#1 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#2 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#3 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#4 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#5 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#6 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#7 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#8 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#9 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#10 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#11 40 39 39 39 77 116 8 12 32 6 24 72 5 17
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#1 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#2 38 18 20 5 1 9 9 1 8 8 0 0 0 0
#3 38 18 18 5 1 9 9 1 8 8 0 0 0 0
#4 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#5 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#6 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#7 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#8 38 18 20 5 1 9 9 1 8 8 0 0 0 0
#9 38 18 18 5 1 9 9 1 8 8 0 0 0 0
#10 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#11 38 18 19 5 1 9 9 1 8 8 0 0 0 0
REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt Ban Page CKE CMD GDM ECC
#0 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#1 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#2 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#3 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#4 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#5 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#6 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#7 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#8 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#9 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#10 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#11 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
MRD:PDA MOD:PDA WRMPR STAG PDM RDDATA WRD WRL RDL XS XP CPDED
#0 32 32 32 32 24 36 0:P:0 31 6 29 34 732 18 12
#1 32 32 32 32 24 36 0:P:0 31 6 29 36 732 18 12
#2 32 32 32 32 24 36 0:P:0 31 6 29 36 732 18 12
#3 32 32 32 32 24 36 0:P:0 31 6 29 34 732 18 12
#4 32 32 32 32 24 36 0:P:0 31 6 29 34 732 18 12
#5 32 32 32 32 24 36 0:P:0 31 6 29 36 732 18 12
#6 32 32 32 32 24 36 0:P:0 31 6 29 34 732 18 12
#7 32 32 32 32 24 36 0:P:0 31 6 29 36 732 18 12
#8 32 32 32 32 24 36 0:P:0 31 6 29 36 732 18 12
#9 32 32 32 32 24 36 0:P:0 31 6 29 34 732 18 12
#10 32 32 32 32 24 36 0:P:0 31 6 29 34 732 18 12
#11 32 32 32 32 24 36 0:P:0 31 6 29 36 732 18 12
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #2
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #3
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #4
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #5
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #6
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #7
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #8
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #9
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #10
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #11
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
Controller #1 Twelve Channel
Bus Rate 2400 MHz Bus Speed 2448 MHz REG DDR5 Speed 4896 MT/s
Cha CL RCDr RCDw RP RAS RC RRDs RRDl FAW WTRs WTRl WR clRR clWW
#0 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#1 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#2 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#3 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#4 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#5 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#6 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#7 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#8 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#9 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#10 40 39 39 39 77 116 8 12 32 6 24 72 5 17
#11 40 39 39 39 77 116 8 12 32 6 24 72 5 17
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#1 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#2 38 18 20 5 1 9 9 1 8 8 0 0 0 0
#3 38 18 18 5 1 9 9 1 8 8 0 0 0 0
#4 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#5 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#6 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#7 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#8 38 18 20 5 1 9 9 1 8 8 0 0 0 0
#9 38 18 18 5 1 9 9 1 8 8 0 0 0 0
#10 38 18 19 5 1 9 9 1 8 8 0 0 0 0
#11 38 18 19 5 1 9 9 1 8 8 0 0 0 0
REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt Ban Page CKE CMD GDM ECC
#0 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#1 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#2 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#3 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#4 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#5 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#6 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#7 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#8 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#9 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#10 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
#11 9347 708 384 312 0 0 ON OFF R0W0 0 0 1T OFF 1
MRD:PDA MOD:PDA WRMPR STAG PDM RDDATA WRD WRL RDL XS XP CPDED
#0 32 32 32 32 24 36 0:P:0 31 6 29 34 732 18 12
#1 32 32 32 32 24 36 0:P:0 31 6 29 36 732 18 12
#2 32 32 32 32 24 36 0:P:0 31 6 29 36 732 18 12
#3 32 32 32 32 24 36 0:P:0 31 6 29 34 732 18 12
#4 32 32 32 32 24 36 0:P:0 31 6 29 34 732 18 12
#5 32 32 32 32 24 36 0:P:0 31 6 29 34 732 18 12
#6 32 32 32 32 24 36 0:P:0 31 6 29 34 732 18 12
#7 32 32 32 32 24 36 0:P:0 31 6 29 36 732 18 12
#8 32 32 32 32 24 36 0:P:0 31 6 29 36 732 18 12
#9 32 32 32 32 24 36 0:P:0 31 6 29 34 732 18 12
#10 32 32 32 32 24 36 0:P:0 31 6 29 34 732 18 12
#11 32 32 32 32 24 36 0:P:0 31 6 29 36 732 18 12
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #2
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #3
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #4
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #5
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #6
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #7
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #8
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #9
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #10
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1
DIMM Geometry for channel #11
Slot Bank Rank Rows Columns Memory Size (MB)
#0 32 2 65536 1024 32768 MTC20F2085S1RC56BD1
#1 [ 0] American Megatrends International, LLC.
[ 1] 2.06
[ 2] 05/06/2024
[ 3] To Be Filled By O.E.M.
[ 4] GENOA2D24G-2L+
[ 5] To Be Filled By O.E.M.
[ 6] T---e---l--- ---O---M-
[ 7] To Be Filled By O.E.M.
[ 8] To Be Filled By O.E.M.
[ 9] ASRockRack
[ 10] GENOA2D24G-2L+
[ 11]
[ 12] B---H---4---0--
[ 13] Number Of Devices:24\Maximum Capacity:13194139533312 kilobytes
[ 14] DIMM 0\P0 CHANNEL A
[ 15] Micron Technology
[ 16] MTC20F2085S1RC56BD1 MMCC
[ 17] DIMM 0\P0 CHANNEL B
[ 18] Micron Technology
[ 19] MTC20F2085S1RC56BD1 MMCC
[ 20] DIMM 0\P0 CHANNEL C
[ 21] Micron Technology
[ 22] MTC20F2085S1RC56BD1 QLFF
[ 23] DIMM 0\P0 CHANNEL D
[ 24] Micron Technology
[ 25] MTC20F2085S1RC56BD1 QLFF
[ 26] DIMM 0\P0 CHANNEL E
[ 27] Micron Technology
[ 28] MTC20F2085S1RC56BD1 MMCC
[ 29] DIMM 0\P0 CHANNEL F
[ 30] Micron Technology
[ 31] MTC20F2085S1RC56BD1 QLFF
[ 32] DIMM 0\P0 CHANNEL G
[ 33] Micron Technology
[ 34] MTC20F2085S1RC56BD1 MMCC
[ 35] DIMM 0\P0 CHANNEL H
[ 36] Micron Technology
[ 37] MTC20F2085S1RC56BD1 MMCC
[ 38] DIMM 0\P0 CHANNEL I
[ 39] Micron Technology
[ 40] MTC20F2085S1RC56BD1 MMCC
[ 41] DIMM 0\P0 CHANNEL J
[ 42] Micron Technology
[ 43] MTC20F2085S1RC56BD1 QLFF
[ 44] DIMM 0\P0 CHANNEL K
[ 45] Micron Technology
[ 46] MTC20F2085S1RC56BD1 MMCC
[ 47] DIMM 0\P0 CHANNEL L
[ 48] Micron Technology
[ 49] MTC20F2085S1RC56BD1 QLFF
[ 50] DIMM 0\P1 CHANNEL A
[ 51] Micron Technology
[ 52] MTC20F2085S1RC56BD1 QLFF
[ 53] DIMM 0\P1 CHANNEL B
[ 54] Micron Technology
[ 55] MTC20F2085S1RC56BD1 QLFF
[ 56] DIMM 0\P1 CHANNEL C
[ 57] Micron Technology
[ 58] MTC20F2085S1RC56BD1 MMCC
[ 59] DIMM 0\P1 CHANNEL D
[ 60] Micron Technology
[ 61] MTC20F2085S1RC56BD1 MMCC
[ 62] DIMM 0\P1 CHANNEL E
[ 63] Micron Technology
[ 64] MTC20F2085S1RC56BD1 MMCC
[ 65] DIMM 0\P1 CHANNEL F
[ 66] Micron Technology
[ 67] MTC20F2085S1RC56BD1 QLFF
[ 68] DIMM 0\P1 CHANNEL G
[ 69] Micron Technology
[ 70] MTC20F2085S1RC56BD1 MMCC
[ 71] DIMM 0\P1 CHANNEL H
[ 72] Micron Technology
[ 73] MTC20F2085S1RC56BD1 QLFF
[ 74] DIMM 0\P1 CHANNEL I
[ 75] Micron Technology
[ 76] MTC20F2085S1RC56BD1 MMCC
[ 77] DIMM 0\P1 CHANNEL J
[ 78] Micron Technology
[ 79] MTC20F2085S1RC56BD1 MMCC
[ 80] DIMM 0\P1 CHANNEL K
[ 81] Micron Technology
[ 82] MTC20F2085S1RC56BD1 MMCC
[ 83] DIMM 0\P1 CHANNEL L
[ 84] Micron Technology
[ 85] MTC20F2085S1RC56BD1 MMCC
[ 86]
Sensors
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