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cyring/gist:dff37a10720945aca2544b7ff76a679a

Created July 6, 2026 23:11
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DGX Spark
@cyring

cyring commented Jul 6, 2026

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Processor                                                          [Cortex-X925]
|- Architecture                                                      [ARMv9.2-A]
|- Vendor ID                                                               [Arm]
|- Revision                                                         [0x00000000]
|- Signature                                                           [ D85_00]
|- Stepping                                                            [   r0p1]
|- Online CPU                                                          [ 20/ 20]
|- Base Clock                                                          [999.890]
|- Frequency            (MHz)                      Ratio                        
                 Min   1377.70                  <   1.38 >                      
                 Max   3899.18                  <   3.90 >                      
|- Factory                                                             [1000.00]
                       1000                     [      1 ]                      
|- Performance                                                                  
                 TGT   1377.82                  <   1.38 >                      
   |- CPPC                                                                      
                 Min      AUTO                  <   0.00 >                      
                 Max      AUTO                  <   0.00 >                      
                 TGT      AUTO                  <   0.00 >                      
|- OPP                                                                          
|- Hybrid                                                              [   LOCK]
|- Uncore                                                              [   LOCK]
                                                                                
Instruction Set Extensions                                                      
|-          AES [Y]        ASIMD [Y]        ATS1A [N]         BF16 [Y]
|-       CLRBHB [N]  CONSTPACFLD [Y]          CPA [N]        CRC32 [Y]
|-         CSSC [N]          DGH [Y]           DP [Y]          DPB [Y]
|-         DPB2 [Y]        EBF16 [N]         EPAC [N]     FAMINMAX [N]
|-         FCMA [Y]          FHM [Y]        FlagM [Y]       FlagM2 [Y]
|-           FP [Y]         FPAC [N]  FPACCOMBINE [Y]     FP_ROUND [Y]
|-    FP_Sh_Vec [N]      FP_SQRT [Y]    FP_DIVIDE [Y]      FP_TRAP [N]
|-        FP_DP [Y]        FP_SP [Y]        FP_HP [Y]       FP_NaN [Y]
|-       FP_FtZ [Y]      FP_MISC [Y]       FPRCVT [N]      FRINTTS [Y]
|-          HBC [N]         I8MM [Y]        JSCVT [Y]        LRCPC [Y]
|-       LRCPC2 [Y]       LRCPC3 [N]         LS64 [N]       LS64_V [N]
|- LS64_ACCDATA [N]          LSE [Y]       LSE128 [N]         LSFE [N]
|-         LSUI [N]          LUT [N]         MOPS [N]        OCCMO [N]
|-        PACGA [N]    PACQARMA3 [Y]    PACQARMA5 [N]        PAuth [N]
|-       PAuth2 [N]     PAuth_LR [N]         PACM [N]     PCDPHINT [N]
|-        PMULL [Y]      PRFMSLC [N]         RAND [N]         RDMA [Y]
|-     RNG-TRAP [N]        RPRES [N]        RPRFM [N]           SB [Y]
|-         SHA1 [Y]       SHA256 [Y]       SHA512 [Y]         SHA3 [Y]
|-     SIMD_REG [Y]     SIMD_FMA [Y]      SIMD_HP [Y]      SIMD_SP [Y]
|-     SIMD_INT [Y]      SIMD_LS [Y]    SIMD_MISC [Y]          SM3 [Y]
|-          SM4 [Y]          SME [N]         SME2 [N]       SME2p1 [N]
|-     SME_FA64 [N]    SME_LUTv2 [N]   SME_I16I64 [N]   SME_F64F64 [N]
|-   SME_I16I32 [N]   SME_B16B16 [N]   SME_F16F16 [N]    SME_F8F16 [N]
|-    SME_F8F32 [N]    SME_I8I32 [N]   SME_F16F32 [N]   SME_B16F32 [N]
|-  SME_BI32I32 [N]   SME_F32F32 [N]   SME_SF8FMA [N]   SME_SF8DP4 [N]
|-   SME_SF8DP2 [N]      SPECRES [Y]     SPECRES2 [N]          SVE [Y]
|-         SVE2 [Y]    SVE_F64MM [N]    SVE_F32MM [N]     SVE_I8MM [Y]
|-      SVE_SM4 [Y]     SVE_SHA3 [Y]     SVE_BF16 [Y]    SVE_EBF16 [N]
|-  SVE_BitPerm [Y]      SVE_AES [Y] SVE_PMULL128 [Y]    SYSREG128 [N]
|-  SYSINSTR128 [N]        TLBIW [N]         WFxT [N]           XS [Y]
                                                                                
Features                                                                        
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Activity Monitor Unit v1p0                                    AMU   [Capable]
|- Mixed-Endianness EL0                                       BigEnd   [Missing]
|- Mixed-Endianness EE|E0E                                    BigEnd   [Capable]
|- Exception-based event profiling                              EBEP   [Missing]
|- Enhanced Counter Virtualization                               ECV   [Capable]
|- Double Fault Extension                                        DF2   [Missing]
|- Data Independent Timing                                       DIT   [Capable]
|- Context Synchronization & Exception Handling                  ExS   [Missing]
|- Fine-Grained Trap controls                                    FGT   [Capable]
|- Fine-Grained Trap controls                                   FGT2   [Missing]
|- Floating-point Mode Register                                 FPMR   [Missing]
|- Physical Fault Address Registers                             PFAR   [Missing]
|- Generic Interrupt Controller v4.1                             GIC   [Capable]
|- Memory Partitioning and Monitoring v1p1                      MPAM   [Capable]
|- Memory Tagging Extension v1                                   MTE   [Capable]
   |- Reporting Tag Check Fault                           TAGGED_FAR   [Missing]
   |- Allocation tag access permissions                         PERM   [Missing]
   |- Store-only Tag checking                              STOREONLY   [Missing]
|- Non Maskable Interrupt                                        NMI   [Missing]
|- Physical Address range 40 bits, 1TB                            PA   [Capable]
|- Privileged Access Never                                       PAN   [Capable]
|- Reliability Availability & Serviceability v1p1                RAS   [Capable]
|- TLB maintenance instructions                               TLBIOS   [Capable]
|- TLB maintenance instructions                            TLBIRANGE   [Capable]
|- Transactional Memory Extension                                TME   [Missing]
|- Time Stamp Counter                                            TSC [Invariant]
|- User Access Override                                          UAO   [Capable]
|- Injection of Undefined Instruction                           UINJ   [Missing]
|- Virtual Address range 48 bits                                  VA   [Capable]
|- Virtualization Host Extensions                                VHE   [Capable]
Mitigation mechanisms                                                           
|- Clear Branch History instruction                           CLRBHB   [ Unable]
|- Speculative Store Bypass Disable                         CSV2_2p0   [ Enable]
|- Speculative Store Bypass Disable                             CSV3   [ Enable]
|- Exploitative Control w/ Branch History Buffer               ECBHB   [Capable]
|- Speculative Store Bypass Safe                                SSBS   [Capable]
Security Features                                                               
|- Branch Target Identification                                  BTI   [Capable]
|- Guarded Control Stack                                         GCS   [Missing]
|- Realm Management Extension                                    RME   [Missing]
|- Secure EL2 Implementation                                    SEL2   [Capable]
|- Translation Hardening Extension                               THE   [Missing]
                                                                                
Technologies                                                                    
|- Instruction Cache Unit                                             I$   [ ON]
|- Data Cache Unit                                                    D$   [ ON]
|- Memory Management Unit                                            MMU   [ ON]
|- Low Power Methods                                                 WFx   [ ON]
|- Simultaneous Multithreading                                       SMT   [OFF]
|- big.LITTLE technology                                          HYBRID   [ ON]
|- Interconnect Technology                                                      
   |- DynamIQ Shared Unit                                        DSU-120   [ ON]
   |- Coherent Mesh Network                                          CMN   [OFF]
   |- CoreLink Network Interconnect                                  CCN   [OFF]
   |- Cache Coherent Interconnect                                    CCI   [OFF]
|- Virtualization                                                    VHE   [ ON]
   |- I/O MMU                                                      IOMMU   [OFF]
   |- Version                                                     [         N/A]
   |- Hypervisor                                              Bare-Metal   [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [3.7]
|- Counters:          General                   Fixed                           
|           { 31,  4,  3 } x 64 bits            1 x 64 bits                     
|- Low Power Methods                                                            
   |- Wait for Interrupt                                         WFI   [ Enable]
   |- Wait for Event                                             WFE   [ Enable]
|- ACPI Processor C-States                                      _CST   [Missing]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     0     0     0     0     0     0     0              
|- Core Cycles Counter                                                 [Capable]
|- Instructions Counter                                                [Missing]
|- Processor Performance Control                                _PCT   [Missing]
|- Performance Supported States                                 _PSS   [Missing]
|- Performance Present Capabilities                             _PPC   [Missing]
|- Continuous Performance Control                               _CPC   [ Enable]
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax <  0:  0 C>
|- CPPC Energy Preference                                        EPP   <      0>
|- Digital Thermal Sensor                                        DTS   [Missing]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
|- Package Thermal Point                                                        
|- Units                                                                        
   |- Power                                               watt   [      Missing]
   |- Energy                                             joule   [      Missing]
   |- Window                                            second   [      Missing]

CPU Pkg  Main  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID  Hybrid ID/ID L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP     0 E D87   0  0   65536  4     65536  4    524288  8   8388608 16  
001:  0   100 E D87   1  0   65536  4     65536  4    524288  8   8388608 16  
002:  0   200 E D87   2  0   65536  4     65536  4    524288  8   8388608 16  
003:  0   300 E D87   3  0   65536  4     65536  4    524288  8   8388608 16  
004:  0   400 E D87   4  0   65536  4     65536  4    524288  8   8388608 16  
005:  0   500 P D85   5  0   65536  4     65536  4   2097152  8   8388608 16  
006:  0   600 P D85   6  0   65536  4     65536  4   2097152  8   8388608 16  
007:  0   700 P D85   7  0   65536  4     65536  4   2097152  8   8388608 16  
008:  0   800 P D85   8  0   65536  4     65536  4   2097152  8   8388608 16  
009:  0   900 P D85   9  0   65536  4     65536  4   2097152  8   8388608 16  
010:  1 10000 E D87   0  0   65536  4     65536  4    524288  8  16777216 16  
011:  1 10100 E D87   1  0   65536  4     65536  4    524288  8  16777216 16  
012:  1 10200 E D87   2  0   65536  4     65536  4    524288  8  16777216 16  
013:  1 10300 E D87   3  0   65536  4     65536  4    524288  8  16777216 16  
014:  1 10400 E D87   4  0   65536  4     65536  4    524288  8  16777216 16  
015:  1 10500 P D85   5  0   65536  4     65536  4   2097152  8  16777216 16  
016:  1 10600 P D85   6  0   65536  4     65536  4   2097152  8  16777216 16  
017:  1 10700 P D85   7  0   65536  4     65536  4   2097152  8  16777216 16  
018:  1 10800 P D85   8  0   65536  4     65536  4   2097152  8  16777216 16  
019:  1 10900 P D85   9  0   65536  4     65536  4   2097152  8  16777216 16  

[ 0] American Megatrends International, LLC.                                    
[ 1] GX10DGX.0101.2025.1014.1350                                                
[ 2] 10/14/2025                                                                 
[ 3] ASUSTeK COMPUTER INC.                                                      
[ 4] GX10                                                                       
[ 5] 5.36_GX10DGX                                                               
[ 6] W---A---6---8--                                                            
[ 7] Default string                                                             
[ 8] DGX Spark                                                                  
[ 9] ASUSTeK COMPUTER INC.                                                      
[10] GX10                                                                       
[11] Default string                                                             
[12] 2---5---8---4--                                                            
[13] Number Of Devices:1\Maximum Capacity:134217728 kilobytes                   
[14] DIMM0\BANK 0                                                               
[15]                                                                            
[16]                                                                            
[17]                                                                            
[18] SK Hynix                                                                   
[19]                                                                            
[20]                                                                            
[21]                                                                            
[22] None                                                                       
[23]                                                                            
[24]                                                                            
[25]                                                                            

FLAG  PM  N   Z   C   V  TCO DIT UAO PAN NMI SSBS D   A   I   F  EL 
#0    -   0   1   1   0   1   1   0   1   -   1   0   0   1   1   2 
#1    -   0   1   1   0   1   1   0   1   -   1   0   0   1   1   2 
#2    -   0   1   1   0   1   1   0   1   -   1   0   0   1   1   2 
#3    -   0   1   1   0   1   1   0   1   -   1   0   0   1   1   2 
#4    -   0   1   1   0   1   1   0   1   -   1   0   0   1   1   2 
#5    -   0   1   1   0   0   1   0   1   -   1   0   0   1   1   2 
#6    -   0   1   1   0   0   1   0   1   -   1   0   0   1   1   2 
#7    -   0   1   1   0   0   1   0   1   -   1   0   0   1   1   2 
#8    -   0   1   1   0   0   1   0   1   -   1   0   0   1   1   2 
#9    -   0   1   1   0   0   1   0   1   -   1   0   0   1   1   2 
#10   -   0   1   1   0   1   1   0   1   -   1   0   0   1   1   2 
#11   -   0   1   1   0   1   1   0   1   -   1   0   0   1   1   2 
#12   -   0   1   1   0   1   1   0   1   -   1   0   0   1   1   2 
#13   -   0   1   1   0   1   1   0   1   -   1   0   0   1   1   2 
#14   -   0   1   1   0   1   1   0   1   -   1   0   0   1   1   2 
#15   -   0   1   1   0   0   1   0   1   -   1   0   0   1   1   2 
#16   -   0   1   1   0   0   1   0   1   -   1   0   0   1   1   2 
#17   -   0   1   1   0   0   1   0   1   -   1   0   0   1   1   2 
#18   -   0   1   1   0   0   1   0   1   -   1   0   0   1   1   2 
#19   -   0   1   1   0   0   1   0   1   -   1   0   0   1   1   2 
       TWE   ID5 DCT ATA   TTL  SCXT    AMVO IC  ID4 GPF FI  FWB NV2
HCR  DLY DEn             BOS BIS En  OCU En  AB          En         
#0    0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#1    0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#2    0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#3    0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#4    0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#5    0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#6    0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#7    0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#8    0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#9    0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#10   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#11   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#12   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#13   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#14   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#15   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#16   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#17   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#18   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#19   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
HCR  AT  NV1 NV  API APK TME IOC TEA ERR LOR E2H ID  CD  RW  RVM HCD
#0    0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#1    0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#2    0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#3    0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#4    0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#5    0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#6    0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#7    0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#8    0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#9    0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#10   0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#11   0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#12   0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#13   0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#14   0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#15   0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#16   0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#17   0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#18   0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
#19   0   0   0   0   0   0   0   0   0   0   1   0   0   1   0   0 
HCR  DZ  GE  VM  TLB PU  PCP SW  ACR ID  SMC ID3 ID2 ID1 ID0 TWE TWI
#0    0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#1    0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#2    0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#3    0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#4    0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#5    0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#6    0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#7    0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#8    0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#9    0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#10   0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#11   0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#12   0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#13   0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#14   0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#15   0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#16   0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#17   0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#18   0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
#19   0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0 
HCR  DC  BSU FB  VSE VI  VF  AMO IMO FMO PTW    SWIO     VM         
#0    0   0   0   0   0   0   1   1   1   0       0       0         
#1    0   0   0   0   0   0   1   1   1   0       0       0         
#2    0   0   0   0   0   0   1   1   1   0       0       0         
#3    0   0   0   0   0   0   1   1   1   0       0       0         
#4    0   0   0   0   0   0   1   1   1   0       0       0         
#5    0   0   0   0   0   0   1   1   1   0       0       0         
#6    0   0   0   0   0   0   1   1   1   0       0       0         
#7    0   0   0   0   0   0   1   1   1   0       0       0         
#8    0   0   0   0   0   0   1   1   1   0       0       0         
#9    0   0   0   0   0   0   1   1   1   0       0       0         
#10   0   0   0   0   0   0   1   1   1   0       0       0         
#11   0   0   0   0   0   0   1   1   1   0       0       0         
#12   0   0   0   0   0   0   1   1   1   0       0       0         
#13   0   0   0   0   0   0   1   1   1   0       0       0         
#14   0   0   0   0   0   0   1   1   1   0       0       0         
#15   0   0   0   0   0   0   1   1   1   0       0       0         
#16   0   0   0   0   0   0   1   1   1   0       0       0         
#17   0   0   0   0   0   0   1   1   1   0       0       0         
#18   0   0   0   0   0   0   1   1   1   0       0       0         
#19   0   0   0   0   0   0   1   1   1   0       0       0         
     TID  SP NMI TPI  TCSO   PAN ALS AS0 ASR   TME     TMT     TWE  
SCTL  CP INT     DR2 EL1 EL0                 EL1 EL0 EL1 EL0 DLY En 
#0    0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#1    0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#2    0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#3    0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#4    0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#5    0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#6    0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#7    0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#8    0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#9    0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#10   0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#11   0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#12   0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#13   0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#14   0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#15   0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#16   0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#17   0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#18   0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
#19   0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0 
    SSBS   ATA     TCF    IT   BTI   FPM MC CMOW IA  IB    LSM   DA 
SCTL     EL1 EL0 EL1 EL0 FSB EL1 EL0     MS              AOE DnT    
#0    0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#1    0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#2    0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#3    0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#4    0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#5    0   0   0   0   0   1   1   1   0   0   0   1   1   1   1   1 
#6    0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#7    0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#8    0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#9    0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#10   0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#11   0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#12   0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#13   0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#14   0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#15   0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#16   0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#17   0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#18   0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
#19   0   0   0   0   0   1   1   1   0   0   0   1   0   1   1   0 
SCTL UCI EE E0E SPAN EIS IES SCN WXN TWE TWI UCT DZE DB   I EOS RCTX
#0    1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#1    1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#2    1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#3    1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#4    1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#5    1   0   0   0   1   1   1   0   1   0   1   1   1   1   1   0 
#6    1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#7    1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#8    1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#9    1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#10   1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#11   1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#12   1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#13   1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#14   1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#15   1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#16   1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#17   1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#18   1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
#19   1   0   0   0   1   1   1   0   1   0   1   1   0   1   1   0 
SCTL UMA SED ITD AA CP15 SA0 SA1  C   A   M                         
#0    0   1   1   0   0   1   1   1   0   1                         
#1    0   1   1   0   0   1   1   1   0   1                         
#2    0   1   1   0   0   1   1   1   0   1                         
#3    0   1   1   0   0   1   1   1   0   1                         
#4    0   1   1   0   0   1   1   1   0   1                         
#5    0   1   1   0   0   1   1   1   0   1                         
#6    0   1   1   0   0   1   1   1   0   1                         
#7    0   1   1   0   0   1   1   1   0   1                         
#8    0   1   1   0   0   1   1   1   0   1                         
#9    0   1   1   0   0   1   1   1   0   1                         
#10   0   1   1   0   0   1   1   1   0   1                         
#11   0   1   1   0   0   1   1   1   0   1                         
#12   0   1   1   0   0   1   1   1   0   1                         
#13   0   1   1   0   0   1   1   1   0   1                         
#14   0   1   1   0   0   1   1   1   0   1                         
#15   0   1   1   0   0   1   1   1   0   1                         
#16   0   1   1   0   0   1   1   1   0   1                         
#17   0   1   1   0   0   1   1   1   0   1                         
#18   0   1   1   0   0   1   1   1   0   1                         
#19   0   1   1   0   0   1   1   1   0   1                         
      CPTM    CPTA    PACM  IDCP EAS AN  AD NMEA                    
SCT2 EL0 EL1 EL0 EL1 EL0 EL1 128    ERR ERR                         
#0    -   -   -   -   -   -   -   -   -   -   -                     
#1    -   -   -   -   -   -   -   -   -   -   -                     
#2    -   -   -   -   -   -   -   -   -   -   -                     
#3    -   -   -   -   -   -   -   -   -   -   -                     
#4    -   -   -   -   -   -   -   -   -   -   -                     
#5    -   -   -   -   -   -   -   -   -   -   -                     
#6    -   -   -   -   -   -   -   -   -   -   -                     
#7    -   -   -   -   -   -   -   -   -   -   -                     
#8    -   -   -   -   -   -   -   -   -   -   -                     
#9    -   -   -   -   -   -   -   -   -   -   -                     
#10   -   -   -   -   -   -   -   -   -   -   -                     
#11   -   -   -   -   -   -   -   -   -   -   -                     
#12   -   -   -   -   -   -   -   -   -   -   -                     
#13   -   -   -   -   -   -   -   -   -   -   -                     
#14   -   -   -   -   -   -   -   -   -   -   -                     
#15   -   -   -   -   -   -   -   -   -   -   -                     
#16   -   -   -   -   -   -   -   -   -   -   -                     
#17   -   -   -   -   -   -   -   -   -   -   -                     
#18   -   -   -   -   -   -   -   -   -   -   -                     
#19   -   -   -   -   -   -   -   -   -   -   -                     
 EL      Level0      Level1        Level2        Level3             
Exec:    64  32      64  32      64  32  SEC     64  32             
#0        1   0       1   0       1   0   1       1   0             
#1        1   0       1   0       1   0   1       1   0             
#2        1   0       1   0       1   0   1       1   0             
#3        1   0       1   0       1   0   1       1   0             
#4        1   0       1   0       1   0   1       1   0             
#5        1   0       1   0       1   0   1       1   0             
#6        1   0       1   0       1   0   1       1   0             
#7        1   0       1   0       1   0   1       1   0             
#8        1   0       1   0       1   0   1       1   0             
#9        1   0       1   0       1   0   1       1   0             
#10       1   0       1   0       1   0   1       1   0             
#11       1   0       1   0       1   0   1       1   0             
#12       1   0       1   0       1   0   1       1   0             
#13       1   0       1   0       1   0   1       1   0             
#14       1   0       1   0       1   0   1       1   0             
#15       1   0       1   0       1   0   1       1   0             
#16       1   0       1   0       1   0   1       1   0             
#17       1   0       1   0       1   0   1       1   0             
#18       1   0       1   0       1   0   1       1   0             
#19       1   0       1   0       1   0   1       1   0             
FPSR  N   Z   C   V  QC  IDC IXC UFC OFC DZC IOC        SVCR ZA  SM 
#0    0   0   0   0   0   0   0   0   0   0   0         #0    -   - 
#1    0   0   0   0   0   0   0   0   0   0   0         #1    -   - 
#2    0   0   0   0   0   0   0   0   0   0   0         #2    -   - 
#3    0   0   0   0   0   0   0   0   0   0   0         #3    -   - 
#4    0   0   0   0   0   0   0   0   0   0   0         #4    -   - 
#5    0   0   0   0   0   0   0   0   0   0   0         #5    -   - 
#6    0   0   0   0   0   0   0   0   0   0   0         #6    -   - 
#7    0   0   0   0   0   0   0   0   0   0   0         #7    -   - 
#8    0   0   0   0   0   0   0   0   0   0   0         #8    -   - 
#9    0   0   0   0   0   0   0   0   0   0   0         #9    -   - 
#10   0   0   0   0   0   0   0   0   0   0   0         #10   -   - 
#11   0   0   0   0   0   0   0   0   0   0   0         #11   -   - 
#12   0   0   0   0   0   0   0   0   0   0   0         #12   -   - 
#13   0   0   0   0   0   0   0   0   0   0   0         #13   -   - 
#14   0   0   0   0   0   0   0   0   0   0   0         #14   -   - 
#15   0   0   0   0   0   0   0   0   0   0   0         #15   -   - 
#16   0   0   0   0   0   0   0   0   0   0   0         #16   -   - 
#17   0   0   0   0   0   0   0   0   0   0   0         #17   -   - 
#18   0   0   0   0   0   0   0   0   0   0   0         #18   -   - 
#19   0   0   0   0   0   0   0   0   0   0   0         #19   -   - 
FPCR AHP DN  FZ  RM  FZH    ACR  TCP TAM POR TTA SME FP  ZEN   RES  
#0    0   0   0   0   0     #0    0   0   0   0   0   3   3   0   0 
#1    0   0   0   0   0     #1    0   0   0   0   0   3   3   0   0 
#2    0   0   0   0   0     #2    0   0   0   0   0   3   3   0   0 
#3    0   0   0   0   0     #3    0   0   0   0   0   3   1   0   0 
#4    0   0   0   0   0     #4    0   0   0   0   0   3   3   0   0 
#5    0   0   0   0   0     #5    0   0   0   0   0   3   1   0   0 
#6    0   0   0   0   0     #6    0   0   0   0   0   3   1   0   0 
#7    0   0   0   0   0     #7    0   0   0   0   0   3   3   0   0 
#8    0   0   0   0   0     #8    0   0   0   0   0   3   3   0   0 
#9    0   0   0   0   0     #9    0   0   0   0   0   3   1   0   0 
#10   0   0   0   0   0     #10   0   0   0   0   0   3   3   0   0 
#11   0   0   0   0   0     #11   0   0   0   0   0   3   1   0   0 
#12   0   0   0   0   0     #12   0   0   0   0   0   3   1   0   0 
#13   0   0   0   0   0     #13   0   0   0   0   0   3   3   0   0 
#14   0   0   0   0   0     #14   0   0   0   0   0   3   3   0   0 
#15   0   0   0   0   0     #15   0   0   0   0   0   3   3   0   0 
#16   0   0   0   0   0     #16   0   0   0   0   0   3   3   0   0 
#17   0   0   0   0   0     #17   0   0   0   0   0   3   3   0   0 
#18   0   0   0   0   0     #18   0   0   0   0   0   3   1   0   0 
#19   0   0   0   0   0     #19   0   0   0   0   0   3   3   0   0 

Linux:                                                                          
|- Release                                                  [6.17.0-1021-nvidia]
|- Version         [#21-Ubuntu SMP PREEMPT_DYNAMIC Wed May 27 19:14:05 UTC 2026]
|- Machine                                                             [aarch64]
Memory:                                                                         
|- Total RAM                                                        125442420 KB
|- Shared RAM                                                            2016 KB
|- Free RAM                                                         122584856 KB
|- Buffer RAM                                                          127284 KB
|- Total High                                                               0 KB
|- Free High                                                                0 KB
Clock Source                                                  <arch_sys_counter>
CPU-Freq driver                                               [    cppc_cpufreq]
Governor                                                      [       schedutil]
CPU-Idle driver                                               [       acpi_idle]
|- Idle Limit                                                 [           LPI-3]
   |- State       LPI-0   LPI-1   LPI-2   LPI-3                                 
   |-           CoreIdl CoreIdl CoreIdl CoreIdl                                 
   |- Power           0       0       0       0                                 
   |- Latency         0      42     231     433                                 
   |- Residency       0    1930    2542    2542

@cyring

cyring commented Jul 18, 2026

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1000015244

@cyring

cyring commented Jul 21, 2026

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CPPC revision-2

2026-07-21-063538_644x676_scrot

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