Daniel Estévez daniestevez

daniestevez / hydra_t.grc

Created February 6, 2025 12:12

HYDRA-T decoder

daniestevez / measure_packets_in_socket.py

Last active December 16, 2024 08:09

Testing UNIX domain socket sizes

	#!/usr/bin/env python3

	import argparse
	import os
	import socket


	def parse_args():
	parser = argparse.ArgumentParser()
	parser.add_argument(

daniestevez / last_chunk.grc

Created January 14, 2024 08:18

Mistery FSK signal demodulator

daniestevez / tea.v

Created July 13, 2023 09:43

Verilog implementation of the Tiny Encryption Algorithm

	//
	// Copyright (c) 2021 - Daniel Estevez <[email protected]>
	//
	// TEA
	//
	// Verilog implementation of the Tiny Encryption Algorithm
	//

	`timescale 1ns / 1ps
	`default_nettype none

daniestevez / euclid.grc

Created July 1, 2023 21:44

EUCLID GNU Radio decoder

daniestevez / euclid.script

Created July 1, 2023 20:47

EUCLID GMAT

	%General Mission Analysis Tool(GMAT) Script
	%Created: 2023-07-01 22:42:05


	%----------------------------------------
	%---------- Spacecraft
	%----------------------------------------

	Create Spacecraft Euclid;
	GMAT Euclid.DateFormat = UTCGregorian;

daniestevez / gr_affinity_bug.py

Created February 28, 2023 17:21

Test script for GNU Radio bug: Setting processor affinity of hier_block2 with message ports segfaults

	#!/usr/bin/env python3

	from gnuradio import gr, blocks
	import pmt

	import argparse
	import signal
	import sys

daniestevez / ad9361_overclock.c

Last active February 19, 2023 20:14

AD9361 overclock snippet

	/// Rx Enable and Filter Control register:
	/// - Rx Enable = 1
	/// The ad9361_en_dis_rx function sets this bit. This bit
	/// determines if the receiver is enabled. Setting the bit enables the
	/// receiver signal path. Clearing the bit disables the receiver.
	/// - RHB3 Enable and Decimation[1:0] = 0b01
	/// See note in 0x002[D5:D4]. These bits set the decimation of the
	/// first filtering stage after the ADC per Table 4.
	/// 00 Decimate by 1, no filtering
	/// 01 Decimate by 2 (half-band filter)

daniestevez / ring_oscillator.json

Created February 12, 2023 09:22

SiliWiz designs

	{
	"version": 1,
	"app": "siliwiz",
	"timestamp": 1676193636,
	"rects": [
	{ "x": 14.4, "y": 2, "height": 390, "width": 382, "layer": "p substrate" },
	{ "x": 17.4, "y": 4, "height": 31, "width": 366, "layer": "n well" },
	{ "x": 18.4, "y": 262, "height": 30, "width": 368, "layer": "n well" },
	{ "x": 51.4, "y": 44, "height": 14, "width": 33, "layer": "n diffusion" },
	{ "x": 334.4, "y": 42, "height": 14, "width": 39, "layer": "n diffusion" },

daniestevez / recording_selection.txt

Created January 5, 2023 15:33

Selection of CAMRAS Artemis I Orion IQ recordings