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October 10, 2024 04:23
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| 1c:00.0 Processing accelerators: Advanced Micro Devices, Inc. [AMD/ATI] Aqua Vanjaram [Instinct MI300X] | |
| Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] Aqua Vanjaram [Instinct MI300X] | |
| Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ | |
| Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- | |
| Latency: 0 | |
| Interrupt: pin A routed to IRQ 17 | |
| NUMA node: 0 | |
| IOMMU group: 61 | |
| Region 0: Memory at 218000000000 (64-bit, prefetchable) [size=256G] | |
| Region 2: Memory at 21c000200000 (64-bit, prefetchable) [size=2M] | |
| Region 5: Memory at 96200000 (32-bit, non-prefetchable) [size=2M] | |
| Expansion ROM at <ignored> [disabled] | |
| Capabilities: [48] Vendor Specific Information: Len=08 <?> | |
| Capabilities: [50] Power Management version 3 | |
| Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold+) | |
| Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- | |
| Capabilities: [64] Express (v2) Endpoint, MSI 00 | |
| DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 unlimited | |
| ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W | |
| DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+ | |
| RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ | |
| MaxPayload 256 bytes, MaxReadReq 4096 bytes | |
| DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- | |
| LnkCap: Port #0, Speed 32GT/s, Width x16, ASPM L1, Exit Latency L1 <1us | |
| ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ | |
| LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk- | |
| ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- | |
| LnkSta: Speed 32GT/s (ok), Width x16 (ok) | |
| TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- | |
| DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR- | |
| 10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1 | |
| EmergencyPowerReduction Form Factor Dev Specific, EmergencyPowerReductionInit- | |
| FRS- TPHComp- ExtTPHComp- | |
| AtomicOpsCap: 32bit+ 64bit+ 128bitCAS- | |
| DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- LTR- OBFF Disabled, | |
| AtomicOpsCtl: ReqEn+ | |
| LnkCap2: Supported Link Speeds: 2.5-32GT/s, Crosslink- Retimer+ 2Retimers+ DRS- | |
| LnkCtl2: Target Link Speed: 32GT/s, EnterCompliance- SpeedDis- | |
| Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- | |
| Compliance De-emphasis: -6dB | |
| LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete- EqualizationPhase1- | |
| EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest- | |
| Retimer- 2Retimers- CrosslinkRes: unsupported | |
| Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ | |
| Address: 0000000000000000 Data: 0000 | |
| Capabilities: [c0] MSI-X: Enable+ Count=9 Masked- | |
| Vector table: BAR=5 offset=00042000 | |
| PBA: BAR=5 offset=00043000 | |
| Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> | |
| Capabilities: [150 v2] Advanced Error Reporting | |
| UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- | |
| UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt+ RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- | |
| UESvrt: DLP+ SDES+ TLP+ FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt- RxOF+ MalfTLP+ ECRC+ UnsupReq- ACSViol- | |
| CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- | |
| CEMsk: RxErr- BadTLP+ BadDLLP+ Rollover+ Timeout+ AdvNonFatalErr+ | |
| AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn- | |
| MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- | |
| HeaderLog: 00000000 00000000 00000000 00000000 | |
| Capabilities: [240 v1] Power Budgeting <?> | |
| Capabilities: [250 v1] Dynamic Power Allocation <?> | |
| Capabilities: [270 v1] Secondary PCI Express | |
| LnkCtl3: LnkEquIntrruptEn- PerformEqu- | |
| LaneErrStat: 0 | |
| Capabilities: [2c0 v1] Page Request Interface (PRI) | |
| PRICtl: Enable- Reset- | |
| PRISta: RF- UPRGI- Stopped+ | |
| Page Request Capacity: 00000100, Page Request Allocation: 00000000 | |
| Capabilities: [2d0 v1] Process Address Space ID (PASID) | |
| PASIDCap: Exec+ Priv+, Max PASID Width: 10 | |
| PASIDCtl: Enable- Exec- Priv- | |
| Capabilities: [328 v1] Alternative Routing-ID Interpretation (ARI) | |
| ARICap: MFVC- ACS-, Next Function: 0 | |
| ARICtl: MFVC- ACS-, Function Group: 0 | |
| Capabilities: [330 v1] Single Root I/O Virtualization (SR-IOV) | |
| IOVCap: Migration-, Interrupt Message Number: 000 | |
| IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+ | |
| IOVSta: Migration- | |
| Initial VFs: 1, Total VFs: 1, Number of VFs: 0, Function Dependency Link: 00 | |
| VF offset: 16, stride: 1, Device ID: 74b5 | |
| Supported Page Size: 00000553, System Page Size: 00000001 | |
| Region 0: Memory at 0000214000000000 (64-bit, prefetchable) | |
| Region 2: Memory at 000021c000000000 (64-bit, prefetchable) | |
| Region 5: Memory at 96000000 (32-bit, non-prefetchable) | |
| VF Migration: offset: 00000000, BIR: 0 | |
| Capabilities: [410 v1] Physical Layer 16.0 GT/s <?> | |
| Capabilities: [450 v1] Lane Margining at the Receiver <?> | |
| Capabilities: [500 v1] Extended Capability ID 0x2a | |
| Capabilities: [700 v1] Vendor Specific Information: ID=0002 Rev=6 Len=520 <?> | |
| Kernel driver in use: amdgpu | |
| Kernel modules: amdgpu |
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