My setup: Visionfive2 1.3b (JH7110)
Build spike with my patch to emulate JH7110: https://github.com/ganboing/riscv-isa-sim/tree/ganboing-jh7110-emu
Run spike with the following command line:
JH7110_BOOTMODE=sdcard ./spike -d -m0x1100000:0x2000,0x2a000000:0x10000 vf2-no-read-csr-7c1.rom.elf 2> spike.log > spike.out
This is how ROM interacts with CRG/IOMUX/OTP... The log is incomplete for sdcard boot, because I didn't implement a virtual sdcard controller, and the trace stopped there. What's interesting is the interaction with OTP. ROM uses the same timing configuration as the U-Boot driver, i.e, writing 0x2040b to reg[0] of OTP. ROM then reads OTP mem offset 0x84. Here, I emulate the OTP by returning 0xffffffff for all read requests, and I also simulate an OTP busy state by having a busy counter and decrement it for each poll from OTP_SR. After the first read, ROM won't read from OTP again before loading SPL from sdcard. It'll be interesting to see what ROM might do if the value returned is not 0xffffffff. Also ROM might read from OTP again once it finishes loading from sdcard (yet to figure out)
$ grep -C1 -F jh7110 spike.log
(spike) core 0: 0x000000002a000250 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_aon_iomux_t::load(reg_t, size_t, uint8_t*): returning 0 for EN_0
(spike) core 0: 0x000000002a000252 (0x00002781) c.addiw a5, 0
--
(spike) core 0: 0x000000002a000260 (0x0000c110) c.sw a2, 0(a0)
virtual bool jh7110_aon_iomux_t::store(reg_t, size_t, const uint8_t*): setting EN_0 to 1
(spike) core 0: 0x000000002a000262 (0x00008082) ret
--
(spike) core 0: 0x000000002a000250 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_aon_iomux_t::load(reg_t, size_t, uint8_t*): reading RGPIO0, returning 1
(spike) core 0: 0x000000002a000252 (0x00002781) c.addiw a5, 0
--
(spike) core 0: 0x000000002a000260 (0x0000c110) c.sw a2, 0(a0)
virtual bool jh7110_aon_iomux_t::store(reg_t, size_t, const uint8_t*): setting RGPIO0 to 1
(spike) core 0: 0x000000002a000262 (0x00008082) ret
--
(spike) core 0: 0x000000002a000250 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_aon_iomux_t::load(reg_t, size_t, uint8_t*): reading RGPIO1, returning 1
(spike) core 0: 0x000000002a000252 (0x00002781) c.addiw a5, 0
--
(spike) core 0: 0x000000002a000260 (0x0000c110) c.sw a2, 0(a0)
virtual bool jh7110_aon_iomux_t::store(reg_t, size_t, const uint8_t*): setting RGPIO1 to 1
(spike) core 0: 0x000000002a000262 (0x00008082) ret
--
(spike) core 0: 0x000000002a000250 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_sys_crg_t::load(reg_t, size_t, uint8_t*): reading APB0, returning 80000000
(spike) core 0: 0x000000002a000252 (0x00002781) c.addiw a5, 0
--
(spike) core 0: 0x000000002a000260 (0x0000c110) c.sw a2, 0(a0)
virtual bool jh7110_sys_crg_t::store(reg_t, size_t, const uint8_t*): setting APB0 to 80000000
(spike) core 0: 0x000000002a000262 (0x00008082) ret
--
(spike) core 0: 0x000000002a000250 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_sys_crg_t::load(reg_t, size_t, uint8_t*): reading UART0_CLK_APB, returning 80000000
(spike) core 0: 0x000000002a000252 (0x00002781) c.addiw a5, 0
--
(spike) core 0: 0x000000002a000260 (0x0000c110) c.sw a2, 0(a0)
virtual bool jh7110_sys_crg_t::store(reg_t, size_t, const uint8_t*): setting UART0_CLK_APB to 80000000
(spike) core 0: 0x000000002a000262 (0x00008082) ret
--
(spike) core 0: 0x000000002a000250 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_sys_crg_t::load(reg_t, size_t, uint8_t*): reading UART0_CLK_CORE, returning 80000000
(spike) core 0: 0x000000002a000252 (0x00002781) c.addiw a5, 0
--
(spike) core 0: 0x000000002a000260 (0x0000c110) c.sw a2, 0(a0)
virtual bool jh7110_sys_crg_t::store(reg_t, size_t, const uint8_t*): setting UART0_CLK_CORE to 80000000
(spike) core 0: 0x000000002a000262 (0x00008082) ret
--
(spike) core 0: 0x000000002a000268 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_sys_crg_t::load(reg_t, size_t, uint8_t*): reading SYSCRG_RESET_ASSERT2, returning ffffffff
(spike) core 0: 0x000000002a00026a (0x0007871b) sext.w a4, a5
--
(spike) core 0: 0x000000002a000274 (0x0000c11c) c.sw a5, 0(a0)
virtual bool jh7110_sys_crg_t::store(reg_t, size_t, const uint8_t*): deasserting U0_DW_UART_APB
virtual bool jh7110_sys_crg_t::store(reg_t, size_t, const uint8_t*): setting SYSCRG_RESET_ASSERT2 to fff7ffff
(spike) core 0: 0x000000002a000276 (0x00001582) c.slli a1, 32
--
(spike) core 0: 0x000000002a00027a (0x0000419c) c.lw a5, 0(a1)
virtual bool jh7110_sys_crg_t::load(reg_t, size_t, uint8_t*): reading SYSCRG_RESET_STATUS2, returning 80000
(spike) core 0: 0x000000002a00027c (0x00002781) c.addiw a5, 0
--
(spike) core 0: 0x000000002a000268 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_sys_crg_t::load(reg_t, size_t, uint8_t*): reading SYSCRG_RESET_ASSERT2, returning fff7ffff
(spike) core 0: 0x000000002a00026a (0x0007871b) sext.w a4, a5
--
(spike) core 0: 0x000000002a000274 (0x0000c11c) c.sw a5, 0(a0)
virtual bool jh7110_sys_crg_t::store(reg_t, size_t, const uint8_t*): deasserting U0_DW_UART_CORE
virtual bool jh7110_sys_crg_t::store(reg_t, size_t, const uint8_t*): setting SYSCRG_RESET_ASSERT2 to ffe7ffff
(spike) core 0: 0x000000002a000276 (0x00001582) c.slli a1, 32
--
(spike) core 0: 0x000000002a00027a (0x0000419c) c.lw a5, 0(a1)
virtual bool jh7110_sys_crg_t::load(reg_t, size_t, uint8_t*): reading SYSCRG_RESET_STATUS2, returning 180000
(spike) core 0: 0x000000002a00027c (0x00002781) c.addiw a5, 0
--
(spike) core 0: 0x000000002a002862 (0x00004198) c.lw a4, 0(a1)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading din3, returning b080000
(spike) core 0: 0x000000002a002864 (0x0025079b) addiw a5, a0, 2
--
(spike) core 0: 0x000000002a00287c (0x0000c19c) c.sw a5, 0(a1)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting din3 to b080000
(spike) core 0: 0x000000002a00287e (0x4025571b) sraiw a4, a0, 2
--
(spike) core 0: 0x000000002a0028ca (0x0000431c) c.lw a5, 0(a4)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading den1, returning 10001
(spike) core 0: 0x000000002a0028cc (0x00a696bb) sllw a3, a3, a0
--
(spike) core 0: 0x000000002a0028de (0x0000c314) c.sw a3, 0(a4)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting den1 to 10001
(spike) core 0: 0x000000002a0028e0 (0x00004501) c.li a0, 0
--
(spike) core 0: 0x000000002a0028a0 (0x0000438c) c.lw a1, 0(a5)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading dout1, returning 1400
(spike) core 0: 0x000000002a0028a2 (0x00a6163b) sllw a2, a2, a0
--
(spike) core 0: 0x000000002a0028b6 (0x0000c390) c.sw a2, 0(a5)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting dout1 to 1400
(spike) core 0: 0x000000002a0028b8 (0x000067c1) c.lui a5, 0x10
--
(spike) core 0: 0x000000002a0028ca (0x0000431c) c.lw a5, 0(a4)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading den1, returning 10001
(spike) core 0: 0x000000002a0028cc (0x00a696bb) sllw a3, a3, a0
--
(spike) core 0: 0x000000002a0028de (0x0000c314) c.sw a3, 0(a4)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting den1 to 10001
(spike) core 0: 0x000000002a0028e0 (0x00004501) c.li a0, 0
--
(spike) core 0: 0x000000002a000250 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_aon_crg_t::load(reg_t, size_t, uint8_t*): reading OTPC_CLK_APB, returning 80000000
(spike) core 0: 0x000000002a000252 (0x00002781) c.addiw a5, 0
--
(spike) core 0: 0x000000002a000260 (0x0000c110) c.sw a2, 0(a0)
virtual bool jh7110_aon_crg_t::store(reg_t, size_t, const uint8_t*): setting OTPC_CLK_APB to 80000000
(spike) core 0: 0x000000002a000262 (0x00008082) ret
--
(spike) core 0: 0x000000002a00495e (0x0000c01c) c.sw a5, 0(s0)
virtual bool jh7110_otp_t::store(reg_t, size_t, const uint8_t*): ignoring write to OTP_CFG, val=2040b
(spike) core 0: 0x000000002a004960 (0x0c800513) li a0, 200
--
(spike) core 0: 0x000000002a0048e0 (0x0000c448) c.sw a0, 12(s0)
virtual bool jh7110_otp_t::store(reg_t, size_t, const uint8_t*): setting OTP_OPR to 1, ignored. setting busy cout 3
(spike) core 0: 0x000000002a0048e2 (0x0000441c) c.lw a5, 8(s0)
virtual bool jh7110_otp_t::load(reg_t, size_t, uint8_t*): returning 80000000 for OTP_SR, busy count=2
(spike) core 0: 0x000000002a0048e4 (0x02079713) slli a4, a5, 32
--
(spike) core 0: 0x000000002a0048f4 (0x0000441c) c.lw a5, 8(s0)
virtual bool jh7110_otp_t::load(reg_t, size_t, uint8_t*): returning 80000000 for OTP_SR, busy count=1
(spike) core 0: 0x000000002a0048f6 (0x02079713) slli a4, a5, 32
--
(spike) core 0: 0x000000002a0048f4 (0x0000441c) c.lw a5, 8(s0)
virtual bool jh7110_otp_t::load(reg_t, size_t, uint8_t*): returning 80000000 for OTP_SR, busy count=0
(spike) core 0: 0x000000002a0048f6 (0x02079713) slli a4, a5, 32
--
(spike) core 0: 0x000000002a0048f4 (0x0000441c) c.lw a5, 8(s0)
virtual bool jh7110_otp_t::load(reg_t, size_t, uint8_t*): returning 0 for OTP_SR, busy count=0
(spike) core 0: 0x000000002a0048f6 (0x02079713) slli a4, a5, 32
--
(spike) core 0: 0x000000002a0049b4 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_otp_t::load(reg_t, size_t, uint8_t*): returning ffffffff for all OTP read, off=84
(spike) core 0: 0x000000002a0049b6 (0x00f92023) sw a5, 0(s2)
(spike) core 0: 0x000000002a0049ba (0x0000449c) c.lw a5, 8(s1)
virtual bool jh7110_otp_t::load(reg_t, size_t, uint8_t*): returning 0 for OTP_SR, busy count=0
(spike) core 0: 0x000000002a0049bc (0x02079713) slli a4, a5, 32
--
(spike) core 0: 0x000000002a0048e0 (0x0000c448) c.sw a0, 12(s0)
virtual bool jh7110_otp_t::store(reg_t, size_t, const uint8_t*): setting OTP_OPR to 0, ignored. setting busy cout 3
(spike) core 0: 0x000000002a0048e2 (0x0000441c) c.lw a5, 8(s0)
virtual bool jh7110_otp_t::load(reg_t, size_t, uint8_t*): returning 80000000 for OTP_SR, busy count=2
(spike) core 0: 0x000000002a0048e4 (0x02079713) slli a4, a5, 32
--
(spike) core 0: 0x000000002a0048f4 (0x0000441c) c.lw a5, 8(s0)
virtual bool jh7110_otp_t::load(reg_t, size_t, uint8_t*): returning 80000000 for OTP_SR, busy count=1
(spike) core 0: 0x000000002a0048f6 (0x02079713) slli a4, a5, 32
--
(spike) core 0: 0x000000002a0048f4 (0x0000441c) c.lw a5, 8(s0)
virtual bool jh7110_otp_t::load(reg_t, size_t, uint8_t*): returning 80000000 for OTP_SR, busy count=0
(spike) core 0: 0x000000002a0048f6 (0x02079713) slli a4, a5, 32
--
(spike) core 0: 0x000000002a0048f4 (0x0000441c) c.lw a5, 8(s0)
virtual bool jh7110_otp_t::load(reg_t, size_t, uint8_t*): returning 0 for OTP_SR, busy count=0
(spike) core 0: 0x000000002a0048f6 (0x02079713) slli a4, a5, 32
--
(spike) core 0: 0x000000002a000240 (0x00004108) c.lw a0, 0(a0)
virtual bool jh7110_aon_iomux_t::load(reg_t, size_t, uint8_t*): reading boot mode 5
(spike) core 0: 0x000000002a000242 (0x00002501) c.addiw a0, 0
--
(spike) core 0: 0x000000002a0028a0 (0x0000438c) c.lw a1, 0(a5)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading dout2, returning 15000000
(spike) core 0: 0x000000002a0028a2 (0x00a6163b) sllw a2, a2, a0
--
(spike) core 0: 0x000000002a0028b6 (0x0000c390) c.sw a2, 0(a5)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting dout2 to 15370000
(spike) core 0: 0x000000002a0028b8 (0x000067c1) c.lui a5, 0x10
--
(spike) core 0: 0x000000002a0028ca (0x0000431c) c.lw a5, 0(a4)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading den2, returning 7010100
(spike) core 0: 0x000000002a0028cc (0x00a696bb) sllw a3, a3, a0
--
(spike) core 0: 0x000000002a0028de (0x0000c314) c.sw a3, 0(a4)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting den2 to 7000100
(spike) core 0: 0x000000002a0028e0 (0x00004501) c.li a0, 0
--
(spike) core 0: 0x000000002a002862 (0x00004198) c.lw a4, 0(a1)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading din11, returning 0
(spike) core 0: 0x000000002a002864 (0x0025079b) addiw a5, a0, 2
--
(spike) core 0: 0x000000002a00287c (0x0000c19c) c.sw a5, 0(a1)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting din11 to b
(spike) core 0: 0x000000002a00287e (0x4025571b) sraiw a4, a0, 2
--
(spike) core 0: 0x000000002a0028a0 (0x0000438c) c.lw a1, 0(a5)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading dout2, returning 15370000
(spike) core 0: 0x000000002a0028a2 (0x00a6163b) sllw a2, a2, a0
--
(spike) core 0: 0x000000002a0028b6 (0x0000c390) c.sw a2, 0(a5)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting dout2 to 15373900
(spike) core 0: 0x000000002a0028b8 (0x000067c1) c.lui a5, 0x10
--
(spike) core 0: 0x000000002a0028ca (0x0000431c) c.lw a5, 0(a4)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading den2, returning 7000100
(spike) core 0: 0x000000002a0028cc (0x00a696bb) sllw a3, a3, a0
--
(spike) core 0: 0x000000002a0028de (0x0000c314) c.sw a3, 0(a4)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting den2 to 7001300
(spike) core 0: 0x000000002a0028e0 (0x00004501) c.li a0, 0
--
(spike) core 0: 0x000000002a002862 (0x00004198) c.lw a4, 0(a1)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading din11, returning b
(spike) core 0: 0x000000002a002864 (0x0025079b) addiw a5, a0, 2
--
(spike) core 0: 0x000000002a00287c (0x0000c19c) c.sw a5, 0(a1)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting din11 to d0b
(spike) core 0: 0x000000002a00287e (0x4025571b) sraiw a4, a0, 2
--
(spike) core 0: 0x000000002a0028a0 (0x0000438c) c.lw a1, 0(a5)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading dout2, returning 15373900
(spike) core 0: 0x000000002a0028a2 (0x00a6163b) sllw a2, a2, a0
--
(spike) core 0: 0x000000002a0028b6 (0x0000c390) c.sw a2, 0(a5)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting dout2 to 3a373900
(spike) core 0: 0x000000002a0028b8 (0x000067c1) c.lui a5, 0x10
--
(spike) core 0: 0x000000002a0028ca (0x0000431c) c.lw a5, 0(a4)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading den2, returning 7001300
(spike) core 0: 0x000000002a0028cc (0x00a696bb) sllw a3, a3, a0
--
(spike) core 0: 0x000000002a0028de (0x0000c314) c.sw a3, 0(a4)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting den2 to 14001300
(spike) core 0: 0x000000002a0028e0 (0x00004501) c.li a0, 0
--
(spike) core 0: 0x000000002a002862 (0x00004198) c.lw a4, 0(a1)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading din11, returning d0b
(spike) core 0: 0x000000002a002864 (0x0025079b) addiw a5, a0, 2
--
(spike) core 0: 0x000000002a00287c (0x0000c19c) c.sw a5, 0(a1)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting din11 to e0d0b
(spike) core 0: 0x000000002a00287e (0x4025571b) sraiw a4, a0, 2
--
(spike) core 0: 0x000000002a0028a0 (0x0000438c) c.lw a1, 0(a5)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading dout3, returning 0
(spike) core 0: 0x000000002a0028a2 (0x00a6163b) sllw a2, a2, a0
--
(spike) core 0: 0x000000002a0028b6 (0x0000c390) c.sw a2, 0(a5)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting dout3 to 3b
(spike) core 0: 0x000000002a0028b8 (0x000067c1) c.lui a5, 0x10
--
(spike) core 0: 0x000000002a0028ca (0x0000431c) c.lw a5, 0(a4)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading den3, returning 101
(spike) core 0: 0x000000002a0028cc (0x00a696bb) sllw a3, a3, a0
--
(spike) core 0: 0x000000002a0028de (0x0000c314) c.sw a3, 0(a4)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting den3 to 115
(spike) core 0: 0x000000002a0028e0 (0x00004501) c.li a0, 0
--
(spike) core 0: 0x000000002a002862 (0x00004198) c.lw a4, 0(a1)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading din11, returning e0d0b
(spike) core 0: 0x000000002a002864 (0x0025079b) addiw a5, a0, 2
--
(spike) core 0: 0x000000002a00287c (0x0000c19c) c.sw a5, 0(a1)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting din11 to 90e0d0b
(spike) core 0: 0x000000002a00287e (0x4025571b) sraiw a4, a0, 2
--
(spike) core 0: 0x000000002a0028a0 (0x0000438c) c.lw a1, 0(a5)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading dout1, returning 1400
(spike) core 0: 0x000000002a0028a2 (0x00a6163b) sllw a2, a2, a0
--
(spike) core 0: 0x000000002a0028b6 (0x0000c390) c.sw a2, 0(a5)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting dout1 to 3c001400
(spike) core 0: 0x000000002a0028b8 (0x000067c1) c.lui a5, 0x10
--
(spike) core 0: 0x000000002a0028ca (0x0000431c) c.lw a5, 0(a4)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading den1, returning 10001
(spike) core 0: 0x000000002a0028cc (0x00a696bb) sllw a3, a3, a0
--
(spike) core 0: 0x000000002a0028de (0x0000c314) c.sw a3, 0(a4)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting den1 to 16010001
(spike) core 0: 0x000000002a0028e0 (0x00004501) c.li a0, 0
--
(spike) core 0: 0x000000002a002862 (0x00004198) c.lw a4, 0(a1)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading din12, returning 0
(spike) core 0: 0x000000002a002864 (0x0025079b) addiw a5, a0, 2
--
(spike) core 0: 0x000000002a00287c (0x0000c19c) c.sw a5, 0(a1)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting din12 to a
(spike) core 0: 0x000000002a00287e (0x4025571b) sraiw a4, a0, 2
--
(spike) core 0: 0x000000002a0028a0 (0x0000438c) c.lw a1, 0(a5)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading dout2, returning 3a373900
(spike) core 0: 0x000000002a0028a2 (0x00a6163b) sllw a2, a2, a0
--
(spike) core 0: 0x000000002a0028b6 (0x0000c390) c.sw a2, 0(a5)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting dout2 to 3a37393d
(spike) core 0: 0x000000002a0028b8 (0x000067c1) c.lui a5, 0x10
--
(spike) core 0: 0x000000002a0028ca (0x0000431c) c.lw a5, 0(a4)
virtual bool jh7110_sys_iomux_t::load(reg_t, size_t, uint8_t*): reading den2, returning 14001300
(spike) core 0: 0x000000002a0028cc (0x00a696bb) sllw a3, a3, a0
--
(spike) core 0: 0x000000002a0028de (0x0000c314) c.sw a3, 0(a4)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): setting den2 to 14001317
(spike) core 0: 0x000000002a0028e0 (0x00004501) c.li a0, 0
--
(spike) core 0: 0x000000002a000250 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_sys_crg_t::load(reg_t, size_t, uint8_t*): reading AHB0, returning 80000000
(spike) core 0: 0x000000002a000252 (0x00002781) c.addiw a5, 0
--
(spike) core 0: 0x000000002a000260 (0x0000c110) c.sw a2, 0(a0)
virtual bool jh7110_sys_crg_t::store(reg_t, size_t, const uint8_t*): setting AHB0 to 80000000
(spike) core 0: 0x000000002a000262 (0x00008082) ret
--
(spike) core 0: 0x000000002a000250 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_sys_crg_t::load(reg_t, size_t, uint8_t*): reading SDIO1_CLK_AHB, returning 80000000
(spike) core 0: 0x000000002a000252 (0x00002781) c.addiw a5, 0
--
(spike) core 0: 0x000000002a000260 (0x0000c110) c.sw a2, 0(a0)
virtual bool jh7110_sys_crg_t::store(reg_t, size_t, const uint8_t*): setting SDIO1_CLK_AHB to 80000000
(spike) core 0: 0x000000002a000262 (0x00008082) ret
--
(spike) core 0: 0x000000002a000250 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_sys_crg_t::load(reg_t, size_t, uint8_t*): reading SDIO1_CLK_SDCARD, returning 80000002
(spike) core 0: 0x000000002a000252 (0x00002781) c.addiw a5, 0
--
(spike) core 0: 0x000000002a000260 (0x0000c110) c.sw a2, 0(a0)
virtual bool jh7110_sys_crg_t::store(reg_t, size_t, const uint8_t*): setting SDIO1_CLK_SDCARD to 80000002
(spike) core 0: 0x000000002a000262 (0x00008082) ret
--
(spike) core 0: 0x000000002a000268 (0x0000411c) c.lw a5, 0(a0)
virtual bool jh7110_sys_crg_t::load(reg_t, size_t, uint8_t*): reading SYSCRG_RESET_ASSERT2, returning ffe7ffff
(spike) core 0: 0x000000002a00026a (0x0007871b) sext.w a4, a5
--
(spike) core 0: 0x000000002a000274 (0x0000c11c) c.sw a5, 0(a0)
virtual bool jh7110_sys_crg_t::store(reg_t, size_t, const uint8_t*): deasserting U1_DW_SDIO_AHB
virtual bool jh7110_sys_crg_t::store(reg_t, size_t, const uint8_t*): setting SYSCRG_RESET_ASSERT2 to ffe7fffd
(spike) core 0: 0x000000002a000276 (0x00001582) c.slli a1, 32
--
(spike) core 0: 0x000000002a00027a (0x0000419c) c.lw a5, 0(a1)
virtual bool jh7110_sys_crg_t::load(reg_t, size_t, uint8_t*): reading SYSCRG_RESET_STATUS2, returning 180002
(spike) core 0: 0x000000002a00027c (0x00002781) c.addiw a5, 0
--
(spike) core 0: 0x000000002a003c74 (0x0000c3d8) c.sw a4, 4(a5)
virtual bool jh7110_sys_iomux_t::store(reg_t, size_t, const uint8_t*): unknown write of jh7110_sys_iomux, off=2fe0004
Appendix:
[vf2.rom] Original ROM dump from visionfive2
[vf2.rom.elf] Loadable ELF for spike
[vf2-no-read-csr-7c1.rom] Patched version of ROM that removed csrw 0x7c1,8