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hurrian/0001-Add-mxl371x-MoCA-2.5-PHY-driver.patch

Created November 15, 2024 05:10
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MXL371x MoCA 2.5 PHY driver for Verizon CR1000A (incomplete)
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0001-Add-mxl371x-MoCA-2.5-PHY-driver.patch
From c1e9572cf8b213988d2a53a0f22c4d220df25777 Mon Sep 17 00:00:00 2001
From: Kenneth Kasilag <kenneth@kasilag.me>
Date: Fri, 15 Nov 2024 04:01:57 +0000
Subject: [PATCH] Add mxl371x MoCA 2.5 PHY driver
---
drivers/net/phy/Kconfig | 5 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/mxl371x/Makefile | 8 +
drivers/net/phy/mxl371x/lib/ClnkIoCtl.h | 298 +
drivers/net/phy/mxl371x/lib/ClnkLibApi.h | 2588 ++++++++
drivers/net/phy/mxl371x/lib/ClnkLibDev.h | 85 +
drivers/net/phy/mxl371x/lib/HostCfgLib.h | 545 ++
drivers/net/phy/mxl371x/mxl_data_types.h | 79 +
drivers/net/phy/mxl371x/mxl_moca_config.h | 404 ++
.../net/phy/mxl371x/mxl_moca_dev_main_linux.c | 1199 ++++
.../net/phy/mxl371x/mxl_moca_host_version.h | 59 +
drivers/net/phy/mxl371x/mxl_moca_ioctl_cmd.h | 103 +
drivers/net/phy/mxl371x/mxl_moca_osal.h | 220 +
drivers/net/phy/mxl371x/mxl_moca_osal_linux.c | 2830 ++++++++
drivers/net/phy/mxl371x/mxl_moca_osal_linux.h | 228 +
drivers/net/phy/mxl371x/mxl_moca_osal_pcie.c | 5677 +++++++++++++++++
drivers/net/phy/mxl371x/mxl_moca_osal_pcie.h | 722 +++
drivers/net/phy/mxl371x/mxl_moca_soc_cmd.h | 3050 +++++++++
18 files changed, 18101 insertions(+)
create mode 100644 drivers/net/phy/mxl371x/Makefile
create mode 100644 drivers/net/phy/mxl371x/lib/ClnkIoCtl.h
create mode 100644 drivers/net/phy/mxl371x/lib/ClnkLibApi.h
create mode 100644 drivers/net/phy/mxl371x/lib/ClnkLibDev.h
create mode 100644 drivers/net/phy/mxl371x/lib/HostCfgLib.h
create mode 100644 drivers/net/phy/mxl371x/mxl_data_types.h
create mode 100644 drivers/net/phy/mxl371x/mxl_moca_config.h
create mode 100644 drivers/net/phy/mxl371x/mxl_moca_dev_main_linux.c
create mode 100644 drivers/net/phy/mxl371x/mxl_moca_host_version.h
create mode 100644 drivers/net/phy/mxl371x/mxl_moca_ioctl_cmd.h
create mode 100644 drivers/net/phy/mxl371x/mxl_moca_osal.h
create mode 100644 drivers/net/phy/mxl371x/mxl_moca_osal_linux.c
create mode 100644 drivers/net/phy/mxl371x/mxl_moca_osal_linux.h
create mode 100644 drivers/net/phy/mxl371x/mxl_moca_osal_pcie.c
create mode 100644 drivers/net/phy/mxl371x/mxl_moca_osal_pcie.h
create mode 100644 drivers/net/phy/mxl371x/mxl_moca_soc_cmd.h
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 107880d13d21..5d401b87d6da 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -237,6 +237,11 @@ config MAXLINEAR_GPHY
Support for the Maxlinear GPY115, GPY211, GPY212, GPY215,
GPY241, GPY245 PHYs.
+config MXL371X
+ tristate "Maxlinear MoCA PHY"
+ help
+ Support for the Maxlinear MXL371x series of MoCA 2.5 PHYs.
+
config MEDIATEK_GE_PHY
tristate "MediaTek Gigabit Ethernet PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index c945ed9bd14b..ced2e367b9f1 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
obj-$(CONFIG_MARVELL_88Q2XXX_PHY) += marvell-88q2xxx.o
obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
+obj-$(CONFIG_MXL371X) += mxl371x/
obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
diff --git a/drivers/net/phy/mxl371x/Makefile b/drivers/net/phy/mxl371x/Makefile
new file mode 100644
index 000000000000..7091ec83d086
--- /dev/null
+++ b/drivers/net/phy/mxl371x/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for MaxLinear MXL371X MoCA 2.5 PHY
+
+obj-$(CONFIG_MXL371X) := mxl_moca_ctrl.o
+mxl_moca_ctrl-objs := mxl_moca_dev_main_linux.o
+mxl_moca_ctrl-objs += mxl_moca_osal_linux.o
+mxl_moca_ctrl-objs += mxl_moca_osal_pcie.o
diff --git a/drivers/net/phy/mxl371x/lib/ClnkIoCtl.h b/drivers/net/phy/mxl371x/lib/ClnkIoCtl.h
new file mode 100644
index 000000000000..a0ecf289c752
--- /dev/null
+++ b/drivers/net/phy/mxl371x/lib/ClnkIoCtl.h
@@ -0,0 +1,298 @@
+/*****************************************************************************************
+ * FILE NAME : ClnkIoCtl.h
+ *
+ *
+ * DATE CREATED : Oct/11/2016
+ * LAST MODIFIED :
+ *
+ * DESCRIPTION : c.LINK Library I/O API(Internal) header file.
+ *
+ *
+ *****************************************************************************************
+ * MaxLinear, Inc. retains all right, title and interest (including all intellectual
+ * property rights) in and to this computer program, which is protected by applicable
+ * intellectual property laws. Unless you have obtained a separate written license from
+ * MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., you are not authorized
+ * to utilize all or a part of this computer program for any purpose (including
+ * reproduction, distribution, modification, and compilation into object code), and you
+ * must immediately destroy or return all copies of this computer program. If you are
+ * licensed by MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., your rights
+ * to utilize this computer program are limited by the terms of that license.
+ *
+ * This computer program contains trade secrets owned by MaxLinear, Inc. and, unless
+ * authorized by MaxLinear, Inc. in writing, you agree to maintain the confidentiality
+ * of this computer program and related information and to not disclose this computer
+ * program and related information to any other person or entity.
+ *
+ * Misuse of this computer program or any information contained in it may results in
+ * violations of applicable law. MaxLinear, Inc. vigorously enforces its copyright,
+ * trade secret, patent, contractual, and other legal rights.
+ *
+ * THIS COMPUTER PROGRAM IS PROVIDED "AS IS" WITHOUT ANY WARRANTIES, AND
+ * MAXLINEAR, INC.EXPRESSLY DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE
+ * WARRANTIES OF MERCHANTIBILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND
+ * NONINFRINGEMENT.
+ *
+ ****************************************************************************************
+ * Copyright (c) 2016, MaxLinear, Inc.
+ ****************************************************************************************/
+
+#ifndef __CLNK_API_LIO_H__
+#define __CLNK_API_LIO_H__
+
+
+/*******************************************************************************
+ * Includes
+ ******************************************************************************/
+#include "mxl_data_types.h"
+#include "mxl_moca_config.h"
+#include "ClnkLibApi.h"
+#ifdef __linux__
+#include "ClnkAppOsalLnx.h"
+#endif
+#include "mxl_moca_soc_cmd.h"
+
+
+/*******************************************************************************
+ * Constants
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Macros
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Types
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Public/Private Data
+ ******************************************************************************/
+
+/*!
+ * \brief c.LINK Library I/O Structure
+ */
+typedef struct
+{
+ uint32_t *in;
+ uint32_t in_len;
+ uint32_t *out;
+ uint32_t out_len;
+} ClnkLio_t;
+
+/*!
+ * \brief c.LINK Library NetIO Structure
+ */
+typedef struct
+{
+ uint32_t magic;
+ uint32_t version;
+ uint32_t cmd;
+ uint32_t transid;
+ uint32_t in_len;
+ uint32_t out_len;
+ uint32_t status;
+ uint32_t reserved[5];
+} ClnkLioNetio_t;
+
+/*******************************************************************************
+ * Public/Private Functions
+ ******************************************************************************/
+int32_t ClnkLio_Open(char *iface, const char *drvname);
+int32_t ClnkLio_Close(char *iface);
+int32_t ClnkLio_SendCmd(ClnkLib_Handle_t *pClnkIf, int cmd, ClnkLio_t *io, int32_t expBytes);
+
+/* 1 argument (typically either "clear stats" or "node ID"); some output struct */
+#define CLNK_CTL_GET_C(ctx, cmd, out_type, outv, code) \
+ { \
+ ClnkLio_t io; \
+ int tmp = 0;\
+ if (outv == NULL) \
+ return CLNK_ERR; \
+ io.in = 0;\
+ io.in_len = 0; \
+ io.out = (uint32_t *) outv; \
+ io.out_len = sizeof(out_type); \
+ tmp = ClnkLio_SendCmd(ctx, cmd, &io, -1); \
+ code;\
+ return tmp;\
+ }
+
+
+/* 1 argument (typically either "clear stats" or "node ID"); some output struct */
+#define CLNK_CTL_GET_1(ctx, cmd, out_type, outv, inv) \
+ { \
+ ClnkLio_t io; \
+ if (outv == NULL) \
+ return CLNK_ERR; \
+ io.in = (uint32_t *)(unsigned long) inv; \
+ io.in_len = 0; \
+ io.out = (uint32_t *) outv; \
+ io.out_len = sizeof(out_type); \
+ return(ClnkLio_SendCmd(ctx, cmd, &io, -1)); \
+ }
+
+/* null input argument ; some output struct */
+#define CLNK_CTL_GET_0(ctx, cmd, out_type, outv) \
+ { \
+ ClnkLio_t io; \
+ if (outv == NULL) \
+ return CLNK_ERR; \
+ io.in = NULL; \
+ io.in_len = 0; \
+ io.out = (uint32_t *) outv; \
+ io.out_len = sizeof(out_type); \
+ return(ClnkLio_SendCmd(ctx, cmd, &io, -1)); \
+ }
+
+/* some input struct argument ; null output value */
+#define CLNK_CTL_SET(ctx, cmd, in_type, inv) \
+ { \
+ ClnkLio_t io; \
+ if (inv == NULL) \
+ return CLNK_ERR; \
+ io.in = (void *) inv; \
+ io.in_len = sizeof(in_type); \
+ io.out = NULL; \
+ io.out_len = 0; \
+ return(ClnkLio_SendCmd(ctx, cmd, &io, -1)); \
+ }
+/* only command, null arguments */
+#define CLNK_CTL_DO(ctx, cmd) \
+ { \
+ ClnkLio_t io; \
+ io.in = NULL; \
+ io.in_len = 0; \
+ io.out = NULL; \
+ io.out_len = 0; \
+ return(ClnkLio_SendCmd(ctx, cmd, &io, -1)); \
+ }
+/* input arguments and out struct should be provided*/
+#define CLNK_CTL_SET_GET(ctx, cmd, in_type,inv,out_type,outv) \
+ { \
+ ClnkLio_t io; \
+ if ((inv == NULL)||(outv == NULL)) \
+ return CLNK_ERR; \
+ io.in = (void *) inv; \
+ io.in_len = sizeof(in_type); \
+ io.out = (uint32_t *)outv; \
+ io.out_len = sizeof(out_type); \
+ return(ClnkLio_SendCmd(ctx, cmd, &io, -1)); \
+ }
+
+
+typedef enum
+{
+ /// Ethernet commands
+ CLNK_MBX_ETH_RESET_CMD = 0x00, /*!< Alias: ETH_MB_RESET, */
+ CLNK_MBX_ETH_ALLOC_TX_FIFO_CMD = 0x01, /*!< Alias: ETH_MB_ALLOCATE_TX_FIFO, */
+ CLNK_MBX_ETH_ALLOC_RX_FIFO_CMD = 0x02, /*!< Alias: ETH_MB_ALLOCATE_RX_FIFO, */
+ CLNK_MBX_ETH_JOIN_MCAST_CMD = 0x03, /*!< Alias: ETH_MB_JOIN_MULTICAST, */
+ CLNK_MBX_ETH_LEAVE_MCAST_CMD = 0x04, /*!< Alias: ETH_MB_LEAVE_MULTICAST, */
+ CLNK_MBX_ETH_REGISTER_MCAST_CMD = 0x05, /*!< Alias: ETH_MB_REGISTER_MULTICAST, */
+ CLNK_MBX_ETH_GET_STATS_CMD = 0x06, /*!< Alias: ETH_MB_QUERY_RCV_STATS, */
+ CLNK_MBX_ETH_SET_RCV_MODE_CMD = 0x07, /*!< Alias: ETH_MB_SET_RCV_MODE, */
+ CLNK_MBX_ETH_GET_RCV_MODE_CMD = 0x08, /*!< Alias: ETH_MB_GET_RCV_MODE, */
+ CLNK_MBX_ETH_PUB_UCAST_CMD = 0x09, /*!< Alias: ETH_MB_PUBLISH_UNICAST_ADDR, */
+ CLNK_MBX_ETH_DEREGISTER_MCAST_CMD = 0x0a, /*!< Alias: ETH_MB_DEREGISTER_MULTICAST, */
+ CLNK_MBX_ETH_DATA_BUF_CMD = 0x0b, /*!< Alias: ETH_MB_DATA_BUF_CMD, */
+ CLNK_MBX_ETH_GET_STATUS_CMD = 0x0c, /*!< Alias: ETH_MB_GET_STATUS, */
+ CLNK_MBX_ETH_SET_SW_CONFIG_CMD = 0x0d, /*!< Alias: ETH_MB_SET_SW_CONFIG, */
+ CLNK_MBX_ETH_ECHO_PROFILE_PROBE_RESPONSE = 0x0e, /*!< Alias: ETH_MB_ECHO_PROFILE_PROBE_RESPONSE, */
+ CLNK_MBX_ETH_GET_CMD = 0x0f, /*!< Alias: ETH_MB_GET_CMD, */
+ CLNK_MBX_ETH_SET_CMD = 0x10, /*!< Alias: ETH_MB_SET_CMD, */
+ CLNK_MBX_ETH_CLINK_ACCEPT_SMALL_ROUTED_MESSAGE = 0x11, /*!< Alias: ETH_MB_CLINK_ACCEPT_SMALL_ROUTED_MESSAGE, */
+ CLNK_MBX_ETH_SET_BEACON_POWER_LEVEL_CMD = 0x12, /*!< Alias: ETH_MB_SET_BEACON_POWER_LEVEL_CMD, */
+ CLNK_MBX_ETH_QOS_ASYNC_REQ_BLOB = 0x13, /*!< Alias: ETH_MB_QOS_ASYNC_REQ_BLOB, */
+ CLNK_MBX_ETH_QFM_RESP_BLOB = 0x14, /*!< Alias: ETH_MB_QFM_RESP_BLOB, */
+ CLNK_MBX_ETH_SET_MIXED_MODE_ACTIVE = 0x15, /*!< Alias: ETH_MB_SET_MIXED_MODE_ACTIVE, */
+ CLNK_MBX_ETH_GET_MIXED_MODE_ACTIVE = 0x16, /*!< Alias: ETH_MB_GET_MIXED_MODE_ACTIVE, */
+ CLNK_MBX_ETH_QFM_CAM_DONE = 0x17, /*!< Alias: ETH_MB_QFM_CAM_DONE, */
+ // MPEG commands
+ CLNK_MBX_MPEG_CREATE_INPUT_CHANNEL_CMD = 0x20,
+ CLNK_MBX_MPEG_JOIN_CHANNEL_CMD = 0x21,
+ CLNK_MBX_MPEG_JOIN_AS_PASSIVE_LISTENER_CMD = 0x22,
+ CLNK_MBX_MPEG_SUBSCRIPTION_REQUEST_CMD = 0x23,
+ CLNK_MBX_MPEG_MODIFY_INPUT_CHANNEL_CMD = 0x24,
+ CLNK_MBX_MPEG_MODIFY_OUTPUT_CHANNEL_CMD = 0x25,
+ CLNK_MBX_MPEG_LEAVE_INPUT_CHANNEL_CMD = 0x26,
+ CLNK_MBX_MPEG_LEAVE_OUTPUT_CHANNEL_CMD = 0x27,
+ CLNK_MBX_MPEG_CREATE_OUTPUT_CHANNEL_CMD = 0x28,
+ CLNK_MBX_MPEG_RESERVED_CMD_FROM = 0x29,
+ CLNK_MBX_MPEG_RESERVED_CMD_TO = 0x2F,
+ CLNK_MBX_MPEG_READ_TRANSMIT_STATS_CMD = 0x30,
+ CLNK_MBX_MPEG_READ_RECEIVE_STATS_CMD = 0x31,
+ CLNK_MBX_MPEG_SUBSCRIPTION_REPORT_REQUEST_CMD = 0x32,
+
+ CLNK_MBX_MAX_CMD /*!< This must always be last */
+} clnk_mbx_cmd_codes_t;
+#define DRV_CLNK_CTL 55
+
+typedef struct
+{
+ uint32_t cmd;
+ void* param1;
+ void* param2;
+ void* param3;
+} IfrDataStruct;
+
+
+
+/// Macros to package up the message properly
+
+/// no input variable, simple response expected
+#define CLNK_DRV_GET_0(io, out_type, outv) \
+ { \
+ if (outv == NULL) \
+ return CLNK_ERR; \
+ io.in = NULL; \
+ io.in_len = 0; \
+ io.out = (uint32_t *) outv; \
+ io.out_len = sizeof(out_type); \
+ }
+
+/// 1 input variable, simple response expected
+#define CLNK_DRV_GET_1(io, out_type, outv, inv) \
+ { \
+ if (outv == NULL) \
+ return CLNK_ERR; \
+ io.in = (uint32_t *)(unsigned long) inv; \
+ io.in_len = 0; \
+ io.out = (uint32_t *) outv; \
+ io.out_len = sizeof(out_type); \
+ }
+
+/// 1 input variable, no response expected
+#define CLNK_DRV_SET(io, in_type, inv) \
+ { \
+ if (inv == NULL) \
+ return CLNK_ERR; \
+ io.in = (void *) inv; \
+ io.in_len = sizeof(in_type); \
+ io.out = NULL; \
+ io.out_len = 0; \
+ }
+
+/// no input variable, no response expected
+#define CLNK_DRV_DO(io) \
+ { \
+ io.in = NULL; \
+ io.in_len = 0; \
+ io.out = NULL; \
+ io.out_len = 0; \
+ }
+/// 1 input variable, complex response expected
+#define CLNK_DRV_SET_GET(io, in_type, inv, out_type, outv) \
+ { \
+ if ((inv == NULL)||(outv == NULL)) \
+ return CLNK_ERR; \
+ io.in = (void *) inv; \
+ io.in_len = sizeof(in_type); \
+ io.out = (uint32_t *)outv; \
+ io.out_len = sizeof(out_type); \
+ }
+
+#endif /* __CLNK_API_LIO_H__ */
diff --git a/drivers/net/phy/mxl371x/lib/ClnkLibApi.h b/drivers/net/phy/mxl371x/lib/ClnkLibApi.h
new file mode 100644
index 000000000000..a9a31b0aeb90
--- /dev/null
+++ b/drivers/net/phy/mxl371x/lib/ClnkLibApi.h
@@ -0,0 +1,2588 @@
+/*****************************************************************************************
+ * FILE NAME : ClnkLibApi.h
+ *
+ *
+ * DATE CREATED : Oct/11/2016
+ * LAST MODIFIED :
+ *
+ * DESCRIPTION : c.LINK API header file.
+ *
+ *
+ *****************************************************************************************
+ * MaxLinear, Inc. retains all right, title and interest (including all intellectual
+ * property rights) in and to this computer program, which is protected by applicable
+ * intellectual property laws. Unless you have obtained a separate written license from
+ * MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., you are not authorized
+ * to utilize all or a part of this computer program for any purpose (including
+ * reproduction, distribution, modification, and compilation into object code), and you
+ * must immediately destroy or return all copies of this computer program. If you are
+ * licensed by MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., your rights
+ * to utilize this computer program are limited by the terms of that license.
+ *
+ * This computer program contains trade secrets owned by MaxLinear, Inc. and, unless
+ * authorized by MaxLinear, Inc. in writing, you agree to maintain the confidentiality
+ * of this computer program and related information and to not disclose this computer
+ * program and related information to any other person or entity.
+ *
+ * Misuse of this computer program or any information contained in it may results in
+ * violations of applicable law. MaxLinear, Inc. vigorously enforces its copyright,
+ * trade secret, patent, contractual, and other legal rights.
+ *
+ * THIS COMPUTER PROGRAM IS PROVIDED "AS IS" WITHOUT ANY WARRANTIES, AND
+ * MAXLINEAR, INC.EXPRESSLY DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE
+ * WARRANTIES OF MERCHANTIBILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND
+ * NONINFRINGEMENT.
+ *
+ ****************************************************************************************
+ * Copyright (c) 2016, MaxLinear, Inc.
+ ****************************************************************************************/
+
+#ifndef __CLNK_API_H__
+#define __CLNK_API_H__
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * Includes
+ ******************************************************************************/
+///int32_t
+#include <inttypes.h>
+///FILE *
+#include <stdbool.h>
+#include <stdio.h>
+#include <net/if.h>
+#include "mxl_moca_config.h"
+#include "mxl_data_types.h"
+#include "mxl_moca_soc_cmd.h"
+#include "mxl_moca_config.h"
+
+
+/*******************************************************************************
+ * Constants
+ ******************************************************************************/
+ // REGISTER MACRO NAME ADDRESS BIT NUM
+ // LOC BITS
+
+#define SRE_PRODUCT_FAMILY_ID 0x08200000, 0, 32
+#define SRE_DEVICE_ID 0x08200004, 0, 16
+#define SRE_REVISION_ID 0x08200004, 16, 16
+#define SRE_INTERRUPT_MASK 0x08200008, 0, 32
+#define SRE_BOND_OPTION 0x0820000c, 16, 4
+#define SRE_BOND_OPTION_PCIE 0x0820000c, 20, 1
+#define SRE_BOND_OPTION_POR_BYPASS 0x0820000c, 21, 1
+
+#define SRE_CPU_SRC_SEL_CSR 0x08200010, 0, 1
+#define SRE_CPU_SRC_FORCE 0x08200010, 3, 1
+#define SRE_CPU_SRC_SELECTED 0x08200014, 0, 2
+
+#define SRE_SPI_DISABLE 0x08200018, 18, 1
+
+#define MRE_PULSEREMOVALFRACTIONLDPC 0x0c1030e0, 16, 8
+#define MRE_LDPCCLKDISABLE 0x0c1030e4, 0, 1
+#define MRE_CPCDATAFLOWCLKDISABLE 0x0c1030e4, 3, 1
+#define MRE_DICDATAFLOWCLKDISABLE 0x0c1030e4, 4, 1
+#define MRE_PHYRXCLK200CH0DISABLE 0x0c1030e4, 6, 1
+#define MRE_PHYTXCLK200CH0DISABLE 0x0c1030e4, 7, 1
+#define MRE_PHYTXCLK600DISABLE 0x0c1030e4, 8, 1
+#define MRE_PHYCLK200CH0DISABLE 0x0c1030e4, 9, 1
+#define MRE_PHYCLKSYSDISABLE 0x0c1030e4, 10, 1
+#define MRE_DATAFLOWCSRCAMDISABLE 0x0c1030e4, 12, 1
+#define MRE_PHYRFICCLK200DISABLE 0x0c1030e4, 13, 1
+#define MRE_PHYCLK200CH1DISABLE 0x0c1030e4, 16, 1
+#define MRE_PHYDBGCLK400DISABLE 0x0c1030e4, 17, 1
+#define MRE_PHYRXCLK200CH1DISABLE 0x0c1030e4, 22, 1
+#define MRE_PHYTXCLK200CH1DISABLE 0x0c1030e4, 23, 1
+
+#define DFC_DICTCCLOCKGAP 0x0cd48050, 8, 8
+#define DFC_CPCTCCLOCKGAP 0x0cd48050, 24, 8
+
+#define KEYGEN_ENABLE 0x0c105028, 0, 1
+
+#define MRX_DFE_MOCA_RX_CHN0_EN 0x0c140010, 0, 1
+#define MRX_DFE_MOCA_RX_CHN1_EN 0x0c140014, 0, 1
+#define MRX_DFE_MOCA_RX_CHN0_CLK_EN 0x0c140050, 0, 1
+#define MRX_DFE_MOCA_RX_CHN1_CLK_EN 0x0c140054, 0, 1
+#define MRX_DFE_MOCA_RX_DCCAL_FREEZE 0x0c140074, 0, 1
+#define MRX_DFE_MOCA_RX_GA_INIT 0x0c1400c0, 0, 7
+#define MRX_DFE_MOCA_RX_GA_INIT_APPLY 0x0c1400c4, 0, 1
+#define MRX_DFE_MOCA_RX_WB_EN 0x0c140270, 0, 1
+
+#define MTX_DFE_MOCA_TX_DYN_EN0 0x0c142008, 0, 1
+#define MTX_DFE_MOCA_TX_DYN_EN1 0x0c14200c, 0, 1
+#define MTX_DFE_MOCA_TX_CLK_EN0 0x0c142010, 0, 1
+#define MTX_DFE_MOCA_TX_CLK_EN1 0x0c142014, 0, 1
+
+#define RADIO_D2A_MOCA_ADC_ADC_EN 0x0c14c000, 0, 3
+#define RADIO_D2A_MOCA_RFFE_MASTER_EN 0x0c14c004, 0, 1
+#define RADIO_D2A_MOCA_RFFE_SPARE2 0x0c14c00c, 0, 4
+
+#define RADIO_D2A_MOCA_TXDRVR_ENA 0x0c14c014, 0, 1
+#define RADIO_D2A_MOCA_TXDRVR_BO 0x0c14c018, 0, 4
+#define RADIO_D2A_MOCA_TXDRVR_AWAKE 0x0c14c034, 0, 1
+
+#define RADIO_D2A_MOCA_DAC_CLK_ENA 0x0c14c048, 0, 1
+#define RADIO_D2A_MOCA_DAC_RSTB 0x0c14c044, 0, 1
+
+#define RADIO_D2A_REFSX_MOCA_ADC_CLK_ENA 0x0c14c0b4, 14, 1
+#define RADIO_D2A_REFSX_MOCA_DAC_CLK_ENA 0x0c14c0b4, 15, 1
+
+#define RADIO_D2A_MOCA_DAC_REGD_ENA 0x0c14c068, 0, 1
+#define RADIO_D2A_MOCA_DAC_AWAKE 0x0c14c078, 0, 1
+
+#define RADIO_D2A_MOCA_ADC_BIAS_EN 0x0c14c0e0, 20, 1
+#define RADIO_D2A_MOCA_ADC_REPLICA_EN 0x0c14c0e0, 21, 1
+#define RADIO_D2A_MOCA_ADC_CML2CMOS_EN 0x0c14c0e0, 31, 1
+#define RADIO_D2A_MOCA_ADC_REG4_EN 0x0c14c0e4, 5, 1
+#define RADIO_D2A_MOCA_ADC_REG4_EN_LEAK1 0x0c14c0e4, 6, 1
+#define RADIO_D2A_MOCA_ADC_REG1_EN 0x0c14c0e4, 20, 1
+#define RADIO_D2A_MOCA_ADC_REG1_EN_LEAK1 0x0c14c0e4, 21, 1
+#define RADIO_D2A_MOCA_ADC_REG2_EN 0x0c14c0e8, 0, 1
+#define RADIO_D2A_MOCA_ADC_REG2_EN_LEAK1 0x0c14c0e8, 1, 1
+
+#define PHY_CTRL_PRCM_ADC_RST_N 0x0c14e000, 16, 1
+
+enum
+{
+ OPT_MOCA_VER = 1 ,//1
+ OPT_TEST_MODE ,//
+ OPT_CLNKLED_MODE ,//
+ OPT_TESTPARAM1 ,//
+ OPT_TESTPARAM2 ,//
+ OPT_TESTPARAM3 ,//
+ OPT_TESTPARAM4 ,//
+ OPT_TURBO_MODE ,//
+ OPT_TURBO_MODE_D ,//
+ OPT_TURBO_MODE_D_LO ,//
+ OPT_TURBO_MODE_D_HI ,//10
+ OPT_TURBO_MODE_E ,//
+ OPT_TURBO_MODE_F_SAT ,//
+ OPT_TURBO_MODE_F_CBL ,//
+ OPT_TURBO_MODE_H ,//
+ OPT_TURBO_MODE_CUSTOM ,//
+ OPT_MII_PPRIO_LEVEL ,//
+ OPT_MII_SPEED ,//
+ OPT_POLICING_MODE ,//
+ OPT_POLICING_MODE_D ,//
+ OPT_POLICING_MODE_D_LO ,//20
+ OPT_POLICING_MODE_D_HI ,//
+ OPT_POLICING_MODE_E ,//
+ OPT_POLICING_MODE_F_SAT ,//
+ OPT_POLICING_MODE_F_CBL ,//
+ OPT_POLICING_MODE_H ,//
+ OPT_POLICING_MODE_CUSTOM ,//
+ OPT_PQOS_CLASS_MODE ,//
+ OPT_RETRANS_PRIO ,//
+ OPT_RETRANS_PRIO_D ,//
+ OPT_RETRANS_PRIO_D_LO ,//30
+ OPT_RETRANS_PRIO_D_HI ,//
+ OPT_RETRANS_PRIO_E ,//
+ OPT_RETRANS_PRIO_F_SAT ,//
+ OPT_RETRANS_PRIO_F_CBL ,//
+ OPT_RETRANS_PRIO_H ,//
+ OPT_RETRANS_PRIO_CUSTOM ,//
+ OPT_TRANS_PRIO_PER ,//
+ OPT_TRANS_PRIO_PER_D ,//
+ OPT_TRANS_PRIO_PER_D_LO ,//
+ OPT_TRANS_PRIO_PER_D_HI ,//40
+ OPT_TRANS_PRIO_PER_E ,//
+ OPT_TRANS_PRIO_PER_F_SAT ,//
+ OPT_TRANS_PRIO_PER_F_CBL ,//
+ OPT_TRANS_PRIO_PER_H ,//
+ OPT_TRANS_PRIO_PER_CUSTOM ,//
+ OPT_FAILOVER_MODE ,//
+ OPT_HANDOFF_MODE ,//
+ OPT_INITIAL_ROLE ,//
+ OPT_LMO_MODE ,//
+ OPT_MOCA_PASSWD ,//50
+ OPT_MOCA_PASSWD_D ,//
+ OPT_MOCA_PASSWD_D_LO ,//
+ OPT_MOCA_PASSWD_D_HI ,//
+ OPT_MOCA_PASSWD_E ,//
+ OPT_MOCA_PASSWD_F_SAT ,//
+ OPT_MOCA_PASSWD_F_CBL ,//
+ OPT_MOCA_PASSWD_H ,//
+ OPT_MOCA_PASSWD_CUSTOM ,//
+ OPT_MOCASEQNUMMR ,//
+ OPT_MOCASEQNUMMR_D ,//60
+ OPT_MOCASEQNUMMR_D_LO ,//
+ OPT_MOCASEQNUMMR_D_HI ,//
+ OPT_MOCASEQNUMMR_E ,//
+ OPT_MOCASEQNUMMR_F_SAT ,//
+ OPT_MOCASEQNUMMR_F_CBL ,//
+ OPT_MOCASEQNUMMR_H ,//
+ OPT_MOCASEQNUMMR_CUSTOM ,//
+ OPT_PREFER_NC_MODE ,//
+ OPT_SECURITY_MODE ,//
+ OPT_SECURITY_MODE_D ,//70
+ OPT_SECURITY_MODE_D_LO ,//
+ OPT_SECURITY_MODE_D_HI ,//
+ OPT_SECURITY_MODE_E ,//
+ OPT_SECURITY_MODE_F_SAT ,//
+ OPT_SECURITY_MODE_F_CBL ,//
+ OPT_SECURITY_MODE_H ,//
+ OPT_SECURITY_MODE_CUSTOM ,//
+ OPT_NET_SEARCH_MODE ,//
+ OPT_LOF ,//
+ OPT_LOF_UPDATE_MODE ,//80
+ OPT_PROF_C_GAP_MODE ,//
+ OPT_FREQ_BAND_MASK ,//
+ OPT_SCAN_MASK ,//
+ OPT_SCAN_MASK_D ,//
+ OPT_SCAN_MASK_D_LO ,//
+ OPT_SCAN_MASK_D_HI ,//
+ OPT_SCAN_MASK_E ,//
+ OPT_SCAN_MASK_F_SAT ,//
+ OPT_SCAN_MASK_F_CBL ,//
+ OPT_SCAN_MASK_H ,//
+ OPT_SCAN_MASK_CUSTOM ,//90
+ OPT_SCAN_OFFSET ,//
+ OPT_SCAN_OFFSET_D ,//
+ OPT_SCAN_OFFSET_D_LO ,//
+ OPT_SCAN_OFFSET_D_HI ,//
+ OPT_SCAN_OFFSET_E ,//
+ OPT_SCAN_OFFSET_F_SAT ,//
+ OPT_SCAN_OFFSET_F_CBL ,//
+ OPT_SCAN_OFFSET_H ,//
+ OPT_SCAN_OFFSET_CUSTOM ,//
+ OPT_PRIM_CHAN_ABOVE ,//100
+ OPT_PRIM_CHAN_ABOVE_D ,//
+ OPT_PRIM_CHAN_ABOVE_D_LO ,//
+ OPT_PRIM_CHAN_ABOVE_D_HI ,//
+ OPT_PRIM_CHAN_ABOVE_E ,//
+ OPT_PRIM_CHAN_ABOVE_F_SAT ,//
+ OPT_PRIM_CHAN_ABOVE_F_CBL ,//
+ OPT_PRIM_CHAN_ABOVE_H ,//
+ OPT_PRIM_CHAN_ABOVE_CUSTOM ,//
+ OPT_PRIM_CHAN_BELOW ,//
+ OPT_PRIM_CHAN_BELOW_D ,//110
+ OPT_PRIM_CHAN_BELOW_D_LO ,//
+ OPT_PRIM_CHAN_BELOW_D_HI ,//
+ OPT_PRIM_CHAN_BELOW_E ,//
+ OPT_PRIM_CHAN_BELOW_F_SAT ,//
+ OPT_PRIM_CHAN_BELOW_F_CBL ,//
+ OPT_PRIM_CHAN_BELOW_H ,//
+ OPT_PRIM_CHAN_BELOW_CUSTOM ,//
+ OPT_SECO_CHAN_ABOVE ,//
+ OPT_SECO_CHAN_ABOVE_D ,//
+ OPT_SECO_CHAN_ABOVE_D_LO ,//120
+ OPT_SECO_CHAN_ABOVE_D_HI ,//
+ OPT_SECO_CHAN_ABOVE_E ,//
+ OPT_SECO_CHAN_ABOVE_F_SAT ,//
+ OPT_SECO_CHAN_ABOVE_F_CBL ,//
+ OPT_SECO_CHAN_ABOVE_H ,//
+ OPT_SECO_CHAN_ABOVE_CUSTOM ,//
+ OPT_SECO_CHAN_BELOW ,//
+ OPT_SECO_CHAN_BELOW_D ,//
+ OPT_SECO_CHAN_BELOW_D_LO ,//
+ OPT_SECO_CHAN_BELOW_D_HI ,//130
+ OPT_SECO_CHAN_BELOW_E ,//
+ OPT_SECO_CHAN_BELOW_F_SAT ,//
+ OPT_SECO_CHAN_BELOW_F_CBL ,//
+ OPT_SECO_CHAN_BELOW_H ,//
+ OPT_SECO_CHAN_BELOW_CUSTOM ,//
+ OPT_TABOO_MASK ,//
+ OPT_TABOO_OFFSET ,//
+ OPT_TLP_MIN ,//
+ OPT_TLP_MIN_D ,//
+ OPT_TLP_MIN_D_LO ,//140
+ OPT_TLP_MIN_D_HI ,//
+ OPT_TLP_MIN_E ,//
+ OPT_TLP_MIN_F_SAT ,//
+ OPT_TLP_MIN_F_CBL ,//
+ OPT_TLP_MIN_H ,//
+ OPT_TLP_MIN_CUSTOM ,//
+ OPT_TLP_MAX ,//
+ OPT_TLP_MAX_D ,//
+ OPT_TLP_MAX_D_LO ,//
+ OPT_TLP_MAX_D_HI ,//150
+ OPT_TLP_MAX_E ,//
+ OPT_TLP_MAX_F_SAT ,//
+ OPT_TLP_MAX_F_CBL ,//
+ OPT_TLP_MAX_H ,//
+ OPT_TLP_MAX_CUSTOM ,//
+ OPT_BEACON_TX_POW ,//
+ OPT_ENCODINGWORDLENNPER ,//
+ OPT_ENCODINGWORDLENVLPER ,//
+ OPT_FEATUREFLAGS ,//
+ OPT_MAX_TX_POW ,//160
+ OPT_BITLOADMARGIN50 ,//
+ OPT_BITLOADMARGIN50_D ,//
+ OPT_BITLOADMARGIN50_D_LO ,//
+ OPT_BITLOADMARGIN50_D_HI ,//
+ OPT_BITLOADMARGIN50_E ,//
+ OPT_BITLOADMARGIN50_F_SAT ,//
+ OPT_BITLOADMARGIN50_F_CBL ,//
+ OPT_BITLOADMARGIN50_H ,//
+ OPT_BITLOADMARGIN50_CUSTOM ,//
+ OPT_BITLOADMARGINNPER ,//170
+ OPT_BITLOADMARGINNPER_D ,//
+ OPT_BITLOADMARGINNPER_D_LO ,//
+ OPT_BITLOADMARGINNPER_D_HI ,//
+ OPT_BITLOADMARGINNPER_E ,//
+ OPT_BITLOADMARGINNPER_F_SAT ,//
+ OPT_BITLOADMARGINNPER_F_CBL ,//
+ OPT_BITLOADMARGINNPER_H ,//
+ OPT_BITLOADMARGINNPER_CUSTOM ,//
+ OPT_BITLOADMARGINVLPER ,//
+ OPT_BITLOADMARGINVLPER_D ,//180
+ OPT_BITLOADMARGINVLPER_D_LO ,//
+ OPT_BITLOADMARGINVLPER_D_HI ,//
+ OPT_BITLOADMARGINVLPER_E ,//
+ OPT_BITLOADMARGINVLPER_F_SAT ,//
+ OPT_BITLOADMARGINVLPER_F_CBL ,//
+ OPT_BITLOADMARGINVLPER_H ,//
+ OPT_BITLOADMARGINVLPER_CUSTOM ,//
+ OPT_TPCMODE ,//
+ OPT_TPCMODE_D ,//
+ OPT_TPCMODE_D_LO ,//190
+ OPT_TPCMODE_D_HI ,//
+ OPT_TPCMODE_E ,//
+ OPT_TPCMODE_F_SAT ,//
+ OPT_TPCMODE_F_CBL ,//
+ OPT_TPCMODE_H ,//
+ OPT_TPCMODE_CUSTOM ,//
+ OPT_TARGETP2PRATE50 ,//
+ OPT_TARGETP2PRATENPER ,//
+ OPT_TARGETP2PRATEVLPER ,//
+ OPT_STRIPVLANTAG ,//200
+ OPT_MPAENABLE ,//
+ OPT_ENHANCEDENABLE ,//
+ OPT_TIMEMISMATCHCAL ,//
+ OPT_MPA_MACADDR ,//
+ OPT_MPA_PKTFILTER ,//
+ OPT_FIRSTCHANNELOFFSET ,//
+ OPT_FIRSTCHANNELOFFSET_D ,//
+ OPT_FIRSTCHANNELOFFSET_D_LO ,//
+ OPT_FIRSTCHANNELOFFSET_D_HI ,//
+ OPT_FIRSTCHANNELOFFSET_E ,//210
+ OPT_FIRSTCHANNELOFFSET_F_SAT ,//
+ OPT_FIRSTCHANNELOFFSET_F_CBL ,//
+ OPT_FIRSTCHANNELOFFSET_H ,//
+ OPT_FIRSTCHANNELOFFSET_CUSTOM ,//
+ OPT_NUMBEROFCHANNELS ,//
+ OPT_NUMBEROFCHANNELS_D ,//
+ OPT_NUMBEROFCHANNELS_D_LO ,//
+ OPT_NUMBEROFCHANNELS_D_HI ,//
+ OPT_NUMBEROFCHANNELS_E ,//
+ OPT_NUMBEROFCHANNELS_F_SAT ,//220
+ OPT_NUMBEROFCHANNELS_F_CBL ,//
+ OPT_NUMBEROFCHANNELS_H ,//
+ OPT_NUMBEROFCHANNELS_CUSTOM ,//
+ OPT_LOADING_CAPS ,//
+ OPT_MAC_ADDR_AGING_TIME ,//
+ OPT_BCN_PWR_ENABLE ,//
+ OPT_BCN_PWR_DIST ,//
+ OPT_BCN_PWR_LOCAL ,//
+ OPT_PRIVACY_SUPPORTED ,//
+ OPT_ENHANCED_PASSWORD ,//230
+ OPT_NETWORK_NAME ,// NETWORK_NAME/NC_NN
+ OPT_NETWORK_NAME_ADMIT_CFG ,// NETWORK_NAME/ADMIT
+ OPT_ME_NETWORK_IE_PAYLOAD_TX ,// ME_NETWORK_IE/PAYLOAD_TX
+ OPT_ME_NETWORK_IE_RESP_TIMEOUT ,// ME_NETWORK_IE/RESP_TIMEOUT
+ OPT_ME_NETWORK_JOIN_EN ,// ME_NETWORK/JOIN Enable
+ OPT_MPS_PRIVACY_DOWN ,//
+ OPT_MPS_PRIVACY_RECEIVE ,//
+ OPT_MPS_UNPAIRED_TIME ,//
+ OPT_MPS_WALK_TIME ,//
+ OPT_AUTH_LINK_ETHERTYPE ,//
+ OPT_AUTH_LINK_BITMASK ,//240
+ OPT_AUTH_LINK_BITMASK_0 ,//
+ OPT_AUTH_LINK_BITMASK_1 ,//
+ OPT_AUTH_LINK_BITMASK_2 ,//
+ OPT_AUTH_LINK_BITMASK_3 ,//
+ OPT_AUTH_LINK_BITMASK_4 ,//
+ OPT_AUTH_LINK_BITMASK_5 ,//
+ OPT_AUTH_LINK_BITMASK_6 ,//
+ OPT_AUTH_LINK_BITMASK_7 ,//
+ OPT_AUTH_LINK_BITMASK_8 ,//
+ OPT_AUTH_LINK_BITMASK_9 ,//250
+ OPT_AUTH_LINK_BITMASK_10 ,//
+ OPT_AUTH_LINK_BITMASK_11 ,//
+ OPT_AUTH_LINK_BITMASK_12 ,//
+ OPT_AUTH_LINK_BITMASK_13 ,//
+ OPT_AUTH_LINK_BITMASK_14 ,//
+ OPT_AUTH_LINK_BITMASK_15 ,//
+ OPT_SGMII0_CONFIG ,//
+ OPT_SGMII1_CONFIG ,//
+ OPT_TWOKPE ,//
+ OPT_PORT0_DISABLE ,//260
+ OPT_PORT1_DISABLE ,//
+ OPT_PORT_MOCA_DISABLE ,//
+ OPT_TRACE_ENABLE ,//
+ OPT_TRACE_LEVEL ,//
+ OPT_TRACE_MODULE ,//
+ OPT_TRACE_DEST ,//
+ OPT_TRACE_HOST_CTL ,//
+ OPT_HANDOFF_TO_LOWERMOCAVER ,//
+ OPT_CLNK_MAX_OPTIONS //
+};
+
+#define OPT_CLNK_WORDS ((OPT_CLNK_MAX_OPTIONS+31)/32)
+
+typedef struct
+{
+ uint32_t words[OPT_CLNK_WORDS];
+}
+clnk_param_mask_t;
+
+#define CLEAR_PARAM_BITS(mask) do \
+{ \
+ memset(mask, 0, sizeof(*mask)); \
+} while (0)
+#define SET_ALL_PARAM_BITS(mask) do \
+{ \
+ memset(mask, 0xff, sizeof(*mask)); \
+} while (0)
+#define GET_PARAM_BIT(mask, opt) (((mask)->words[(opt)/32] & (1 << ((opt)%32))) != 0)
+#define SET_PARAM_BIT(mask, opt) do \
+{ \
+ (mask)->words[(opt)/32] |= (1 << ((opt)%32)); \
+} while (0)
+
+/*******************************************************************************
+ * Macros
+ ******************************************************************************/
+#define MXL_MOCA_LSB_MASK(bitWidth) ((bitWidth) < (uint8_t) 32 ? (((uint32_t) 1 << (bitWidth)) - (uint32_t) 1) : 0xFFFFFFFF)
+#define ClnkLib_UpdateRegBitField(a,b,c) ClnkLib_UpdateRegisterField(a,b,c)
+
+/*
+ * USER CONFIGURABLES
+ */
+
+#define CLNKLIB_MAX_DEV_NUM 29
+
+///using in printf("%02x%02x:%02x:%02x:%02x:%02x",mac0,mac1,mac2,mac3,mac4,mac5);
+#define GET_FLAGS(f, p) ((p < 33) ? (f.lo&(1<<(p-1))):(f.hi&(1<<(p-33))))
+#define SET_FLAGS(f, p) ((p < 33) ? (f.lo |= (1<<(p-1))):(f.hi |= (1<<(p-33))))
+#define FLAGS_IS_EMPTY(f) ((f).lo == 0 && (f).hi == 0)
+
+// Count elements in an array at compile time
+#define APPS_ARRAY_LENGTH(a) (sizeof(a) / sizeof(*(a)))
+
+#define GET_ARRAY_LEN(_array) (sizeof(_array)/sizeof(*(_array)))
+#define MIN(a,b) (((a) < (b)) ? (a) : (b))
+#define MAX(a,b) (((a) > (b)) ? (a) : (b))
+
+#define SWAPLONG(x) (((x & 0x00000000ffffffff) << 32) | ((x & 0xffffffff00000000) >> 32))
+
+/** Created to mark simplificant modifications done duriung Jaws
+ * Pre Alpha BRADMBX */
+
+#define APPS_LOG(_fmt, _args...) do \
+{ \
+ printf("%s(%d): " _fmt "\n", __FILE__, __LINE__, ##_args ); \
+ /*sleep(1);*/ \
+} while (0)
+
+#define APPS_COMMENT(_fmt, _args...)
+
+#ifdef DBG_APPS
+#define APPS_FATAL_IF(_cond, _fmt, _args...) do \
+{ \
+ if (_cond) \
+ { \
+ printf(" %s(%d): FATAL: " _fmt " (condition " #_cond ")\n", \
+ __FILE__, __LINE__, ##_args ); \
+ exit(EXIT_FAILURE); \
+ } \
+} while (0)
+#else
+#define APPS_FATAL_IF(_cond, _fmt, _args...) do \
+{ \
+ if (_cond) \
+ { \
+ printf(_fmt "\n", ##_args ); \
+ exit(EXIT_FAILURE); \
+ } \
+} while (0)
+#endif
+
+#define APPS_FATAL_UNLESS(_cond, _fmt, _args...) APPS_FATAL_IF(!(_cond), _fmt, ##_args)
+#define APPS_FATAL(_fmt, _args...) APPS_FATAL_IF(1, _fmt, ##_args)
+#define APPS_FATAL_PTRNULL(_ptr) APPS_FATAL_IF(NULL == (_ptr), "null pointer")
+
+/* APPS_ERROR_... same as APPS_FATAL_ except return CLNK_ERR or CLNK_OK instead of
+ exiting. This allows the app to exit in orderly fashion */
+#ifdef DBG_APPS
+#define APPS_ERROR_IF(_cond, _fmt, _args...) ( \
+{ \
+ int32_t e = 0; \
+ if (_cond) \
+ { \
+ printf(" %s(%d): FATAL: " _fmt " (condition " #_cond ")\n", \
+ __FILE__, __LINE__, ##_args ); \
+ e = -1; \
+ } \
+ e; \
+} )
+#else
+#define APPS_ERROR_IF(_cond, _fmt, _args...) ( \
+{ \
+ int32_t e = 0; \
+ if (_cond) \
+ { \
+ printf(_fmt "\n", ##_args ); \
+ e = -1; \
+ } \
+ e; \
+} )
+#endif
+
+#define APPS_ERROR_UNLESS(_cond, _fmt, _args...) APPS_ERROR_IF(!(_cond), _fmt, ##_args)
+#define APPS_ERROR(_fmt, _args...) APPS_ERROR_IF(1, _fmt, ##_args)
+#define APPS_ERROR_PTRNULL(_ptr) APPS_ERROR_IF(NULL == (_ptr), "null pointer")
+
+
+#ifndef MXL_ENABLE_DEBUG_PRINT
+#define MXL_ENABLE_DEBUG_PRINT 0
+#endif
+
+#ifndef MXL_ENABLE_DEBUG_ENTER_EXIT_FUNCTION
+#define MXL_ENABLE_DEBUG_ENTER_EXIT_FUNCTION 0
+#endif
+
+#if MXL_ENABLE_DEBUG_PRINT
+#define DEBUG_PRINT(lev, fmt, args...) ClnkOsal_PrintLog(lev,"(%s)%d " fmt " \n", __func__, __LINE__, ##args)
+#else
+#define DEBUG_PRINT(lev, fmt, args...)
+#endif
+
+#if MXL_ENABLE_DEBUG_ENTER_EXIT_FUNCTION
+#define MXL_ENTER_FUNCTION(fmt, args...) ClnkOsal_PrintLog(L_INFO, "+++ (%s), line: %d " fmt "\n",__func__, __LINE__, ##args)
+#define MXL_EXIT_FUNCTION(fmt, args...) ClnkOsal_PrintLog(L_INFO, "--- (%s), line: %d " fmt "\n",__func__, __LINE__, ##args)
+#else
+#define MXL_ENTER_FUNCTION(mod, fmt, args...)
+#define MXL_EXIT_FUNCTION(mod, fmt, args...)
+#endif
+
+#define LIBAPI_COMMENT(_fmt, args...)
+#define DEFINE_PREFIX(x)
+
+#if MXL_ENABLE_DEBUG_PRINT
+#define LIBAPI_LOG(_fmt, args...) DEBUG_PRINT(L_INFO, _fmt, ##args)
+#define LIBAPI_VERBOSE(_fmt, args...) DEBUG_PRINT(L_VERBOSE, _fmt, ##args)
+#else
+#define LIBAPI_LOG(_fmt, args...) printf("%s(%d): LIBJPA_LOG: " _fmt "\n", __FILE__, __LINE__, ##args )
+#define LIBAPI_VERBOSE(_fmt, args...)
+#endif
+
+/** During the Pre Alpha release of Jaws, c.LINK Daemon was
+ * heavily simplified in a temporary fashion to quickly
+ * enable all headline applcations 'clnkstat', 'clnkmem',
+ * 'clnkcfg', etc to function as per external requirements.
+ * This macro marks places boundaries between jaws temporary
+ * development and the existing daemon design. BRADMBX */
+#define LIBAPI_OFFICIAL_DESIGN 0
+typedef enum
+{
+ CCPU_IDX=0,
+ CLINK_IDX,
+ MCAST_IDX,
+ RLAPM_IDX,
+ ENDET_IDX,
+ SAPM_IDX,
+ RSSI_IDX,
+ PLATFORM_IDX,
+ MAX_FW_IDX,
+}firmware_idx_t;
+
+typedef struct
+{
+ uint32_t size;
+ uint8_t *data;
+ void **pages;
+} clnk_fw_entry_t;
+
+typedef struct
+{
+ clnk_fw_entry_t *fw_entry[MAX_FW_IDX];
+ uint32_t ret;
+} clnk_firmware_t;
+
+/*****************************************************************************
+ * Types
+ ******************************************************************************/
+
+typedef struct
+{
+ uint32_t hi;
+ uint32_t lo;
+} flags_t;
+
+
+typedef struct
+{
+ int mcastUseBackupOnly; //mcast
+} comm_cfg_msg_struct;
+
+typedef struct
+{
+ uint32_t diplexer;
+ uint32_t miiClkDelay;
+ uint32_t freq;
+ uint32_t platHwCfg;
+}ClnkLib_BoardInfo_t;
+
+typedef enum
+{
+ //API Return Codes
+ CLNK_OK = 0,
+ CLNK_ERR = -1,
+ CLNK_NODEV = -2,
+ CLNK_WHICHDEV = -3,
+ CLNK_TIMEOUT = -4,
+ CLNK_WRONGVER = -5,
+ CLNK_PERM = -6,
+ //c.LINK Common Return Codes for CD, driver
+ CLNK_MEM_ALLOC_ERR = -7,
+ CLNK_RESET_ERR = -8,
+ CLNK_NOT_OPEN_ERR = -9,
+ CLNK_LINK_DOWN_ERR = -10,
+ CLNK_NO_HOST_DESC_ERR = -11,
+ CLNK_UCAST_FLOOD_ERR = -12,
+ CLNK_NO_KEY_ERROR = -13,
+
+ CLNK_RET_CODE_MAX = -14 // This must always be last
+} CLNK_RET_CODES;
+
+
+enum
+{
+ NO_DATA_MAXLINEAR, //'MAXLINEAR' ends conflict with linux networking 'NO_DATA' sym
+ IQ_RX_I_COEF,
+ IQ_RX_Q_COEF,
+ IQ_RX_DELAY,
+ IQ_RX_DBINS,
+ IQ_RX_DSLOPE,
+ IQ_TX_I_COEF,
+ IQ_TX_Q_COEF,
+ IQ_TX_DBINS,
+ IQ_TX_DSLOPE,
+ FREQ_OFFSET,
+ RANGE_VALID,
+ NODE_DELAY,
+ RX_CP_LEN,
+ RX_CP_LEN2,
+ RX_CHN_PRECUR_BIAS,
+ TX_CP_LEN,
+ AGC_ANALOG_GAIN,
+ AGC_FRONTEND_GAIN,
+ AGC_DIGI_GAIN,
+ RX_BITLOADING,
+ RX_EVM,
+ RX_NUM_SYMBOLS,
+ RX_BITS_PER_SYMBOL,
+ RX_CHN_USABLE,
+ RX_PREAMBLE,
+ RX_TPC_BACKOFF,
+ TX_BITLOADING,
+ TX_NUM_SYMBOLS,
+ TX_BITS_PER_SYAMBOL,
+ TX_CHN_USABLE,
+ TX_PREAMBLE,
+ TX_TPC_BACKOFF,
+};
+
+enum
+{
+ //normal operation
+ JAWS_NORMAL_OPERATION = 0,
+
+ //continuous transmit mode
+ JAWS_HARDWARE_TEST_MODE = 1,
+
+ //continuous wave mode
+ JAWS_CONTINUOUS_WAVE_MODE = 2,
+
+ /* no SoC download mode
+ * freqIdx = testparam1[6:0] with freqIdx = (freq(MHz)-450)/12.5
+ * vcoMode = testparam1[9:8]
+ * 0x0 = normal mode (no override)
+ * 0x1 = synth1
+ * 0x2 = synth2
+ * 0x3 = TBD
+ */
+ JAWS_NO_SOC_DOWNLOAD_MODE = 3,
+
+ //no health monitoring mode
+ JAWS_NO_HEALTH_MONITOR_MODE = 4,
+
+ //test harness mode
+ JAWS_TWOTONE_MODE = 5,
+ JAWS_DIPLEXER_CAL_MODE = 6,
+ JAWS_CONSTANT_TRANSMIT_50 = 7,
+
+ /* new test mode, formally testmode=0 testparam1=0x8000
+ * tpcBackoff = testparam1[5:0]
+ */
+ JAWS_CONSTANT_TRANSMIT_100 = 8,
+
+ /* new test mode, formally testmode=0 testparam1=0x11000
+ * tpcBackoff = testparam1[5:0]
+ */
+ JAWS_CONSTANT_RECEIVE_100 = 9,
+
+ /* testparam1 = log_gain (0 - 72)
+ * testparam2 = test_mux_select (0 - 7)
+ * if both testparam1 and testparam2 are == 0, default mode
+ */
+ JAWS_MAC_LOOPBACK_MODE = 10,
+ JAWS_TEST_TX_SNR = 11,
+
+ /* tpcBackoff = testparam1[5:0]
+ *numCarriers = testparam1[17:8] - default=4
+ * toneMode = testparam1[20] - default=0, notchMode
+ * carrier0 = testparam2[31:0]
+ */
+ JAWS_TEST_PWRSUP_TRANSIENTS = 12,
+
+ JAWS_DIPLEXER_BHR_LAN_TX_MODE = 13,
+ JAWS_CONSTANT_RECEIVE_50 = 15,
+ JAWS_CONSTANT_TRANSMIT_SEC_100 = 16,
+ JAWS_CONSTANT_TRANSMIT_BOND_100 = 17,
+ SOC_CONSTANT_TRANSMIT_CHN2_100 = 18,
+ SOC_CONSTANT_TRANSMIT_CHN3_100 = 19,
+ SOC_CONSTANT_TRANSMIT_CHN4_100 = 20,
+ SOC_CONSTANT_TRANSMIT_5CHNS_100 = 21,
+ SOC_CONSTANT_TRANSMIT_3CHNS_100 = 22,
+ SOC_CONSTANT_TRANSMIT_4CHNS_100 = 23,
+ SOC_CONSTANT_TRANSMIT_CHN1_100 = 25,
+ SOC_CONSTANT_TRANSMIT_CHN0_100 = 26,
+ MAX_TEST_MODE,
+};
+
+#define MAX_NODES 16
+#define MAX_OFDMA_TABLES 8
+#define MAX_OFDMA_PROFILES 3
+#ifndef IFNAMSIZ
+//#define IFNAMSIZ 16
+#endif
+#define MAX_BRIDGE_ENTRIES 192
+// QOSTODO: shrink this for memory savings?
+#define MAX_FLOWS_IN_LIST 32
+#define MAX_FILE_NAME 256
+#define DEFAULT_CLINK_CONFIG_PATH "/etc/clink/"
+#define DEFAULT_FW_PATH "/lib/firmware/"
+
+#if FEATURE_SAPM
+#define SS_CARRIER_DISABLED 0xff // force bit loading of 0
+#define SS_THRESHOLD_MIN 0 // valid min threshold value
+#define SS_THRESHOLD_MAX 65 // valid max threshold value
+#endif
+
+///model for read configuration file
+#ifndef USE_BACKUP_ONLY
+///read backup configuration file only
+#define USE_BACKUP_ONLY 1
+#endif
+#ifndef USE_BACKUP_FIRST
+///first read backup configuration file, then override with current configuration file
+#define USE_BACKUP_FIRST 0
+#endif
+
+///Table 7.9.6 Multicast Filter Configuration
+//
+#define CFG_MCAST_FILTER_MODE "filtermode"
+///there could be 1-48 entries prefiexed with string below
+#define CFG_MCAST_MAC_PREFIX "mcastmacaddr"
+
+
+// Energy detect array dimensions
+#define MAX_ATSC_CATV_FREQS 4
+#define MAX_ATSC_CATV_GAPS 8
+#define MAX_WEIGHTS 4
+#define MAX_BTS_CSS_FREQS 6
+#define MAX_BTS_CSS_VALUES 5
+
+// Energy detection related constant
+#define CATV_DETECTED 1<<0
+#define OTA_ATSC_DETECTED 1<<1
+#define CSS_DETECTED 1<<2
+#define BTS_DETECTED 1<<3
+#define NUM_BAND_E_100MHZ_RANK 5
+#define NUM_BAND_F_100MHZ_RANK 6
+#define NUM_BAND_D_100MHZ_RANK 19
+
+#define NUM_BAND_E_50MHZ_RANK 7
+#define NUM_BAND_F_50MHZ_RANK 8
+#define NUM_BAND_D_50MHZ_RANK 21
+
+// Spectrum Analyzer Definitions
+#define MIN_SPECTRUM_FREQUENCY 400
+#define MAX_SPECTRUM_FREQUENCY 1750
+
+// Production and BondOption register Definitions, only for API function usage
+#define SYS_RES_PRODUCT_FAMILY_ID 0x08200000
+#define SYS_RES_EXT_CONFIG_STATUS 0x0820000c
+#define SYS_RES_BOND_OPT_MASK 0x000f0000
+#define SYS_RES_BOND_OPT_SKU_MASK 0x003f0000
+#define SYS_RES_BOND_OPT_OFFSET 16
+
+typedef unsigned char ClnkLib_NodeId_t;
+typedef unsigned int ClnkLib_NodeMask_t;
+
+
+typedef struct
+{
+ uint32_t mocaVer;//default 20
+ // uint32_t clinkGuidHi; ///TODO API document no such field
+ // uint32_t clinkGuidLo; ///TODO API document no such field
+ uint32_t testMode;//def val 0
+ uint32_t clnkLedMode;//def val 1
+ uint32_t turboMode;//def val 0
+ uint32_t testParam1;
+ uint32_t testParam2;
+ uint32_t testParam3;
+ uint32_t testParam4;
+
+ int32_t miiPausePriLevel; //def val -1
+ uint32_t miiSpeed; ///i.e. XmiiSaf;
+ uint32_t policingMode;// defal disabled 0, enabled 1 using only 1bit
+ uint32_t pqosClassifyMode; //defval is moca1.1 classification(0), other val is pre upnp classification(1)
+ /*
+ *bit 3: high priority enable
+ *bit 2: medium priority enable
+ *bit 1: low priority enable
+ *bit 0: background priority enable
+ */
+ uint32_t retxPriority;//defal 0
+ /*
+ *bit 3: high priority (NPER(0) or VLPER(1))
+ *bit 2: medium priority(NPER(0) or VLPER(1))
+ *bit 1: low priority(NPER(0) or VLPER(1))
+ *bit 0: background priority(NPER(0) or VLPER(1))
+ *
+ */
+ uint32_t txPriorityPer;
+ // uint32_t datapathMode; ///TODO API document no such field Jaws SoC Hi document has
+ // uint32_t xmiiSaf; ///TODO API document no such field Jaws SoC Hi document has
+
+
+ //control parameters
+ /**
+ * this field is used only when the node is NC.
+ *
+ * disabled(0),
+ * enabled(1)
+ */
+ uint32_t failoverMode;//defval 1
+ /**
+ * this field is used only when the node is NC.
+ *
+ * disabled(0),
+ * enabled(1)
+ */
+ uint32_t handoffMode;//defval 1
+ /**
+ * this field is used only when the node is NC.
+ *
+ * disabled(0),
+ * enabled(1)
+ */
+ uint32_t initialRole;//defval normal(0), NC only(1) client only(2)
+
+ uint32_t lmoMode;//defval 1
+ uint8_t mocaPasswd[18];//defval "99999999988888888"
+ /**
+ * the preferred NC mode for the c.Link device.
+ * the values for preferred NC mode are follows:
+ * disabled(0), enabled(1);
+ */
+ uint32_t preferredNcMode;//defval disabled(0), enabled(1)
+ /**
+ * the security mode for c.Link device.
+ * the values for security mode are follows:
+ * disabled(0), enabled(1)
+ */
+ uint32_t securityMode;//defval disabled(0), enabled(1)
+ /**
+ * the network search mode for the c.Link device.
+ * the values for network search mode are as follows:
+ * disabled(0), enabled(1)
+ */
+
+ uint32_t networkSearchMode;//defval 1
+ /**
+ * the frequency plan for the c.Link device.
+ * the values for freq plan are defined as below:
+ * Band D(0), Extended Band D(1),
+ * Sub-Band D-Low(2), Sub-Band D-High (3)
+ * Band M(4)
+ */
+ uint32_t freqPlan; ///defval 1
+ /**
+ * the channel mask defines the "active" channels that user
+ * has selected. the channel represents the center freq of
+ * the beacon.
+ *
+ * For Extended Band D, the bits for channel mask are defined
+ * as follows: bit 32(1150 MHz), bit 30(1175MHz), ... and bit
+ * 12(1625 MHz).
+ *
+ * For Sub-Band D-Low, the bits for channel mask are defined as
+ * follow: bit 31 (1175 MHz).
+ *
+ * For Sub-Band D-High, the bits for channel mask are define as
+ * follow: bit 31 (1400 MHz), bit 30 (1425 MHz),...and bit 22
+ * (1625 MHz)
+ *
+ * For Band M, the bits for channel mask are defined as follows:
+ * bit 31 (500 MHz), bit 30 (525 MHz),...and bit 16 (875 MHz).
+ *
+ */
+ uint32_t channelMask;///defval 0xfffff000
+
+ /**
+ * the last operating freq(lof) for the c.Link device.
+ *
+ * the values for lof are:
+ * none(-1) or the freq value(e.g. 1150 MHz)
+ *
+ * the default value for lof is different based on the freq plan.
+ * the default values are as follows:
+ *-----------------------------
+ * |Frequency Plan | Default |
+ * ----------------------------
+ * |Band D | -1 |
+ * ----------------------------
+ * |Extended Band D | 1150 MHz|
+ * ----------------------------
+ * |Sub-Band D-Low | 1150 MHz|
+ * ----------------------------
+ * |Sub-Band D-High | 1400 MHz|
+ * ----------------------------
+ * |Band M | 525 MHz |
+ * ----------------------------
+ */
+ int32_t lof;///defval is 1150
+ /**
+ * the primary channel offset is the center freq of the primary
+ * channel relative to the channel for the beacon.
+ * this field is used only when the Node is NC.
+ */
+ uint32_t primChnOffset;/// Mask of primary channel offsets
+ /**
+ * the secondary channel offset is the center freq of the secondary
+ * channel relative to the channel for the beacon.
+ * this field is used only when the Node is NC.
+ */
+ uint32_t secChnOffset;/// Mask of secondary channel offsets
+
+ uint32_t tabooMask; //defval 0xee0000
+ uint32_t tabooOffset; //defval 3
+ uint32_t tlpMin; //defval 0
+ uint32_t tlpMax; //defval 95
+
+ uint32_t tpcMode;
+ uint32_t tpcPhyRate50;
+ uint32_t tpcPhyRateNper;
+ uint32_t tpcPhyRateVlper;
+ uint32_t encWordLenNper;
+ uint32_t encWordLenVlper;
+ /**
+ * The beacon transmit power for the c.LINK device
+ * when TPC is enabled. The values for transmit power
+ * are the same as defined for the Maximum TX Power
+ * parameter
+ */
+ uint32_t beaconTxPower;///defval 10
+ /**
+ * The beacon transmit power for the c.LINK device
+ * when TPC is enabled. The values for transmit power
+ * are the same as defined for the
+ * Maximum TX Power parameter
+ * Value ECB (dBM) Mini Card (dBM)
+ * 0 -28 -31
+ * 1 -25 -28
+ * 2 -22 -25
+ * 3 -19 -22
+ * 4 -16 -19
+ * 5 -13 -16
+ * 6 -10 -13
+ * 7 -7 -10
+ * 8 -4 -7
+ * 9 -1 -3
+ * 10 +2 0
+ *
+ */
+ uint32_t maxTxPower;///defval 10
+ uint32_t phyMargin50;
+ uint32_t phyMarginNper;
+ uint32_t phyMarginVlper;
+ uint32_t featureFlags;
+
+ //added to indicate whether write to flash
+ //int32_t update;
+
+ uint32_t mocaSeqNumMr;
+} ClnkLib_StaticCfg_t;
+
+
+///c.LINK Configuration Parameters
+typedef MXL_MOCA_CFG_V2_T ClnkLib_ClnkCfgV2_t;
+
+/***************************************************
+ *Gets the current device status.
+ *
+ **************************************************/
+typedef struct
+{
+ uint32_t status; /// Booting or active
+ uint32_t resetCount;
+} ClnkLib_DevStatus_t;
+
+typedef struct
+{
+ uint32_t cdUpTimeInSecs;
+ uint32_t linkUpTimeInSecs;
+ uint32_t resetCount;
+ uint32_t resetHistory;
+ uint32_t resetLine;
+ uint32_t resetEpc;
+ uint32_t linkLostCount; // link lost count record
+ uint32_t drvVersionStr[MAX_HOST_VERSION_STR_SIZE / 4];
+ uint32_t pkgVersionStr[MAX_HOST_VERSION_STR_SIZE / 4];
+}
+ClnkLib_CdInfo_t;
+
+typedef MXL_MOCA_MCAST_CFG_T ClnkLib_McastCfg_t;
+
+typedef struct
+{
+ uint32_t pktsTx2Node[MAX_NUM_NODES];
+} ClnkLib_MacDataStats_t;
+
+typedef struct
+{
+ //uint32_t maxPktsPerAggr;
+ uint32_t txAggr[MAX_AGGR_FRAMES_V25];
+ uint32_t rxAggr[MAX_AGGR_FRAMES_V25];
+} ClnkLib_AggrStats_t;
+
+typedef struct
+{
+ uint32_t ucastDstEntries;
+ uint32_t mcastDstEntries;
+ uint32_t pqosDstEntries;
+ //uint32_t totalSourceEntries; changed to ucastSrcEntries and mcastSrcEntries
+ uint32_t ucastSrcEntries;
+ uint32_t mcastSrcEntries;
+ uint32_t totalHits;
+ uint32_t totalMisses;
+} ClnkLib_BridgeStats_t;
+
+typedef struct
+{
+ uint32_t macAddrHi;
+ uint32_t macAddrLoIds;
+} ClnkLib_BridgeEntry_t;
+
+typedef struct
+{
+ //int32_t numEntries;
+ //char macAddr[16];
+ ClnkLib_BridgeEntry_t entry[MAX_BRIDGE_ENTRIES];
+ //the two below do not need according to
+ //table 16 Bridge Entry Element in
+ //JawsHostCcpuInterface.028-TO_KEN.DOCX
+ //clink_node_id_t destNodeId;
+ //flow_id_t destFlowId;
+} ClnkLib_BridgeTable_t;
+
+
+typedef struct
+{
+ uint32_t sgmii0Rx;
+ uint32_t sgmii0Tx;
+ uint32_t pcieRx;
+ uint32_t pcieTx;
+ uint32_t sgmii1Rx;
+ uint32_t sgmii1Tx;
+ uint32_t mocaRx;
+ uint32_t mocaTx;
+
+ uint32_t debug0;
+ uint32_t debug1;
+ uint32_t debug2;
+ uint32_t debug3;
+ uint32_t debug4;
+ uint32_t debug5;
+ uint32_t debug6;
+ uint32_t debug7;
+ uint32_t debug8;
+ uint32_t debug9;
+ uint32_t debug10;
+ uint32_t debug11;
+ uint32_t debug12;
+ uint32_t debug13;
+ uint32_t debug14;
+ uint32_t debug15;
+ uint32_t debug16;
+
+} ClnkLib_EcbStats_t;
+
+typedef struct
+{
+ uint32_t miiPausePriLvl;
+ uint32_t miiSpeed;
+ uint32_t rxGood[2];
+ uint32_t rxDrop[2];
+ uint32_t rxError[2];
+ uint32_t txGood[2];
+ uint32_t txDrop[2];
+ uint32_t txError[2];
+} ClnkLib_EphyStats_t;
+
+typedef struct
+{
+ uint32_t rxGood[4];
+ uint32_t rxDrop[4];
+ uint32_t rxError[4];
+ uint32_t txGood[4];
+ uint32_t txDrop[4];
+ uint32_t txError[4];
+} ClnkLib_SwitchStats_t;
+
+typedef struct
+{
+ uint32_t macHi;
+ uint32_t macLo;
+ uint32_t tmo;
+ uint32_t vlanCheck[2];
+ uint32_t vlanStrip[2];
+ uint32_t vlanPvid[2];
+ uint32_t vlanId[2][SWITCH_PORT_MAX_VLAN_IDS];
+} ClnkLib_SwitchConfig_t;
+
+
+/* eSwitch config:
+ * ---------------
+ * eSwitch port control eSwitchPortConfig[2:0]
+ * A value of 1 in a given bit position indicates disable. Default port setting is 000'b
+ * Bit0 EPHY0(RGMII)
+ * Bit1 EPHY1(SGMII)
+ * Bit2 MoCA ifc.
+ * Other bits are reserved
+ */
+typedef struct
+
+{ uint32_t eSwitchPortConfig;
+} ClnkLib_SwitchPortConfig_t; /* Hi_TxnSetSwitchPortConfigCmd_t */
+
+typedef struct
+{
+ uint32_t retxFrames[MAX_NODES];
+ uint32_t txTimeout[MAX_NODES];
+} ClnkLib_RetxStats_t;
+
+typedef struct
+{
+ uint64_t txTotalPkts;
+ uint64_t txTotalBytes;
+ uint64_t txDroppedPkts;
+ uint64_t txBcastPkts;
+ uint64_t txBcastBytes;
+ uint64_t txMcastPkts;
+ uint64_t txMcastBytes;
+ uint64_t txUcastPkts[MAX_NUM_NODES];
+ uint64_t txUcastBytes[MAX_NUM_NODES];
+ uint64_t txGoodPktsInLast60s[MAX_NUM_NODES];
+ uint64_t txDroppedPktsInLast60s[MAX_NUM_NODES];
+ uint64_t rxTotalPkts;
+ uint64_t rxTotalBytes;
+ uint64_t rxDroppedPkts;
+ uint64_t rxBcastPkts[MAX_NUM_NODES];
+ uint64_t rxBcastBytes[MAX_NUM_NODES];
+ uint64_t rxMcastPkts[MAX_NUM_NODES];
+ uint64_t rxMcastBytes[MAX_NUM_NODES];
+ uint64_t rxUcastPkts[MAX_NUM_NODES];
+ uint64_t rxUcastBytes[MAX_NUM_NODES];
+ uint64_t rxGoodPktsInLast60s[MAX_NUM_NODES];
+ uint64_t rxBadPktsInLast60s[MAX_NUM_NODES];
+} ClnkLib_DataStats_t;
+
+typedef struct
+{
+ uint32_t rxFragFrames;
+ uint32_t txFragFrames;
+} ClnkLib_FragStats_t;
+
+typedef struct
+{
+ uint32_t l2meIssuedTxns;
+ uint32_t l2meSuccessfulTxns;
+ uint32_t l2meTimedOutCycles;
+ uint32_t l2meFailedTxns;
+} ClnkLib_L2meStats_t;
+
+typedef struct
+{
+ uint64_t txMapGood;
+ uint64_t txMapError;
+ uint64_t txMapDropped;
+ uint64_t rxMapGood;
+ uint64_t rxMapError;
+ uint64_t rxMapDropped;
+ uint64_t txRrGood;
+ uint64_t txRrError;
+ uint64_t txRrDropped;
+ uint64_t rxRrGood;
+ uint64_t rxRrError;
+ uint64_t rxRrDropped;
+ uint64_t txLcfGood;
+ uint64_t txLcfError;
+ uint64_t txLcfDropped;
+ uint64_t rxLcfGood;
+ uint64_t rxLcfError;
+ uint64_t rxLcfDropped;
+ uint64_t txBcnGood;
+ uint64_t txBcnError;
+ uint64_t txBcnDropped;
+ uint64_t rxBcnGood;
+ uint64_t rxBcnError;
+ uint64_t rxBcnDropped;
+ uint64_t txAcfGood;
+ uint64_t txAcfError;
+ uint64_t txAcfDropped;
+ uint64_t rxAcfGood;
+ uint64_t rxAcfError;
+ uint64_t rxAcfDropped;
+ uint64_t txProbeGood;
+ uint64_t txProbeError;
+ uint64_t txProbeDropped;
+ uint64_t rxProbeGood;
+ uint64_t rxProbeError;
+ uint64_t rxProbeDropped;
+ uint64_t txEthGood;
+ uint64_t txEthError;
+ uint64_t txEthDropped;
+ uint64_t rxEthGood;
+ uint64_t rxEthError;
+ uint64_t rxEthDropped;
+
+ uint64_t txOfdmaRrGood;
+ uint64_t txOfdmaRrError;
+ uint64_t txOfdmaRrDropped;
+ uint64_t rxOfdmaRrGood;
+ uint64_t rxOfdmaRrError;
+ uint64_t rxOfdmaRrDropped;
+
+ uint64_t txOfdmaEvmGood;
+ uint64_t txOfdmaEvmError;
+ uint64_t txOfdmaEvmDropped;
+ uint64_t rxOfdmaEvmGood;
+ uint64_t rxOfdmaEvmError;
+ uint64_t rxOfdmaEvmDropped;
+} ClnkLib_FrameStats_t;
+
+typedef struct
+{
+ uint32_t nodeId;
+ uint32_t ncNodeId;
+ uint32_t nextNcNodeId;
+ uint32_t backupNodeId;
+ uint32_t lmoNodeId;
+ uint32_t linkStatus;
+ uint32_t lastAdmStatus;
+ uint32_t beaconRxPwrLevel; /* Beacon Rx power level (dBm) */
+ uint32_t role;
+ uint32_t networkState;
+ uint32_t resetCnt;
+ uint32_t networkMocaVer;
+ uint32_t activeNodeBitmask;
+ uint32_t sleepM1NodeBitmask;
+ uint32_t sleepM2NodeBitmask;
+ uint32_t sleepM3NodeBitmask;
+ uint32_t tabooMask;
+ uint32_t tabooOffset;
+ int32_t priChnOffset;
+ int32_t secChnOffset;
+ uint32_t pqosFlowPolicingFlag;
+ uint32_t socVersionStr[MAX_VERSION_STR_SIZE / 4];
+ uint32_t reqStatus;
+ uint32_t customBandProfCGapMode;
+} ClnkLib_LocalInfo_t;
+
+typedef struct
+{
+ //clink_guid_t guid;
+ uint32_t guidHi;
+ uint32_t guidLo;
+ uint32_t state; // Inactive (0), assigned (1), MAP active (2), admitted (3),
+ // active (4), low power idle (5), standby (6), sleep (7)
+ uint32_t protoSupport;
+ uint32_t mocaVer;
+ uint64_t txFrameGood;
+ uint64_t txFrameError;
+ uint64_t txFrameDropped;
+ uint64_t rxFrameGood;
+ uint64_t rxFrameError;
+ uint64_t rxFrameDropped;
+ uint64_t txDataFrameGood;
+ uint64_t txDataFrameDropped;
+ uint64_t rxDataFrameGood;
+ uint64_t rxDataFrameBad;
+} ClnkLib_NetInfo_t;
+
+typedef struct
+{
+ uint32_t status;
+ uint32_t fatalCode;
+ uint32_t state;
+ uint32_t dbg;
+ uint32_t bbTemp;
+ uint32_t rfTemp;
+} ClnkLib_SocStatus_t;
+
+
+typedef struct
+{
+ uint8_t gapNper;
+ uint8_t gapVLper;
+ uint16_t ofdmbNper;
+ uint16_t ofdmbVLper;
+} ClnkLib_NodeFmrInfo_t;
+
+typedef struct
+{
+ uint32_t numOfNodes;
+ uint32_t nodeMask;
+ struct
+ {
+ uint32_t validInfo;
+ struct
+ {
+ uint8_t gapNper;
+ uint8_t gapVLper;
+ uint16_t ofdmbNper;
+ uint16_t ofdmbVLper;
+ uint16_t rateNper;
+ uint16_t rateVLper;
+ } p2p[MAX_NODES];
+ uint8_t gapGcd;
+ uint16_t ofdmbGcd;
+ uint16_t rateGcd;
+ uint8_t defTableNum;
+ struct
+ {
+ uint32_t nodeBitmask;
+ uint8_t subchannelNum;
+ uint8_t gapOfdma;
+ uint16_t ofdmab;
+ uint16_t rateOfdma;
+ } ofdma[3];
+ } nodeFmr[MAX_NODES];
+} ClnkLib_FmrInfo_t;
+
+typedef enum
+{
+ CLNK_LIB_DD_DEV_ATTR_PQOS,
+ CLNK_LIB_DD_DEV_ATTR_AGGR,
+ CLNK_LIB_DD_DEV_ATTR_MAP,
+ CLNK_LIB_DD_DEV_ATTR_BND_AGGR,
+ CLNK_LIB_DD_DEV_ATTR_MOCA25_AGGR,
+ CLNK_LIB_DD_DEV_ATTR_MAX,
+ MAX_DD_IES = CLNK_LIB_DD_DEV_ATTR_MAX /* # of Device discovery attrib */
+}ClnkLib_DDdevAttrID_t;
+
+typedef struct
+{
+ uint32_t numOfNodes;
+ struct
+ {
+ uint32_t nodeId;
+ uint32_t numOfAttr;
+ struct
+ {
+ uint8_t attrId;
+ uint8_t attrLen;
+ union
+ {
+ struct
+ {
+ uint8_t supportPqosIngressFlows;
+ uint8_t supportPqosEgressFlows;
+ } ClnkLib_NodeDdIePqos;
+
+ struct
+ {
+ uint8_t pduNum;
+ uint8_t aggrSize;
+ } ClnkLib_NodeDdIeRcvAggr;
+
+ struct
+ {
+ uint8_t aeNum;
+ uint8_t reserved2;
+ } ClnkLib_NodeDdIeMapProc;
+ } ddIe;
+ } AttrData[MAX_DD_IES];
+ } nodeDd[MAX_NODES];
+ uint32_t nodeOffset;
+} ClnkLib_DdInfo_t;
+
+typedef enum
+{
+ CLNK_LIB_ACA_TYPE_QUIET, //!< Quiet line
+ CLNK_LIB_ACA_TYPE_EVM //!< EVM type
+}
+ClnkLib_AcaType_t;
+
+//! ACA status codes
+typedef enum
+{
+ CLNK_LIB_ACA_STATUS_SUCCESS, //!< Operation successful
+ CLNK_LIB_ACA_STATUS_TUNE_FAILED, //!< Failed: Unable to tune to selected channel
+ CLNK_LIB_ACA_STATUS_NO_PROBES, //!< Failed: No EVM probe was detected
+ CLNK_LIB_ACA_STATUS_GEN_ERROR //!< Failed: Other reason
+}
+ClnkLib_AcaStatus_t;
+
+//! Handoff request information
+typedef struct
+{
+ uint32_t nodeId; //!< Source node ID
+ uint32_t isBnc;
+}
+ClnkLib_HandoffRequest_t;
+
+//! LMO type
+typedef enum
+{
+ CLNK_LIB_LMO_TYPE_OOO_LMO, //!< Out of order LMO
+ CLNK_LIB_LMO_TYPE_RX_DET_PROBE, //!< Receiver determined probe
+ CLNK_LIB_LMO_TYPE_UNSOL_PROBE_RPT, //!< Unsolicited probe report
+ CLNK_LIB_LMO_TYPE_SILENT_PROBE, //!< Silent probe report
+ CLNK_LIB_LMO_TYPE_LB_PROBE, //!< Loopback probe report
+ CLNK_LIB_LMO_TYPE_ACA //!< Alternate Channel Assessment
+}
+ClnkLib_LmoType_t;
+
+//! LMO request information
+typedef struct
+{
+ ClnkLib_LmoType_t type; //!< LMO type
+ union
+ {
+
+ struct
+ {
+ ClnkLib_AcaType_t type; //!< Assessment type
+ uint32_t channel; //!< Alternate channel
+ uint32_t srcNodeId; //!< Source node ID
+ uint32_t dstNodeMask; //!< Destination node bit mask
+ } aca; // prev was ClnkLib_AcaRequest_t
+
+ struct
+ {
+ uint32_t nodeId; //!< OOO lmo node ID
+ } ooo;
+
+ struct
+ {
+ uint32_t type; //!< 0 - Unicast, 1 OFDMA
+ uint32_t nodeMask; //!< Mask of nodes invloved
+ } upr;
+
+ struct
+ {
+ uint32_t nodeId; //!< Tx node Id
+ uint32_t probeId; //!< Pre-Defined Probe identifier
+ } rdp;
+
+ struct
+ {
+ uint32_t timeSlots;
+ } silent;
+
+ struct
+ {
+ uint32_t timeSlots;
+ } loopBack;
+
+ } data;
+}
+ClnkLib_LmoRequest_t;
+
+//! LMO report information
+typedef struct
+{
+ uint32_t type; //!< LMO type
+ uint32_t nodeId; //!< LMO node ID
+ uint32_t result;
+
+ union
+ {
+ struct
+ {
+ ClnkLib_AcaType_t type; //!< Assessment type
+ ClnkLib_AcaStatus_t txStatus; //!< TX Operation status
+ ClnkLib_AcaStatus_t status; //!< Operation status
+ uint32_t power; //!< Total power
+ uint32_t relativePower; //!< Total relative power
+ uint8_t powerProfile[LMO_ACA_RPT_PWR_PRFL_SZ]; //!< Received spectral power profile
+ } aca;
+ } data;
+
+}
+ClnkLib_LmoReport_t;
+
+
+
+//! Topology report information
+typedef struct
+{
+ uint32_t nodeId; //!< Node ID for topology information
+ uint32_t nperGap[16];
+ uint32_t nperBitsPerSym[16];
+ uint32_t vlperGap;
+ uint32_t vlperBitsPerSym[16];
+ uint32_t gcd50Gap;
+ uint32_t gcd50BitsPerSym;
+ uint32_t ofdmaNumTables;
+ uint32_t ofdmaNodeBitmask[MAX_OFDMA_TABLES];
+ uint32_t ofdmaNumSubChannels[MAX_OFDMA_TABLES];
+ uint32_t ofdmaGap[MAX_OFDMA_TABLES];
+ uint32_t ofdmaBitsPerSym[MAX_OFDMA_TABLES];
+}
+ClnkLib_TopoReport_t;
+
+
+//! MoCA Reset request structure
+typedef struct
+{
+ uint32_t lof;
+ uint32_t nodemask;
+ uint32_t seconds;
+ /* Hi_TxnMocaResetRequest_t*/
+} ClnkLib_MocaResetRequest_t;
+
+//! MoCA Reset Code- result of operation attempt
+typedef enum
+{
+ CLNKLIB_MRCODE_LIB_ERROR, //!< No Reset Issued: library error
+ CLNKLIB_MRCODE_SUCCESS_PART, //!< Partial network reset issued and scheduled
+ CLNKLIB_MRCODE_SUCCESS_NW, //!< Entire network reset issued and scheduled
+ CLNKLIB_MRCODE_FAIL_CLEAN, //!< Nodes refused to reset, transaction completed
+ CLNKLIB_MRCODE_FAIL_UNKNOWN1, //!< L2ME transaction did not complete correctly
+ CLNKLIB_MRCODE_FAIL_UNKNOWN2, //!< L2ME transaction did not complete correctly
+ CLNKLIB_MRCODE_FAIL_TIMEOUT, //!< L2ME transaction did not take place
+ CLNKLIB_MRCODE_FAIL_NO_NODES, //!< no nodes selected, no L2ME transaction
+ /* Hi_MRCode_t*/
+} ClnkLib_MRCode_t;
+
+//! MoCA Reset response structure
+typedef struct
+{
+ uint32_t mrCode;
+ uint32_t issuedNodemask;
+ uint32_t topLastResetStatus;
+ uint32_t nodeLastResetStatus[MAX_NODES];
+ uint32_t nodeLastResponseCode[MAX_NODES];
+ /* Hi_TxnMocaResetResponse_t*/
+} ClnkLib_MocaResetResponse_t;
+
+
+//! Maximum number of bytes for NMS response
+//
+//! NMS operation type
+typedef enum
+{
+ CLNK_LIB_NMS_TYPE_REQUESTED
+}
+ClnkLib_NmsType_t;
+
+//! NMS request information
+typedef struct
+{
+ uint32_t reserved; //!< Reserved
+}
+ClnkLib_NmsRequest_t;
+
+//! NMS response information
+typedef struct
+{
+ uint32_t result;
+}
+ClnkLib_NmsReport_t;
+
+typedef struct
+{
+ uint32_t active;
+ uint32_t assignmentTable[64];
+ uint32_t bitloading[64];
+ uint32_t maxDelay;
+ uint32_t delayOffset;
+ uint32_t ni;
+ uint32_t k;
+ uint32_t tpc;
+ uint32_t cpLen;
+}
+ClnkLib_PhyOfdma_t;
+
+
+typedef struct
+{
+ uint32_t txProfileValid;
+ uint32_t iqTxCoef;
+ uint32_t iqTxDelay;
+ uint32_t iqTxDslope_AB;
+ uint32_t iqTxDslope_CD;
+ uint32_t txCpLen;
+ uint32_t txNumSymbols;
+ uint32_t txBitsPerSymbol;
+ uint32_t txChnUsable;
+ uint32_t txPreamble;
+ uint32_t txTpcBackoff;
+ uint32_t txKLdpcMax;
+ uint32_t txPhyrate;
+ uint32_t seqNum;
+ uint32_t nodeMask;
+ uint32_t txBitloading[64];
+ /* Hi_TxnGetPhyTxProfileRsp_t*/
+} ClnkLib_PhyTxProfile_t;
+
+typedef struct
+{
+ uint32_t rxProfileValid;
+ uint32_t iqRxCoef;
+ uint32_t iqRxDelay;
+ uint32_t iqRxDslope_AB;
+ uint32_t iqRxDslope_CD;
+ uint32_t rxCpLen;
+ uint32_t rxChnPrecurBias;
+ uint32_t agc_b8_f8_digi16;
+ uint32_t agc_b8_f8_digi3_16;
+ uint32_t rxNumSymbols;
+ uint32_t rxBitsPerSymbol;
+ uint32_t rxChnUsable;
+ uint32_t rxPreamble;
+ uint32_t rxTpcBackoff;
+ uint32_t rxKLdpcMax;
+ uint32_t rxPhyrate;
+ uint32_t rxPwrLevel;
+ uint32_t seqNum;
+ uint32_t rxBitloading[64];
+ uint32_t rxChnSnr;
+ /* Hi_TxnGetPhyRxProfileRsp_t*/
+} ClnkLib_PhyRxProfile_t;
+
+
+typedef struct
+{
+ uint32_t valid;
+ uint32_t freqOffset;
+ uint32_t rangeValid;
+ uint32_t nodeDelay;
+ uint32_t validTxProf;
+ /* Hi_TxnGetPhyNodeRsp_t*/
+} ClnkLib_PhyNode_t;
+
+typedef struct
+{
+ uint32_t rxProfileValid;
+ uint32_t rxEvm[128];
+ /* Hi_TxnGetPhyEvmRsp_t*/
+} ClnkLib_PhyEvm_t;
+
+typedef struct
+{
+ uint32_t temperature;
+ uint32_t currentOperatingFrequency;
+ /* Hi_TxnGetPhyMiscRsp_t*/
+} ClnkLib_PhyMisc_t;
+
+typedef struct
+{
+ uint32_t temperature;
+ uint32_t currentOperatingFrequency;
+ uint32_t firstChannelFrequency;
+ uint32_t numberM25Channels;
+ /* Hi_TxnGetM25PhyMiscRsp_t*/
+} ClnkLib_M25PhyMisc_t;
+
+typedef struct
+{
+ struct
+ {
+ uint32_t subchanDefID;
+ uint32_t nodeBitmask;
+ uint32_t bitsPerSubchanelPerSym;
+ uint32_t gapOfdma;
+ uint32_t numSubchan;
+ } profile[MAX_OFDMA_PROFILES];
+ /* Hi_TxnGetPhyOfdmaDefRsp_t*/
+} ClnkLib_OfdmaDef_t;
+
+typedef struct
+{
+ struct
+ {
+ uint32_t frameID;
+ uint32_t subchanDefID;
+ uint32_t numSubchan;
+ uint32_t nodeBitmask;
+ uint32_t cpLen;
+ } profile[MAX_OFDMA_PROFILES];
+} ClnkLib_OfdmaAssign_t;
+/* Hi_TxnGetPhyOfdmaAssignRsp_t*/
+
+typedef struct
+{
+ int32_t result;
+ uint32_t ofdmaGrps;
+ uint32_t m2NodeMask;
+ uint32_t ofdmaNodeMask;
+ /*Hi_TxnGetOfdmaParamsRsp_t*/
+} ClnkLib_OfdmaParams_t;
+
+typedef struct
+{
+ int32_t result;
+ uint32_t usedProfileTypeMask;
+ uint32_t numAsgnTbls;
+ uint32_t blt[64];
+ uint32_t phyFrameId;
+ uint32_t preambleType;
+ uint32_t cpLen;
+ uint32_t kLdpcMax;
+ uint32_t rrUnitLength;
+ uint32_t rateMultNi;
+ uint32_t bitsPerSymbol;
+ int32_t TPC;
+ uint32_t propDelay;
+ int32_t propDelayOffset;
+ uint32_t propDelayMax;
+ int32_t freqOffset;
+ int32_t txIq[2];
+ /*Hi_TxnGetOfdmaTxProfileRsp_t*/
+} ClnkLib_OfdmaTxProfile_t;
+
+typedef struct
+{
+ int32_t result;
+ uint32_t numAsgnTbls;
+ uint32_t sumNi;
+ uint32_t blt[64];
+ uint32_t contextId[64];
+ uint32_t phyFrameId;
+ uint32_t clNodeMask;
+ uint32_t preambleType;
+ uint32_t cpLen;
+ uint32_t kLdpcMax;
+ uint32_t rrUnitLength;
+ uint32_t rateMultNi[8];
+ uint32_t bitsPerSymbolPerNi;
+ int32_t TPC[8];
+ uint32_t digitalGain;
+ uint32_t analogGain;
+ uint32_t feGain;
+ uint32_t beGain;
+ int32_t powerLevel;
+ uint32_t propDelayMax;
+ int32_t rxIq[2];
+ int32_t rxIdDslope[4];
+ /*Hi_TxnGetOfdmaRxProfileRsp_t*/
+} ClnkLib_OfdmaRxProfile_t;
+
+typedef struct
+{
+ uint32_t powerState;
+ uint32_t lastHbIvSecs;
+ int32_t ncHbIvExpiresInSecs;
+ uint32_t clStartedHbIvTimerCount;
+/* Hi_TxnQueryPmStateRsp_t*/
+} ClnkLib_QueryPmStateRsp_t;
+
+typedef struct
+{
+ uint32_t nodeId;
+ uint32_t isLocal;
+ uint32_t state;
+/* Hi_PmSleepEventData_t*/
+} ClnkLib_PmSleepEventData_t;
+
+typedef struct
+{
+ uint32_t nodeId;
+ uint32_t isLocal;
+/* Hi_PmWakeEventData_t*/
+} ClnkLib_PmWakeEventData_t;
+
+typedef struct
+{
+ uint32_t nodeId;
+ uint32_t isLocal;
+/* Hi_PmWomEventData_t*/
+} ClnkLib_PmWomEventData_t;
+
+typedef union
+{
+ ClnkLib_PmSleepEventData_t sleep;
+ ClnkLib_PmWakeEventData_t wake;
+ ClnkLib_PmWomEventData_t wom;
+/* Hi_PmEventData_t*/
+} ClnkLib_PmEventData_t;
+
+// QOSTODO: Scrub list of error codes
+typedef enum
+{
+ /** The operation succeeded. */
+ CLNKLIB_FLOWCODE_SUCCESS /*HI_FLOWCODE_SUCCESS*/ = 0x01,
+
+ /** The operation did not happen due to a network timeout during
+ * concurrent operations; in a typical network the application
+ * may retry the operation and expect the operation to happen. */
+ CLNKLIB_FLOWCODE_TIMEOUT /*HI_FLOWCODE_TIMEOUT*/ = 0x08,
+
+ /** QoS services are not available since the network currently
+ * has nodes that are not QoS capable. */
+ CLNKLIB_FLOWCODE_QOS_UNAVAIL /*HI_FLOWCODE_QOS_UNAVAIL*/ = 0x0c,
+
+ /** A very infrequent error that must be trapped: a transaction
+ * requiring multiple node synchronization may fail in the event
+ * of a node failure at a critical time. This can be due to
+ * rare transient events (a node leaves the network during a
+ * transaction) or the more sinister case of wire
+ * interferance (during which there can be no QOS assurances in
+ * the network).
+ *
+ * If a caller sees this during a qos creation operation, the
+ * caller should attempt to delete the flow until certain that
+ * the flow has been deleted. Then the creation may be
+ * reattempted.
+ *
+ * If a caller sees this during an update operation, the caller
+ * should repeat the operation. */
+ CLNKLIB_FLOWCODE_UNKNOWN /*HI_FLOWCODE_UNKNOWN*/ = 0x10,
+
+ /** An internal error occurred and the operation should be
+ * reattempted. */
+ CLNKLIB_FLOWCODE_INTERNAL_ERROR /*HI_FLOWCODE_INTERNAL_ERROR*/ = 0x14,
+
+ /** Flow creation was unsuccessful due to the network already
+ * hosting a flow with the specified flow_id. */
+ CLNKLIB_FLOWCODE_FLOW_EXISTS /*HI_FLOWCODE_FLOW_EXISTS*/ = 0x1C,
+
+ /** Updating a flow failed since the flow could not be found. */
+ CLNKLIB_FLOWCODE_NO_SUCH_FLOW /*HI_FLOWCODE_NO_SUCH_FLOW*/ = 0x20,
+
+ /** Flow creation was unsuccessful due to a node involved in the
+ * flow not having enough resources to allocate one more flow. */
+ CLNKLIB_FLOWCODE_TOO_MANY_FLOWS /*HI_FLOWCODE_TOO_MANY_FLOWS*/ = 0x24,
+
+ /** Flow creation was unsuccessful due to ingress node not
+ * having enough resources to allocate one more multicast
+ * flow. */
+ CLNKLIB_FLOWCODE_TOO_MANY_MCAST_F /*HI_FLOWCODE_TOO_MANY_MCAST_F*/ = 0x25,
+
+ /** Flow creation unsuccessful due to violation of
+ * restriction of flow classification rules at ingress. */
+ CLNKLIB_FLOWCODE_BAD_INGRESS_CFY /*HI_FLOWCODE_BAD_INGRESS_CFY*/ = 0x26,
+
+ /** The specified flow destination address is not usable.
+ * Either the caller did not precisely match a multicast form
+ * PACKET_DA with the flow id or the caller passed a unicast
+ * PACKET_DA that was not tied to the node with the egress
+ * guid. */
+ CLNKLIB_FLOWCODE_UNUSABLE_DA /*HI_FLOWCODE_UNUSABLE_DA*/ = 0x28,
+
+ /** A node in the network rejected the flow creation due to
+ * MoCA specification dicated issues about the particular DA
+ * used: see the MoCA decision code definition. */
+ CLNKLIB_FLOWCODE_INVALID_DA /*HI_FLOWCODE_INVALID_DA*/ = 0x29,
+
+ /** The proposed ingress node cannot support the flow due to
+ * being in M1 sleep. */
+ CLNKLIB_FLOWCODE_INGRESS_M1 /*HI_FLOWCODE_INGRESS_M1*/ = 0x2a,
+
+ /** The ingress guid specified in the tspec is not currently on
+ * the network. */
+ CLNKLIB_FLOWCODE_BAD_INGR /*HI_FLOWCODE_BAD_INGR*/ = 0x2c,
+
+ /** An egress guid specified in the tspec is not currently on
+ * the network. */
+ CLNKLIB_FLOWCODE_BAD_EGR /*HI_FLOWCODE_BAD_EGR*/ = 0x30,
+
+ /** The operation was not successful due to a bandwidth
+ * constraint at the ingress node for the flow. See the other
+ * field in the response structure to determine for what
+ * bandwidth the operation would have succeeded. */
+ CLNKLIB_FLOWCODE_INGR_BW_UNAVAIL /*HI_FLOWCODE_INGR_BW_UNAVAIL*/ = 0x34,
+
+ /** The operation was not successful due to a bandwidth
+ * constraint at an egress node for the flow. See the other
+ * field in the response structure to determine for what
+ * bandwidth the operation would have succeeded. */
+ CLNKLIB_FLOWCODE_EGR_BW_UNAVAIL /*HI_FLOWCODE_EGR_BW_UNAVAIL*/ = 0x38,
+
+ /** The operation was not successful due to a network bandwidth
+ * constraint (not enough PQoS slot times per second available
+ * for proposed flow). See the other field in the response
+ * structure to determine for what bandwidth the operation
+ * would have succeeded. */
+ CLNKLIB_FLOWCODE_NW_STPS_UNAVAIL /*HI_FLOWCODE_NW_STPS_UNAVAIL*/ = 0x3c,
+
+ /** The operation was not successful due to a network bandwidth
+ * constraint (not enough PQoS transmissions per second
+ * available for proposed flow). See the other field in the
+ * response structure to determine for what bandwidth the
+ * operation would have succeeded. */
+ CLNKLIB_FLOWCODE_NW_TXPS_UNAVAIL /*HI_FLOWCODE_NW_TXPS_UNAVAIL*/ = 0x40,
+
+ /** Requested maximum retransmission number cannot be
+ * supported. */
+ CLNKLIB_FLOWCODE_BAD_RETRANS /*HI_FLOWCODE_BAD_RETRANS*/ = 0x42,
+
+ /** The operation was not successful since the lease expiration
+ * has become imminent; the flow will soon disappear on its own
+ * accord. */
+ CLNKLIB_FLOWCODE_LEASE_EXPR_SOON /*HI_FLOWCODE_LEASE_EXPR_SOON*/ = 0x44,
+
+ /** The operation was not successful due to an invalid peak
+ * bandwidth. */
+ CLNKLIB_FLOWCODE_BAD_PEAK_BW /*HI_FLOWCODE_BAD_PEAK_BW*/ = 0x50,
+
+ /** The operation failed due to an invalid burst size. */
+ CLNKLIB_FLOWCODE_BAD_BURST_SIZE /*HI_FLOWCODE_BAD_BURST_SIZE*/ = 0x54,
+
+ /** The operation failed due to a node in the network
+ * rejecting the tspec during the L2ME operation. This is
+ * named as 'MoCA 2.0' but can be seen from a 'MoCA 1.1'
+ * node as well. */
+ CLNKLIB_FLOWCODE_BAD_M20_TSPEC /*HI_FLOWCODE_BAD_M20_TSPEC*/ = 0x58,
+
+ /** The operation failed since flow id is not multicast */
+ CLNKLIB_FLOWCODE_INVALID_FLOW_ID /*HI_FLOWCODE_INVALID_FLOW_ID*/ = 0x5c,
+
+ /** The operation was not successful due to a driver error; this
+ * is typically an Maxlinear internal error */
+ CLNKLIB_FLOWCODE_DRIVER_ERROR /*HI_FLOWCODE_DRIVER_ERROR*/ = 0x60,
+
+ /** The operation failed during an attempt to create a MoCA
+ * 1.1 type flow with illegal TSPEC values. The operation
+ * was not attempted since it would expose a MoCA 1.1 node
+ * to fields it is unprepared to interpret. */
+ CLNKLIB_FLOWCODE_BAD_M11_TSPEC /*HI_FLOWCODE_BAD_M11_TSPEC*/ = 0x64,
+
+ /** The operation failed due to an illegal DSCP_MOCA value. */
+ CLNKLIB_FLOWCODE_INVALID_DSCP /*HI_FLOWCODE_INVALID_DSCP*/ = 0x68,
+
+ /** The operation failed due to an illegal VLAN_TAG value. */
+ CLNKLIB_FLOWCODE_INVALID_VLAN /*HI_FLOWCODE_INVALID_VLAN*/ = 0x6c,
+
+ /** The operation failed due to an illegal
+ * INGRESS_CLASSIFICATION_RULE value. */
+ CLNKLIB_FLOWCODE_INVALID_ICR /*HI_FLOWCODE_INVALID_ICR*/ = 0x70,
+
+ /** The operation failed due to an unusable link. */
+ CLNKLIB_FLOWCODE_UNUSABLE_LINK /*HI_FLOWCODE_UNUSABLE_LINK*/ = 0x74,
+} ClnkLib_FlowCode_e;
+typedef uint32_t ClnkLib_FlowCode_t
+/* Hi_FlowCode_t */;
+
+/**
+ * MAC Address, used for Ethernet, PQoS FlowID, and MoCA
+ * GUID. NOT used for DFID. By convention, the most
+ * significant MAC Address byte is the most significant byte
+ * of field 'hi' and the least significant two MAC Address
+ * bytes are found in the upper two bytes of field 'lo'.
+ */
+typedef struct
+{
+ uint32_t hi;
+ uint32_t lo;
+} ClnkLib_MacAddr_t;
+
+
+/**
+ * PQoS Flow Parameter (PFP) information, fields used in
+ * creation, modification (i.e. update), and query of MoCA PQoS
+ * 1.1 and 2.0 Flows; fields match those in the Submit L2ME
+ * frame for Create and Update as well as those in Response to
+ * Wave 0 of the PQoS Query. Some fields are only meaningful
+ * when Ingress, Egress, and NC are MoCA 2.0 (M2).
+ *
+ * NOTE: at the time of this writing, the working standard does
+ * not provide for PQOS query transaction to access
+ * INORDER_DELIVERY_RECOMMENDED and TRAFFIC_PROTOCOL. It is
+ * possible this will be adjusted in a future rev so we'll keep
+ * the same structure for PFP at this time.
+ */
+typedef struct
+{
+ ClnkLib_MacAddr_t flowId; //!< PQoS flow ID
+ uint32_t tPktSize; //!< Traffic packet size
+ ClnkLib_MacAddr_t ingressGuid; //!< Ingress GUID
+ ClnkLib_MacAddr_t egressGuid; //!< Egress GUID
+ uint32_t flowTag; //!< Flow tag
+ ClnkLib_MacAddr_t packetDa; //!< Packet destination address
+ uint32_t tPeakDataRateKbps; //!< Traffic peak data rate
+ uint32_t tLeaseTimeSec; //!< Traffic lease time
+ uint32_t tBurstSize; //!< Traffic burst size
+
+ uint32_t maxLatencyMs; //!< M2: Maximum latency
+ uint32_t stAvgRatio; //!< M2: Short term average ratio
+ uint32_t maxNumRetry; //!< M2: Maximum number of retx attempts
+ uint32_t flowPer; //!< M2: Flow PER (NPER or VLPER)
+ uint32_t inOrderDeliver; //!< M2, no query: In order delivery recommendation
+ uint32_t tProtocol; //!< M2, no query: Traffic protocol
+ uint32_t ingressClass; //!< M2: Ingress classification rule
+ uint32_t vlanTag; //!< M2: VLAN tag
+ uint32_t dscpMoca; //!< M2: DSCP MoCA value
+} ClnkLib_PFP_t
+/*Hi_PFP_t*/;
+
+
+/** Results of attempted PQoS Create/Update. Fields marked with
+ * W1REQ are copied from specific fields or bits in the PQoS
+ * Create/Update Wave 1 Request.
+ */
+typedef struct
+{
+ ClnkLib_FlowCode_t flowCode; //!< Response code, encodes DECISION
+ uint32_t postStps; //!< W1REQ: POST_STPS
+ uint32_t postTxps; //!< W1REQ: POST_TXPS
+ uint32_t dfid; //!< W1REQ: DFID
+ uint32_t maxRetryNum; //!< W1REQ: Maximum allowed retry number
+ uint32_t maxShortTermAvRatio;//!< W1REQ: Maximum allowed short term avg ratio
+ uint32_t remainKbps; //!< W1REQ: MAX_PEAK_DATA_RATE
+ uint32_t remainBurst; //!< W1REQ: MAX_BURST_SIZE
+ uint32_t decision; //!< W1REQ: DECISION
+ uint32_t bwLimitInfo; //!< W1REQ: BW_LIMIT_INFO
+ uint32_t isIngressLimited; //!< W1REQ: BW_LIMIT_INFO(3)
+ uint32_t isEgressLimited; //!< W1REQ: BW_LIMIT_INFO(3)
+ uint32_t isAggrStpsLimited; //!< W1REQ: BW_LIMIT_INFO(1)
+ uint32_t isAggrTxpsLimited; //!< W1REQ: BW_LIMIT_INFO(0)
+ uint32_t currMaxStps; //!< Estimate of current max MOCA STPS
+ uint32_t currMaxTxps; //!< Estimate of current max MOCA TXPS
+} ClnkLib_FlowCURsp_t
+/*Hi_FlowCURsp_t*/;
+
+
+//! Flow delete response
+typedef struct
+{
+ ClnkLib_FlowCode_t flowCode; //!< Response
+ uint32_t numNodesDelRsrc; //!< Number of nodes that deleted something
+} ClnkLib_FlowDeleteRsp_t
+/*Hi_FlowDeleteRsp_t*/;
+
+
+//! Flow list request. See MoCA 1.1 Specification Table 4-14 for precision.
+typedef struct
+{
+ ClnkLib_MacAddr_t ingressGuid; //!< Queried node
+ uint32_t flowStartIndex; //!< First flow index to return in logical table
+ uint32_t flowMaxReturn; //!< Maximum number of flows to return
+} ClnkLib_FlowListReq_t
+/*Hi_FlowListReq_t*/;
+
+
+//! Flow list response. See the MoCA 1.1 Specification Table 4-15 for precision.
+typedef struct
+{
+ ClnkLib_FlowCode_t flowCode; //!< Response
+ uint32_t flowUpdateCount; //!< Event for each flow change at node
+ uint32_t totalFlowIdCount; //!< Flows for which node is Ingress
+ uint32_t numReturnedFlowIds; //!< Num flows populated in table below
+ ClnkLib_MacAddr_t returnedFlowId[MAX_FLOWS_IN_LIST];
+} ClnkLib_FlowListRsp_t
+/*Hi_FlowListRsp_t*/;
+
+
+/** Flow query information
+ *
+ * NOTE: at the time of this writing, the working standard does
+ * not provide for PQOS query transaction to access
+ * INORDER_DELIVERY_RECOMMENDED and TRAFFIC_PROTOCOL. It is
+ * possible this will be adjusted in a future rev so we'll keep
+ * the same structure for PFP at this time.
+ * */
+typedef struct
+{
+ ClnkLib_FlowCode_t flowCode; //!< Response code, encodes W1REQ DECISION
+ uint32_t leaseTimeLeft; //!< Lease time left (seconds)
+ ClnkLib_PFP_t pfp; //!< Parameters for PQoS Flow
+ uint32_t dfid; //!< DFID, 8 bit routing number
+} ClnkLib_FlowQueryRsp_t
+/*Hi_FlowQueryRsp_t*/;
+
+//! Flow statistics
+typedef struct
+{
+ /** Number of times that this node has seen other nodes admit and drop */
+ uint32_t countTopologyChanged;
+ /** Number of times that this node has been the ingress for a creation,
+ * update, or deletion of a Flow. */
+ uint32_t countIngressFlowChanged;
+ /** Number of times a PQoS maintenance cycle has reported that Flows
+ * in the network are at risk due to changing topology or bandwidth
+ * availability. */
+ uint32_t countBwExceeded;
+ /** Number of times this node has detected that a change in the network
+ * version has occurred. This directly corresponds to events that cause
+ * network-wide PQoS guarantee changes. */
+ uint32_t countNwVersionChange;
+ /** Node's estimate of maximum STPS possible in the network, may differ from
+ * the NC's version. */
+ uint32_t currentMaxStps;
+ /** Node's estimate of maximum TXPS possible in the network, may differ from
+ * the NC's version. */
+ uint32_t currentMaxTxps;
+ /** Flow Maintenance: several fields update every PQoS maintenance cycle- this
+ * field increments every maintenance. */
+ uint32_t fmUpdateCount;
+ /** Flow Maintenance: cache of the IOC_NODEMASK value during the last
+ * maintenance. Represents which nodeIds are over ingress commitment */
+ uint32_t fmIocNodemask;
+ /** Flow Maintenance: cache of the ALLOCATED_STPS value during the last
+ * maintenance. Represents networkwide allocation of slot times. */
+ uint32_t fmAllocatedStps;
+ /** Flow Maintenance: cache of the ALLOCATED_TXPS value during the last
+ * maintenance. Represents networkwide allocation of transmissions. */
+ uint32_t fmAllocatedTxps;
+} ClnkLib_FlowStats_t
+/*Hi_FlowStats_t*/;
+
+//! Flow statistics
+typedef struct
+{
+ ClnkLib_FlowCode_t flowCode; //!< Response
+ uint32_t allocatedStps; //!< if flowCode _SUCCESS, current alloc of STPS
+ uint32_t allocatedTxps; //!< if flowCode _SUCCESS, current alloc of TXPS
+} ClnkLib_FlowCapacityRsp_t;
+
+
+
+//! DES key
+typedef uint32_t MocaDesKey_t[2];
+
+//! AES key
+typedef uint32_t MocaAesKey_t[4];
+
+//! Security information
+typedef struct
+{
+ uint32_t state; //!< Security state (enabled or disabled)
+ MocaDesKey_t mmk; //!< DES MAC management key
+ MocaDesKey_t pmkInit; //!< DES initial privacy management key
+ MocaDesKey_t pmk[2]; //!< DES privacy management keys
+ uint32_t activePmk; //!< Active DES PMK (even or odd)
+ MocaDesKey_t tek[2]; //!< DES traffic encryption keys
+ uint32_t activeTek; //!< Active DES TEK (even or odd)
+ MocaAesKey_t ammk; //!< AES MAC management key
+ MocaAesKey_t apmkInit; //!< AES initial privacy management key
+ MocaAesKey_t apmk[2]; //!< AES privacy management keys
+ uint32_t activeApmk; //!< Active AES PMK (even or odd)
+ MocaAesKey_t atek[2]; //!< AES traffic encryption keys
+ uint32_t activeAtek; //!< Active AES TEK (even or odd)
+ uint32_t permSalt[3]; //!< Permanent Salt
+}
+ClnkLib_SecInfo_t;
+
+//! Security statistics
+typedef struct
+{
+ uint32_t txNoSec; //!< Frames txed with no security
+ uint32_t txPmkInit; //!< Frames txed with PMKInit
+ uint32_t txMmk; //!< Frames txed with MMK
+ uint32_t txPmk; //!< Frames txed with PMK
+ uint32_t txTek; //!< Frames txed with TEK
+ uint32_t txApmkInit; //!< Frames txed with APMKInit
+ uint32_t txAmmk; //!< Frames txed with AMMK
+ uint32_t txApmk; //!< Frames txed with APMK
+ uint32_t txAtek; //!< Frames txed with ATEK
+}
+ClnkLib_SecStats_t;
+
+#if FEATURE_SAPM
+typedef struct
+{
+ uint32_t threshold;
+ uint32_t sapmTbl[FFT_LENGTH / 4];
+} ClnkLib_SapmSocProfile_t;
+
+typedef struct
+{
+ int32_t sapmProfileId; // only used to pass pid through API calls
+ uint32_t threshold;
+ uint32_t sapmTbl[FFT_LENGTH / 4];
+} ClnkLib_SapmProfile_t;
+
+typedef struct
+{
+ int32_t sapmProfileId;
+ int32_t profile;
+ uint32_t sapmThreshold[MAX_SAPM_PROFILES];
+ uint32_t sapmTbl[MAX_SAPM_PROFILES][FFT_LENGTH / 4];
+} ClnkLib_SapmCfg_t;
+#endif
+
+#if FEATURE_RLAPM
+typedef struct
+{
+ int32_t rlapmProfileId;
+ int32_t profile;
+ uint32_t rlapmTbl[MAX_RLAPM_PROFILES][MAX_RX_LEVELS_PADDED / 4];
+} ClnkLib_RlapmCfg_t;
+
+//! SAPM table
+typedef MXL_MOCA_SAPM_TABLE_V2_T ClnkLib_SapmTableV2_t;
+
+//! SAPM configuration
+typedef MXL_MOCA_SAPM_CFG_V2_T ClnkLib_SapmCfgV2_t;
+
+typedef struct
+{
+ uint32_t sapmmode;
+ int32_t sapmProfileId;
+ // we refer the ClnkLib_SapmCfgV2_t type to reuse the underlying APIs,
+ // but note the rlapmmode field in profiles is meaningless
+ ClnkLib_SapmCfgV2_t profiles[MAX_SAPM_PROFILES];
+} ClnkLib_SapmStaticCfgV2_t;
+
+//! RLAPM table
+typedef MXL_MOCA_RLAPM_TABLE_V2_T ClnkLib_RlapmTableV2_t;
+
+//! RLAPM configuration
+typedef MXL_MOCA_RLAPM_CFG_V2_T ClnkLib_RlapmCfgV2_t;
+
+typedef struct
+{
+ //! RLAPM mode
+ uint32_t rlapmmode;
+
+ //! RLAPM tables
+ ClnkLib_RlapmTableV2_t tbl;
+} ClnkLib_RlapmActiveCfgV2_t;
+
+typedef struct
+{
+ uint32_t rlapmmode;
+ int32_t rlapmProfileId;
+ // we refer the ClnkLib_RlapmCfgV2_t type to reuse the underlying APIs,
+ // but note the rlapmmode field in profiles is meaningless
+ ClnkLib_RlapmCfgV2_t profiles[MAX_RLAPM_PROFILES];
+} ClnkLib_RlapmStaticCfgV2_t;
+
+#endif
+
+typedef enum
+{
+ CLNKLIB_ICR_VLAN_TAG_4_5 = 0,
+ CLNKLIB_ICR_IGNORE_VLAN_TAG_AND_DSCP_MOCA = 4,
+ CLNKLIB_ICR_USE_DSCP_MOCA = 5,
+ CLNKLIB_ICR_USE_VLAN = 6,
+ CLNKLIB_ICR_USE_VLAN_OR_DSCP_MOCA = 7,
+} ClnkLib_Icr_t;
+
+typedef struct
+{
+ uint32_t rssiWordTbl[MAX_RSSI_LEN / 4];
+} ClnkLib_RssiCfg_t;
+
+typedef MXL_MOCA_RSSI_CFG_V2_T ClnkLib_RssiCfgV2_t;
+
+typedef MXL_MOCA_PLATFORM_CFG_T ClnkLib_PlatformCfg_t;
+
+// Summing over 25 subcarriers for Ui and Li, each one separate by 31. i.e. U2 = U1+31
+// ATSC and CATV table
+// E2, EE3, F3, F7
+typedef MXL_MOCA_BAND_E_TABLE_T BandEFTbl_t;
+
+// CATV and ATSC
+typedef MXL_MOCA_ATSC_CATV_WEIGHT_T AtscCatvWeight_t;
+
+// D2, D4, D6, D8, D10, 1100
+typedef MXL_MOCA_BAND_D_TABLE_T BandDTbl_t;
+
+// BTS constants
+typedef MXL_MOCA_BTS_T Bts_t;
+
+// CSS constants
+typedef MXL_MOCA_CSS_T Css_t;
+
+// Energy and usability related thresholds
+typedef MXL_MOCA_BAND_DEF_THRESHOLDS_T BandDEFThresholds_t;
+
+// ClnkLib energy detection configuration parameters
+typedef MXL_MOCA_ENERGY_DETECT_CFG_T ClnkLib_EndetCfg_t;
+
+typedef struct
+{
+ uint32_t rawDetectedServiceBitmask;
+ uint8_t channelInfo50MhzBandE[NUM_BAND_E_50MHZ_RANK]; // NUM_BAND_E_50MHZ_RANK
+ uint8_t channelInfo50MhzBandF[NUM_BAND_F_50MHZ_RANK]; // NUM_BAND_F_50MHZ_RANK
+ uint8_t channelInfo50MhzBandD[NUM_BAND_D_50MHZ_RANK]; // NUM_BAND_D_50MHZ_RANK
+ uint8_t channelInfo100MhzBandE[NUM_BAND_E_100MHZ_RANK]; // NUM_BAND_E_100MHZ_RANK
+ uint8_t channelInfo100MhzBandF[NUM_BAND_F_100MHZ_RANK]; // NUM_BAND_F_100MHZ_RANK
+ uint8_t channelInfo100MhzBandD[NUM_BAND_D_100MHZ_RANK]; // NUM_BAND_D_100MHZ_RANK
+ uint8_t pad[2];
+
+ uint32_t bandEF50MhzEnergyBitmask;
+ uint32_t bandD50MhzEnergyBitmask;
+
+ uint32_t bandEF100MhzEnergyBitmask;
+ uint32_t bandD100MhzEnergyBitmask;
+}ClnkLib_EndetStatus_t;
+
+//! Active SAPM
+typedef struct
+{
+ //! SAPM mode
+ uint32_t sapmmode;
+
+ //! Added PHY margin table
+ uint8_t phymargin[FFT_LENGTH];
+
+ //! Threshold and frequency
+ uint16_t frequency;
+ uint8_t threshold;
+ uint8_t pad;
+} ClnkLib_ActiveSapm_t;
+
+//Tx beacon power for local or distribute, range -10~7db
+typedef MXL_MOCA_SOC_SET_BCN_POWER_RSP_T ClnkLib_SetBcnPowerRsp_t;
+
+//Tx beacon power for local or distribute, range -10~7db
+typedef MXL_MOCA_SOC_SET_BCN_POWER_CMD_T ClnkLib_SetBcnPowerCmd_t;
+
+//Tx beacon power for local or distribute, range -10~7db
+typedef MXL_MOCA_SOC_GET_BCN_POWER_RSP_T ClnkLib_GetBcnPowerRsp_t;
+
+/*******************************************************************************
+ * Public/Private Data
+ ******************************************************************************/
+
+/*!
+ * \brief c.LINK Interface Handle Structure
+ *
+ * Handle (or context) for the c.LINK interface. This structure is used to
+ * store the context for c.LINK interface.
+ */
+typedef struct
+{
+ char ifname[IFNAME_MAX + 1];
+ char conf_path[256];
+ char fwdir[256];
+ char drvname[256];
+ int32_t drv_fd;
+ int32_t phy_id;
+ int32_t pcie;
+ int32_t testParam4;
+ int32_t stopped;
+ int32_t force_reset;
+ int32_t retCodes;
+ int32_t testMode;
+ int32_t socChipType;
+} ClnkLib_Handle_t;
+
+
+/*!
+ * \brief c.LINK Interface Name Structure
+ *
+ * A structure to store clink interface names. (for acch add/delete)
+ */
+typedef struct ClinkIfName_s
+{
+ int8_t ifName[IFNAMSIZ];
+} ClnkLib_Name_t;
+
+
+#include "HostCfgLib.h"
+
+/*******************************************************************************
+ * Public/Private Functions
+ ******************************************************************************/
+///c.LINK library apis
+//
+//Interface management
+int32_t ClnkLib_Open(ClnkLib_Handle_t *pHandle);
+int32_t ClnkLib_OpenByName(ClnkLib_Handle_t *pHandle, char *ifNameString);
+int32_t ClnkLib_ListNames(ClnkLib_Name_t *ifNamePtr, int32_t max);
+int32_t ClnkLib_GetName(ClnkLib_Handle_t *pHandle, ClnkLib_Name_t *pName);
+int32_t ClnkLib_DisplayInterfaces();
+void ClnkLib_Close(ClnkLib_Handle_t *pHandle);
+int32_t ClnkLib_Start(ClnkLib_Handle_t *pHandle);
+int32_t ClnkLib_Stop(ClnkLib_Handle_t *pHandle);
+int32_t ClnkLib_Reset(ClnkLib_Handle_t *pHandle);
+
+//Device Configuration
+int32_t ClnkLib_GetStaticCfg(ClnkLib_Handle_t *pHandle, int flags, ClnkLib_StaticCfg_t *setup);
+int32_t ClnkLib_SetStaticCfg(ClnkLib_Handle_t *pHandle, ClnkLib_StaticCfg_t *setup);
+int32_t ClnkLib_GetClnkCfgV2(ClnkLib_Handle_t *pHandle, int flag, ClnkLib_ClnkCfgV2_t *setup);
+int32_t ClnkLib_SetClnkCfgV2(ClnkLib_Handle_t *pHandle, ClnkLib_ClnkCfgV2_t *setup);
+int32_t ClnkLib_GetClnkCfgV2Params(ClnkLib_Handle_t *pHandle, clnk_param_mask_t *mask, ClnkLib_ClnkCfgV2_t *setup);
+int32_t ClnkLib_SetClnkCfgV2Params(ClnkLib_Handle_t *pHandle, clnk_param_mask_t *mask, ClnkLib_ClnkCfgV2_t *setup);
+int32_t ClnkLib_RestoreClnkCfgV2(ClnkLib_Handle_t *pHandle);
+#if FEATURE_SAPM
+// The following functions can be used to manage the Sapm profile config
+int ClnkLib_SetSapmCfg(ClnkLib_Handle_t *pHandle, const ClnkLib_SapmStaticCfgV2_t *pCfg);
+int ClnkLib_GetSapmCfg(ClnkLib_Handle_t *pHandle, ClnkLib_SapmStaticCfgV2_t *pCfg);
+int ClnkLib_ReplaceSapmCfg(ClnkLib_Handle_t *pHandle, const char *newFile);
+int ClnkLib_GetActiveSapm(ClnkLib_Handle_t *pHandle, ClnkLib_ActiveSapm_t *pActiveSapm);
+int ClnkLib_GetActiveSapmByChIndex(ClnkLib_Handle_t *pHandle, uint32_t index, ClnkLib_ActiveSapm_t *pActiveSapm);
+int ClnkLib_SetSapmProfileId(ClnkLib_Handle_t *pHandle, int32_t profileId);
+int ClnkLib_SetSapmMode(ClnkLib_Handle_t *pHandle, uint32_t band, uint32_t mode);
+int ClnkLib_SetSapmSimpleCfg(ClnkLib_Handle_t *pHandle, int32_t freq, int32_t threshold, int32_t scStart, int32_t carrier, int32_t margin);
+#endif
+#if FEATURE_RLAPM
+int ClnkLib_SetRlapmCfg(ClnkLib_Handle_t *pHandle, const ClnkLib_RlapmStaticCfgV2_t *pRlapmStaticCfg);
+int ClnkLib_GetRlapmCfg(ClnkLib_Handle_t *pHandle, ClnkLib_RlapmStaticCfgV2_t *pRlapmStaticCfg);
+int ClnkLib_ReplaceRlapmCfg(ClnkLib_Handle_t *pHandle, const char *newFile);
+int ClnkLib_GetActiveRlapm(ClnkLib_Handle_t *pHandle, ClnkLib_RlapmActiveCfgV2_t *pRlapmCfg);
+int ClnkLib_GetActiveRlapmByChIndex(ClnkLib_Handle_t *pHandle, uint32_t index, ClnkLib_RlapmActiveCfgV2_t *pRlapmCfg);
+int ClnkLib_SetRlapmProfileId(ClnkLib_Handle_t *pHandle, int32_t profileId);
+int ClnkLib_SetRlapmMode(ClnkLib_Handle_t *pHandle, uint32_t band, uint32_t mode);
+int ClnkLib_SetRlapmSimpleCfg(ClnkLib_Handle_t *pHandle, int32_t freq, int32_t rxLevel, int32_t margin);
+#endif
+int ClnkLib_GetBoardInfo(ClnkLib_Handle_t *pHandle, ClnkLib_BoardInfo_t *binfo);
+int ClnkLib_GetChipName(ClnkLib_Handle_t *pHandle, char **chipname);
+int ClnkLib_GetChipType(ClnkLib_Handle_t *pHandle, int32_t *pSocChipType);
+
+//Device Management:switch
+int32_t ClnkLib_GetSwitchTable(ClnkLib_Handle_t *pHandle, uint32_t type, uint32_t startIndex, uint32_t *pMaxEntries, ClnkLib_BridgeTable_t *brg_table);
+int32_t ClnkLib_GetSwitchStats(ClnkLib_Handle_t *pHandle, int32_t clear, ClnkLib_SwitchStats_t *pSwitchStats);
+int32_t ClnkLib_GetSwitchConfig(ClnkLib_Handle_t *pHandle, ClnkLib_SwitchConfig_t *pSwitchConfig);
+int32_t ClnkLib_SetSwitchPortConfig(ClnkLib_Handle_t *pHandle, ClnkLib_SwitchPortConfig_t *pSwitchPortConfig, uint32_t* pRsp);
+int32_t ClnkLib_ResetSwitchConfig(ClnkLib_Handle_t *pHandle);
+int32_t ClnkLib_SetSwitchTmo(ClnkLib_Handle_t *pHandle, uint32_t tmo);
+int32_t ClnkLib_EnableSwitchVlanCheck(ClnkLib_Handle_t *pHandle, int32_t port);
+int32_t ClnkLib_DisableSwitchVlanCheck(ClnkLib_Handle_t *pHandle, int32_t port);
+int32_t ClnkLib_EnableSwitchVlanStrip(ClnkLib_Handle_t *pHandle, int32_t port);
+int32_t ClnkLib_DisableSwitchVlanStrip(ClnkLib_Handle_t *pHandle, int32_t port);
+int32_t ClnkLib_SetSwitchVlanPvid(ClnkLib_Handle_t *pHandle, int32_t port, uint32_t pvid);
+int32_t ClnkLib_AddSwitchVlanId(ClnkLib_Handle_t *pHandle, int32_t port, uint32_t vid);
+int32_t ClnkLib_DelSwitchVlanId(ClnkLib_Handle_t *pHandle, int32_t port, uint32_t vid);
+int32_t ClnkLib_SetMgmtMac(ClnkLib_Handle_t *pHandle, uint32_t macHi, uint32_t macLo);
+int32_t ClnkLib_SetSwitchMgmtMac(ClnkLib_Handle_t *pHandle, uint32_t macHi, uint32_t macLo);
+
+//Device Management:ethernet
+int32_t ClnkLib_GetAggrStats(ClnkLib_Handle_t *pHandle, int clear, ClnkLib_AggrStats_t *);
+int32_t ClnkLib_GetBridgeStats(ClnkLib_Handle_t *pHandle, int32_t clear, ClnkLib_BridgeStats_t *pBridgeStats);
+int32_t ClnkLib_GetBridgeTable(ClnkLib_Handle_t *pHandle, uint32_t type, uint32_t startIndex, uint32_t *pMaxEntries, ClnkLib_BridgeTable_t *brg_table);
+int32_t ClnkLib_GetEphyStats(ClnkLib_Handle_t *, int32_t clear, ClnkLib_EphyStats_t *pEphyStats);
+int32_t ClnkLib_GetEcbStats(ClnkLib_Handle_t *, int32_t clear, ClnkLib_EcbStats_t *pEphyStats);
+int ClnkLib_SetMcastFilter(ClnkLib_Handle_t *pHandle, uint32_t macAddrHi, uint32_t macAddrLo, uint32_t flag);
+int ClnkLib_GetMcastFilterMode(ClnkLib_Handle_t *pHandle, uint32_t *pMode);
+int ClnkLib_SetMcastFilterMode(ClnkLib_Handle_t *pHandle, uint32_t mode);
+int ClnkLib_GetMcastCfg(ClnkLib_Handle_t *pHandle, uint32_t flag, ClnkLib_McastCfg_t *pCfg, int *numEntries);
+int ClnkLib_SetMcastCfg(ClnkLib_Handle_t *pHandle, ClnkLib_McastCfg_t *pCfg);
+int ClnkLib_RestoreMcastCfg(ClnkLib_Handle_t *pHandle);
+int32_t ClnkLib_GetMacDataStats(ClnkLib_Handle_t *pHandle, int clear, ClnkLib_MacDataStats_t *pMacData);
+int32_t ClnkLib_GetRetxStats(ClnkLib_Handle_t *pHandle, uint32_t clear, ClnkLib_RetxStats_t *pStats);
+
+//Device Management:link
+int32_t ClnkLib_GetCdInfo(ClnkLib_Handle_t *pHandle, uint32_t clear, ClnkLib_CdInfo_t *pInfo);
+int32_t ClnkLib_GetFrameStats(ClnkLib_Handle_t *pHandle, int32_t clear, ClnkLib_FrameStats_t *pFrameStats);
+int32_t ClnkLib_GetDataStats(ClnkLib_Handle_t *pHandle, uint32_t clear, ClnkLib_DataStats_t *pStats);
+int32_t ClnkLib_GetFragStats(ClnkLib_Handle_t *pHandle, uint32_t clear, ClnkLib_FragStats_t *pStats);
+int32_t ClnkLib_GetL2meStats(ClnkLib_Handle_t *pHandle, uint32_t clear, ClnkLib_L2meStats_t *pL2meStats);
+int32_t ClnkLib_GetSocStatus(ClnkLib_Handle_t *pHandle, ClnkLib_SocStatus_t *pSocStatus);
+int32_t ClnkLib_GetLocalInfo(ClnkLib_Handle_t *pHandle, ClnkLib_LocalInfo_t *pLocalInfo);
+int32_t ClnkLib_GetFmrInfo(ClnkLib_Handle_t *pHandle, uint32_t fmrMask, uint32_t version, ClnkLib_FmrInfo_t *pFmrInfo);
+int32_t ClnkLib_GetDdInfo(ClnkLib_Handle_t *pHandle, uint32_t ddMask, ClnkLib_DdInfo_t *pDdInfo);
+int32_t ClnkLib_GetNetInfo(ClnkLib_Handle_t *pHandle, uint32_t nodeId, ClnkLib_NetInfo_t *pNetInfo);
+int ClnkLib_RequestHandoff(ClnkLib_Handle_t *pHandle, ClnkLib_HandoffRequest_t *pReq); ///Debug
+int ClnkLib_RequestLmo(ClnkLib_Handle_t *pHandle, ClnkLib_LmoRequest_t *pReq, ClnkLib_LmoReport_t *pRpt);
+
+//Device Management:NMS
+int ClnkLib_IssueMocaReset(ClnkLib_Handle_t *pHandle, ClnkLib_MocaResetRequest_t *pRequest, ClnkLib_MocaResetResponse_t *pResponse);
+int ClnkLib_RequestNms(ClnkLib_Handle_t *pHandle, ClnkLib_NmsRequest_t *pReq, ClnkLib_NmsReport_t *pRpt);
+int32_t ClnkLib_SendNetProxyPacket(ClnkLib_Handle_t *pHandle, uint8_t* pPkt, uint32_t length, uint32_t* pRsp);
+int32_t ClnkLib_WaitForNetProxyResponse(ClnkLib_Handle_t *pHandle, uint8_t* pPkt, uint32_t* pLength, uint32_t* pRsp);
+int32_t ClnkLib_WaitForNetProxyRcvReq(ClnkLib_Handle_t *pHandle, uint8_t* pPkt, uint32_t* pLength, uint32_t* pRsp);
+int32_t ClnkLib_SendNetProxyResponse(ClnkLib_Handle_t *pHandle, uint8_t* pPkt, uint32_t length, uint32_t* pRsp);
+int32_t ClnkLib_SendNetProxyTestModeCtrl(ClnkLib_Handle_t *pHandle, uint32_t enable);
+
+//Device management:PHY
+int32_t ClnkLib_GetPhyTxProfile(ClnkLib_Handle_t *pHandle, uint32_t nodeId, uint32_t profileId, uint32_t getBitloading, ClnkLib_PhyTxProfile_t *pRsp);
+int32_t ClnkLib_GetPhyRxProfile(ClnkLib_Handle_t *pHandle, uint32_t nodeId, uint32_t profileId, uint32_t getBitloading, ClnkLib_PhyRxProfile_t *pRsp);
+int32_t ClnkLib_GetPhyNode(ClnkLib_Handle_t *pHandle, uint32_t nodeId, ClnkLib_PhyNode_t *pRsp);
+int32_t ClnkLib_GetPhyEvm(ClnkLib_Handle_t *pHandle, uint32_t nodeId, uint32_t profileId, ClnkLib_PhyEvm_t *pRsp);
+int32_t ClnkLib_GetPhyMisc(ClnkLib_Handle_t *pHandle, ClnkLib_PhyMisc_t *pRsp);
+int32_t ClnkLib_GetM25PhyMisc(ClnkLib_Handle_t *pHandle, ClnkLib_M25PhyMisc_t *pRsp);
+int ClnkLib_GetOfdmaParams(ClnkLib_Handle_t *pHandle, ClnkLib_OfdmaParams_t *pOfdmaParams);
+int ClnkLib_GetOfdmaTxProfile(ClnkLib_Handle_t *pHandle, ClnkLib_OfdmaTxProfile_t *pOfdmaTxProfile, uint32_t role, uint32_t asgnTblIdx);
+int ClnkLib_GetOfdmaRxProfile(ClnkLib_Handle_t *pHandle, ClnkLib_OfdmaRxProfile_t *pOfdmaRxProfile, uint32_t profileNum, uint32_t asgnTblIdx);
+int ClnkLib_SetPhyModBitmask(ClnkLib_Handle_t *pHandle, uint32_t nodeId, uint32_t type, uint32_t value);
+int ClnkLib_GetEndetStatus(ClnkLib_Handle_t *pHandle, ClnkLib_EndetStatus_t *pEndetStatus);
+int ClnkLib_SetGetTxPwrVar(ClnkLib_Handle_t *pHandle, uint32_t set, uint32_t nodeId, uint32_t *txPwrVar);
+int ClnkLib_GetTxPwr(ClnkLib_Handle_t *pHandle, float *txPwr, uint32_t nodeId);
+
+//Device Management:PM
+int ClnkLib_Sleep(ClnkLib_Handle_t *pHandle, uint32_t state);
+int ClnkLib_Wake(ClnkLib_Handle_t *pHandle);
+int ClnkLib_GetPmCaps(ClnkLib_Handle_t *pHandle, uint32_t *pPmCapsMask);
+int ClnkLib_QueryPmState(ClnkLib_Handle_t *pHandle, uint32_t nodeId, ClnkLib_QueryPmStateRsp_t *pRsp);
+int ClnkLib_GetPmEvent(ClnkLib_Handle_t *pHandle, uint32_t *pEvent, ClnkLib_PmEventData_t *pEventData, uint32_t clearEvent);
+int ClnkLib_HostIfReady(ClnkLib_Handle_t *pHandle);
+int32_t ClnkLib_StandaloneLowPowerMode(ClnkLib_Handle_t *pHandle, int8_t powerDown);
+
+//Device Management:QOS
+int ClnkLib_CreateFlow(ClnkLib_Handle_t *pHandle, ClnkLib_PFP_t *pReq, ClnkLib_FlowCURsp_t *pRsp);
+int ClnkLib_UpdateFlow(ClnkLib_Handle_t *pHandle, ClnkLib_PFP_t *pReq, ClnkLib_FlowCURsp_t *pRsp);
+int ClnkLib_DeleteFlow(ClnkLib_Handle_t *pHandle, ClnkLib_MacAddr_t *pFlowId, ClnkLib_FlowDeleteRsp_t *pRsp);
+int ClnkLib_ListFlows(ClnkLib_Handle_t *pHandle, ClnkLib_FlowListReq_t *pReq, ClnkLib_FlowListRsp_t *pRsp);
+int ClnkLib_QueryFlow(ClnkLib_Handle_t *pHandle, ClnkLib_MacAddr_t *pFlowId, ClnkLib_FlowQueryRsp_t *pRsp);
+int ClnkLib_GetFlowStats(ClnkLib_Handle_t *pHandle, uint32_t clear, ClnkLib_FlowStats_t *pStats);
+int ClnkLib_QueryFlowCapacity(ClnkLib_Handle_t *pHandle, ClnkLib_FlowCapacityRsp_t *pCapacity);
+
+//Device Management:Security
+int ClnkLib_GetSecPassword(ClnkLib_Handle_t *pHandle, uint8_t *pass);
+int ClnkLib_GetSecInfo(ClnkLib_Handle_t *pHandle, ClnkLib_SecInfo_t *pInfo);
+int ClnkLib_GetSecStats(ClnkLib_Handle_t *pHandle, uint32_t clear, ClnkLib_SecStats_t *pStats);
+
+//Device Management:Spectrum Analyzer
+uint32_t ClnkLib_GetSpectrumSize(uint32_t startFreq, uint32_t endFreq);
+int32_t ClnkLib_GetSpectrum(ClnkLib_Handle_t *pHandle, int startFreq, int endFreq,
+ bool maxHold, ClnkLib_MacAddr_t *txMacAddr, bool postProcess,
+ int8_t *buf, int *bufSize);
+
+//Device Management:Bridge Control
+int32_t ClnkLib_BridgeCtrlGetNwNamePayload(ClnkLib_Handle_t *pHandle, uint8_t* pRsp);
+int32_t ClnkLib_BridgeCtrlGetNwNameRec(ClnkLib_Handle_t *pHandle, uint32_t reset, int32_t* pRsp);
+int32_t ClnkLib_BridgeCtrlNwNamePayloadTx(ClnkLib_Handle_t *pHandle, uint8_t set, uint8_t* pSetStr, uint8_t* pGetStr);
+int32_t ClnkLib_BridgeCtrlNwNamePayloadRx(ClnkLib_Handle_t *pHandle, uint8_t set, uint8_t* pSetStr, uint8_t* pGetStr);
+int32_t ClnkLib_BridgeCtrlNetworkJoinCfg(ClnkLib_Handle_t *pHandle, uint32_t enable, uint32_t reset, int32_t* pRsp);
+int32_t ClnkLib_BridgeCtrlNetworkJoin(ClnkLib_Handle_t *pHandle, int32_t* pRsp);
+
+//Device Management:Debug
+int32_t ClnkLib_ReadMem(ClnkLib_Handle_t *pHandle, uint32_t addr, uint8_t *pBuf, int len);
+int32_t ClnkLib_WriteMem(ClnkLib_Handle_t *pHandle, uint32_t addr, uint8_t *pBuf, int len);
+#if LIBAPI_OFFICIAL_DESIGN
+#else
+// Test
+int32_t ClnkLib_DoMailboxTest(ClnkLib_Handle_t *);
+#endif
+int32_t ClnkLib_DumpBin(ClnkLib_Handle_t *pHandle, char *iface, const char *confdir, const char *fwdir, int flags);
+#ifdef SET_CD_FW_SUPPORT
+int32_t ClnkLib_SetCdFirmwares(ClnkLib_Handle_t *pctx, const char *ifname);
+#endif
+int32_t ClnkLib_StartDaemon(ClnkLib_Handle_t *pctx, MXL_MOCA_DRV_START_DAEMON_CMD_T *pStartOption);
+int32_t ClnkLib_SetApplicationTrace(ClnkLib_Handle_t *pHandle, uint32_t flag);
+
+// MoCA2.5 Features
+// Beacon Power
+int32_t ClnkLib_SetBeaconPower(ClnkLib_Handle_t *pHandle, MXL_BCN_PWR_TYPE_T type, int32_t bcnPower);
+int32_t ClnkLib_GetBeaconPower(ClnkLib_Handle_t *pHandle, ClnkLib_GetBcnPowerRsp_t *pRsp);
+int32_t ClnkLib_SendBeaconPowerPIE(ClnkLib_Handle_t *pHandle, int32_t bcnPower, uint32_t bcnType, uint32_t nodeMask);
+
+// MPS
+int32_t ClnkLib_SetMpsTrigger(ClnkLib_Handle_t *pHandle, MXL_MOCA_SOC_SET_MPS_TRIGGER_RSP_T *pMpsTrigger);
+int32_t ClnkLib_GetMpsState(ClnkLib_Handle_t *pHandle, MXL_MOCA_SOC_GET_MPS_STATE_RSP_T *pMpsState);
+int32_t ClnkLib_GetMpsReport(ClnkLib_Handle_t *pHandle, MXL_MOCA_SOC_GET_MPS_REPORT_RSP_T *pMpsReport);
+
+// Enhanced Privacy
+int32_t ClnkLib_GetEnhancedSecInfo(ClnkLib_Handle_t *pHandle, MXL_MOCA_SOC_GET_EP_SEC_INFO_RSP_T *pEpSecInfo);
+int32_t ClnkLib_GetTrafficPermit(ClnkLib_Handle_t *pHandle, MXL_MOCA_SOC_GET_TRAFFIC_PERMIT_STS_RSP_T *pTrafficPermitRsp);
+int32_t ClnkLib_SetTrafficPermit(ClnkLib_Handle_t *pHandle, MXL_MOCA_SOC_SET_TRAFFIC_PERMIT_CFG_CMD_T *pTrafficPermitCfg);
+int32_t ClnkLib_GetEtherTypeInfo(ClnkLib_Handle_t *pHandle, MXL_MOCA_SOC_GET_ETHER_TYPE_INFO_RSP_T *pEtherTypeInfoRsp);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __CLNK_API_H__ */
+
diff --git a/drivers/net/phy/mxl371x/lib/ClnkLibDev.h b/drivers/net/phy/mxl371x/lib/ClnkLibDev.h
new file mode 100644
index 000000000000..c3241e62e36a
--- /dev/null
+++ b/drivers/net/phy/mxl371x/lib/ClnkLibDev.h
@@ -0,0 +1,85 @@
+/*****************************************************************************************
+ * FILE NAME : ClnkLibDev.h
+ *
+ *
+ * DATE CREATED : Mar/15/2017
+ * LAST MODIFIED :
+ *
+ * DESCRIPTION : c.LINK library device header file.
+ *
+ *
+ *****************************************************************************************
+ * MaxLinear, Inc. retains all right, title and interest (including all intellectual
+ * property rights) in and to this computer program, which is protected by applicable
+ * intellectual property laws. Unless you have obtained a separate written license from
+ * MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., you are not authorized
+ * to utilize all or a part of this computer program for any purpose (including
+ * reproduction, distribution, modification, and compilation into object code), and you
+ * must immediately destroy or return all copies of this computer program. If you are
+ * licensed by MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., your rights
+ * to utilize this computer program are limited by the terms of that license.
+ *
+ * This computer program contains trade secrets owned by MaxLinear, Inc. and, unless
+ * authorized by MaxLinear, Inc. in writing, you agree to maintain the confidentiality
+ * of this computer program and related information and to not disclose this computer
+ * program and related information to any other person or entity.
+ *
+ * Misuse of this computer program or any information contained in it may results in
+ * violations of applicable law. MaxLinear, Inc. vigorously enforces its copyright,
+ * trade secret, patent, contractual, and other legal rights.
+ *
+ * THIS COMPUTER PROGRAM IS PROVIDED "AS IS" WITHOUT ANY WARRANTIES, AND
+ * MAXLINEAR, INC.EXPRESSLY DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE
+ * WARRANTIES OF MERCHANTIBILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND
+ * NONINFRINGEMENT.
+ *
+ ****************************************************************************************
+ * Copyright (c) 2017, MaxLinear, Inc.
+ ****************************************************************************************/
+
+#ifndef __CLNK_LIB_DEV_H__
+#define __CLNK_LIB_DEV_H__
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * Includes
+ ******************************************************************************/
+#include "ClnkLibApi.h"
+
+/*******************************************************************************
+ * Constants
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Macros
+ ******************************************************************************/
+
+/*****************************************************************************
+ * Types
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Public/Private Data
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Public/Private Functions
+ ******************************************************************************/
+
+int32_t ClnkLibDev_Open(ClnkLib_Handle_t *pHandle);
+int32_t ClnkLibDev_OpenByName(ClnkLib_Handle_t *pHandle, char *pName);
+int32_t ClnkLibDev_ListNames(ClnkLib_Name_t *ifNamePtr, int32_t max);
+int32_t ClnkLibDev_GetName(ClnkLib_Handle_t *pHandle, ClnkLib_Name_t *pName);
+int32_t ClnkLibDev_DisplayInterfaces();
+void ClnkLibDev_Close(ClnkLib_Handle_t *pHandle);
+int32_t ClnkLibDev_SendCmd(ClnkLib_Handle_t *pHandle, int cmd,
+ void *in_buf, uint32_t in_len,
+ void *out_buf, uint32_t out_len);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __CLNK_LIB_DEV_H__ */
+
diff --git a/drivers/net/phy/mxl371x/lib/HostCfgLib.h b/drivers/net/phy/mxl371x/lib/HostCfgLib.h
new file mode 100644
index 000000000000..b88e311adafd
--- /dev/null
+++ b/drivers/net/phy/mxl371x/lib/HostCfgLib.h
@@ -0,0 +1,545 @@
+/*****************************************************************************************
+ * FILE NAME : HostCfgLib.h
+ *
+ *
+ * DATE CREATED : Oct/11/2016
+ * LAST MODIFIED :
+ *
+ * DESCRIPTION : Platform &ECB API header file.
+ *
+ *
+ *****************************************************************************************
+ * MaxLinear, Inc. retains all right, title and interest (including all intellectual
+ * property rights) in and to this computer program, which is protected by applicable
+ * intellectual property laws. Unless you have obtained a separate written license from
+ * MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., you are not authorized
+ * to utilize all or a part of this computer program for any purpose (including
+ * reproduction, distribution, modification, and compilation into object code), and you
+ * must immediately destroy or return all copies of this computer program. If you are
+ * licensed by MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., your rights
+ * to utilize this computer program are limited by the terms of that license.
+ *
+ * This computer program contains trade secrets owned by MaxLinear, Inc. and, unless
+ * authorized by MaxLinear, Inc. in writing, you agree to maintain the confidentiality
+ * of this computer program and related information and to not disclose this computer
+ * program and related information to any other person or entity.
+ *
+ * Misuse of this computer program or any information contained in it may results in
+ * violations of applicable law. MaxLinear, Inc. vigorously enforces its copyright,
+ * trade secret, patent, contractual, and other legal rights.
+ *
+ * THIS COMPUTER PROGRAM IS PROVIDED "AS IS" WITHOUT ANY WARRANTIES, AND
+ * MAXLINEAR, INC.EXPRESSLY DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE
+ * WARRANTIES OF MERCHANTIBILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND
+ * NONINFRINGEMENT.
+ *
+ ****************************************************************************************
+ * Copyright (c) 2016, MaxLinear, Inc.
+ ****************************************************************************************/
+
+#ifndef __ECBLIB_API_H__
+#define __ECBLIB_API_H__
+
+
+/*******************************************************************************
+ * Includes
+ ******************************************************************************/
+#include <inttypes.h>
+#include <stdio.h>
+#include <string.h>
+#include "mxl_moca_config.h"
+#include "ClnkLibApi.h"
+
+
+/*******************************************************************************
+ * Constants
+ ******************************************************************************/
+#define CFG_HOSTID "hostid"
+#define CFG_TESTMODE "testmode"
+#define CFG_IPADDR "ipaddr"
+#define CFG_NETMASK "netmask"
+#define CFG_DHCP "netcfgmode"
+#define CFG_GATEWAY "gateway"
+#define CFG_ADMPSWD "admpassword"
+#define CFG_MFR_VENDOR_ID "mfrvendorid"
+#define CFG_MFR_HW_VER "mfrhwver"
+#define CFG_MFR_SW_VER "mfrswver"
+#define CFG_PERSONALITY "personality"
+
+// Configuration file name to be used
+
+#define PLATFORM_CFG_FILE "platform.conf"
+
+#define MOCA_PASSWORD_MAX_LEN 18
+
+#define MAX_RLAPM_MODE_STR_SIZE (17 + 1)
+#define RLAPM_CONF_FILENAME "rlapm.conf"
+#define RLAPM_BACKUP_FILENAME "rlapm.backup"
+#define RLAPM_PS_FILENAME "INCF"
+
+#define MAX_SAPM_MODE_STR_SIZE (16 + 1)
+#define SAPM_CONF_FILENAME "sapm.conf"
+#define SAPM_BACKUP_FILENAME "sapm.backup"
+#define SAPM_PS_FILENAME "SSCF"
+
+#define RSSI_CONF_FILENAME "rssi.conf"
+#define RSSI_BACKUP_FILENAME "rssi.backup"
+#define RSSI_PS_FILENAME "RSCF"
+
+#define ENDET_CONF_FILENAME "endet.conf"
+#define ENDET_BACKUP_FILENAME "endet.backup"
+#define ENDET_PS_FILENAME "EDCF"
+
+#define CLNK_CONF_FILENAME "clink.conf"
+#define CLNK_BACKUP_FILENAME "clink.backup"
+#define CLNK_PS_FILENAME "CLNK"
+
+#define MCAST_CONF_FILENAME "mcast.conf"
+#define MCAST_BACKUP_FILENAME "mcast.backup"
+#define MCAST_PS_FILENAME "MCAS"
+
+
+#define PSAL_RETURN_OK 0
+#define PSAL_RETURN_FAIL -1
+
+#define HW_MAC_ADDR_FMT(x,y) ((x) >>24), (((x)>>16)&0xff), (((x)>>8) &0xff), ((x)&0xff), ((y)>>24) , (((y)>>16) &0xff)
+#define HW_MAC_ADDR_FMT_STR "%02X:%02X:%02X:%02X:%02X:%02X"
+
+#define INT4(a, b, c, d) ( ( (a) << 24) | ((b) << 16) | ( (c) << 8) | d)
+#define IPSTR(d) (uint8_t)((d) >> 24), (uint8_t)(((d) >>16)&0xff), (uint8_t)(((d)>>8) &0xff), (uint8_t)((d) &0xff)
+
+enum
+{
+ MASK_BAND_ED =0,
+ MASK_BAND_D_LO ,
+ MASK_BAND_D_HI ,
+ MASK_BAND_E ,
+ MASK_BAND_FSAT,
+ MASK_BAND_FCBL,
+ MASK_BAND_H,
+ MASK_BAND_CUSTOM,
+};
+
+///Table 7-2. c.LINK Configuration paramters
+///System parameters
+#define CFG_MOCA_VER "mocaversion"
+#define CFG_TEST_MODE "testmode"
+#define CFG_CLNKLED_MODE "clnkledmode"
+#define CFG_TEST_PARAM_1 "testparam1"
+#define CFG_TEST_PARAM_2 "testparam2"
+#define CFG_TEST_PARAM_3 "testparam3"
+#define CFG_TEST_PARAM_4 "testparam4"
+#define CFG_TURBO_MODE "turbomode"
+///ECL Parameters
+#define CFG_MII_PAUSE_PRIO_LEVEL "miipauseprilevel"
+#define CFG_POLICING_MODE "policingmode"
+#define CFG_PQOS_CLASSI_MODE "pqosclassifymode"
+#define CFG_RETRANS_PRIO "retxpriority"
+#define CFG_TRANS_PRIO_PER "txpriorityper"
+//#define CFG_XMII_SAF "xmii"
+#define CFG_MII_SPEED "miispeed"
+///LC Parameters
+#define CFG_FAILOVER_MODE "failovermode"
+#define CFG_HANDOFF_MODE "handoffmode"
+#define CFG_INITIAL_ROLE "initialrole"
+#define CFG_LMO_MODE "lmomode"
+#define CFG_MOCA_PASSWD "mocapassword"
+#define CFG_PREF_NC_MODE "preferrednc"
+#define CFG_SECU_MODE "securitymode"
+#define CFG_NETWORK_SEARCH_MODE "networksearch"
+#define CFG_FREQ_PLAN "freqplan"
+#define CFG_CHANNEL_MASK "channelmask"
+#define CFG_LAST_OPER_FREQ "lof"
+#define CFG_PRIMARY_CHANN_OFFSET "primchnoffset"
+#define CFG_SECOND_CHANN_OFFSET "secchnoffset"
+#define CFG_TABOO_MASK "taboomask"
+#define CFG_TABOO_OFFSET "taboooffset"
+#define CFG_TLP_MIN "tlpmin"
+#define CFG_TLP_MAX "tlpmax"
+///PHY PARAMETERS
+#define CFG_BEACON_TX_POWER "beacontxpower"
+#define CFG_MAX_TX_POWER "maxtxpower"
+#define CFG_TARGET_P2P_RATE50 "tpcphyrate50"
+#define CFG_TARGET_P2P_RATENPER "tpcphyratenper"
+#define CFG_TARGET_P2P_RATEVLPER "tpcphyratevlper"
+#define CFG_STRIP_VLAN_TAG "stripvlantag"
+#define CFG_ENCODING_WORD_LEN_NPER "encwordlennper"
+#define CFG_ENCODING_WORD_LEN_VLPER "encwordlenvlper"
+#define CFG_BITLOAD_MARGIN50 "phymargin"
+#define CFG_BITLOAD_MARGINNPER "phymarginnper"
+#define CFG_BITLOAD_MARGINVLPER "phymarginvlper"
+#define CFG_FEATURE_FLAGS "featureflags"
+#define CFG_TPC_MODE "tpcmode"
+#define CFG_BITLOAD_UCAST50 "phymoducast50"
+#define CFG_BITLOAD_BCAST50 "phymodbcast50"
+#define CFG_BITLOAD_UCAST100 "phymoducast100"
+#define CFG_BITLOAD_BCAST100 "phymodbcast100"
+#define CFG_MOCA_SEQ_NUM_MR "mocaseqnummr"
+///V2 CFGS
+#define CFG_SCAN_OFFSET "scanoffset"
+#define CFG_PRIM_CHN_ABOVE "primchnabove"
+#define CFG_PRIM_CHN_BELOW "primchnbelow"
+#define CFG_SEC_CHN_ABOVE "secchnabove"
+#define CFG_SEC_CHN_BELOW "secchnbelow"
+#define CFG_FREQ_PROFC_GAP_MODE "custombandprofcgapmode"
+#define CFG_FREQ_BAND_MASK "freqbandmask"
+#define CFG_SCAN_MASK "scanmask"
+#define CFG_SCAN_MASK_BAND_D "scanmaskbandd"
+#define CFG_SCAN_MASK_BAND_D_LO "scanmaskbanddlo"
+#define CFG_SCAN_MASK_BAND_D_HI "scanmaskbanddhi"
+#define CFG_SCAN_MASK_BAND_E "scanmaskbande"
+#define CFG_SCAN_MASK_BAND_FSAT "scanmaskbandfsat"
+#define CFG_SCAN_MASK_BAND_FCBL "scanmaskbandfcbl"
+#define CFG_SCAN_MASK_BAND_H "scanmaskbandh"
+#define CFG_SCAN_MASK_CUSTOM "scanmaskcustom"
+#define CFG_SCAN_OFFSET_BAND_D "scanoffsetbandd"
+#define CFG_SCAN_OFFSET_BAND_D_LO "scanoffsetbanddlo"
+#define CFG_SCAN_OFFSET_BAND_D_HI "scanoffsetbanddhi"
+#define CFG_SCAN_OFFSET_BAND_E "scanoffsetbande"
+#define CFG_SCAN_OFFSET_BAND_FSAT "scanoffsetbandfsat"
+#define CFG_SCAN_OFFSET_BAND_FCBL "scanoffsetbandfcbl"
+#define CFG_SCAN_OFFSET_BAND_H "scanoffsetbandh"
+#define CFG_SCAN_OFFSET_CUSTOM "scanoffsetcustom"
+#define CFG_LOF_UPDATE_MODE "lofupdmode"
+#define CFG_PRIM_CHN_ABOVE_BAND_D "primchnabovebandd"
+#define CFG_PRIM_CHN_ABOVE_BAND_D_LO "primchnabovebanddlo"
+#define CFG_PRIM_CHN_ABOVE_BAND_D_HI "primchnabovebanddhi"
+#define CFG_PRIM_CHN_ABOVE_BAND_E "primchnabovebande"
+#define CFG_PRIM_CHN_ABOVE_BAND_FSAT "primchnabovebandfsat"
+#define CFG_PRIM_CHN_ABOVE_BAND_FCBL "primchnabovebandfcbl"
+#define CFG_PRIM_CHN_ABOVE_BAND_H "primchnabovebandh"
+#define CFG_PRIM_CHN_ABOVE_CUSTOM "primchnabovecustom"
+#define CFG_PRIM_CHN_BELOW_BAND_D "primchnbelowbandd"
+#define CFG_PRIM_CHN_BELOW_BAND_D_LO "primchnbelowbanddlo"
+#define CFG_PRIM_CHN_BELOW_BAND_D_HI "primchnbelowbanddhi"
+#define CFG_PRIM_CHN_BELOW_BAND_E "primchnbelowbande"
+#define CFG_PRIM_CHN_BELOW_BAND_FSAT "primchnbelowbandfsat"
+#define CFG_PRIM_CHN_BELOW_BAND_FCBL "primchnbelowbandfcbl"
+#define CFG_PRIM_CHN_BELOW_BAND_H "primchnbelowbandh"
+#define CFG_PRIM_CHN_BELOW_CUSTOM "primchnbelowcustom"
+#define CFG_SEC_CHN_ABOVE_BAND_D "secchnabovebandd"
+#define CFG_SEC_CHN_ABOVE_BAND_D_LO "secchnabovebanddlo"
+#define CFG_SEC_CHN_ABOVE_BAND_D_HI "secchnabovebanddhi"
+#define CFG_SEC_CHN_ABOVE_BAND_E "secchnabovebande"
+#define CFG_SEC_CHN_ABOVE_BAND_FSAT "secchnabovebandfsat"
+#define CFG_SEC_CHN_ABOVE_BAND_FCBL "secchnabovebandfcbl"
+#define CFG_SEC_CHN_ABOVE_BAND_H "secchnabovebandh"
+#define CFG_SEC_CHN_ABOVE_CUSTOM "secchnabovecustom"
+#define CFG_SEC_CHN_BELOW_BAND_D "secchnbelowbandd"
+#define CFG_SEC_CHN_BELOW_BAND_D_LO "secchnbelowbanddlo"
+#define CFG_SEC_CHN_BELOW_BAND_D_HI "secchnbelowbanddhi"
+#define CFG_SEC_CHN_BELOW_BAND_E "secchnbelowbande"
+#define CFG_SEC_CHN_BELOW_BAND_FSAT "secchnbelowbandfsat"
+#define CFG_SEC_CHN_BELOW_BAND_FCBL "secchnbelowbandfcbl"
+#define CFG_SEC_CHN_BELOW_BAND_H "secchnbelowbandh"
+#define CFG_SEC_CHN_BELOW_CUSTOM "secchnbelowcustom"
+#define CFG_TURBO_MODE_BAND_D "turbomodebandd"
+#define CFG_TURBO_MODE_BAND_D_LO "turbomodebanddlo"
+#define CFG_TURBO_MODE_BAND_D_HI "turbomodebanddhi"
+#define CFG_TURBO_MODE_BAND_E "turbomodebande"
+#define CFG_TURBO_MODE_BAND_FSAT "turbomodebandfsat"
+#define CFG_TURBO_MODE_BAND_FCBL "turbomodebandfcbl"
+#define CFG_TURBO_MODE_BAND_H "turbomodebandh"
+#define CFG_TURBO_MODE_CUSTOM "turbomodecustom"
+#define CFG_POLICING_MODE_BAND_D "policingmodebandd"
+#define CFG_POLICING_MODE_BAND_D_LO "policingmodebanddlo"
+#define CFG_POLICING_MODE_BAND_D_HI "policingmodebanddhi"
+#define CFG_POLICING_MODE_BAND_E "policingmodebande"
+#define CFG_POLICING_MODE_BAND_FSAT "policingmodebandfsat"
+#define CFG_POLICING_MODE_BAND_FCBL "policingmodebandfcbl"
+#define CFG_POLICING_MODE_BAND_H "policingmodebandh"
+#define CFG_POLICING_MODE_CUSTOM "policingmodecustom"
+#define CFG_RETXPRIORITY_BAND_D "retxprioritybandd"
+#define CFG_RETXPRIORITY_BAND_D_LO "retxprioritybanddlo"
+#define CFG_RETXPRIORITY_BAND_D_HI "retxprioritybanddhi"
+#define CFG_RETXPRIORITY_BAND_E "retxprioritybande"
+#define CFG_RETXPRIORITY_BAND_FSAT "retxprioritybandfsat"
+#define CFG_RETXPRIORITY_BAND_FCBL "retxprioritybandfcbl"
+#define CFG_RETXPRIORITY_BAND_H "retxprioritybandh"
+#define CFG_RETXPRIORITY_CUSTOM "retxprioritycustom"
+#define CFG_TXPRIORITYPER_BAND_D "txpriorityperbandd"
+#define CFG_TXPRIORITYPER_BAND_D_LO "txpriorityperbanddlo"
+#define CFG_TXPRIORITYPER_BAND_D_HI "txpriorityperbanddhi"
+#define CFG_TXPRIORITYPER_BAND_E "txpriorityperbande"
+#define CFG_TXPRIORITYPER_BAND_FSAT "txpriorityperbandfsat"
+#define CFG_TXPRIORITYPER_BAND_FCBL "txpriorityperbandfcbl"
+#define CFG_TXPRIORITYPER_BAND_H "txpriorityperbandh"
+#define CFG_TXPRIORITYPER_CUSTOM "txprioritypercustom"
+#define CFG_MOCA_PASSWD_BAND_D "mocapasswordbandd"
+#define CFG_MOCA_PASSWD_BAND_D_LO "mocapasswordbanddlo"
+#define CFG_MOCA_PASSWD_BAND_D_HI "mocapasswordbanddhi"
+#define CFG_MOCA_PASSWD_BAND_E "mocapasswordbande"
+#define CFG_MOCA_PASSWD_BAND_FSAT "mocapasswordbandfsat"
+#define CFG_MOCA_PASSWD_BAND_FCBL "mocapasswordbandfcbl"
+#define CFG_MOCA_PASSWD_BAND_H "mocapasswordbandh"
+#define CFG_MOCA_PASSWD_CUSTOM "mocapasswordcustom"
+#define CFG_MOCA_SEQNUMMR_BAND_D "mocaseqnummrbandd"
+#define CFG_MOCA_SEQNUMMR_BAND_D_LO "mocaseqnummrbanddlo"
+#define CFG_MOCA_SEQNUMMR_BAND_D_HI "mocaseqnummrbanddhi"
+#define CFG_MOCA_SEQNUMMR_BAND_E "mocaseqnummrbande"
+#define CFG_MOCA_SEQNUMMR_BAND_FSAT "mocaseqnummrbandfsat"
+#define CFG_MOCA_SEQNUMMR_BAND_FCBL "mocaseqnummrbandfcbl"
+#define CFG_MOCA_SEQNUMMR_BAND_H "mocaseqnummrbandh"
+#define CFG_MOCA_SEQNUMMR_CUSTOM "mocaseqnummrcustom"
+#define CFG_TLP_MIN_BAND_D "tlpminbandd"
+#define CFG_TLP_MIN_BAND_D_LO "tlpminbanddlo"
+#define CFG_TLP_MIN_BAND_D_HI "tlpminbanddhi"
+#define CFG_TLP_MIN_BAND_E "tlpminbande"
+#define CFG_TLP_MIN_BAND_FSAT "tlpminbandfsat"
+#define CFG_TLP_MIN_BAND_FCBL "tlpminbandfcbl"
+#define CFG_TLP_MIN_BAND_H "tlpminbandh"
+#define CFG_TLP_MIN_CUSTOM "tlpmincustom"
+#define CFG_TLP_MAX_BAND_D "tlpmaxbandd"
+#define CFG_TLP_MAX_BAND_D_LO "tlpmaxbanddlo"
+#define CFG_TLP_MAX_BAND_D_HI "tlpmaxbanddhi"
+#define CFG_TLP_MAX_BAND_E "tlpmaxbande"
+#define CFG_TLP_MAX_BAND_FSAT "tlpmaxbandfsat"
+#define CFG_TLP_MAX_BAND_FCBL "tlpmaxbandfcbl"
+#define CFG_TLP_MAX_BAND_H "tlpmaxbandh"
+#define CFG_TLP_MAX_CUSTOM "tlpmaxcustom"
+#define CFG_SECURITY_MODE_BAND_D "securitymodebandd"
+#define CFG_SECURITY_MODE_BAND_D_LO "securitymodebanddlo"
+#define CFG_SECURITY_MODE_BAND_D_HI "securitymodebanddhi"
+#define CFG_SECURITY_MODE_BAND_E "securitymodebande"
+#define CFG_SECURITY_MODE_BAND_FSAT "securitymodebandfsat"
+#define CFG_SECURITY_MODE_BAND_FCBL "securitymodebandfcbl"
+#define CFG_SECURITY_MODE_BAND_H "securitymodebandh"
+#define CFG_SECURITY_MODE_CUSTOM "securitymodecustom"
+#define CFG_TPC_MODE_BAND_D "tpcmodebandd"
+#define CFG_TPC_MODE_BAND_D_LO "tpcmodebanddlo"
+#define CFG_TPC_MODE_BAND_D_HI "tpcmodebanddhi"
+#define CFG_TPC_MODE_BAND_E "tpcmodebande"
+#define CFG_TPC_MODE_BAND_FSAT "tpcmodebandfsat"
+#define CFG_TPC_MODE_BAND_FCBL "tpcmodebandfcbl"
+#define CFG_TPC_MODE_BAND_H "tpcmodebandh"
+#define CFG_TPC_MODE_CUSTOM "tpcmodecustom"
+#define CFG_BITLOAD_MARGIN50_BAND_D "phymarginbandd"
+#define CFG_BITLOAD_MARGIN50_BAND_D_LO "phymarginbanddlo"
+#define CFG_BITLOAD_MARGIN50_BAND_D_HI "phymarginbanddhi"
+#define CFG_BITLOAD_MARGIN50_BAND_E "phymarginbande"
+#define CFG_BITLOAD_MARGIN50_BAND_FSAT "phymarginbandfsat"
+#define CFG_BITLOAD_MARGIN50_BAND_FCBL "phymarginbandfcbl"
+#define CFG_BITLOAD_MARGIN50_BAND_H "phymarginbandh"
+#define CFG_BITLOAD_MARGIN50_CUSTOM "phymargincustom"
+#define CFG_BITLOAD_MARGINNPER_BAND_D "phymarginnperbandd"
+#define CFG_BITLOAD_MARGINNPER_BAND_D_LO "phymarginnperbanddlo"
+#define CFG_BITLOAD_MARGINNPER_BAND_D_HI "phymarginnperbanddhi"
+#define CFG_BITLOAD_MARGINNPER_BAND_E "phymarginnperbande"
+#define CFG_BITLOAD_MARGINNPER_BAND_FSAT "phymarginnperbandfsat"
+#define CFG_BITLOAD_MARGINNPER_BAND_FCBL "phymarginnperbandfcbl"
+#define CFG_BITLOAD_MARGINNPER_BAND_H "phymarginnperbandh"
+#define CFG_BITLOAD_MARGINNPER_CUSTOM "phymarginnpercustom"
+#define CFG_BITLOAD_MARGINVLPER_BAND_D "phymarginvlperbandd"
+#define CFG_BITLOAD_MARGINVLPER_BAND_D_LO "phymarginvlperbanddlo"
+#define CFG_BITLOAD_MARGINVLPER_BAND_D_HI "phymarginvlperbanddhi"
+#define CFG_BITLOAD_MARGINVLPER_BAND_E "phymarginvlperbande"
+#define CFG_BITLOAD_MARGINVLPER_BAND_FSAT "phymarginvlperbandfsat"
+#define CFG_BITLOAD_MARGINVLPER_BAND_FCBL "phymarginvlperbandfcbl"
+#define CFG_BITLOAD_MARGINVLPER_BAND_H "phymarginvlperbandh"
+#define CFG_BITLOAD_MARGINVLPER_CUSTOM "phymarginvlpercustom"
+#define CFG_MPA_MAC_ADDR "mpadstmacaddr"
+#define CFG_MPA_PKT_FILTER "mpamocapktfilter"
+#define CFG_FIRST_CHANNEL_OFFSET_BAND_D "firstchanneloffsetbandd"
+#define CFG_FIRST_CHANNEL_OFFSET_BAND_D_LO "firstchanneloffsetbanddlo"
+#define CFG_FIRST_CHANNEL_OFFSET_BAND_D_HI "firstchanneloffsetbanddhi"
+#define CFG_FIRST_CHANNEL_OFFSET_BAND_E "firstchanneloffsetbande"
+#define CFG_FIRST_CHANNEL_OFFSET_BAND_FSAT "firstchanneloffsetbandfsat"
+#define CFG_FIRST_CHANNEL_OFFSET_BAND_FCBL "firstchanneloffsetbandfcbl"
+#define CFG_FIRST_CHANNEL_OFFSET_BAND_H "firstchanneloffsetbandh"
+#define CFG_FIRST_CHANNEL_OFFSET_CUSTOM "firstchanneloffsetcustom"
+#define CFG_NUMBER_OF_CHANNELS_BAND_D "numberofchannelsbandd"
+#define CFG_NUMBER_OF_CHANNELS_BAND_D_LO "numberofchannelsbanddlo"
+#define CFG_NUMBER_OF_CHANNELS_BAND_D_HI "numberofchannelsbanddhi"
+#define CFG_NUMBER_OF_CHANNELS_BAND_E "numberofchannelsbande"
+#define CFG_NUMBER_OF_CHANNELS_BAND_FSAT "numberofchannelsbandfsat"
+#define CFG_NUMBER_OF_CHANNELS_BAND_FCBL "numberofchannelsbandfcbl"
+#define CFG_NUMBER_OF_CHANNELS_BAND_H "numberofchannelsbandh"
+#define CFG_NUMBER_OF_CHANNELS_CUSTOM "numberofchannelscustom"
+#define CFG_LOADING_CAPS "loadingcaps"
+#define CFG_MAC_ADDR_AGING_TIME "macaddragingtime"
+#define CFG_BCN_PWR_ENABLE "beaconpowerenable"
+#define CFG_BCN_PWR_DIST "beaconpowerdist"
+#define CFG_BCN_PWR_LOCAL "beaconpowerlocal"
+#define CFG_PRIVACY_SUPPORTED "privacysupported"
+#define CFG_ENHANCED_PASSWORD "enhancedpassword"
+#define CFG_NETWORK_NAME "networkname"
+#define CFG_NETWORK_NAME_ADMIT_CFG "networknameadmitcfg"
+#define CFG_ME_NETWORK_IE_PAYLOAD_TX "menetworkiepayloadtx"
+#define CFG_ME_NETWORK_IE_RESP_TIMEOUT "menetworkieresptimeout"
+#define CFG_ME_NETWORK_JOIN_EN "menetworkjoinen"
+#define CFG_MPS_PRIVACY_RECEIVE "mpsprivacyreceive"
+#define CFG_MPS_PRIVACY_DOWN "mpsprivacydown"
+#define CFG_MPS_UNPAIRED_TIME "mpsunpairedtime"
+#define CFG_MPS_WALK_TIME "mpswalktime"
+#define CFG_AUTH_LINK_ETHERTYPE "authlinkethtype"
+#define CFG_AUTH_LINK_BITMASK_0 "authlinkbitmask0"
+#define CFG_AUTH_LINK_BITMASK_1 "authlinkbitmask1"
+#define CFG_AUTH_LINK_BITMASK_2 "authlinkbitmask2"
+#define CFG_AUTH_LINK_BITMASK_3 "authlinkbitmask3"
+#define CFG_AUTH_LINK_BITMASK_4 "authlinkbitmask4"
+#define CFG_AUTH_LINK_BITMASK_5 "authlinkbitmask5"
+#define CFG_AUTH_LINK_BITMASK_6 "authlinkbitmask6"
+#define CFG_AUTH_LINK_BITMASK_7 "authlinkbitmask7"
+#define CFG_AUTH_LINK_BITMASK_8 "authlinkbitmask8"
+#define CFG_AUTH_LINK_BITMASK_9 "authlinkbitmask9"
+#define CFG_AUTH_LINK_BITMASK_10 "authlinkbitmask10"
+#define CFG_AUTH_LINK_BITMASK_11 "authlinkbitmask11"
+#define CFG_AUTH_LINK_BITMASK_12 "authlinkbitmask12"
+#define CFG_AUTH_LINK_BITMASK_13 "authlinkbitmask13"
+#define CFG_AUTH_LINK_BITMASK_14 "authlinkbitmask14"
+#define CFG_AUTH_LINK_BITMASK_15 "authlinkbitmask15"
+#define CFG_TRACE_ENABLE "traceenable"
+#define CFG_TRACE_LEVEL "tracelevel"
+#define CFG_TRACE_MODULE "tracemodule"
+#define CFG_TRACE_DEST "tracedest"
+#define CFG_TRACE_HOST_CTL "tracehostctl"
+#define CFG_HANDOFF_TO_LOWERMOCAVER "handofftolowermocaver"
+
+
+#define MAX_ADMINPASSWORD_LEN 64
+#define TR69_PARAM_NAME_MAX_SIZE 256
+#define TR69_MAX_ACS_URL_SIZE TR69_PARAM_NAME_MAX_SIZE
+#define MAX_ACS_USR_NAME_IN_BYTES 64
+#define MAX_ACS_PASSWD_IN_BYTES 64
+#define MAX_TLS_COMMON_NAME_STR_SIZE_IN_BYTES 64
+#define MAX_TLS_HOST_FILE_SERVER_IN_BYTES 64
+
+/******************************************************************************
+ * Data types
+ *****************************************************************************/
+typedef struct
+{
+ uint32_t hostId;//default val 0
+ uint32_t testmode;//Test mode: normal mode(0), Ethernet control port mode (1)
+ uint32_t netCfgMode;//default static(0) other val is dhcp 1 link local 2
+ uint32_t ipAddr; //default val 192.168.144.20
+ uint32_t netMask; //default val 255.255.255.0
+ uint32_t gateway;//default val 0.0.0.0
+ char adminPasswd[MAX_ADMINPASSWORD_LEN];//max len is 64 , default val maxlinear
+ uint32_t mfrVendorId; //default val 0
+ uint32_t mfrSwVer;//default 0
+ uint32_t mfrHwVer;//default 0
+ uint32_t personality;//default val 0
+ uint32_t tr69Enable;
+ char tr69AcsUrl[TR69_MAX_ACS_URL_SIZE];
+ char tr69AcsUsername[MAX_ACS_USR_NAME_IN_BYTES];
+ char tr69AcsPassword[MAX_ACS_PASSWD_IN_BYTES];
+ uint32_t dnsServer;//default val 0
+ uint32_t acsInformIntervalInSecs;
+ char tlsCommonName[MAX_TLS_COMMON_NAME_STR_SIZE_IN_BYTES];
+ char tlsHostFileServer[MAX_TLS_HOST_FILE_SERVER_IN_BYTES];
+} Lib_EcbCfg_t;
+
+int32_t ClnkHostCfg_GetEcbCfg(int, Lib_EcbCfg_t *); /// 1 to read def, 0 to read current
+int32_t ClnkHostCfg_SetEcbCfg(Lib_EcbCfg_t *);
+
+void ClnkHostCfg_Parse_Number(FILE *fp, int *val);
+void ClnkHostCfg_Parse_Number_Ull(FILE *fp, uint64_t *val);
+void ClnkHostCfg_Parse_String(FILE *fp, char *str, size_t maxlen);
+int ClnkHostCfg_Parse_Macstr(FILE *fp, uint32_t *hi, uint32_t *lo);
+void ClnkHostCfg_Parse_Pwd(FILE *fp, char *str, uint32_t maxlen);
+void ClnkHostCfg_Parse_Mpwd(FILE *fp, char *str, uint32_t maxlen);
+
+void ClnkHostCfg_Plop_Number(FILE *fp, const char *variable, const int value);
+void ClnkHostCfg_Plop_String(FILE *fp, const char *variable, const char *value);
+void ClnkHostCfg_Plop_Ipaddr(FILE *fp, const char *variable, uint32_t value);
+void ClnkHostCfg_Plop_Macaddr(FILE *fp, const char *variable, uint32_t hi, uint32_t lo);
+void ClnkHostCfg_Plop_Hex(FILE *fp, const char *variable, const int value);
+void ClnkHostCfg_Plop_Hex_U8(FILE *fp, const char *variable, const int value);
+void ClnkHostCfg_Plop_Hex_Ull(FILE *fp, const char *variable, const uint64_t value);
+void ClnkHostCfg_Plop_Pwd(FILE *fp, const char *variable, const char *value);
+void ClnkHostCfg_Plop_Mpwd(FILE *fp, const char *variable, const char *value);
+
+
+int ClnkHostCfg_PsWriteClnk(ClnkLib_Handle_t *pHandle, ClnkLib_StaticCfg_t *setup, const char *file_path, const char *fwdir);
+int ClnkHostCfg_PsReadClnk(ClnkLib_Handle_t *pHandle, ClnkLib_StaticCfg_t *setup, int flag, const char *file_path);
+int ClnkHostCfg_PsWriteClnkV2(ClnkLib_Handle_t *pHandle, ClnkLib_ClnkCfgV2_t *setup, const char *file_path, const char *fwdir);
+int ClnkHostCfg_PsReadClnkV2(ClnkLib_Handle_t *pHandle, ClnkLib_ClnkCfgV2_t *setup, int flag, const char *file_path);
+int ClnkHostCfg_PsWriteClnkV2Params(ClnkLib_Handle_t *pHandle, clnk_param_mask_t *mask, ClnkLib_ClnkCfgV2_t *setup);
+int ClnkHostCfg_PsReadClnkV2Params(ClnkLib_Handle_t *pHandle, clnk_param_mask_t *mask, ClnkLib_ClnkCfgV2_t *setup);
+int ClnkHostCfg_PsRestoreClnkV2(ClnkLib_Handle_t *pHandle);
+int ClnkHostCfg_PsWriteMcast(ClnkLib_Handle_t *pHandle, ClnkLib_McastCfg_t *pCfg, const char *file_path, const char *fwdir);
+int ClnkHostCfg_PsReadMcast(ClnkLib_Handle_t *pHandle, ClnkLib_McastCfg_t *pCfg, int flag, const char *file_path);
+int ClnkHostCfg_PsSetMcastFilter(ClnkLib_Handle_t *pHandle, uint32_t macAddrHi, uint32_t macAddrLo, uint32_t mode);
+int ClnkHostCfg_PsSetMcastFilterMode(ClnkLib_Handle_t *pHandle, uint32_t mode);
+int ClnkHostCfg_PsRestoreMcast(ClnkLib_Handle_t *pHandle);
+int ClnkHostCfg_PsReadRlapmV2(ClnkLib_Handle_t *pHandle, ClnkLib_RlapmCfgV2_t *pRlapmCfgV2, int flag, const char *pFilePath);
+int ClnkHostCfg_PsReadStaticRlapmV2(ClnkLib_Handle_t *pHandle, ClnkLib_RlapmStaticCfgV2_t *pRlapmStaticCfgV2, int flag, const char *pFilePath);
+int ClnkHostCfg_PsSaveStaticRlapmV2(ClnkLib_Handle_t *pHandle, const ClnkLib_RlapmStaticCfgV2_t *pRlapmStaticCfgV2, const char *pFilePath, const char *fwdir);
+int ClnkHostCfg_PsReplaceRlapmV2(ClnkLib_Handle_t *pHandle, const char *pNewPathFileName, const char *pFilePath, const char *fwdir);
+int ClnkHostCfg_PsGetRlapmFilenameV2(ClnkLib_Handle_t *pHandle, char *pDstPathFile, const char *pFilePath);
+int ClnkHostCfg_PsSetRlapmProfileId(ClnkLib_Handle_t *pHandle, int32_t profileId);
+int ClnkHostCfg_PsSetRlapmMode(ClnkLib_Handle_t *pHandle, uint32_t band, uint32_t mode);
+int ClnkHostCfg_PsSetRlapmSimpleCfg(ClnkLib_Handle_t *pHandle, int32_t freq, int32_t rxLevel, int32_t margin);
+int ClnkHostCfg_PsReadSapmV2(ClnkLib_Handle_t *pHandle, ClnkLib_SapmCfgV2_t *pSapmCfgV2, int flag, const char *pFilePath);
+int ClnkHostCfg_PsReadStaticSapmV2(ClnkLib_Handle_t *pHandle, ClnkLib_SapmStaticCfgV2_t *pSapmStaticCfgV2, int flag, const char *pFilePath);
+int ClnkHostCfg_PsSaveStaticSapmV2(ClnkLib_Handle_t *pHandle, const ClnkLib_SapmStaticCfgV2_t *pSapmStaticCfgV2, const char *pFilePath, const char *fwdir);
+int ClnkHostCfg_PsReplaceSapmV2(ClnkLib_Handle_t *pHandle, const char *pNewPathFileName, const char *pFilePath, const char *fwdir);
+int ClnkHostCfg_PsGetSapmFilenameV2(ClnkLib_Handle_t *pHandle, char *pDstPathFile, const char *pFilePath);
+int ClnkHostCfg_PsSetSapmProfileId(ClnkLib_Handle_t *pHandle, int32_t profileId);
+int ClnkHostCfg_PsSetSapmMode(ClnkLib_Handle_t *pHandle, uint32_t band, uint32_t mode);
+int ClnkHostCfg_PsSetSapmSimpleCfg(ClnkLib_Handle_t *pHandle, int32_t freq, int32_t threshold, int32_t scStart, int32_t carrier, int32_t margin);
+int ClnkHostCfg_PsWriteRssiV2(ClnkLib_Handle_t *pHandle, ClnkLib_RssiCfgV2_t *pRssiCfgV2, const char *pFilePath, const char *fwdir);
+int ClnkHostCfg_PsReadRssiV2(ClnkLib_Handle_t *pHandle, ClnkLib_RssiCfgV2_t *pRssiCfgV2, int flag, const char *pFilePath);
+int ClnkHostCfg_PsReplaceRssiV2(ClnkLib_Handle_t *pHandle, const char *pNewPathFileName, const char *pFilePath, const char *fwdir);
+int ClnkHostCfg_PsWriteEndet(ClnkLib_Handle_t *pHandle, const ClnkLib_EndetCfg_t *pEndetCfg, const char *pFilePath, const char *fwdir);
+int ClnkHostCfg_PsReadEndet(ClnkLib_Handle_t *pHandle, ClnkLib_EndetCfg_t *pEndetCfg, int flag, const char *pFilePath);
+int ClnkHostCfg_PsReadPlatform(ClnkLib_Handle_t *pHandle, ClnkLib_PlatformCfg_t *pPlatformCfg, int flag, const char *pFilePath);
+int ClnkHostCfg_FromV2ToV1(ClnkLib_ClnkCfgV2_t *v2, ClnkLib_StaticCfg_t *v1);
+int ClnkHostCfg_FromV1ToV2(ClnkLib_StaticCfg_t *v1, ClnkLib_ClnkCfgV2_t *v2);
+uint64_t ConvertPrimChnOffset2PrimChnABMask(uint32_t primChnOffset, uint8_t scanOffset, uint64_t *above, uint64_t *below, int freqplan);
+uint32_t ConvertPrimChnAB2PrimChnOffset(uint64_t above, uint64_t below, int scanOffset, int freq, int32_t lof);
+uint64_t ConvertSecChnOffset2SecChnABMask(uint32_t secChnOffset, uint8_t scanOffset, uint64_t *above, uint64_t *below, int freqplan);
+uint32_t ConvertSecChnAB2SecChnOffset(uint64_t above, uint64_t below, int scanOffset, int freq, int32_t lof);
+uint64_t ConvertChannelMask2ScanMask(uint32_t channelMask, int freqplan);
+int32_t ConvertChannelMask2ScanOffset(uint32_t channelMask, int freqplan);
+uint32_t ConvertScanInfo2ChannelMask(uint64_t scanMask, uint8_t scanOffset, int freq);
+int ClnkHostCfg_GetHwDefVal(ClnkLib_Handle_t *pHandle, char *modnum, uint32_t *diplexCal, uint32_t *miiClkDelay,
+ uint32_t *hwCfgWord, uint32_t *freq, const char *pFilePath);
+ssize_t ClnkHostCfg_SafeWrite(int fd, const void *buf, size_t count);
+ssize_t ClnkHostCfg_FullWrite(int fd, const void *buf, size_t len);
+int32_t ClnkHostCfg_DumpBin(ClnkLib_Handle_t *pHandle, char *iface, const char *confdir, const char *fwdir, int flags);
+
+
+int32_t clnk_parse_configV2(ClnkLib_ClnkCfgV2_t *setup, char *fname);
+int32_t mcast_parse_cfg(ClnkLib_McastCfg_t *pCfg, char *fname);
+int rlapm_parse_rlapmmode_lineV2(FILE *fp, ClnkLib_RlapmCfgV2_t *pRlapmCfgV2, int bandIndex, const char *pFileName);
+int rlapm_parse_rlapmprofileid_lineV2(FILE *fp, int *pRlapmProfileId, const char *pFileName);
+int rlapm_parse_profile_lineV2(FILE *fp, int *pProfile, const char *pFileName);
+int rlapm_parse_freq_lineV2(FILE *fp, ClnkLib_RlapmCfgV2_t *pRlapmCfgV2, int freqIndex, const char *pFileName);
+int rlapm_parse_rxlevel_lineV2(FILE *fp, ClnkLib_RlapmCfgV2_t *pRlapmCfgV2, int freqIndex, const char *pFileName);
+int rlapm_parse_cfgV2(ClnkLib_RlapmCfgV2_t *pRlapmCfgV2, const char *pFileName);
+int rlapm_parse_static_cfgV2(ClnkLib_RlapmStaticCfgV2_t *pRlapmStaticCfgV2, const char *pFileName);
+int sapm_parse_sapmmode_lineV2(FILE *fp, ClnkLib_SapmCfgV2_t *pSapmCfgV2, int bandIndex, const char *pFileName);
+int sapm_parse_sapmprofileid_lineV2(FILE *fp, int *pSapmProfileId, const char *pFileName);
+int sapm_parse_profile_lineV2(FILE *fp, int *pProfile, const char *pFileName);
+int sapm_parse_freq_lineV2(FILE *fp, ClnkLib_SapmCfgV2_t *pSapmCfgV2, int freqIndex, const char *pFileName);
+int sapm_parse_threshold_lineV2(FILE *fp, ClnkLib_SapmCfgV2_t *pSapmCfgV2, int freqIndex, const char *pFileName);
+int sapm_parse_scstart_lineV2(FILE *fp, ClnkLib_SapmCfgV2_t *pSapmCfgV2, int freqIndex, const char *pFileName);
+int sapm_parse_scoffset_lineV2(FILE *fp, ClnkLib_SapmCfgV2_t *pSapmCfgV2, int freqIndex, const char *pFileName);
+int sapm_parse_cfgV2(ClnkLib_SapmCfgV2_t *pSapmCfgV2, const char *pFileName);
+int sapm_parse_static_cfgV2(ClnkLib_SapmStaticCfgV2_t *pSapmStaticCfgV2, const char *pFileName);
+int rssi_parse_tbl_lineV2(FILE *fp, ClnkLib_RssiCfgV2_t *pRssiCfgV2, const char *pFileName);
+int rssi_parse_sfi_lineV2(FILE *fp, ClnkLib_RssiCfgV2_t *pRssiCfgV2, const char *pFileName);
+int rssi_parse_cs_lineV2(FILE *fp, ClnkLib_RssiCfgV2_t *pRssiCfgV2, const char *pFileName);
+int rssi_parse_lgo_lineV2(FILE *fp, ClnkLib_RssiCfgV2_t *pRssiCfgV2, const char *pFileName);
+int32_t rssi_parse_cfgV2(ClnkLib_RssiCfgV2_t *pRssiCfgV2, const char *pFileName);
+int endet_parse_1_arg_str_line(FILE *fp, const char *pParamName,
+ unsigned int *pReturnValueU32,
+ const unsigned int maxValue, const char *pFileName);
+int endet_parse_1_arg_num_line(FILE *fp, const char *pParamName,
+ unsigned int *pReturnValueU32,
+ const unsigned int maxValue, const char *pFileName);
+int endet_parse_4_arg_num_line(FILE *fp, const char *pParamName,
+ unsigned int *pReturnValuesU32,
+ const unsigned int maxValue, const char *pFileName);
+
+int endet_parse_5_arg_num_line(FILE *fp, const char *pParamName,
+ unsigned int *pReturnValuesU32,
+ const unsigned int maxValue, const char *pFileName);
+int endet_parse_8_arg_num_line(FILE *fp, const char *pParamName,
+ unsigned int *pReturnValuesU32,
+ const unsigned int maxValue, const char *pFileName);
+int32_t endet_parse_cfg(ClnkLib_EndetCfg_t *pEndetCfg, const char *pFileName);
+
+#endif
diff --git a/drivers/net/phy/mxl371x/mxl_data_types.h b/drivers/net/phy/mxl371x/mxl_data_types.h
new file mode 100644
index 000000000000..b03c25b4cb71
--- /dev/null
+++ b/drivers/net/phy/mxl371x/mxl_data_types.h
@@ -0,0 +1,79 @@
+/*****************************************************************************************
+ *
+ * FILE NAME : mxl_data_types.h
+ *
+ *
+ *
+ * DATE CREATED : Sep/14/2016
+ *
+ * LAST MODIFIED :
+ *
+ * DESCRIPTION : This file contains MaxLinear's data types.
+ * Instead of using ANSI C data type directly in source code
+ * All modules should include this header file.
+ *
+ *****************************************************************************************
+ * MaxLinear, Inc. retains all right, title and interest (including all intellectual
+ * property rights) in and to this computer program, which is protected by applicable
+ * intellectual property laws. Unless you have obtained a separate written license from
+ * MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., you are not authorized
+ * to utilize all or a part of this computer program for any purpose (including
+ * reproduction, distribution, modification, and compilation into object code), and you
+ * must immediately destroy or return all copies of this computer program. If you are
+ * licensed by MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., your rights
+ * to utilize this computer program are limited by the terms of that license.
+ *
+ * This computer program contains trade secrets owned by MaxLinear, Inc. and, unless
+ * authorized by MaxLinear, Inc. in writing, you agree to maintain the confidentiality
+ * of this computer program and related information and to not disclose this computer
+ * program and related information to any other person or entity.
+ *
+ * Misuse of this computer program or any information contained in it may results in
+ * violations of applicable law. MaxLinear, Inc. vigorously enforces its copyright,
+ * trade secret, patent, contractual, and other legal rights.
+ *
+ * THIS COMPUTER PROGRAM IS PROVIDED "AS IS" WITHOUT ANY WARRANTIES, AND
+ * MAXLINEAR, INC.EXPRESSLY DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE
+ * WARRANTIES OF MERCHANTIBILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND
+ * NONINFRINGEMENT.
+ *
+ ****************************************************************************************
+ * Copyright (c) 2021, MaxLinear, Inc.
+ ****************************************************************************************/
+
+#ifndef __MXL_DATA_TYPES_H__
+#define __MXL_DATA_TYPES_H__
+
+
+/*****************************************************************************************
+ Include Header Files
+ (No absolute paths - paths handled by make file)
+ ****************************************************************************************/
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+
+
+/*****************************************************************************************
+ Macros
+ ****************************************************************************************/
+
+/*****************************************************************************************
+ User-Defined Types (Typedefs)
+ ****************************************************************************************/
+
+typedef float real32_t;
+typedef double real64_t;
+
+/*****************************************************************************************
+ Global Variable Declarations
+ ****************************************************************************************/
+
+/*****************************************************************************************
+ Function Prototypes
+ ****************************************************************************************/
+
+#endif // __MXL_DATA_TYPES_H__
diff --git a/drivers/net/phy/mxl371x/mxl_moca_config.h b/drivers/net/phy/mxl371x/mxl_moca_config.h
new file mode 100644
index 000000000000..2aa90cd325e0
--- /dev/null
+++ b/drivers/net/phy/mxl371x/mxl_moca_config.h
@@ -0,0 +1,404 @@
+/*****************************************************************************************
+ *
+ * FILE NAME : mxl_moca_config.h
+ *
+ *
+ *
+ * DATE CREATED : Sep/14/2016
+ *
+ * LAST MODIFIED :
+ *
+ * DESCRIPTION : Common definitions used by the driver and the lib
+ *
+ *****************************************************************************************
+ * MaxLinear, Inc. retains all right, title and interest (including all intellectual
+ * property rights) in and to this computer program, which is protected by applicable
+ * intellectual property laws. Unless you have obtained a separate written license from
+ * MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., you are not authorized
+ * to utilize all or a part of this computer program for any purpose (including
+ * reproduction, distribution, modification, and compilation into object code), and you
+ * must immediately destroy or return all copies of this computer program. If you are
+ * licensed by MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., your rights
+ * to utilize this computer program are limited by the terms of that license.
+ *
+ * This computer program contains trade secrets owned by MaxLinear, Inc. and, unless
+ * authorized by MaxLinear, Inc. in writing, you agree to maintain the confidentiality
+ * of this computer program and related information and to not disclose this computer
+ * program and related information to any other person or entity.
+ *
+ * Misuse of this computer program or any information contained in it may results in
+ * violations of applicable law. MaxLinear, Inc. vigorously enforces its copyright,
+ * trade secret, patent, contractual, and other legal rights.
+ *
+ * THIS COMPUTER PROGRAM IS PROVIDED "AS IS" WITHOUT ANY WARRANTIES, AND
+ * MAXLINEAR, INC.EXPRESSLY DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE
+ * WARRANTIES OF MERCHANTIBILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND
+ * NONINFRINGEMENT.
+ *
+ ****************************************************************************************
+ * Copyright (c) 2021, MaxLinear, Inc.
+ ****************************************************************************************/
+
+#ifndef __MXL_MOCA_CONFIG_H__
+#define __MXL_MOCA_CONFIG_H__
+
+
+/*****************************************************************************************
+ Include Header Files
+ (No absolute paths - paths handled by make file)
+ ****************************************************************************************/
+
+#include "mxl_data_types.h"
+
+/*****************************************************************************************
+ Macros
+ ****************************************************************************************/
+
+#define DRV_NAME_MDIO "mxl_moca_ctrl"
+#define DRV_NAME_PCIE "mxl_moca_pcie"
+
+#define MAX_NUM_CHANNELS 5
+
+#define LINK_UP 1
+#define LINK_DOWN 0
+#define LINK_FORCE_DOWN -1
+
+#define MXL_MOCA_DATAPATH_MODE_PCIE 0
+#define MXL_MOCA_DATAPATH_MODE_XMII 1
+#define MXL_MOCA_DATAPATH_MODE_UNKNOWN -1
+
+#define FFT_LENGTH 512
+#define MAX_RX_LEVELS 81
+#define MAX_RX_LEVELS_PADDED (((MAX_RX_LEVELS + 3) / 4) * 4) // 84
+#define MAX_RLAPM_FREQS 6
+#define MAX_SAPM_FREQS 4
+#define MAX_MINI_SAPM_MARGIN_LEN 256
+#define MOCA_MAX_PACKET_SIZE 1520 //must align with word boundary
+
+// PclInit_statusWd defines ([31:16]exceptions, [15:0] status)
+#define PCL_INIT_EXCEPTION_SUMMARY_BIT 0x80000000
+
+// PclInit_exceptionWd defines:
+#define PCL_INIT_EXCEPTION_SUMMARY_BIT 0x80000000
+#define GPIO_TO_ASPEN_FAILED 0x00000001
+//set if Aspen Rev B0 in ASPEN_C0 build
+#define INVALID_DEV_ASPEN_C0_BLD 0x00000002
+//set if ! Aspen Rev B0 in !ASPEN_C0 build
+#define INVALID_DEV_ASPEN_B0_BLD 0x00000004
+#define JAWS_SERDES_PLL_LOCK_FAILED 0x00000008
+#define ASPEN_SERDES_PLL_LOCK_FAILED 0x00000010
+#define JAWS_ASPEN_SERDES_LOCK_FAILED 0x00000020
+#define JAWS_ASPEN_SERDES_COMM_CHECK_FAILED 0x00000040
+#define JAWS_ASPEN_SERDES_COMM_FAILURE 0x00000080
+#define LPF_CAL_VALIDATION_FAILED 0x00000100
+#define IQ_COMP_TX_XFER_STS_FAILED 0x00000200
+#define IQ_COMP_RX_XFER_STS_FAILED 0x00000400
+#define IQ_COMP_FAILED_TO_RX_PROBE 0x00000800
+#define PCL_INIT_EXCEPTION_C 0x00001000
+#define PCL_INIT_EXCEPTION_D 0x00002000
+#define PCL_INIT_EXCEPTION_E 0x00004000
+#define PCL_INIT_EXCEPTION_F 0x00008000
+
+
+#define MAX_NUM_NODES 16
+
+#define IFNAME_MAX 15
+#define MAX_NODES 16
+#define MAX_FLOWS_IN_LIST 32
+
+// ADM
+#define ADM_RESULT_ERROR 6
+
+// Energy detect array dimensions
+#define MAX_ATSC_CATV_FREQS 4
+#define MAX_ATSC_CATV_GAPS 8
+#define MAX_WEIGHTS 4
+#define MAX_BTS_CSS_FREQS 6
+#define MAX_BTS_CSS_VALUES 5
+
+// Energy detection related constant
+#define CATV_DETECTED 1<<0
+#define OTA_ATSC_DETECTED 1<<1
+#define CSS_DETECTED 1<<2
+#define BTS_DETECTED 1<<3
+#define NUM_BAND_E_100MHZ_RANK 5
+#define NUM_BAND_F_100MHZ_RANK 6
+#define NUM_BAND_D_100MHZ_RANK 19
+
+#define NUM_BAND_E_50MHZ_RANK 7
+#define NUM_BAND_F_50MHZ_RANK 8
+#define NUM_BAND_D_50MHZ_RANK 21
+
+#define GET_BIT(var, bitoffset) (((var) >> (bitoffset)) & 1)
+
+#define MAX_START_FREQ_INDEX 48
+#define MIN_CHANNEL_SPACING 1
+#define MAX_CHANNEL_SPACING 4
+#define MIN_LOG_GAIN_OFFSET -128
+#define MAX_LOG_GAIN_OFFSET 127
+#define MAX_GCD_TX_POWER 5 // 5dbm out of Chip & ~2.5dbm at F connector on ECA.
+#define MAX_ALLOWED_BACKOFF 30 // db
+
+#define MAX_VERSION_STR_SIZE 24
+#define MAX_HOST_VERSION_STR_SIZE 128
+#define SWITCH_PORT_MAX_VLAN_IDS 16
+#define SWITCH_CAM_STATIC_ENTRIES 128
+#define SWITCH_CAM_DYNAMIC_ENTRIES 128
+#define CLNK_SWITCH_BRIDGE_STATIC_DST 0
+#define CLNK_SWITCH_BRIDGE_DYNAMIC_DST 1
+
+#define MAX_SAPM_PROFILES 16
+#define MAX_RLAPM_PROFILES 16
+#define MAX_FREQ_COMP_TBL_LEN 49
+#define MAX_RSSI_VARS 3
+#define MAX_RSSI_LEN (MAX_FREQ_COMP_TBL_LEN + MAX_RSSI_VARS)
+
+#define LMO_ACA_RPT_PWR_PRFL_SZ 512
+#define MAX_OFDMA_PROFILES 3 // defines for OFDMA
+#define CONFDIR_NAME_MAX 256
+#define FWDIR_NAME_MAX 256
+#define HDRCMD_READ_SW_RESET_STATUS 0x80
+#define HDRCMD_READ_DIP_LINE_STATUS 0x81
+#define HDRCMD_VAL_ON 0x88
+#define HDRCMD_VAL_OFF 0xff
+
+// Bridge detection
+#define MAX_MOCA25_ENHANCED_PASSWORD_LEN 64
+#define MAX_NW_NAME_LEN 32
+#define MOCA25_ME_IE_REQ_PAYLOAD_SIZE_BYTES 60
+#define MOCA25_ME_IE_RSP_PAYLOAD_SIZE_BYTES 62
+#define MOCA25_ME_IE_REQ_MBOX_SIZE_BYTES (MOCA25_ME_IE_RSP_PAYLOAD_SIZE_BYTES + 10)
+#define MOCA25_ME_IE_RSP_MBOX_SIZE_BYTES (MOCA25_ME_IE_RSP_PAYLOAD_SIZE_BYTES + 10)
+#define MAX_ME_NW_IE_PAYLOAD_LEN MOCA25_ME_IE_REQ_MBOX_SIZE_BYTES
+#define DEFAULT_ME_IE_RSP_TIMEOUT 1000 /* Increments of 10 msec */
+
+#define MIN_VAL(x, y) (((x) > (y)) ? (y) : (x))
+#define MAX_VAL(x, y) (((x) > (y)) ? (x) : (y))
+
+/* NOTE: must be large enough to hold EPP data, EVM data, or bridge table */
+#define CLNK_CTL_MAX_IN_LEN 0x4800
+#define CLNK_CTL_MAX_OUT_LEN 0x4800
+
+#define CLNK_HI_PCIE 0
+#define CLNK_HI_MII 1
+#define CLNK_MII_SPD_100M 1
+#define CLNK_MII_SPD_200M 2
+#define CLNK_MII_SPD_1000M 3
+#define CLNK_MII_SPD_1000M_RGMII 4
+
+#define CLNK_BRIDGE_UCAST_DST 0
+#define CLNK_BRIDGE_MCAST_DST 1
+#define CLNK_BRIDGE_PQOS_FLOW 2
+#define CLNK_BRIDGE_UCAST_SRC 3
+#define CLNK_BRIDGE_MCAST_SRC 4
+
+
+// hwCfgWord bit definitions
+#define HW_CFG_HW_REV_0304 0x00000001 // 1 - HW rev 0304; 0 - pre-0304 HW revs
+#define DIPLEXER_ONT 0x00000010
+#define DIPLEXER_BHR 0x00000020
+#define DIPLEXER_UNV 0x00000040
+#define SERDES_TRACE_LENGTH_MASK 0x000F0000
+#define SERDES_TRACE_LENGTH_MIN_TRACE 0x00010000
+#define SERDES_TRACE_LENGTH_MID_TRACE 0x00020000
+#define SERDES_TRACE_LENGTH_MAX_TRACE 0x00040000 //Default - the setting of this bit is not required
+#define SERDES_TRACE_LENGTH_MS_SWITCH 0x00080000
+#define HW_CFG_BAND_D_EXTENDED 0x80000000
+#define HW_CFG_BAND_D_LOW 0x40000000
+#define HW_CFG_BAND_D_HIGH 0x20000000
+#define HW_CFG_BAND_E 0x10000000
+#define HW_CFG_BAND_F 0x08000000
+#define MINDSPEED_CPS_INSTALLED SERDES_TRACE_LENGTH_MS_SWITCH
+
+/* legal values for priv->enable */
+#define PRIV_DISABLED 0 /* must be zero */
+#define PRIV_ENABLED 1
+#define PRIV_SHUTDOWN 2
+#define PRIV_STATUS_EOE 3 /* END OF ENUM */
+
+
+#ifndef MAX_PASSWORD_LENGTH
+#define MAX_PASSWORD_LENGTH 17
+#endif
+#define MAX_PASSWORD_LENGTH_PADDED (((MAX_PASSWORD_LENGTH + 3) / 4) * 4)
+#define MAX_MOCA_EP_PASSWORD_LEN_PADDED 64
+
+#define GPIO_PIN_INVALID -1
+
+// MoCA 2.0 spec limits maximum Ethernet packets per aggregation to 20
+#define MAX_AGGR_FRAMES 20
+// MoCA 2.5 support maximum Ethernet packets per aggregation to 160
+#define MAX_AGGR_FRAMES_V25 160
+
+// The Number of Channel range is 1~5
+#define FREQ_CHN_NUM_MIN 1
+#define FREQ_CHN_NUM_MAX 5
+
+// Define NULL for beacon power
+#define BEACON_POWER_NULL 100 // decimal, the same value as in default config file
+
+#define MAX_BEACON_TX_POWER 10
+
+#define ADM_STATUS_INCORRECT_PSWD 5
+
+/** The module debug flag */
+#define TRACE_HAL (0x00000001)
+#define TRACE_CPCR (0x00000008)
+#define TRACE_OSWP (0x00000020)
+#define TRACE_MBX (0x00000040)
+#define TRACE_CD (0x00000100)
+
+/*******************************************************************************
+* # f e a t u r e d e f i n i t i o n *
+********************************************************************************/
+
+#define NETWORK_TYPE_HIRF_MESH 1
+#define NETWORK_TYPE_MIDRF_MESH 0
+#define NETWORK_TYPE_MESH 1 // needed for mara to compile
+
+/* For SoC JTAG debug */
+#define CARDIFF_JTAG_DEBUG 0
+#
+#define FEATURE_QOS 1
+#define FEATURE_SAPM 1
+#define FEATURE_RLAPM 1
+
+/**
+ * This marks code belonging to the FEIC Power Calibration project.
+ */
+#if ! defined(FEATURE_FEIC_PWR_CAL)
+#define FEATURE_FEIC_PWR_CAL 1
+#endif
+
+/**
+ * This marks code belonging to the Pre UPnP PQoS NMS project.
+ */
+#if ! defined(FEATURE_PUPQ_NMS)
+#define FEATURE_PUPQ_NMS 1
+#endif
+
+/**
+ * This marks code added to round out last minute customer requests.
+ */
+#if ! defined(FEATURE_PUPQ_NMS_QUICK_APIS)
+#define FEATURE_PUPQ_NMS_QUICK_APIS 1
+#endif
+
+/**
+ * This marks code belonging to the Pre UPnP PQoS NMS project-
+ * new configuration items. It is not tested disabled.
+ */
+#if ! defined(FEATURE_PUPQ_NMS_CONF)
+#define FEATURE_PUPQ_NMS_CONF 1
+#endif
+
+/**
+ * This marks code used to collect per-node statistics on receiver
+ * received packet errors, both sync and async.
+ */
+#if ! defined(FEATURE_PUPQ_RX_NODE_STATS)
+#define FEATURE_PUPQ_RX_NODE_STATS 1
+#endif
+
+/**
+ * Define which UEVENTS to generate, note udev is required for systems using
+ * this feature. UEVENTS disabled by default, set to 1 to enable
+ */
+#define ENABLE_LINK_UEVENT 0
+#define ENABLE_ADM_STATUS_UEVENT 0
+
+/*****************************************************************************************
+ User-Defined Types (Typedefs)
+ ****************************************************************************************/
+ // Return Codes
+typedef enum
+{
+ MXL_MOCA_OK = 0, /* OK */
+ MXL_MOCA_ERR = -1, /* Error */
+ MXL_MOCA_NODEV_ERR = -2, /* No MoCA device */
+ MXL_MOCA_WHICHDEV_ERR = -3, /* Which MoCA device to select */
+ MXL_MOCA_MEM_ALLOC_ERR = -4, /* Memory allocation error */
+ MXL_MOCA_RESET_ERR = -5, /* Reset */
+ MXL_MOCA_NOT_OPEN_ERR = -6, /* Not open */
+ MXL_MOCA_LINK_DOWN_ERR = -7, /* Link down */
+ MXL_MOCA_NO_HOST_DESC_ERR = -8, /* No host description */
+ MXL_MOCA_UCAST_FLOOD_ERR = -9, /* Unicast flood */
+ MXL_MOCA_NO_KEY_ERROR = -10, /* No key */
+ MXL_MOCA_PKT_LEN_ERR = -11, /* Packet length error */ // SYS Define
+ MXL_MOCA_INPUT_OUTPUT_ERR = -12, /* Input/output error */
+ MXL_MOCA_PERMISSION_ERR = -13, /* Permission denied (-EACCESS) */
+ MXL_MOCA_INVALID_ADDRESS_ERR = -14, /* Invalid address */
+ MXL_MOCA_INVALID_ARGUMENT_ERR = -15, /* Invalid argument */
+ MXL_MOCA_OUT_OF_SPACE_ERR = -16, /* Out of space */
+ MXL_MOCA_DIR_NOT_EMPTY_ERR = -17, /* Directory not empty */
+ MXL_MOCA_BAD_MSG_TYPE_ERR = -18, /* Bad message type */
+ MXL_MOCA_INVALID_CMD_ERR = -19, /* Operation not supported */
+ MXL_MOCA_TIMEOUT_ERR = -20, /* Timeout */
+ MXL_MOCA_INVALID_PARAM_ERR = -21, /* Invalid input paramters to functions */
+
+ MXL_MOCA_SIGNAL_RECVED = -22, /* Signal received */
+ MXL_MOCA_NO_SOC_RSP = -23, /* SOC did not respond to a command yet */
+ MXL_MOCA_UNKNOWN_SOC_CMD = -24, /* SOC did not recognize a command */
+ MXL_MOCA_BUSY_ERR = -25, /* The device is busy */
+ MXL_MOCA_KTHREAD_SHOULD_STOP = -26, /* Thread should stop */
+ MXL_MOCA_BUS_ERR = -27, /* Bus Error */
+
+ MXL_MOCA_RET_CODE_MAX = -28, /* This must always be last*/
+} MXL_MOCA_STATUS_E;
+
+typedef enum
+{
+ MXL_MOCA_CCPU_IDX=0, // MoCA firmware
+ MXL_MOCA_CLINK_IDX, // MoCA Config: MXL_MOCA_CFG_V2_T
+ MXL_MOCA_MCAST_IDX, // MXL_MOCA_MCAST_CFG_T
+ MXL_MOCA_RLAPM_IDX, // Receive-level added PHY margin
+ MXL_MOCA_ENDET_IDX, // MXL_MOCA_ENERGY_DETECT_CFG_T
+ MXL_MOCA_SAPM_IDX, // Subcarrier added PHY margin
+ MXL_MOCA_RSSI_IDX, // MXL_MOCA_RSSI_CFG_V2_T
+ MXL_MOCA_PLATFORM_IDX, // MXL_MOCA_PLATFORM_CFG_T
+ MXL_MOCA_MAX_FW_IDX,
+} MXL_MOCA_FIRMWARE_IDX_E;
+
+typedef enum
+{
+ MXL_MOCA_SOC_TYPE_JAWS = 0,
+ MXL_MOCA_SOC_TYPE_MALAGA,
+ MXL_MOCA_SOC_TYPE_CARDIFF,
+ MXL_MOCA_SOC_TYPE_LEUCADIA,
+ MXL_MOCA_SOC_TYPE_UNKNOWN,
+ MXL_MOCA_SOC_TYPE_MAX
+} MXL_MOCA_SOC_TYPE_E;
+
+typedef enum
+{
+ MOCA_BAND_D_EXT,
+ MOCA_BAND_D_LO,
+ MOCA_BAND_D_HI,
+ MOCA_BAND_E,
+ MOCA_BAND_F_SAT,
+ MOCA_BAND_F_CBL,
+ MOCA_BAND_H,
+ MOCA_BAND_CUSTOM,
+ MAX_BANDS
+} MXL_MOCA_BAND_E;
+
+enum {
+ CHANNEL_PRIMARY = 0, // Primary Channel
+ CHANNEL_SECONDARY = 1, // Secondary Channel
+ CHANNEL_MAX,
+};
+
+enum {
+ TYPE_OF_LEGACY_PASSWORD = 0,
+ TYPE_OF_ENHANCED_PASSWORD = 1,
+ TYPE_OF_PASSWORD_MAX,
+};
+/*****************************************************************************************
+ Global Variable Declarations
+ ****************************************************************************************/
+
+/*****************************************************************************************
+ Function Prototypes
+ ****************************************************************************************/
+
+#endif // __MXL_MOCA_CONFIG_H__
diff --git a/drivers/net/phy/mxl371x/mxl_moca_dev_main_linux.c b/drivers/net/phy/mxl371x/mxl_moca_dev_main_linux.c
new file mode 100644
index 000000000000..82f45b3f4ce3
--- /dev/null
+++ b/drivers/net/phy/mxl371x/mxl_moca_dev_main_linux.c
@@ -0,0 +1,1199 @@
+/*****************************************************************************************
+ *
+ * FILE NAME : mxl_moca_dev_main_linux.c
+ *
+ *
+ *
+ * DATE CREATED : Sep/21/2016
+ *
+ * LAST MODIFIED :
+ *
+ * DESCRIPTION : This file include the linux related oswp functions
+ *
+ *****************************************************************************************
+ * This file is licensed under GNU General Public license.
+ *
+ * This file is free software: you can redistribute and/or modify it under the
+ * terms of the GNU General Public License, Version 2, as published by the Free
+ * Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but AS-IS and
+ * WITHOUT ANY WARRANTY; without even the implied warranties of MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT. Redistribution,
+ * except as permitted by the GNU General Public License is prohibited.
+ *
+ * You should have received a copy of the GNU General Public License, Version 2
+ * along with this file; if not, see <http://www.gnu.org/licenses/>.
+ *
+ *****************************************************************************************
+ * Copyright (c) 2016 MaxLinear, Inc. All rights reserved.
+ ****************************************************************************************/
+
+#include <linux/init.h>
+#include <linux/version.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)
+#include <generated/autoconf.h>
+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33) ) && ( LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18))
+#include <linux/autoconf.h>
+#else
+#include <linux/config.h>
+#endif
+#include <linux/string.h>
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/proc_fs.h>
+#include <linux/fcntl.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)
+#include <asm/system.h>
+#endif
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <linux/ioport.h>
+#include <linux/sockios.h>
+#include <linux/ethtool.h>
+#include <linux/mtd/mtd.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/device.h>
+#include <linux/netdevice.h>
+#include <linux/firmware.h>
+
+
+#include "mxl_moca_host_version.h"
+#include "mxl_data_types.h"
+#include "mxl_moca_config.h"
+#include "mxl_moca_soc_cmd.h"
+#include "mxl_moca_osal.h"
+# #include "mxl_moca_drv_mdio.h"
+# #include "mxl_moca_drv_soc.h"
+# #include "mxl_moca_drv_main.h"
+# #include "mxl_moca_dev_mgr.h"
+# #include "mxl_moca_hal_mdio_ctrl.h"
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MaxLinear MoCA Driver");
+MODULE_AUTHOR("MaxLinear SW Development Team");
+
+int32_t major;
+
+MXL_MOCA_STATUS_E MxL_MoCA_DrvProcessEthToolCmd(void *pEthToolCmdBuff);
+MXL_MOCA_STATUS_E MxL_MoCA_DrvProcessSIOCSMIIREG(int32_t mocaDevId, void *pSioCmdBuff);
+MXL_MOCA_STATUS_E MxL_MoCA_DrvProcessSIOCGMIIREG(int32_t mocaDevId, void *pSioCmdBuff);
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DbgShowMocaCmdInfo
+ *
+ *
+ * DATE CREATED : Oct/4/2016
+ *
+ * DESCRIPTION : Display CmdInfo
+ *
+ *
+ * IN PARAMS : ioctlCmd Ioctl request command.
+ * pMocaOpCmd Pointer to MoCA CMD structure
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_DbgShowMocaCmdInfo(uint32_t ioctlCmd, MXL_MOCA_OP_CMD_T *pMocaOpCmd)
+{
+ uint32_t *pCmdBuf;
+ uint32_t cnt;
+
+ pCmdBuf = (uint32_t *)pMocaOpCmd;
+
+ // Display some cmd buf
+ for (cnt = 0; cnt < 5; cnt++)
+ {
+ DEBUG_PRINT(TRACE_OSWP, L_INFO,"CmdBuf[%d]: %08x \n", cnt, *pCmdBuf);
+ pCmdBuf++;
+ }
+
+ // Display CMD, can add more for other command debug in the future
+ switch (ioctlCmd)
+ {
+ case SIOC_MXL_MOCA_START_DAEMON:
+ DEBUG_PRINT(TRACE_OSWP, L_INFO, ": START DAEMON, cmdId = %#x, len=%x (%d) \n",
+ pMocaOpCmd->mocaCmdId,
+ pMocaOpCmd->mocaCmdLenInBytes,
+ pMocaOpCmd->mocaCmdLenInBytes);
+ for (cnt = 0; cnt < (pMocaOpCmd->mocaCmdLenInBytes/4); cnt++)
+ DEBUG_PRINT(TRACE_OSWP, L_INFO,"startDaemonCmdBuf[%d]: %08x \n", cnt, *pCmdBuf);
+ break;
+
+ case SIOC_MXL_MOCA_DBG_GET_MEM:
+ DEBUG_PRINT(TRACE_OSWP, L_INFO, ": GET mem, cmdId = %#x, len=%x, addr=0x%x \n",
+ pMocaOpCmd->mocaCmdId,
+ pMocaOpCmd->mocaCmdLenInBytes,
+ pMocaOpCmd->uCmd.drvGetDbgMemCmd.socMemAddr);
+ break;
+
+ case SIOC_MXL_MOCA_DBG_SET_MEM:
+ DEBUG_PRINT(TRACE_OSWP, L_INFO, ": SET mem, cmdId = %#x, len=%x, addr=0x%x\n",
+ pMocaOpCmd->mocaCmdId,
+ pMocaOpCmd->mocaCmdLenInBytes,
+ pMocaOpCmd->uCmd.drvSetDbgMemCmd.socMemAddr[0]);
+ break;
+
+ default:
+ DEBUG_PRINT(TRACE_OSWP, L_INFO, "SIO command :%#010x \n", pMocaOpCmd->mocaCmdId);
+ break;
+ }
+
+ return ;
+}
+
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DbgShowMocaCmdRspInfo
+ *
+ *
+ * DATE CREATED : Oct/4/2016
+ *
+ * DESCRIPTION : Display RspInfo
+ *
+ *
+ * IN PARAMS : ioctlCmd Ioctl request command.
+ * pMocaOpRsp Pointer to MoCA CMD Rsp structure
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_DbgShowMocaCmdRspInfo(uint32_t ioctlCmd, MXL_MOCA_OP_RSP_T *pMocaOpRsp)
+{
+ // Can add more for debug in the future
+ switch (ioctlCmd)
+ {
+ case SIOC_MXL_MOCA_DBG_GET_MEM:
+ DEBUG_PRINT(TRACE_OSWP, L_INFO, ": GET mem, Rsp, cmdId = %#x, len=%x, addr=0x%x \n",
+ pMocaOpRsp->mocaCmdId,
+ pMocaOpRsp->mocaRspLenInBytes,
+ pMocaOpRsp->uRsp.drvGetDbgMemRsp.usrData[0]);
+ break;
+
+ case SIOC_MXL_MOCA_DBG_SET_MEM:
+ DEBUG_PRINT(TRACE_OSWP, L_INFO, ": SET mem, Rsp, cmdId = %#x, len=%x\n",
+ pMocaOpRsp->mocaCmdId,
+ pMocaOpRsp->mocaRspLenInBytes);
+ break;
+
+ default:
+ DEBUG_PRINT(TRACE_OSWP, L_INFO, "MoCA command :%#010x \n", pMocaOpRsp->mocaCmdId);
+ break;
+ }
+
+ return ;
+}
+
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevIoctl
+ *
+ *
+ * DATE CREATED : Sep/21/2016
+ *
+ * DESCRIPTION : add Mdio protocol
+ *
+ *
+ * IN PARAMS : inode The standard device node link.
+ * filp Driver file descriptor, all the dynamic resource saved
+ * in the private_data area.
+ * ioctlCmd Ioctl request command.
+ * pMocaParam The ioctl parameters
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : status of success or failure
+ *--------------------------------------------------------------------------------------*/
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
+static long MxL_MoCA_DevIoctl(struct file *filp,
+ uint32_t ioctlCmd,
+ unsigned long pMocaParam)
+#else
+static int32_t MxL_MoCA_DevIoctl(struct inode *inode,
+ struct file *filp,
+ uint32_t ioctlCmd,
+ unsigned long pMocaParam)
+#endif
+{
+ MXL_MOCA_DEV_CTRL_MGR_T *pDevCtrlMgr;
+ uint32_t mocaDevId = 0;
+ uint32_t mocaSubCmdId = 0;
+ struct ifreq ifr;
+ MXL_MOCA_CMD_PARAMS ioctlMocaCmdParam; // MoCA comamnd parameter pointers from User Mode
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
+ struct inode *inode = filp->f_path.dentry->d_inode;
+ long ret = MXL_MOCA_ERR;
+#else
+ int32_t ret = MXL_MOCA_ERR;
+#endif
+
+ MXL_ENTER_FUNCTION(TRACE_OSWP, "inode = %p, filp = %p, ioctlCmd = %#x, pMocaParam = %#x",
+ inode, filp, ioctlCmd, pMocaParam);
+
+ // Get MoCA control device ID
+ mocaDevId = iminor(inode);
+
+ // Get MoCA devMgr global data for this control device
+ pDevCtrlMgr = MxL_MoCA_DevGetCtrlMgrInstanceHandle(mocaDevId);
+
+ if (NULL == pDevCtrlMgr)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "NULL pointer in %s line %d\n", __func__, __LINE__);
+ return MXL_MOCA_ERR;
+ }
+
+ // Lock for MoCA processing, TODO: add lock timeout processing
+ MxL_MoCA_OsalLock(&pDevCtrlMgr->mocaDevLock);
+
+ // CMD processing
+ do
+ {
+ // Copy ifreq structure data from user space (use ioctl system param)
+ ret = MxL_MoCA_OsalCopyFromUser(&ifr, (void*)pMocaParam, sizeof(ifr));
+
+ if (MXL_MOCA_OK != ret)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "Line %d, cmd 0x%x: copy data from user FAILED!\n",
+ __LINE__, ioctlCmd);
+ break;
+ }
+
+ // MoCA sub command processing
+ if (ioctlCmd >= SIOC_MXL_MOCA_CMD && ioctlCmd <= SIOC_MXL_MOCA_START_DAEMON)
+ {
+ // Copy moca cmd data from user space (use ifreq data pointer)
+ ret = MxL_MoCA_OsalCopyFromUser(&ioctlMocaCmdParam,
+ (void*)ifr.ifr_data,
+ sizeof(MXL_MOCA_CMD_PARAMS));
+ if (MXL_MOCA_OK != ret)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "Line %d, cmd 0x%x: copy data from user FAILED!\n",
+ __LINE__, ioctlCmd);
+ break;
+ }
+
+ // Copy moca command data (mocaCmdId and mocaCmdLenInBytes) from user space
+ ret = MxL_MoCA_OsalCopyFromUser(&pDevCtrlMgr->mocaOpCmd,
+ (void*)ioctlMocaCmdParam.pParam1,
+ sizeof(pDevCtrlMgr->mocaOpCmd.mocaCmdId) +
+ sizeof(pDevCtrlMgr->mocaOpCmd.mocaCmdLenInBytes));
+ if (MXL_MOCA_OK != ret)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "Line %d, cmd 0x%x: copy data from user FAILED!\n",
+ __LINE__, ioctlCmd);
+ break;
+ }
+
+ // Check mocaCmdLenInBytes is valid
+ if (pDevCtrlMgr->mocaOpCmd.mocaCmdLenInBytes > sizeof(pDevCtrlMgr->mocaOpCmd.uCmd))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "Line %d, cmd 0x%x, inLen 0x%x is large than cmdLen 0x%x\n",
+ __LINE__, ioctlCmd, pDevCtrlMgr->mocaOpCmd.mocaCmdLenInBytes,
+ sizeof(pDevCtrlMgr->mocaOpCmd.uCmd));
+ break;
+ }
+
+ // Copy moca command data (uCmd) from user space
+ ret = MxL_MoCA_OsalCopyFromUser(&pDevCtrlMgr->mocaOpCmd.uCmd,
+ (void*)(ioctlMocaCmdParam.pParam1 +
+ sizeof(pDevCtrlMgr->mocaOpCmd.mocaCmdId) +
+ sizeof(pDevCtrlMgr->mocaOpCmd.mocaCmdLenInBytes)),
+ pDevCtrlMgr->mocaOpCmd.mocaCmdLenInBytes);
+ if (MXL_MOCA_OK != ret)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "Line %d, cmd 0x%x: copy data from user FAILED!\n",
+ __LINE__, ioctlCmd);
+ break;
+ }
+
+ // Display cmd info for debug
+ MxL_MoCA_DbgShowMocaCmdInfo(ioctlCmd, &pDevCtrlMgr->mocaOpCmd);
+
+ // Get and check the expected response length from user space, and will stop
+ // this command processing if the rsp len size is bigger than max rsp len size
+ ret = MxL_MoCA_OsalCopyFromUser(&pDevCtrlMgr->mocaOpRsp,
+ (void*)ioctlMocaCmdParam.pParam2,
+ sizeof(pDevCtrlMgr->mocaOpRsp.mocaCmdId) +
+ sizeof(pDevCtrlMgr->mocaOpRsp.mocaRspLenInBytes));
+ if (MXL_MOCA_OK != ret)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "Line %d, cmd 0x%x: copy data from user FAILED!\n",
+ __LINE__, ioctlCmd);
+ break;
+ }
+ if (pDevCtrlMgr->mocaOpRsp.mocaRspLenInBytes > sizeof(pDevCtrlMgr->mocaOpRsp.uRsp))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "Line %d, cmd 0x%x, outLen 0x%x is large than rspLen 0x%x\n",
+ __LINE__, ioctlCmd, pDevCtrlMgr->mocaOpRsp.mocaRspLenInBytes,
+ sizeof(pDevCtrlMgr->mocaOpRsp.uRsp));
+ break;
+ }
+
+ // Display Rsp info from APP for debug
+ MxL_MoCA_DbgShowMocaCmdRspInfo(ioctlCmd, &pDevCtrlMgr->mocaOpRsp);
+ }
+
+ switch (ioctlCmd)
+ {
+ // ### MoCA command processing ###
+
+ case SIOC_MXL_MOCA_START_DAEMON:
+ // Save MoCA sub command for cmd status return status check later in this function
+ mocaSubCmdId = pDevCtrlMgr->mocaOpCmd.mocaCmdId;
+
+ // Start daemon command handler
+ ret = MxL_MoCA_DevProcessDaemonCmd(pDevCtrlMgr);
+ break;
+
+ case SIOC_MXL_MOCA_DBG_GET_MEM:
+ case SIOC_MXL_MOCA_DBG_SET_MEM:
+ // Save MoCA sub command for cmd status return status check later in this function
+ mocaSubCmdId = pDevCtrlMgr->mocaOpCmd.mocaCmdId;
+
+ ret = MxL_MoCA_DevProcessDbgCmd(pDevCtrlMgr);
+ break;
+
+ case SIOC_MXL_MOCA_CMD:
+ // Save MoCA sub command for cmd status return status check later in this function
+ mocaSubCmdId = pDevCtrlMgr->mocaOpCmd.mocaCmdId;
+
+ // MoCA driver and SoC command handler
+ ret = MxL_MoCA_DevProcessCmd(pDevCtrlMgr);
+ break;
+
+ // ### OS service related command processing ###
+
+ case SIOCETHTOOL:
+ // Input/output buffer from appication is passed as part of ifr data structure
+ ret = MxL_MoCA_DrvProcessEthToolCmd((void*)ifr.ifr_data);
+ break;
+
+ case SIOCSMIIREG:
+ // Input/output buffer from appication is passed as part of raw request i.e not using ifr data structure
+ ret = MxL_MoCA_DrvProcessSIOCSMIIREG(mocaDevId, (void *)pMocaParam);
+ break;
+
+ case SIOCGMIIREG:
+ // Input/output buffer from appication is passed as part of raw request i.e not using ifr data structure
+ ret = MxL_MoCA_DrvProcessSIOCGMIIREG(mocaDevId, (void *)pMocaParam);
+ break;
+
+ default:
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "ioctlCmd :%#010x is not supported\n",
+ ioctlCmd);
+ ret = MXL_MOCA_INVALID_CMD_ERR;
+ break;
+ }
+
+ // MoCA command rsp processing
+ if (MXL_MOCA_OK == ret &&
+ (ioctlCmd >= SIOC_MXL_MOCA_CMD && ioctlCmd <= SIOC_MXL_MOCA_START_DAEMON))
+ {
+ // Display Rsp info to APP for debug
+ MxL_MoCA_DbgShowMocaCmdRspInfo(ioctlCmd, &pDevCtrlMgr->mocaOpRsp);
+
+ // Send Rsp back to user mode Apps
+ pDevCtrlMgr->mocaOpRsp.mocaCmdId = mocaSubCmdId;
+
+ if (MxL_MoCA_OsalCopyToUser((MXL_MOCA_OP_RSP_T *)ioctlMocaCmdParam.pParam2,
+ &pDevCtrlMgr->mocaOpRsp,
+ pDevCtrlMgr->mocaOpRsp.mocaRspLenInBytes +
+ sizeof(pDevCtrlMgr->mocaOpRsp.mocaCmdId) +
+ sizeof(pDevCtrlMgr->mocaOpRsp.mocaRspLenInBytes)))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR,
+ "MxL_MoCA_OsalCopyToUser() failed for ioctlCmd: %#x!\n",
+ ioctlCmd);
+ }
+ }
+
+ } while (0);
+
+ // Unlock for MoCA CMD processing
+ MxL_MoCA_OsalUnlock(&pDevCtrlMgr->mocaDevLock);
+
+ // Check return status and print info if not OK
+ if (MXL_MOCA_OK != ret)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "## Failed to handle ioctlCmd = %#x\n",
+ ioctlCmd);
+ }
+
+ MXL_EXIT_FUNCTION(TRACE_OSWP, "status = %d", ret);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevRelease
+ *
+ *
+ * DATE CREATED : Sep/24/2016
+ *
+ * DESCRIPTION : Driver release function, judge if the driver has no caller, if it is,
+ * then release the dynamic resource.
+ *
+ *
+ * IN PARAMS : inode The standard device node link.
+ * : filp Driver file descriptor, all the dynamic resource saved
+ * in the private_data area.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : 0 for success, others for failure
+ *--------------------------------------------------------------------------------------*/
+
+static int32_t MxL_MoCA_DevRelease(struct inode *inode, struct file *filp)
+{
+ return 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevRead
+ *
+ *
+ * DATE CREATED : Sep/24/2016
+ *
+ * DESCRIPTION : Driver read function, provide the standard method to read memory
+ * from user space.
+ *
+ *
+ * IN PARAMS : filp Driver file descriptor, all the dynamic resource saved
+ * in the private_data area.
+ * : buf The user space memory pointer.
+ * : count How many bytes to be read.
+ * : f_pos The file pointer to control where to read.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : The number of bytes read, or -1 for failure.
+ *--------------------------------------------------------------------------------------*/
+
+ssize_t MxL_MoCA_DevRead(struct file *filp, char *buf, size_t count, loff_t *f_pos)
+{
+ ssize_t sz = 0;
+
+ MXL_ENTER_FUNCTION(TRACE_OSWP, "filp = %p, buf = %p, count = %u, f_pos = %d", filp, buf, count, f_pos);
+
+ MXL_EXIT_FUNCTION(TRACE_OSWP, "status = %u", sz);
+
+ return sz;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevWrite
+ *
+ *
+ * DATE CREATED : Sep/24/2016
+ *
+ * DESCRIPTION : Driver write function, provide the standard method to write to device
+ * from user space.
+ *
+ *
+ * IN PARAMS : filp Driver file descriptor, all the dynamic resource saved
+ * in the private_data area.
+ * : buf The user space memory pointer.
+ * : count How many bytes to write.
+ * : f_pos The file pointer to control where to write.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : The number of bytes written, or -1 for failure.
+ *--------------------------------------------------------------------------------------*/
+
+ssize_t MxL_MoCA_DevWrite(struct file *filp, const char *buf, size_t count, loff_t *f_pos)
+{
+ ssize_t sz = 0;
+
+ MXL_ENTER_FUNCTION(TRACE_OSWP, "filp = %p, buf = %p, count = %u, f_pos = %d", filp, buf, count, f_pos);
+
+ MXL_EXIT_FUNCTION(TRACE_OSWP, "status = %u", sz);
+
+ return sz;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevOpen
+ *
+ *
+ * DATE CREATED : Sep/24/2016
+ *
+ * DESCRIPTION : Driver open function, provide the standard method to open the driver.
+ *
+ *
+ * IN PARAMS : inode The standard device node link.
+ * filp Driver file descriptor, all the dynamic resource saved
+ * in the private_data area.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : 0 for success, others for failure
+ *--------------------------------------------------------------------------------------*/
+
+static int32_t MxL_MoCA_DevOpen(struct inode *inode, struct file *filp)
+{
+ return MXL_MOCA_OK;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DrvProcessEthToolCmd
+ *
+ *
+ * DATE CREATED : Sep/28/2016
+ *
+ * DESCRIPTION : Process the eth tool command
+ *
+ *
+ * IN PARAMS : pMxlMocaOpCmd The command to process
+ *
+ * OUT PARAMS : pMxlMocaOpRsp The response for the command
+ *
+ * RETURN VALUE : status of success or failure
+ *
+ * NOTES : Used the linux data struct "ethtool_drvinfo", not put in command handler
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_DrvProcessEthToolCmd(void *pEthToolCmdBuff)
+{
+ uint32_t ethToolCmd;
+ struct ethtool_drvinfo drvInfo = {ETHTOOL_GDRVINFO};
+ MXL_MOCA_STATUS_E status = MXL_MOCA_OK;
+
+
+ if (NULL == pEthToolCmdBuff)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, " %s : INVALID input parameter\n", __func__);
+ return MXL_MOCA_ERR;
+ }
+
+
+ if (MxL_MoCA_OsalCopyFromUser(&ethToolCmd, (void *)pEthToolCmdBuff, sizeof(ethToolCmd)))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, " %s : MxL_MoCA_OsalCopyFromUser FAILED!\n", __func__);
+ status = MXL_MOCA_ERR;
+ }
+ else
+ {
+ switch (ethToolCmd)
+ {
+ case ETHTOOL_GDRVINFO:
+
+ MxL_MoCA_OsalMemcpy(drvInfo.driver, DRV_NAME, sizeof(DRV_NAME));
+ MxL_MoCA_OsalMemcpy(drvInfo.version, VERSION_HOST_STR, sizeof(VERSION_HOST_STR));
+
+ if(MxL_MoCA_OsalCopyToUser(pEthToolCmdBuff, &drvInfo, sizeof(drvInfo)))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, " %s : %d ethToolCmd -- MxL_MoCA_OsalCopyToUser FAILED!\n", __func__, __LINE__);
+ status = MXL_MOCA_ERR;
+ }
+
+ break;
+
+ default:
+ status = MXL_MOCA_ERR;
+ break;
+ }
+
+ }
+
+ return status;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DrvProcessSIOCSMIIREG
+ *
+ *
+ * DATE CREATED : Oct/04/2016
+ *
+ * DESCRIPTION : Process SIOCSMIIREG command - Write MMI Register
+ *
+ * IN PARAMS : mocaDevId Moca device ID
+ * pSioCmdBuff Pointer to command buffer
+ *
+ * OUT PARAMS : MXL_MOCA_STATUS_E
+ *
+ * RETURN VALUE : status of success or failure
+ *
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_DrvProcessSIOCSMIIREG(int32_t mocaDevId, void *pSioCmdBuff)
+{
+ MXL_MOCA_DRV_RW_MII_REG_CMD_T sioCmdBuff;
+ MXL_MOCA_DEV_CTRL_MGR_T *pDevCtrlMgr = NULL;
+ MXL_MOCA_STATUS_E status = MXL_MOCA_OK;
+
+ pDevCtrlMgr = MxL_MoCA_DevGetCtrlMgrInstanceHandle(mocaDevId);
+
+ if (NULL == pDevCtrlMgr)
+ {
+ status = MXL_MOCA_NODEV_ERR;
+ return status;
+ }
+
+ // Copy input parameter from host app to (user mode) to kernel memory
+ if (MxL_MoCA_OsalCopyFromUser(&sioCmdBuff, pSioCmdBuff, sizeof(sioCmdBuff)))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, " %s : %d SET MMI -- MxL_MoCA_OsalCopyToUser FAILED!\n", __func__, __LINE__);
+ status = MXL_MOCA_ERR;
+ }
+ else
+ {
+ // Call lower level driver to perform mmi write operation
+ status = MxL_MoCA_DevProcessWriteMiiCmd(pDevCtrlMgr, &sioCmdBuff);
+
+ if (MXL_MOCA_OK != status)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, " %s : %d SET MMI -- MxL_MoCA_DevProcessWriteMiiCmd FAILED!\n", __func__, __LINE__);
+ }
+ }
+
+ return status;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DrvProcessSIOCGMIIREG
+ *
+ *
+ * DATE CREATED : Oct/04/2016
+ *
+ * DESCRIPTION : Process SIOCGMIIREG command - Read MMI Register
+ *
+ * IN PARAMS : mocaDevId Moca device ID
+ * pSioCmdBuff Pointer to command buffer
+ *
+ * OUT PARAMS : MXL_MOCA_STATUS_E
+ *
+ * RETURN VALUE : status of success or failure
+ *
+ *--------------------------------------------------------------------------------------*/
+MXL_MOCA_STATUS_E MxL_MoCA_DrvProcessSIOCGMIIREG(int32_t mocaDevId, void *pSioCmdBuff)
+{
+ MXL_MOCA_DRV_RW_MII_REG_CMD_T sioCmdBuff;
+ MXL_MOCA_DEV_CTRL_MGR_T *pDevCtrlMgr = NULL;
+ MXL_MOCA_STATUS_E status = MXL_MOCA_OK;
+
+ pDevCtrlMgr = MxL_MoCA_DevGetCtrlMgrInstanceHandle(mocaDevId);
+ if (NULL == pDevCtrlMgr)
+ {
+ status = MXL_MOCA_NODEV_ERR;
+ return status;
+ }
+
+ // Copy input parameter from host app to (user mode) to kernel memory
+ if (MxL_MoCA_OsalCopyFromUser(&sioCmdBuff, pSioCmdBuff, sizeof(sioCmdBuff)))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, " %s : %d GET MMI -- MxL_MoCA_OsalCopyToUser FAILED!\n", __func__, __LINE__);
+ status = MXL_MOCA_ERR;
+ }
+ else
+ {
+ // Call lower level driver to perform mmi read operation
+ status = MxL_MoCA_DevProcessReadMiiCmd(pDevCtrlMgr, &sioCmdBuff);
+
+ if (MXL_MOCA_OK != status)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, " %s : %d GET MMI -- MxL_MoCA_DevProcessWriteMiiCmd FAILED!\n", __func__, __LINE__);
+ }
+
+ // Copy back data read from device using mmi interface
+ if (MxL_MoCA_OsalCopyToUser(pSioCmdBuff, &sioCmdBuff, sizeof(sioCmdBuff)))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, " %s : %d GET MMI -- MxL_MoCA_OsalCopyToUser FAILED!\n", __func__, __LINE__);
+ status = MXL_MOCA_ERR;
+ }
+ }
+
+ return status;
+}
+
+static struct file_operations fops =
+{
+ .read = MxL_MoCA_DevRead,
+ .write = MxL_MoCA_DevWrite,
+ .open = MxL_MoCA_DevOpen,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
+ /**************************************************************************
+ * Answer: From The new way of ioctl() by Jonathan Corbet:
+ *
+ * ioctl() is one of the remaining parts of the kernel which runs under
+ * the Big Kernel Lock (BKL). In the past, the usage of the BKL has made
+ * it possible for long-running ioctl() methods to create long latencies
+ * for unrelated processes.
+ *
+ * Follows an explanation of the patch that introduced unlocked_ioctl
+ * and compat_ioctl into 2.6.11. The removal of the ioctl field happened
+ * a lot later, in 2.6.36.
+ *
+ * Explanation: When ioctl was executed, it took the Big Kernel Lock
+ * (BKL), so nothing else could execute at the same time. This is very
+ * bad on a multiprocessor machine, so there was a big effort to get rid
+ * of the BKL. First, unlocked_ioctl was introduced. It lets each driver
+ * writer choose what lock to use instead. This can be difficult, so there
+ * was a period of transition during which old drivers still worked
+ * (using ioctl) but new drivers could use the improved interface
+ * (unlocked_ioctl). Eventually all drivers were converted and ioctl could
+ * be removed.
+ *
+ * compat_ioctl is actually unrelated, even though it was added at the same
+ * time. Its purpose is to allow 32-bit userland programs to make ioctl calls
+ * on a 64-bit kernel. The meaning of the last argument to ioctl depends on
+ * the driver, so there is no way to do a driver-independent conversion.
+ ********************************************************************************/
+ .unlocked_ioctl = MxL_MoCA_DevIoctl,
+#else
+ .ioctl = MxL_MoCA_DevIoctl,
+#endif
+ .release = MxL_MoCA_DevRelease,
+};
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevInit
+ *
+ *
+ * DATE CREATED : Sep/21/2016
+ *
+ * DESCRIPTION : System device init function, called when insmod
+ *
+ *
+ * IN PARAMS : None
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : status of success or failure
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_DevInit(void)
+{
+ MXL_MOCA_STATUS_E result = MXL_MOCA_ERR;
+
+ MXL_ENTER_FUNCTION(TRACE_OSWP, "void");
+
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_INFO, "MoCA driver version: v%s\n", VERSION_HOST_STR);
+
+ // Register as character device
+ major = register_chrdev(major, DRV_NAME, &fops);
+
+ if (major < 0)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "%s %s register_chrdev failed\n", DRV_NAME, VERSION_HOST_STR);
+ }
+ else
+ {
+ result = MxL_MoCA_DrvInit();
+ }
+
+ if (MXL_MOCA_OK != result)
+ {
+ if (major >= 0)
+ unregister_chrdev(major, DRV_NAME);
+ }
+
+ MXL_EXIT_FUNCTION(TRACE_OSWP, "status = %d", result);
+
+ return result;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevExit
+ *
+ *
+ * DATE CREATED : Sep/21/2016
+ *
+ * DESCRIPTION : Driver exit function, un-register the driver
+ * The global resources will be freed
+ *
+ *
+ * IN PARAMS : None
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_DevExit(void)
+{
+ MXL_ENTER_FUNCTION(TRACE_OSWP, "void");
+
+ MxL_MoCA_DrvExit();
+
+ unregister_chrdev(major, DRV_NAME);
+
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_INFO, "%s %s Unloaded\n", DRV_NAME, VERSION_HOST_STR);
+
+ MXL_EXIT_FUNCTION(TRACE_OSWP, "status = %d", MXL_MOCA_OK);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevSysfsShowLof
+ *
+ *
+ * DATE CREATED : Nov/4/2016
+ *
+ * DESCRIPTION : Sysfs function to display the lof in driver which will be
+ * updated by daemon
+ * This function will be called by linux kernel when user issue following
+ * command (assume the moca device name is en15):
+ * `cat /sys/devices/virtual/mxl_moca_ctrl/en15/lof`
+ *
+ * IN PARAMS : pDev Pointer to the device struct
+ * pAttr Pointer to device attribute
+ * pBuf Buffer for displaying the lof
+ *
+ * OUT PARAMS : none
+ *
+ * RETURN VALUE : Size of the displayed value
+ *--------------------------------------------------------------------------------------*/
+
+static ssize_t MxL_MoCA_DevSysfsShowLof(struct device *pDev,
+ struct device_attribute *pAttr,
+ char *pBuf)
+{
+ int32_t i;
+ ssize_t ret;
+ uint32_t lof;
+ MXL_MOCA_DEV_CTRL_MGR_T *pDevCtrlMgr = NULL;
+
+ for (i = 0; i < MAX_SOC_NUMBER; i++)
+ {
+ if (gMxlMocaDevManager[i].pDev == pDev)
+ {
+ pDevCtrlMgr = &gMxlMocaDevManager[i];
+ break;
+ }
+ }
+
+ // If read before the device manager init, dislay 0 for lof
+ if (NULL != pDevCtrlMgr)
+ lof = pDevCtrlMgr->daemonContext.lof;
+ else
+ lof = 0;
+
+ ret = scnprintf(pBuf, PAGE_SIZE, "%d\n", lof);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevSysfsShowLinkStatus
+ *
+ *
+ * DATE CREATED : Nov/4/2016
+ *
+ * DESCRIPTION : Sysfs function to display the link status in driver which will
+ * be updated by daemon.
+ * This function will be called by linux kernel when user issue following
+ * command (assume the moca device name is en15):
+ * `cat /sys/devices/virtual/mxl_moca_ctrl/en15/link_status`
+ *
+ * IN PARAMS : pDev Pointer to the device struct
+ * pAttr Pointer to device attribute
+ * pBuf Buffer for displaying the link status
+ *
+ * OUT PARAMS : none
+ *
+ * RETURN VALUE : Size of the displayed value
+ *--------------------------------------------------------------------------------------*/
+
+static ssize_t MxL_MoCA_DevSysfsShowLinkStatus(struct device *pDev,
+ struct device_attribute *pAttr,
+ char *pBuf)
+{
+ int32_t i;
+ ssize_t ret;
+ uint32_t link_status;
+ MXL_MOCA_DEV_CTRL_MGR_T *pDevCtrlMgr = NULL;
+
+ for (i = 0; i < MAX_SOC_NUMBER; i++)
+ {
+ if (gMxlMocaDevManager[i].pDev == pDev)
+ {
+ pDevCtrlMgr = &gMxlMocaDevManager[i];
+ break;
+ }
+ }
+
+ // If read before the device manager init, dislay 0 (LINK DOWN) for link status
+ if (NULL != pDevCtrlMgr)
+ link_status = pDevCtrlMgr->daemonContext.linkUpFlag;
+ else
+ link_status = 0;
+
+ ret = scnprintf(pBuf, PAGE_SIZE, "%d\n", link_status);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevSysfsShowLinkStatus
+ *
+ *
+ * DATE CREATED : Jan/27/2017
+ *
+ * DESCRIPTION : Sysfs function to display the admission status in driver which will
+ * be updated by daemon.
+ * This function will be called by linux kernel when user issue following
+ * command (assume the moca device name is en15):
+ * `cat /sys/devices/virtual/mxl_moca_ctrl/en15/adm_status`
+ *
+ * IN PARAMS : pDev Pointer to the device struct
+ * pAttr Pointer to device attribute
+ * pBuf Buffer for displaying the admission status
+ *
+ * OUT PARAMS : none
+ *
+ * RETURN VALUE : Size of the displayed value
+ *--------------------------------------------------------------------------------------*/
+
+static ssize_t MxL_MoCA_DevSysfsShowAdmStatus(struct device *pDev,
+ struct device_attribute *pAttr,
+ char *pBuf)
+{
+ int32_t i;
+ ssize_t ret;
+ uint32_t adm_status;
+ MXL_MOCA_DEV_CTRL_MGR_T *pDevCtrlMgr = NULL;
+
+ for (i = 0; i < MAX_SOC_NUMBER; i++)
+ {
+ if (gMxlMocaDevManager[i].pDev == pDev)
+ {
+ pDevCtrlMgr = &gMxlMocaDevManager[i];
+ break;
+ }
+ }
+
+ // If read before the device manager init, dislay 6 (ADM_RESULT_ERROR) for link status
+ if (NULL != pDevCtrlMgr)
+ adm_status = pDevCtrlMgr->daemonContext.lastAdmStatus;
+ else
+ adm_status = ADM_RESULT_ERROR;
+
+ ret = scnprintf(pBuf, PAGE_SIZE, "%d\n", adm_status);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevSysfsShowBridgeControlReqStatus
+ *
+ *
+ * DATE CREATED : Mar/02/2017
+ *
+ * DESCRIPTION : Sysfs function to display the proxy packet status in driver which will
+ * be updated by daemon.
+ * This function will be called by linux kernel when user issue following
+ * command (assume the moca device name is en15):
+ * `cat /sys/devices/virtual/mxl_moca_ctrl/en15/bridge_ctrl_status`
+ *
+ * IN PARAMS : pDev Pointer to the device struct
+ * pAttr Pointer to device attribute
+ * pBuf Buffer for displaying the admission status
+ *
+ * OUT PARAMS : none
+ *
+ * RETURN VALUE : Size of the displayed value
+ *--------------------------------------------------------------------------------------*/
+
+static ssize_t MxL_MoCA_DevSysfsShowBridgeControlReqStatus(struct device *pDev,
+ struct device_attribute *pAttr,
+ char *pBuf)
+{
+ int32_t i;
+ ssize_t ret;
+ uint32_t bridge_ctrl_req_status;
+ MXL_MOCA_DEV_CTRL_MGR_T *pDevCtrlMgr = NULL;
+
+ for (i = 0; i < MAX_SOC_NUMBER; i++)
+ {
+ if (gMxlMocaDevManager[i].pDev == pDev)
+ {
+ pDevCtrlMgr = &gMxlMocaDevManager[i];
+ break;
+ }
+ }
+
+ // If read before the device manager init, dislay 0 (LINK DOWN) for link status
+ if (NULL != pDevCtrlMgr)
+ bridge_ctrl_req_status = (pDevCtrlMgr->daemonContext.reqStatus & 2) >> 1; /* Bridge Control */
+ else
+ bridge_ctrl_req_status = 0;
+
+ ret = scnprintf(pBuf, PAGE_SIZE, "%d\n", bridge_ctrl_req_status);
+
+ return ret;
+}
+
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevSysfsShowProxyReqStatus
+ *
+ *
+ * DATE CREATED : Jan/27/2017
+ *
+ * DESCRIPTION : Sysfs function to display the proxy packet status in driver which will
+ * be updated by daemon.
+ * This function will be called by linux kernel when user issue following
+ * command (assume the moca device name is en15):
+ * `cat /sys/devices/virtual/mxl_moca_ctrl/en15/net_proxy_req_status`
+ *
+ * IN PARAMS : pDev Pointer to the device struct
+ * pAttr Pointer to device attribute
+ * pBuf Buffer for displaying the admission status
+ *
+ * OUT PARAMS : none
+ *
+ * RETURN VALUE : Size of the displayed value
+ *--------------------------------------------------------------------------------------*/
+
+static ssize_t MxL_MoCA_DevSysfsShowProxyReqStatus(struct device *pDev,
+ struct device_attribute *pAttr,
+ char *pBuf)
+{
+ int32_t i;
+ ssize_t ret;
+ uint32_t net_proxy_req_status;
+ MXL_MOCA_DEV_CTRL_MGR_T *pDevCtrlMgr = NULL;
+
+ for (i = 0; i < MAX_SOC_NUMBER; i++)
+ {
+ if (gMxlMocaDevManager[i].pDev == pDev)
+ {
+ pDevCtrlMgr = &gMxlMocaDevManager[i];
+ break;
+ }
+ }
+
+ // If read before the device manager init, dislay 0 (LINK DOWN) for link status
+ if (NULL != pDevCtrlMgr)
+ net_proxy_req_status = pDevCtrlMgr->daemonContext.reqStatus & 1; /* Net Proxy */
+ else
+ net_proxy_req_status = 0;
+
+ ret = scnprintf(pBuf, PAGE_SIZE, "%d\n", net_proxy_req_status);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevSysfsShowBeaconPowerDistStatus
+ *
+ *
+ * DATE CREATED : Jun/28/2017
+ *
+ * DESCRIPTION : Sysfs function to display the beacon power distributed in driver
+ * which will be updated by daemon
+ * This function will be called by linux kernel when user issue following
+ * command (assume the moca device name is en15):
+ * `cat /sys/devices/virtual/mxl_moca_ctrl/en15/beacon_power_dist_status`
+ *
+ * IN PARAMS : pDev Pointer to the device struct
+ * pAttr Pointer to device attribute
+ * pBuf Buffer for displaying the lof
+ *
+ * OUT PARAMS : none
+ *
+ * RETURN VALUE : Size of the displayed value
+ *--------------------------------------------------------------------------------------*/
+
+static ssize_t MxL_MoCA_DevSysfsShowBeaconPowerDistStatus(struct device *pDev,
+ struct device_attribute *pAttr,
+ char *pBuf)
+{
+ int32_t i;
+ ssize_t ret;
+ uint32_t beacon_power_dist_status;
+ MXL_MOCA_DEV_CTRL_MGR_T *pDevCtrlMgr = NULL;
+
+ for (i = 0; i < MAX_SOC_NUMBER; i++)
+ {
+ if (gMxlMocaDevManager[i].pDev == pDev)
+ {
+ pDevCtrlMgr = &gMxlMocaDevManager[i];
+ break;
+ }
+ }
+
+ // If read before the device manager init, dislay 0 for beacon power dist status
+ if (NULL != pDevCtrlMgr)
+ beacon_power_dist_status = (pDevCtrlMgr->daemonContext.reqStatus >> 3) & 1; /* Beacon Power */
+ else
+ beacon_power_dist_status = 0;
+
+ ret = scnprintf(pBuf, PAGE_SIZE, "%d\n", beacon_power_dist_status);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_DevSysfsShowPrvacyUpdateStatus
+ *
+ *
+ * DATE CREATED : Mar/15/2017
+ *
+ * DESCRIPTION : Sysfs function to display the privacy update status in driver which will
+ * be updated by daemon.
+ * This function will be called by linux kernel when user issue following
+ * command (assume the moca device name is en15):
+ * `cat /sys/devices/virtual/mxl_moca_ctrl/en15/privacy_update_status`
+ *
+ * IN PARAMS : pDev Pointer to the device struct
+ * pAttr Pointer to device attribute
+ * pBuf Buffer for displaying the admission status
+ *
+ * OUT PARAMS : none
+ *
+ * RETURN VALUE : Size of the displayed value
+ *--------------------------------------------------------------------------------------*/
+
+static ssize_t MxL_MoCA_DevSysfsShowPrvacyUpdateStatus(struct device *pDev,
+ struct device_attribute *pAttr,
+ char *pBuf)
+{
+ int32_t i;
+ ssize_t ret;
+ uint32_t privacy_update_status;
+ MXL_MOCA_DEV_CTRL_MGR_T *pDevCtrlMgr = NULL;
+
+ for (i = 0; i < MAX_SOC_NUMBER; i++)
+ {
+ if (gMxlMocaDevManager[i].pDev == pDev)
+ {
+ pDevCtrlMgr = &gMxlMocaDevManager[i];
+ break;
+ }
+ }
+
+ // If read before the device manager init, dislay 0 (LINK DOWN) for privacy update status
+ if (NULL != pDevCtrlMgr)
+ privacy_update_status = (pDevCtrlMgr->daemonContext.reqStatus >> 2) & 1; /* Bit2: Privacy update */
+ else
+ privacy_update_status = 0;
+
+ ret = scnprintf(pBuf, PAGE_SIZE, "%d\n", privacy_update_status);
+
+ return ret;
+}
+
+// dev_attr_lof and dev_attr_link_status used to create sysfs files for displaying lof and link_status
+DEVICE_ATTR(lof, S_IRUGO, MxL_MoCA_DevSysfsShowLof, NULL);
+DEVICE_ATTR(link_status, S_IRUGO, MxL_MoCA_DevSysfsShowLinkStatus, NULL);
+DEVICE_ATTR(adm_status, S_IRUGO, MxL_MoCA_DevSysfsShowAdmStatus, NULL);
+DEVICE_ATTR(bridge_ctrl_req_status, S_IRUGO, MxL_MoCA_DevSysfsShowBridgeControlReqStatus, NULL);
+DEVICE_ATTR(net_proxy_req_status, S_IRUGO, MxL_MoCA_DevSysfsShowProxyReqStatus, NULL);
+DEVICE_ATTR(beacon_power_dist_status, S_IRUGO, MxL_MoCA_DevSysfsShowBeaconPowerDistStatus, NULL);
+DEVICE_ATTR(privacy_update_status, S_IRUGO, MxL_MoCA_DevSysfsShowPrvacyUpdateStatus, NULL);
+
+
+module_init(MxL_MoCA_DevInit);
+module_exit(MxL_MoCA_DevExit);
diff --git a/drivers/net/phy/mxl371x/mxl_moca_host_version.h b/drivers/net/phy/mxl371x/mxl_moca_host_version.h
new file mode 100644
index 000000000000..0cb3408ced93
--- /dev/null
+++ b/drivers/net/phy/mxl371x/mxl_moca_host_version.h
@@ -0,0 +1,59 @@
+/*****************************************************************************************
+ * FILE NAME : mxl_moca_host_version.h
+ *
+ *
+ * DATE CREATED : Oct/12/2016
+ * LAST MODIFIED :
+ *
+ * DESCRIPTION : Common host revision numbers constants.
+ * Host system use this common file to obtain revision numbers.
+ *
+ *
+ *****************************************************************************************
+ * MaxLinear, Inc. retains all right, title and interest (including all intellectual
+ * property rights) in and to this computer program, which is protected by applicable
+ * intellectual property laws. Unless you have obtained a separate written license from
+ * MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., you are not authorized
+ * to utilize all or a part of this computer program for any purpose (including
+ * reproduction, distribution, modification, and compilation into object code), and you
+ * must immediately destroy or return all copies of this computer program. If you are
+ * licensed by MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., your rights
+ * to utilize this computer program are limited by the terms of that license.
+ *
+ * This computer program contains trade secrets owned by MaxLinear, Inc. and, unless
+ * authorized by MaxLinear, Inc. in writing, you agree to maintain the confidentiality
+ * of this computer program and related information and to not disclose this computer
+ * program and related information to any other person or entity.
+ *
+ * Misuse of this computer program or any information contained in it may results in
+ * violations of applicable law. MaxLinear, Inc. vigorously enforces its copyright,
+ * trade secret, patent, contractual, and other legal rights.
+ *
+ * THIS COMPUTER PROGRAM IS PROVIDED "AS IS" WITHOUT ANY WARRANTIES, AND
+ * MAXLINEAR, INC.EXPRESSLY DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE
+ * WARRANTIES OF MERCHANTIBILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND
+ * NONINFRINGEMENT.
+ *
+ ****************************************************************************************
+ * Copyright (c) 2016, MaxLinear, Inc.
+ ****************************************************************************************/
+
+#ifndef __MXL_MOCA_HOST_VERSION_H__
+#define __MXL_MOCA_HOST_VERSION_H__
+
+/*******************************************************************************
+* Constants
+******************************************************************************/
+
+// PKG(host&soc),HOST version information
+#define VERSION_PKG_STR "MXL371x_MHOST_v3.11.25_FW_v1.18.13"
+#define VERSION_HOST_STR "3.11.25"
+
+// System build numbers
+#define VERSION_APPS ( -1)
+#define VERSION_CD (0)
+#define VERSION_DRV ( -1)
+#define VERSION_LIB ( -1)
+
+#endif // __MXL_MOCA_HOST_VERSION_H__
+
diff --git a/drivers/net/phy/mxl371x/mxl_moca_ioctl_cmd.h b/drivers/net/phy/mxl371x/mxl_moca_ioctl_cmd.h
new file mode 100644
index 000000000000..0116c0f2c3c0
--- /dev/null
+++ b/drivers/net/phy/mxl371x/mxl_moca_ioctl_cmd.h
@@ -0,0 +1,103 @@
+/*****************************************************************************************
+ *
+ * FILE NAME : mxl_moca_ioctl_cmd.h
+ *
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * LAST MODIFIED :
+ *
+ * DESCRIPTION : Supported systems/debug IOCTL commands
+ *
+ *****************************************************************************************
+ * MaxLinear, Inc. retains all right, title and interest (including all intellectual
+ * property rights) in and to this computer program, which is protected by applicable
+ * intellectual property laws. Unless you have obtained a separate written license from
+ * MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., you are not authorized
+ * to utilize all or a part of this computer program for any purpose (including
+ * reproduction, distribution, modification, and compilation into object code), and you
+ * must immediately destroy or return all copies of this computer program. If you are
+ * licensed by MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., your rights
+ * to utilize this computer program are limited by the terms of that license.
+ *
+ * This computer program contains trade secrets owned by MaxLinear, Inc. and, unless
+ * authorized by MaxLinear, Inc. in writing, you agree to maintain the confidentiality
+ * of this computer program and related information and to not disclose this computer
+ * program and related information to any other person or entity.
+ *
+ * Misuse of this computer program or any information contained in it may results in
+ * violations of applicable law. MaxLinear, Inc. vigorously enforces its copyright,
+ * trade secret, patent, contractual, and other legal rights.
+ *
+ * THIS COMPUTER PROGRAM IS PROVIDED "AS IS" WITHOUT ANY WARRANTIES, AND
+ * MAXLINEAR, INC.EXPRESSLY DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE
+ * WARRANTIES OF MERCHANTIBILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND
+ * NONINFRINGEMENT.
+ *
+ ****************************************************************************************
+ * Copyright (c) 2021, MaxLinear, Inc.
+ ****************************************************************************************/
+
+#ifndef __MXL_MOCA_IOCTL_CMD_H__
+#define __MXL_MOCA_IOCTL_CMD_H__
+
+
+/*****************************************************************************************
+ Include Header Files
+ (No absolute paths - paths handled by make file)
+ ****************************************************************************************/
+
+
+/*****************************************************************************************
+ Macros
+ ****************************************************************************************/
+
+#define DEVPRIVATE 0x89F0
+#define SIOC_MXL_MOCA_CMD (DEVPRIVATE+1) //Systems IOCTL for MaxLinear MoCA command
+#define SIOC_MXL_MOCA_DBG_GET_MEM (DEVPRIVATE+2) //Debug IOCTL for extended SoC memory read operation.
+#define SIOC_MXL_MOCA_DBG_SET_MEM (DEVPRIVATE+3) //Debug IOCTL for extended SoC memory write operation.
+#define SIOC_MXL_MOCA_START_DAEMON (DEVPRIVATE+4) //Systems IOCTL for start MoCA Daemon command
+
+
+/*****************************************************************************************
+ User-Defined Types (Typedefs)
+ ****************************************************************************************/
+
+// ECB OTP (One Time Program) Parameters
+typedef struct
+{
+ char acEcbModNum[30];
+ char acEcbSerNum[30];
+ uint8_t acClkMacAddr[6];
+ uint8_t acEthMacPort0[6];
+ uint8_t acEthMacPort1[6];
+ uint8_t acEthMacPort2[6];
+#if MXLWARE_CONFIG_BOARD_ECA_5M_L3_MVL || MXLWARE_CONFIG_BOARD_ECA_8M_L3_MVL
+ uint8_t acCpuMacAddr[6];
+#elif MXLWARE_CONFIG_BOARD_ECA_9M_L3_NXP
+ uint8_t acEthMacPort3[6];
+ uint8_t acEthMacPort4[6];
+#endif
+#if MXLWARE_CONFIG_BOARD_ECA_5M_L3_MVL || MXLWARE_CONFIG_BOARD_ECA_8M_L3_MVL || MXLWARE_CONFIG_BOARD_ECA_9M_L3_NXP
+ uint32_t acClnkFreqBand;
+ uint32_t acMiiMode;
+ uint32_t uiMasterMode;
+ uint32_t uiMacMode;
+#endif
+ uint32_t acDiplexerCal;
+ uint32_t acRgmiiClkCfg;
+ uint32_t acHwCfg;
+ uint32_t uiCfgCrcNum;
+} MXL_MOCA_DRV_SET_OTP_CONFIG_CMD_T;
+
+
+/*****************************************************************************************
+ Global Variable Declarations
+ ****************************************************************************************/
+
+/*****************************************************************************************
+ Function Prototypes
+ ****************************************************************************************/
+
+#endif // __MXL_MOCA_IOCTL_CMD_H__
diff --git a/drivers/net/phy/mxl371x/mxl_moca_osal.h b/drivers/net/phy/mxl371x/mxl_moca_osal.h
new file mode 100644
index 000000000000..b854dd4bac2a
--- /dev/null
+++ b/drivers/net/phy/mxl371x/mxl_moca_osal.h
@@ -0,0 +1,220 @@
+/*****************************************************************************************
+ *
+ * FILE NAME : mxl_moca_osal.h
+ *
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * LAST MODIFIED :
+ *
+ * DESCRIPTION : This file contains MoCA device related define and data structrue
+ *
+ *****************************************************************************************
+ * This file is licensed under GNU General Public license.
+ *
+ * This file is free software: you can redistribute and/or modify it under the
+ * terms of the GNU General Public License, Version 2, as published by the Free
+ * Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but AS-IS and
+ * WITHOUT ANY WARRANTY; without even the implied warranties of MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT. Redistribution,
+ * except as permitted by the GNU General Public License is prohibited.
+ *
+ * You should have received a copy of the GNU General Public License, Version 2
+ * along with this file; if not, see <http://www.gnu.org/licenses/>.
+ *
+ *****************************************************************************************
+ * Copyright (c) 2016 MaxLinear, Inc. All rights reserved.
+ ****************************************************************************************/
+
+#ifndef __MXL_MOCA_OSAL_H__
+#define __MXL_MOCA_OSAL_H__
+
+
+/*****************************************************************************************
+ Include Header Files
+ (No absolute paths - paths handled by make file)
+ ****************************************************************************************/
+#include "mxl_moca_osal_linux.h"
+#include "mxl_data_types.h"
+#include "mxl_moca_config.h"
+#include "mxl_moca_soc_cmd.h"
+
+/*****************************************************************************************
+ Macros
+ ****************************************************************************************/
+#define LOG_PRINT_BUFSIZE 1024
+
+/*****************************************************************************************
+ User-Defined Types (Typedefs)
+ ****************************************************************************************/
+/// OS timer expiration callback function
+typedef void (*timer_function_t)(long);
+
+/// Wait Q Timer exit condition function
+typedef int32_t (*osal_wqt_condition)(void *vp);
+
+/// Wait Q exit condition function
+typedef int32_t (*osal_waitq_condition)(void *vp);
+
+typedef struct
+{
+ void *dev;
+ void *dkcp;
+} osal_device_t;
+
+enum
+{
+ L_ERR = 0,
+ L_WARN,
+ L_INFO,
+ L_VERBOSE,
+ L_DBG,
+ L_TMP,
+};
+
+// HostOS_ control -- define to have console print
+#define HOST_OS_PRINTLOG_THRESHOLD L_INFO
+#define MXL_ENABLE_DEBUG_PRINT 0
+#define MXL_ENABLE_DEBUG_ENTER_EXIT_FUNCTION 0
+
+#if MXL_ENABLE_DEBUG_PRINT
+#define DEBUG_PRINT(mod, lev, fmt, args...) MxL_MoCA_OsalPrintLog(mod, lev,"(%s)%d " fmt " \n", __func__, __LINE__, ##args)
+#else
+#define DEBUG_PRINT(mod, lev, fmt, args...)
+#endif
+
+#if MXL_ENABLE_DEBUG_ENTER_EXIT_FUNCTION
+#define MXL_ENTER_FUNCTION(mod, fmt, args...) MxL_MoCA_OsalPrintLog(mod, L_INFO, "+++ %s(), line: %d " fmt "\n", __func__, __LINE__, ##args)
+#define MXL_EXIT_FUNCTION(mod, fmt, args...) MxL_MoCA_OsalPrintLog(mod, L_INFO, "--- %s(), line: %d " fmt "\n", __func__, __LINE__, ##args)
+#else
+#define MXL_ENTER_FUNCTION(mod, fmt, args...)
+#define MXL_EXIT_FUNCTION(mod, fmt, args...)
+#endif
+
+/*****************************************************************************************
+ Global Variable Declarations
+ ****************************************************************************************/
+
+/*****************************************************************************************
+ Function Prototypes
+ ****************************************************************************************/
+struct MXL_MOCA_DAEMON_STARTUP_OPTIONS_T *MxL_MoCA_OsalGetDsoFromIface(void *iface);
+void MxL_MoCA_OsalAllocGetTimeInit(void **tv);
+void MxL_MoCA_OsalGetTime(void *tv);
+void MxL_MoCA_OsalAllocGetTime(void **tv);
+long MxL_MoCA_OsalDiffTimeInUs(void *tv1, void *tv2);
+long MxL_MoCA_OsalDiffTime(void *tv1, void *tv2);
+void MxL_MoCA_OsalAssignTime(void *tv1, void *tv2);
+void MxL_MoCA_OsalFreeGetTime(void *tv);
+void *MxL_MoCA_OsalAlloc(int32_t size);
+void MxL_MoCA_OsalFree(void *pMem, int32_t size);
+
+void MxL_MoCA_OsalMemcpy(void *pTo, void *pFrom, int32_t size);
+void MxL_MoCA_OsalMemset(void *pMem, int32_t val, int32_t size);
+void MxL_MoCA_OsalPrintLog(int32_t mod, int32_t lev, const int8_t *fmt, ...);
+void MxL_MoCA_OsalPrintString(int8_t* pStr);
+void MxL_MoCA_OsalSetLogLev(int32_t mod, int32_t lev);
+void MxL_MoCA_OsalDelay(int32_t timeInUsec);
+void MxL_MoCA_OsalDelayUsec(uint32_t timeInUsec);
+void MxL_MoCA_OsalMSleep(int32_t timeInMilliSec);
+void MxL_MoCA_OsalSscanf(const int8_t *buf, const int8_t *fmt, ...);
+int32_t MxL_MoCA_OsalTimerMod(void *pTmr, unsigned long timeout);
+
+unsigned long MxL_MoCA_OsalCopyFromUser(void *to, const void *from, unsigned long nbytes);
+unsigned long MxL_MoCA_OsalCopyToUser(void *to, const void *from, unsigned long nbytes);
+
+/// Mutex/Semaphore API's used by MxLWare while accessing shared resources like MDIO driver
+void MxL_MoCA_OsalMutexInit(void *vmt);
+void MxL_MoCA_OsalMutexRelease(void *vmt);
+void MxL_MoCA_OsalMutexAcquire(void *vmt);
+int32_t MxL_MoCA_OsalMutexAcquireIntr(void *vmt);
+void *MxL_MoCA_OsalGetResetMutex(void);
+
+// MXL OSAL Semaphore API's
+MXL_MOCA_STATUS_E MxL_MoCA_OsalCreateLock(MxL_OSAL_LOCK_T *pLock);
+void MxL_MoCA_OsalDestroyLock(MxL_OSAL_LOCK_T *pLock);
+void MxL_MoCA_OsalLock(MxL_OSAL_LOCK_T *pLock);
+void MxL_MoCA_OsalUnlock(MxL_OSAL_LOCK_T *pLock);
+
+unsigned long MxL_MoCA_OsalTimerExpireSeconds(uint32_t future);
+unsigned long MxL_MoCA_OsalTimerExpireTicks(uint32_t future);
+void *MxL_MoCA_OsalWqtAlloc(void);
+void MxL_MoCA_OsalWqtFree(void *vwqt);
+void MxL_MoCA_OsalWqtTimerInit(void *vwqt);
+void MxL_MoCA_OsalWqtTimerDel(void *vwqt);
+int32_t MxL_MoCA_OsalWqtTimerDelSync(void *vwqt);
+int32_t MxL_MoCA_OsalWqtTimerMod(void *vwqt, unsigned long timeout);
+void MxL_MoCA_OsalWqtTimerAdd(void *vwqt);
+void MxL_MoCA_OsalWqtTimerSetup(void *vwqt, timer_function_t func, unsigned long data);
+void MxL_MoCA_OsalWqtTimerSetTimeout(void *vwqt, unsigned long timeout);
+void MxL_MoCA_OsalWqtWaitqInit(void *vwqt);
+void MxL_MoCA_OsalWqtWaitqWakeupIntr(void *vwqt);
+void MxL_MoCA_OsalWqtWaitqWaitEventIntr(void *vwqt, osal_wqt_condition func, void *vp);
+int32_t MxL_MoCA_OsalSignalPending(void *vtask);
+void MxL_MoCA_OsalMsleepInterruptible(uint32_t msecs);
+MXL_MOCA_STATUS_E MxL_MoCA_OsalThreadCreateAndStart(int32_t (*pThreadFn)(void *pData),
+ void *pData,
+ const int8_t *pNameFmt,
+ void *pArg,
+ void **ppTask);
+MXL_MOCA_STATUS_E MxL_MoCA_OsalTestPtrErrCondition(void *pTask);
+
+MXL_MOCA_STATUS_E MxL_MoCA_OsalGetDaemonThreadStopStatus(void);
+MXL_MOCA_STATUS_E MxL_MoCA_OsalDetectPCIeDevice(int32_t vendor, int32_t device, int8_t checkDriverLoad);
+int32_t MxL_MoCA_OsalThreadStart(uint32_t *pThreadID, int8_t *pName, void (*func)(void *), void *pArg);
+int32_t MxL_MoCA_OsalThreadStop(unsigned long threadID);
+uint32_t MxL_MoCA_OsalReadWord( void *pAddr );
+void MxL_MoCA_OsalWriteWord( uint32_t val, void *pAddr);
+
+void MxL_MoCA_OsalLogInfo(int8_t *pFormat, ...);
+int32_t MxL_MoCA_OsalKthreadStop(void *pTsk);
+void *MxL_MoCA_OsalGetPointerToFirmwareData(MXL_MOCA_FIRMWARE_T *pFw, int32_t index);
+int32_t MxL_MoCA_OsalGetFirmwareLen(MXL_MOCA_FIRMWARE_T *pFw, int32_t index);
+void MxL_MoCA_OsalFreeFirmwares(MXL_MOCA_FIRMWARE_T *pFw);
+MXL_MOCA_STATUS_E MxL_MoCA_OsalGetFirmwareAndConfigData(uint32_t chipTypeIndex, void *pDev,
+ const int8_t *pDevName,
+ MXL_MOCA_FIRMWARE_T *pFw,
+ int32_t* pFwBitMaskRet);
+int8_t *MxL_MoCA_OsalStrcpy(int8_t *pDst, const int8_t *pSrc);
+int32_t MxL_MoCA_OsalSnprintf(int8_t *pBuf, uint32_t size, const int8_t *pFmt, ...);
+uint16_t MxL_MoCA_OsalHtons(uint16_t n);
+uint32_t MxL_MoCA_OsalHtonl(uint32_t n);
+uint32_t MxL_MoCA_OsalNtohl(uint32_t n);
+uint16_t MxL_MoCA_OsalNtohs(uint16_t n);
+int8_t *MxL_MoCA_OsalStrstr(int8_t *pStr1, int8_t *pStr2);
+//MOCA_UEVENT
+#if ENABLE_ADM_STATUS_UEVENT || ENABLE_LINK_UEVENT
+void Mxl_MoCA_OsalGenerateUevent(void * pDev);
+#endif
+//MOCA_UEVENT
+MXL_MOCA_STATUS_E MxL_MoCA_OsalCreateMocaDev(uint8_t ePhyAddr, void** ppDev);
+
+MXL_MOCA_STATUS_E MxL_MoCA_OsalCheckImage(uint8_t *pElfData, uint32_t elfSize);
+void *MxL_MoCA_OsalGetFirstPhdr(uint8_t *pElfData);
+uint32_t MxL_MoCA_OsalGetNumOfProgHeader(void *pData);
+uint32_t MxL_MoCA_OsalGetProgHeaderPhyAddr(void *pHdr);
+uint32_t MxL_MoCA_OsalGetProgHeaderOffset(void *pHdr);
+uint32_t MxL_MoCA_OsalGetProgHeaderFileSZ(void *pHdr);
+void *MxL_MoCA_OsalNextProgHeader(void *pHdr);
+
+void *MxL_MoCA_OsalGetFirstShdr(uint8_t * elfData);
+uint32_t MxL_MoCA_OsalGetNumOfSecHeaders(void *pData);
+uint32_t MxL_MoCA_OsalGetSecIndexByName(void *pData, char* pName);
+uint32_t MxL_MoCA_OsalGetSecFileOffset(void *pData, uint32_t sectionId);
+
+#if defined(INCLUDE_PCI)
+/* DP interface func */
+void MxL_MoCA_OsalSetMacAddress(uint32_t devIndex, uint32_t *pMac);
+MXL_MOCA_STATUS_E MxL_MoCA_OsalPcieAvailable(int8_t devIndex);
+MXL_MOCA_STATUS_E MxL_MoCA_OsalPcieBusRead(uint32_t devIndex, unsigned long addr, uint32_t *pData);
+MXL_MOCA_STATUS_E MxL_MoCA_OsalPcieBusWrite(uint32_t devIndex, unsigned long addr, uint32_t data);
+MXL_MOCA_STATUS_E MxL_MoCA_OsalDataPlaneIfRestart(uint32_t devIndex);
+MXL_MOCA_STATUS_E MxL_MoCA_OsalDataPlaneResetSoC(uint32_t devIndex);
+#endif
+
+void MxL_MoCA_OsalDestroyMocaDev(uint8_t ePhyAddr, void* ppDev);
+void MxL_MoCA_OsalDestroyMocaDevClass(void);
+#endif // __MXL_MOCA_OSAL_H__
diff --git a/drivers/net/phy/mxl371x/mxl_moca_osal_linux.c b/drivers/net/phy/mxl371x/mxl_moca_osal_linux.c
new file mode 100644
index 000000000000..c7165b4f0d76
--- /dev/null
+++ b/drivers/net/phy/mxl371x/mxl_moca_osal_linux.c
@@ -0,0 +1,2830 @@
+/*****************************************************************************************
+ *
+ * FILE NAME : mxl_moca_osal_linux.c
+ *
+ *
+ *
+ * DATE CREATED : Sep/14/2016
+ *
+ * LAST MODIFIED :
+ *
+ * DESCRIPTION : This file include linux OSAL implementation
+ *
+ *****************************************************************************************
+ * This file is licensed under GNU General Public license.
+ *
+ * This file is free software: you can redistribute and/or modify it under the
+ * terms of the GNU General Public License, Version 2, as published by the Free
+ * Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but AS-IS and
+ * WITHOUT ANY WARRANTY; without even the implied warranties of MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT. Redistribution,
+ * except as permitted by the GNU General Public License is prohibited.
+ *
+ * You should have received a copy of the GNU General Public License, Version 2
+ * along with this file; if not, see <http://www.gnu.org/licenses/>.
+ *
+ *****************************************************************************************
+ * Copyright (c) 2016 MaxLinear, Inc. All rights reserved.
+ ****************************************************************************************/
+
+#include <stdarg.h>
+#include <linux/hardirq.h>
+#include <linux/string.h>
+#include <linux/sched.h>
+#include <linux/time.h>
+#include <linux/pci.h>
+#include <linux/version.h>
+#include <linux/firmware.h>
+#include <linux/types.h>
+#include <linux/device.h>
+
+#include "mxl_data_types.h"
+#include "mxl_moca_config.h"
+#include "mxl_moca_soc_cmd.h"
+#include "mxl_moca_dev_mgr.h"
+#include "mxl_moca_drv_daemon.h"
+#include "mxl_moca_osal_linux.h"
+#include "mxl_moca_osal.h"
+#include "mxl_moca_hal_mdio_ctrl.h"
+#include "mxl_moca_drv_mdio.h"
+#ifdef INCLUDE_PCI
+#include "mxl_moca_osal_pcie.h"
+#endif
+
+static uint32_t logMod = 0;
+static uint32_t logLev = 0;
+
+bool gGetFwViaIoctl = false;
+
+static struct class *pClass;
+
+// MOCA_UEVENT
+#if ENABLE_ADM_STATUS_UEVENT || ENABLE_LINK_UEVENT
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : Mxl_MoCA_OsalGenerateUevent
+ *
+ * DATE CREATED : Apr/20/2018
+ *
+ * DESCRIPTION : Generates the Uevent that is handled by the Udev
+ *
+ *
+ * IN PARAMS : EPHY Addr of the MxL MoCA SOC in the specified MDIO bus
+ *
+ * OUT PARAMS : none
+ *
+ * RETURN VALUE : none
+ *--------------------------------------------------------------------------------------*/
+
+void Mxl_MoCA_OsalGenerateUevent(void * pDev)
+{
+
+ struct device * dev = (struct device *) pDev;
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_INFO, "uevent Start \n");
+
+ if (pDev == NULL )
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_INFO, "pDev is NULL \n");
+ return;
+ }
+
+ dev_set_uevent_suppress(dev, false);
+ kobject_uevent(&dev->kobj, KOBJ_CHANGE); // This function sends the uevent
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_INFO, "uevent End \n");
+}
+#endif
+// MOCA_UEVENT
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalCreateMocaDev
+ *
+ *
+ * DATE CREATED : Sep/27/2016
+ *
+ * DESCRIPTION : Create MoCA control device, for example: /dev/en15
+ *
+ *
+ * IN PARAMS : EPHY Addr of the MxL MoCA SOC in the specified MDIO bus
+ *
+ * OUT PARAMS : none
+ *
+ * RETURN VALUE : MXL_MOCA_OK for success, MXL_MOCA_ERR for failure
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_OsalCreateMocaDev(uint8_t ePhyAddr, void** ppDev)
+{
+ void *pDevice;
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+
+ MXL_ENTER_FUNCTION(TRACE_OSWP, "ephy addr = %d",ePhyAddr);
+
+ // Only create once for class
+ if (NULL == pClass)
+ {
+ pClass = class_create(THIS_MODULE, DRV_NAME);
+
+ if (pClass == NULL)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "Class create failed for MoCA driver\n");
+ return MXL_MOCA_ERR;
+ }
+ }
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
+ pDevice = device_create(pClass, 0, MKDEV(major, ePhyAddr), 0, "en%d", ePhyAddr);
+#else
+ pDevice = device_create(pClass, 0, MKDEV(major, ePhyAddr), "en%d", ePhyAddr);
+#endif
+
+ if (MxL_MoCA_OsalTestPtrErrCondition(pDevice) == MXL_MOCA_ERR)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "Create MoCA control device failed!\n");
+ ret = MXL_MOCA_ERR;
+ }
+ else
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_DBG, "pDevice = %p", *ppDev);
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_INFO,
+ "Created MoCA control device for the driver(/dev/en%d)\n",
+ ePhyAddr);
+ // Set for return
+ *ppDev = pDevice;
+
+ // Create Sysfs files to display lof and link status
+ if (MXL_MOCA_OK != device_create_file((struct device *)pDevice, &dev_attr_lof))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_INFO, "Warning: create sysfs for lof fails.\n");
+ }
+
+ if (MXL_MOCA_OK != device_create_file((struct device *)pDevice, &dev_attr_link_status))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_INFO, "Warning: create sysfs for link_status fails.\n");
+ }
+
+ if (MXL_MOCA_OK != device_create_file((struct device *)pDevice, &dev_attr_adm_status))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_INFO, "Warning: create sysfs for adm_status fails.\n");
+ }
+
+ if (MXL_MOCA_OK != device_create_file((struct device *)pDevice, &dev_attr_bridge_ctrl_req_status))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_INFO, "Warning: create sysfs for dev_attr_bridge_ctrl_req_status fails.\n");
+ }
+
+ if (MXL_MOCA_OK != device_create_file((struct device *)pDevice, &dev_attr_net_proxy_req_status))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_INFO, "Warning: create sysfs for net_proxy_req_status fails.\n");
+ }
+
+ if (MXL_MOCA_OK != device_create_file((struct device *)pDevice, &dev_attr_beacon_power_dist_status))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_INFO, "Warning: create sysfs for beacon_power_dist_status fails.\n");
+ }
+
+ // Create Sysfs files to display privacy update status
+ if (MXL_MOCA_OK != device_create_file((struct device *)pDevice, &dev_attr_privacy_update_status))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_INFO, "Warning: create sysfs for privacy_update_status fails.\n");
+ }
+ }
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalDestroyMocaDev
+ *
+ *
+ * DATE CREATED : Oct/14/2016
+ *
+ * DESCRIPTION : Destroy MoCA control device, will be called by MxL_MoCA_DrvExit()
+ *
+ *
+ * IN PARAMS : EPHY Addr of the MxL MoCA SOC in the specified MDIO bus and Device handle
+ *
+ * OUT PARAMS : none
+ *
+ * RETURN VALUE : none
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalDestroyMocaDev(uint8_t ePhyAddr, void* pDev)
+{
+ MXL_ENTER_FUNCTION(TRACE_OSWP, "ephy addr = %d",ePhyAddr);
+
+ // Remove Sysfs files to display lof and link status
+ device_remove_file((struct device *)pDev, &dev_attr_lof);
+ device_remove_file((struct device *)pDev, &dev_attr_link_status);
+ device_remove_file((struct device *)pDev, &dev_attr_adm_status);
+ device_remove_file((struct device *)pDev, &dev_attr_bridge_ctrl_req_status);
+ device_remove_file((struct device *)pDev, &dev_attr_net_proxy_req_status);
+ device_remove_file((struct device *)pDev, &dev_attr_beacon_power_dist_status);
+ device_remove_file((struct device *)pDev, &dev_attr_privacy_update_status);
+
+ device_destroy(pClass, MKDEV(major, ePhyAddr));
+
+ MXL_EXIT_FUNCTION(TRACE_OSWP, "status = %d", ret);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalDestroyMocaDevClass
+ *
+ *
+ * DATE CREATED : Oct/14/2016
+ *
+ * DESCRIPTION : Destroy MoCA control device class, will be called by MxL_MoCA_DrvExit()
+ *
+ *
+ * IN PARAMS : none
+ *
+ * OUT PARAMS : none
+ *
+ * RETURN VALUE : none
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalDestroyMocaDevClass(void)
+{
+ class_destroy(pClass);
+}
+
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalAllocGetTimeInit
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Alloc time value and get init time
+ *
+ * IN PARAMS : tv Pointer to time value pointer
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalAllocGetTimeInit(void **tv)
+{
+ *tv = MxL_MoCA_OsalAlloc(sizeof(apposal_timeval_t));
+
+ if (*tv)
+ memset(*tv, 0, sizeof(apposal_timeval_t));
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetTime
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Get current time
+ *
+ * IN PARAMS : tv Pointer to time value
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalGetTime(void *tv)
+{
+ apposal_timeval_t *ptv;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0))
+ struct timespec ts;
+#endif
+
+ if (!tv)
+ return;
+
+ ptv = tv;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0))
+ getrawmonotonic(&ts);
+ monotonic_to_bootbased(&ts);
+ ptv->timeVal.tv_sec = ts.tv_sec;
+ ptv->timeVal.tv_usec = ts.tv_nsec/1000;
+#else
+ do_gettimeofday(&ptv->timeVal);
+#endif
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalAllocGetTime
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : tv Alloc time value and get current time
+ *
+ * IN PARAMS : Pointer to time value pointer
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalAllocGetTime(void **tv)
+{
+ apposal_timeval_t *ptv ;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0))
+ struct timespec ts;
+#endif
+
+ if (!tv)
+ return;
+
+ if (tv && (*tv))
+ {
+ ptv = *tv;
+ }
+ else
+ {
+ ptv = MxL_MoCA_OsalAlloc(sizeof(apposal_timeval_t));
+ }
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0))
+ getrawmonotonic(&ts);
+ monotonic_to_bootbased(&ts);
+ ptv->timeVal.tv_sec = ts.tv_sec;
+ ptv->timeVal.tv_usec = ts.tv_nsec/1000;
+#else
+ do_gettimeofday(&ptv->timeVal);
+#endif
+
+ if (*tv == 0)
+ *tv = ptv;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalDiffTimeInUs
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Get time difference by us unit
+ *
+ * IN PARAMS : tv1 Pointer to time value1
+ * IN PARAMS : tv2 Pointer to time value2
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Time difference by us unit
+ *--------------------------------------------------------------------------------------*/
+
+long MxL_MoCA_OsalDiffTimeInUs(void *tv1, void *tv2)
+{
+ apposal_timeval_t *ptv1 = tv1;
+ apposal_timeval_t *ptv2 = tv2;
+
+ if (tv1 == 0 || tv2 == 0)
+ {
+ //MxL_MoCA_OsalPrintLog(TRACE_CPCR, L_INFO, "NULL Pointer\n");
+ return 0;
+ }
+
+ return ((ptv1->timeVal.tv_sec - ptv2->timeVal.tv_sec) * 1000000) +
+ (ptv1->timeVal.tv_usec - ptv2->timeVal.tv_usec);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalDiffTime
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Get time difference by sec
+ *
+ * IN PARAMS : tv1 Pointer to time value1
+ * IN PARAMS : tv2 Pointer to time value2
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Time difference by sec
+ *--------------------------------------------------------------------------------------*/
+
+long MxL_MoCA_OsalDiffTime(void *tv1, void *tv2)
+{
+ apposal_timeval_t *ptv1 = tv1;
+ apposal_timeval_t *ptv2 = tv2;
+
+ if (tv1 == 0 || tv2 == 0)
+ {
+ //MxL_MoCA_OsalPrintLog(TRACE_CPCR, L_INFO, "NULL Pointer\n");
+ return 0;
+ }
+
+
+ return ptv1->timeVal.tv_sec - ptv2->timeVal.tv_sec ;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalAssignTime
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Assign time
+ *
+ * IN PARAMS : tv1 Pointer to destion time value
+ * IN PARAMS : tv2 Pointer to source time value
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalAssignTime(void *tv1, void *tv2)
+{
+ apposal_timeval_t *ptv1 = tv1;
+ apposal_timeval_t *ptv2 = tv2;
+ if (tv1 == 0 || tv2 == 0)
+ {
+ //MxL_MoCA_OsalPrintLog(TRACE_CPCR, L_INFO, "NULL Pointer\n");
+ return;
+ }
+ memcpy(ptv1, ptv2, sizeof(apposal_timeval_t));
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalFreeGetTime
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Free time
+ *
+ * IN PARAMS : tv Pointer to destion time value pointer
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalFreeGetTime(void *tv)
+{
+ MxL_MoCA_OsalFree(tv, sizeof(apposal_timeval_t));
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalAlloc
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Allocates memory
+ *
+ * IN PARAMS : size Size of allocate
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Pointer to allocated block if successful, Null pointer otherwise
+ *--------------------------------------------------------------------------------------*/
+
+void *MxL_MoCA_OsalAlloc(int32_t size)
+{
+ void *pMem;
+
+ if (size < KMALLOC_MAX)
+ pMem = kmalloc(size, GFP_KERNEL /* | __GFP_DMA */);
+ else
+ pMem = (void *)__get_free_pages(GFP_KERNEL, get_order(size));
+
+ return (pMem);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalFree
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Free memory
+ *
+ * IN PARAMS : pMem Allocation pointer from get free pages
+ * IN PARAMS : size Requested block size
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalFree(void *pMem, int32_t size)
+{
+ if (size < KMALLOC_MAX)
+ kfree(pMem);
+ else
+ free_pages((unsigned long)pMem, get_order(size));
+
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalMemcpy
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Copies size bytes of memory from pFrom to pTo
+ *
+ * IN PARAMS : pTo Pointer to destination memory area
+ * IN PARAMS : pFrom Pointer to source memory area
+ * IN PARAMS : size Number of bytes to copy
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalMemcpy(void *pTo, void *pFrom, int32_t size)
+{
+ memcpy(pTo, pFrom, size);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalMemset
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Sets size bytes of memory to a given byte value
+ *
+ * IN PARAMS : pMem Pointer to block of memory to set
+ * IN PARAMS : val Value to set each byte to
+ * IN PARAMS : size Number of bytes to set
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalMemset(void *pMem, int32_t val, int32_t size)
+{
+ memset(pMem, val, size);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalPrintLog
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Variable argument OS print
+ *
+ * KERN_EMERG "<0>" / * system is unusable * /
+ * KERN_ALERT "<1>" / * action must be taken immediately * /
+ * KERN_CRIT "<2>" / * critical conditions * /
+ * KERN_ERR "<3>" / * error conditions * /
+ * KERN_WARNING "<4>" / * warning conditions * /
+ * KERN_NOTICE "<5>" / * normal but significant condition * /
+ * KERN_INFO "<6>" / * informational * /
+ * KERN_DEBUG "<7>" / * debug-level messages * /
+ *
+ * IN PARAMS : mod The modules to be traced
+ * IN PARAMS : lev Severity level
+ * IN PARAMS : fmt Printf format string
+ * IN PARAMS : ... Printf format arguments
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalPrintLog(int32_t mod, int32_t lev, const int8_t *fmt, ...)
+{
+ va_list args;
+ static int8_t printk_buf[LOG_PRINT_BUFSIZE];
+
+ /* When you need to see lots message pumped out, make HOST_OS_PRINTLOG_THRESHOLD HIGHER,
+ * for example, you call the API with lev L_VERBOSE, and make HOST_OS_PRINTLOG_THRESHOLD = L_DBG*/
+ if (lev <= HOST_OS_PRINTLOG_THRESHOLD)
+ {
+ /* Emit the output into the temporary buffer */
+ va_start(args, fmt);
+ vsnprintf(printk_buf, sizeof(printk_buf), fmt, args);
+ va_end(args);
+
+ switch (lev)
+ {
+ case L_ERR:
+ printk(KERN_ERR HPFMT, DRV_NAME, printk_buf); //changed to KERN_EMERG
+ break ;
+ case L_WARN:
+ printk(KERN_WARNING HPFMT, DRV_NAME, printk_buf); // Change to KERN_ALERT
+ break ;
+ case L_INFO:
+ printk(KERN_INFO HPFMT, DRV_NAME, printk_buf);
+ break ;
+ case L_VERBOSE:
+ printk(KERN_ERR HPFMT, DRV_NAME, printk_buf);
+ break ;
+ case L_DBG :
+ printk(KERN_DEBUG HPFMT, DRV_NAME, printk_buf);
+ break ;
+ }
+ }
+ else if (lev <= logLev)
+ {
+ /* Emit the output into the temporary buffer */
+ va_start(args, fmt);
+ vsnprintf(printk_buf, sizeof(printk_buf), fmt, args);
+ va_end(args);
+
+ printk(KERN_ERR HPFMT, DRV_NAME, printk_buf);
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalPrintString
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : print string (used for progress bar)
+ * (Note Cannot use MxL_MoCA_OsalPrintLog - it is adding newline)
+ *
+ * IN PARAMS : pStr - character to print
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalPrintString(int8_t* pStr)
+{
+ printk ("%s", pStr);
+}
+
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalSetLogLev
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Set log level
+ *
+ * IN PARAMS : mod The modules to be traced
+ * IN PARAMS : lev Severity level
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalSetLogLev(int32_t mod, int32_t lev)
+{
+ logMod = mod;
+ logLev = lev;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalDelay
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Delays for about timeInUsec microseconds
+ *
+ * IN PARAMS : timeInUsec Delay in microseconds
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalDelay(int32_t timeInUsec)
+{
+ if (timeInUsec < USEC_PER_MS)
+ {
+ udelay(timeInUsec);
+ }
+ else
+ {
+ mdelay(timeInUsec/USEC_PER_MS);
+ }
+}
+
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalDelayUsec
+ *
+ *
+ * DATE CREATED : Oct/02/2016
+ *
+ * DESCRIPTION : Delays for about timeInUsec microseconds
+ *
+ * IN PARAMS : timeInUsec Delay in microseconds
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalDelayUsec(uint32_t timeInUsec)
+{
+ if (timeInUsec < USEC_PER_MS)
+ {
+ udelay(timeInUsec);
+ }
+ else
+ {
+ mdelay(timeInUsec/USEC_PER_MS);
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalMSleep
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Sleep for about timeInMilliSec microseconds
+ *
+ * IN PARAMS : timeInMilliSec Sleep in MilliSec
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalMSleep(int32_t timeInMilliSec)
+{
+ msleep(timeInMilliSec);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalSscanf
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Scans input buffer and according to format specified
+ *
+ * IN PARAMS : buf Input buffer
+ * IN PARAMS : fmt Input format
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalSscanf(const int8_t *buf, const int8_t *fmt, ...)
+{
+ va_list args;
+
+ va_start(args, fmt);
+ vsscanf(buf, fmt, args);
+ va_end(args);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalTermLock
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Terminates a lock
+ *
+ * IN PARAMS : pLock Pointer to an initialized lock structure
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalTermLock(void *pLock)
+{
+ //Null code in current implemenation
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalTimerMod
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Modifies a timer
+ *
+ * IN PARAMS : pTmr Pointer to the timer to deactivate
+ * IN PARAMS : timeout Timeout value from MxL_MoCA_Osaltimer_expire_seconds
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : 1 for the timer was active (not expired), 0 for the timer was not active
+ *--------------------------------------------------------------------------------------*/
+
+int32_t MxL_MoCA_OsalTimerMod(void *pTmr, unsigned long timeout)
+{
+ osal_timer_t *tmr = (osal_timer_t *)pTmr ;
+
+ return (mod_timer(&tmr->ostimer, timeout)) ;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalCopyFromUser
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Copies a block from user space to kernel space
+ *
+ * IN PARAMS : to Pointer to a kernel space buffer to receive the data
+ * IN PARAMS : form Pointer to a user space buffer as the source data
+ * IN PARAMS : nbytes Length for copy
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : 0 for success, others for number of bytes NOT copied
+ *--------------------------------------------------------------------------------------*/
+
+unsigned long MxL_MoCA_OsalCopyFromUser(void *to, const void *from, unsigned long nbytes)
+{
+ unsigned long n ;
+
+ n = copy_from_user(to, from, nbytes);
+
+ return(n) ;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalCopyToUser
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Copies a block from kernel space to user space
+ *
+ * IN PARAMS : to Pointer to a user space buffer to receive the data
+ * IN PARAMS : from Pointer to a kernel space buffer as the source data
+ * IN PARAMS : nbytes Length for copy
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : 0 for success, others for number of bytes NOT copied
+ *--------------------------------------------------------------------------------------*/
+
+unsigned long MxL_MoCA_OsalCopyToUser(void *to, const void *from, unsigned long nbytes)
+{
+ unsigned long n ;
+
+ n = copy_to_user(to, from, nbytes);
+
+ return(n) ;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalMutexInit
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Initialize a mutex
+ *
+ * IN PARAMS : vmt Pointer to the mutex structure
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalMutexInit(void *vmt)
+{
+ init_MUTEX((struct semaphore *)vmt) ; /// abstraction
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalMutexRelease
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Release a mutex
+ * Do NOT call this from an ISR!
+ * Do NOT call this if you are not the current holder of the mutex.
+ *
+ * IN PARAMS : vmt Pointer to the mutex structure
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalMutexRelease(void *vmt)
+{
+ up((struct semaphore *)vmt) ; /// abstraction
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalMutexAcquire
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Acquire a mutex
+ * Might sleep, when this returns you have the mutex.
+ * This is NOT the preferred method. See MxL_MoCA_Osalmutex_acquire_intr().
+ * Do NOT call this from an ISR!
+ *
+ * IN PARAMS : vmt Pointer to the mutex structure
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalMutexAcquire(void *vmt)
+{
+ down((struct semaphore *)vmt) ; /// abstraction
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalMutexAcquireIntr
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Acquire (down) a mutex. Interruptible
+ *
+ * Might sleep.
+ * When this returns 0 you have the mutex.
+ * When this returns -EINTR you have been interrupted
+ * and must bail out. You do NOT have the mutex. The
+ * purpose here is to allow the caller, probably a
+ * user space app, to be interrupted and die quickly
+ * and quietly; rather than becoming a zombie because
+ * the driver won't let go.
+ * This is the preferred method.
+ * Do NOT call this from an ISR!
+ *
+ * IN PARAMS : vmt Pointer to the mutex structure
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : 0 Got the mutex
+ * EINTR Have been interrupted, no mutex
+ *--------------------------------------------------------------------------------------*/
+
+int32_t MxL_MoCA_OsalMutexAcquireIntr(void *vmt)
+{
+ int32_t rc;
+
+ MXL_ENTER_FUNCTION(TRACE_OSWP, "vmt = %p", vmt);
+
+ rc = down_interruptible((struct semaphore *)vmt) ; /// abstraction
+
+ MXL_EXIT_FUNCTION(TRACE_OSWP, "rc = %d", rc);
+
+ return(rc) ;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalTimerExpireSeconds
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Calculate a future expiration point in seconds
+ *
+ * IN PARAMS : future Number of seconds into the future
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : A number for use in the timer expiration
+ *--------------------------------------------------------------------------------------*/
+
+unsigned long MxL_MoCA_OsalTimerExpireSeconds(uint32_t future)
+{
+
+ return (jiffies + (future * HZ));
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalTimerExpireTicks
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Calculate a future expiration point in jiffies
+ *
+ * IN PARAMS : future Number of ticks into the future
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : A number for use in the timer expiration
+ *--------------------------------------------------------------------------------------*/
+
+unsigned long MxL_MoCA_OsalTimerExpireTicks(uint32_t future)
+{
+
+ return (jiffies + future);
+}
+
+// MxL: do not use timer in current code
+#if defined(INCLUDE_OSAL_WQT_TIMER)
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalWqtAlloc
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Allocates a wqt entry from the heap
+ *
+ * IN PARAMS : None
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : 0 Allocation failure
+ * Othres Void pointer to opaque data
+ *--------------------------------------------------------------------------------------*/
+
+void *MxL_MoCA_OsalWqtAlloc(void)
+{
+ osal_wqt_t *wqt ;
+
+ wqt = kmalloc(sizeof(osal_wqt_t), GFP_KERNEL) ;
+
+ return ((void *)wqt);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalWqtFree
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Free a wqt entry from the heap
+ *
+ * IN PARAMS : vwqt Pointer to the osal_wqt_t to be freed
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalWqtFree(void *vwqt)
+{
+
+ kfree(vwqt) ;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalWqtTimerInit
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Initialize a timer and register it
+ *
+ * IN PARAMS : vwqt Pointer to the osal_wqt_t with timer to initialize
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalWqtTimerInit(void *vwqt)
+{
+ osal_wqt_t *wqt = (osal_wqt_t *)vwqt ;
+
+ wqt->wqt_allocated = 1 ; /// mark the timer inited
+ init_timer(&wqt->wqt_timer) ;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalWqtTimerDel
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Delete a wqt timer
+ *
+ * IN PARAMS : vwqt Pointer to the osal_wqt_t with timer to deactivate
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalWqtTimerDel(void *vwqt)
+{
+ osal_wqt_t *wqt = (osal_wqt_t *)vwqt ;
+
+ if (wqt->wqt_allocated)
+ {
+ del_timer(&wqt->wqt_timer) ;
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalWqtTimerDelSync
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Deactivate a registered timer
+ *
+ * IN PARAMS : vwqt Pointer to the osal_wqt_t with timer to deactivate
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : 1 the timer was active (not expired), 0 the timer was not active
+ *--------------------------------------------------------------------------------------*/
+
+int32_t MxL_MoCA_OsalWqtTimerDelSync(void *vwqt)
+{
+ osal_wqt_t *wqt = (osal_wqt_t *)vwqt ;
+
+ return (del_timer_sync(&wqt->wqt_timer)) ;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalWqtTimerMod
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Modifies a timer
+ *
+ * IN PARAMS : vwqt Pointer to the osal_wqt_t with timer to modify
+ * timeout Timeout value from MxL_MoCA_Osaltimer_expire_seconds
+ or MxL_MoCA_Osaltimer_expire_ticks.
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : 1 the timer was active (not expired), 0 the timer was not active
+ *--------------------------------------------------------------------------------------*/
+
+int32_t MxL_MoCA_OsalWqtTimerMod(void *vwqt, unsigned long timeout)
+{
+ osal_wqt_t *wqt = (osal_wqt_t *)vwqt ;
+
+ return (mod_timer(&wqt->wqt_timer, timeout)) ;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalWqtTimerAdd
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Add a timer, call this after HostOS_timer_setup
+ *
+ * IN PARAMS : vwqt Pointer to the osal_wqt_t with timer to add
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : 1 the timer was active (not expired), 0 the timer was not active
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalWqtTimerAdd(void *vwqt)
+{
+ osal_wqt_t *wqt = (osal_wqt_t *)vwqt ;
+
+ add_timer(&wqt->wqt_timer) ;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalWqtTimerSetup
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Sets up a timer with function and user data
+ *
+ * IN PARAMS : vwqt Pointer to the osal_wqt_t with timer to init
+ * func Callback function to call at timer expiration
+ * data Data to pass to callback
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalWqtTimerSetup(void *vwqt, timer_function_t func, unsigned long data)
+{
+ osal_wqt_t *wqt = (osal_wqt_t *)vwqt ;
+
+ wqt->wqt_timer.function = func ;
+ wqt->wqt_timer.data = data ;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalWqtTimerSetTimeout
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Sets a timer's time out
+ *
+ * IN PARAMS : vwqt Pointer to the osal_wqt_t with timer to set
+ * timeout Timeout value from MxL_MoCA_Osaltimer_expire_seconds
+ * or MxL_MoCA_Osaltimer_expire_ticks
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalWqtTimerSetTimeout(void *vwqt, unsigned long timeout)
+{
+ osal_wqt_t *wqt = (osal_wqt_t *)vwqt ;
+
+ wqt->wqt_timer.expires = timeout ;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalWqtWaitqInit
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Inits a wait queue head in a osal_wqt_t
+ *
+ * IN PARAMS : vwqt Pointer to the osal_wqt_t with wait queue to init
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalWqtWaitqInit(void *vwqt)
+{
+ osal_wqt_t *wqt = (osal_wqt_t *)vwqt ;
+
+ init_waitqueue_head(&wqt->wqt_wq);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalWqtWaitqWakeupIntr
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Wakes up a wait queue in a osal_wqt_t
+ *
+ * IN PARAMS : vwqt Pointer to the osal_wqt_t with wait queue to wake
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalWqtWaitqWakeupIntr(void *vwqt)
+{
+ osal_wqt_t *wqt = (osal_wqt_t *)vwqt ;
+
+ if (wqt)
+ {
+ wake_up_interruptible(&wqt->wqt_wq);
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalWqtWaitqWaitEventIntr
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Waits for a wait queue event in a osal_wqt_t
+ *
+ * IN PARAMS : vwqt Pointer to the osal_wqt_t with wait queue to wait on
+ * func Fountion execute in the interrupt
+ * vp Pointer to void data
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalWqtWaitqWaitEventIntr(void *vwqt, osal_wqt_condition func, void *vp)
+{
+ osal_wqt_t *wqt = (osal_wqt_t *)vwqt ;
+
+ wait_event_interruptible(wqt->wqt_wq, /** pass by value */
+ func(vp));
+}
+
+#endif // INCLUDE_OSAL_TIMER
+
+DECLARE_MUTEX(reset_mutex);
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalSignalPending
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Check pending signal of task
+ *
+ * IN PARAMS : vtask Pointer to the task
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : 0 - no pending signal, 1 - has pendign signal
+ *--------------------------------------------------------------------------------------*/
+
+int32_t MxL_MoCA_OsalSignalPending(void *vtask)
+{
+ struct task_struct *p;
+
+ if (vtask== NULL)
+ p = current;
+ else
+ p = (struct task_struct *)vtask;
+
+ return signal_pending(p);
+}
+
+#if defined(CANDD_DRVR_SUPPORT)
+
+/** declaring mutexes for kernel thread start/stop */
+DECLARE_MUTEX(osal_thread_mutex);
+
+osal_kthread_t hostosThread;
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalJiffiesToMsecs
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Convert jiffies to milliseconds
+ *
+ * IN PARAMS : j jiffies
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Number of milliseconds
+ *--------------------------------------------------------------------------------------*/
+
+static inline uint32_t MxL_MoCA_OsalJiffiesToMsecs(const unsigned long j)
+{
+ uint32_t ret;
+#if HZ <= USEC_PER_MS && !(USEC_PER_MS % HZ)
+ ret = (USEC_PER_MS / HZ) * j;
+#elif HZ > USEC_PER_MS && !(HZ % USEC_PER_MS)
+ ret = (j + (HZ / USEC_PER_MS) - 1)/(HZ / USEC_PER_MS);
+#else
+ ret = (j * USEC_PER_MS) / HZ;
+#endif
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalMsecsToJiffies
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Convert milliseconds to jiffies
+ *
+ * IN PARAMS : m milliseconds
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Number of jiffies
+ *--------------------------------------------------------------------------------------*/
+
+static inline unsigned long MxL_MoCA_OsalMsecsToJiffies(const uint32_t m)
+{
+ unsigned long ret;
+
+#if HZ <= USEC_PER_MS && !(USEC_PER_MS % HZ)
+ ret = (m + (USEC_PER_MS / HZ) - 1) / (USEC_PER_MS / HZ);
+#elif HZ > USEC_PER_MS && !(HZ % USEC_PER_MS)
+ ret = m *(HZ / USEC_PER_MS);
+#else
+ ret = (m * HZ + USEC_PER_MS - 1) / USEC_PER_MS;
+#endif
+
+ if (m > MxL_MoCA_OsalJiffiesToMsecs(MAX_JIFFY_OFFSET))
+ ret = MAX_JIFFY_OFFSET;
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalMsleepInterruptible
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Sleep waiting for waitqueue interruptions
+ *
+ * IN PARAMS : msecs Time in milliseconds to sleep for
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalMsleepInterruptible(uint32_t msecs)
+{
+ unsigned long timeout = MxL_MoCA_OsalMsecsToJiffies(msecs) + 1;
+
+ while (timeout)
+ {
+ __set_current_state(TASK_INTERRUPTIBLE);
+ timeout = schedule_timeout(timeout);
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalThreadInterFunc
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Kernel thread internal function
+ *
+ * IN PARAMS : pdata Pointer to thread struct
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_OsalThreadInterFunc(void *pdata)
+{
+ osal_kthread_t *pThread = (osal_kthread_t *)pdata;
+
+ if (pdata != NULL)
+ {
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)
+ allow_signal(SIGKILL);
+ allow_signal(SIGTERM);
+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+ daemonize(hostosThread.name, 0);
+ allow_signal(SIGKILL);
+ allow_signal(SIGTERM);
+#else
+ daemonize();
+#endif
+
+ /** kernel thread main function */
+ pThread->func(pThread->arg);
+ }
+
+ return ;
+}
+
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalTestPtrErrCondition
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Checks for ERR_PTR(-ENOMEM).
+ *
+ * IN PARAMS : A previously kernel returned pointer from calls such as kthread...
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : MXL_MOCA_OK or MXL_MOCA_ERR
+ *--------------------------------------------------------------------------------------*/
+
+int32_t MxL_MoCA_OsalTestPtrErrCondition(void *pTask)
+{
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+
+ if (IS_ERR(pTask))
+ {
+ ret = MXL_MOCA_ERR;
+ }
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalThreadCreateAndStart
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : create and wake a thread. A wrapper functiion for kthread_run.
+ *
+ * IN PARAMS : threadfn - the function to run until signal_pending(current).
+ * data - data ptr for threadfn
+ * namefmt - printf-style name for the thread
+ * arg - arguments
+ *
+ * OUT PARAMS : ppTask - double pointer to the kThread task
+ * RETURN VALUE : Returns the kthread or
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_OsalThreadCreateAndStart(int32_t (*threadfn)(void *data),
+ void *data,
+ const int8_t *namefmt,
+ void *arg,
+ void **ppTask)
+{
+ *ppTask = kthread_run(threadfn, data, namefmt, arg);
+
+ return MxL_MoCA_OsalTestPtrErrCondition(*ppTask);
+}
+
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_OsalGetDaemonThreadStopStatus
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : should this kthread return now (kthread_stop was called to stop thread)?
+ *
+ * IN PARAMS : None
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_KTHREAD_SHOULD_STOP if someone had called kthread_stop.
+ * else, MXL_MOCA_OK
+ *
+ *--------------------------------------------------------------------------------------*/
+MXL_MOCA_STATUS_E MxL_MoCA_OsalGetDaemonThreadStopStatus()
+{
+ MXL_MOCA_STATUS_E status = MXL_MOCA_OK;
+
+ if (kthread_should_stop() == true)
+ {
+ status = MXL_MOCA_KTHREAD_SHOULD_STOP;
+ }
+ return status;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalThreadStart
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Start a keneral thread
+ *
+ * IN PARAMS : pThreadID Pointer to new kernel threadID
+ * pName Pointer to thread name string
+ * func Pointer to thread internal function
+ * arg Argument to pass to thread function
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : 0 - success, others - failed
+ *--------------------------------------------------------------------------------------*/
+
+int32_t MxL_MoCA_OsalThreadStart(uint32_t *pThreadID, int8_t *pName, void (*func)(void *), void *arg)
+{
+ int32_t ret = MXL_MOCA_OK;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
+ struct task_struct *tsk;
+#endif
+
+ down(&osal_thread_mutex);
+
+ strncpy(hostosThread.name, pName,16);
+ hostosThread.func = func;
+ hostosThread.arg = arg;
+
+ do
+ {
+ /** Create kernel thread */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
+ tsk = kthread_run((int32_t (*)(void *))MxL_MoCA_OsalThreadInterFunc, &hostosThread, hostosThread.name);
+ if (IS_ERR(tsk))
+ {
+ ret = MXL_MOCA_ERR;
+ break;
+ }
+
+ hostosThread.threadID = (uintptr_t)get_pid(task_pid(tsk));
+#else
+ hostosThread.threadID = kernel_thread((int32_t (*)(void *))MxL_MoCA_OsalThreadInterFunc, &hostosThread, 0);
+ if (hostosThread.threadID < 0)
+ {
+ ret = MXL_MOCA_ERR;
+ break;
+ }
+#endif
+
+ *pThreadID = hostosThread.threadID;
+ } while (0);
+
+ up(&osal_thread_mutex);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalThreadStop
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Stop a keneral thread
+ *
+ * IN PARAMS : threadID Kernel threadID that to be stopped
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : 0 - success, others - failed
+ *--------------------------------------------------------------------------------------*/
+
+int32_t MxL_MoCA_OsalThreadStop(unsigned long threadID)
+{
+ int32_t ret = MXL_MOCA_OK;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
+ struct pid *pPid;
+#endif
+
+ down(&osal_thread_mutex);
+
+ do
+ {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
+ pPid = find_get_pid(threadID);
+ if(pPid == NULL)
+ {
+ ret = MXL_MOCA_OK;
+ break;
+ }
+
+ if ((ret = kill_pid(pPid, SIGKILL, 1)))
+#else
+ if ((ret = kill_proc(threadID, SIGKILL, 1)))
+#endif
+ {
+ ret = MXL_MOCA_ERR;
+ break;
+ }
+ } while (0);
+
+ up(&osal_thread_mutex);
+
+ return ret;
+}
+
+#endif
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalReadWord
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : register/memory read access from kernel space
+ *
+ * IN PARAMS : addr Address to read from
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : 32 bits value from given address
+ *--------------------------------------------------------------------------------------*/
+
+uint32_t MxL_MoCA_OsalReadWord(void *addr)
+{
+ uint32_t rv ;
+
+#if defined(CONFIG_ARCH_MAXLINEAR_ECB) && (defined(CONFIG_ARCH_IXP425) || defined(CONFIG_ARCH_IXP4XX))
+ rv = *(volatile uint32_t *)addr ;
+#else
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
+ rv = readl((const volatile void *)addr);
+#else
+ rv = readl(addr);
+#endif
+#endif
+
+#if defined(CONFIG_ARCH_LAYERSCAPE)
+ rv = (rv & 0xff) << 24
+ | (rv & 0xff00) << 8
+ | (rv & 0xff0000) >> 8
+ | (rv & 0xff000000) >> 24;
+#endif
+ return (rv);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalWriteWord
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Register/Memory write access from kernel space
+ *
+ * IN PARAMS : val 32 bit value to write
+ * addr Address to write to
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalWriteWord(uint32_t val, void *addr)
+{
+
+#if defined(CONFIG_ARCH_LAYERSCAPE)
+ val = (val & 0xff) << 24
+ | (val & 0xff00) << 8
+ | (val & 0xff0000) >> 8
+ | (val & 0xff000000) >> 24;
+#endif
+#if defined(CONFIG_ARCH_MAXLINEAR_ECB) && (defined(CONFIG_ARCH_IXP425) || defined(CONFIG_ARCH_IXP4XX))
+ *(volatile uint32_t *)addr = val ;
+#else
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
+ writel(val, (volatile void *)addr);
+#else
+ writel(val, addr);
+#endif
+#endif
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalLogInfo
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Print the debug string
+ *
+ * IN PARAMS : format String format
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalLogInfo(int8_t* format, ...)
+{
+ int8_t linebuf[400];
+ va_list ap;
+
+ va_start(ap, format);
+ vsnprintf(linebuf, sizeof(linebuf), format, ap);
+ va_end(ap);
+
+ printk(KERN_INFO DRV_NAME "%s\n", linebuf);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalKthreadStop
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Stop a thread created by kthread_create
+ *
+ * IN PARAMS : tsk Pointer to task structure
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : The result of threadfn(), or -EINTR if wake_up_process()
+ *--------------------------------------------------------------------------------------*/
+
+int32_t MxL_MoCA_OsalKthreadStop(void *tsk)
+{
+ return kthread_stop(tsk);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetPointerToFirmwareData
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Get the firmware data via the firmware index
+ *
+ * IN PARAMS : pFw Pointer to MxL MoCA firmware
+ * idx Index of firmware data to get
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Pointer to firmware data, or NULL if failure
+ *--------------------------------------------------------------------------------------*/
+
+void *MxL_MoCA_OsalGetPointerToFirmwareData(MXL_MOCA_FIRMWARE_T *pFw, int32_t idx)
+{
+ void *p = NULL;
+
+ if (NULL != pFw)
+ {
+ do
+ {
+ if (idx < MXL_MOCA_CCPU_IDX || idx >= MXL_MOCA_MAX_FW_IDX)
+ break;
+
+ if (pFw->fw_entry[idx])
+ p = (void *)((struct firmware*)pFw->fw_entry[idx])->data;
+
+ } while (0);
+ }
+ else
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "Get Pointer To Firmware Data: NULL\n");
+ }
+
+ return p;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetFirmwareLen
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Get the firmware length via the firmware index
+ *
+ * IN PARAMS : pFw Pointer to clink firmware
+ * idx Index of firmware data to get length
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Length of firmware with index \a idx, or 0 if not found
+ *--------------------------------------------------------------------------------------*/
+
+int32_t MxL_MoCA_OsalGetFirmwareLen(MXL_MOCA_FIRMWARE_T *pFw, int32_t idx)
+{
+ int32_t len = 0;
+
+ if (NULL != pFw)
+ {
+ do
+ {
+ if (idx < MXL_MOCA_CCPU_IDX || idx >= MXL_MOCA_MAX_FW_IDX)
+ break;
+
+ if (pFw->fw_entry[idx])
+ len = ((struct firmware *)pFw->fw_entry[idx])->size;
+
+ } while (0);
+ }
+
+ return len;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalFreeFirmwares
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Free firmwares
+ *
+ * IN PARAMS : pFw Pointer to firmware data
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalFreeFirmwares(MXL_MOCA_FIRMWARE_T *pFw)
+{
+ int32_t i;
+#ifdef SET_CD_FW_SUPPORT
+ MXL_MOCA_FIRMWARE_ENTRY_T *pfwentry;
+#endif
+
+ MXL_ENTER_FUNCTION(TRACE_OSWP, "pFw = %p", pFw);
+
+ if (pFw != NULL)
+ {
+ for (i = 0; i < MXL_MOCA_MAX_FW_IDX; i++)
+ {
+ if (pFw->ret & (1 << i))
+ {
+#ifdef SET_CD_FW_SUPPORT
+ if (gGetFwViaIoctl)
+ {
+ if (pFw->fw_entry[i])
+ {
+ pfwentry = (MXL_MOCA_FIRMWARE_ENTRY_T *)pFw->fw_entry[i];
+
+ if (pfwentry->data && MXL_MOCA_CCPU_IDX != i) // ccpu elf put in global buf
+ {
+ MxL_MoCA_OsalFree(pfwentry->data, pfwentry->size);
+ }
+
+ MxL_MoCA_OsalFree(pFw->fw_entry[i], sizeof(MXL_MOCA_FIRMWARE_ENTRY_T));
+ pFw->fw_entry[i] = NULL;
+ }
+ }
+ else
+#endif
+ {
+ if ((struct firmware*)pFw->fw_entry[i])
+ {
+ release_firmware((struct firmware *)pFw->fw_entry[i]);
+ }
+ }
+ }
+ }
+
+ pFw->ret = 0;
+ }
+
+ MXL_EXIT_FUNCTION(TRACE_OSWP, "status = %d", (pFw != NULL) ? pFw->ret : MXL_MOCA_ERR);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetFirmwareAndConfigData
+ *
+ *
+ * DATE CREATED : Sep/30/2016
+ *
+ * DESCRIPTION : Setup firmware, this will request the ccpu elf and all configs from
+ * user space for the device
+ *
+ * IN PARAMS : pDev MoCA device
+ * : pDevName Device name
+ * : pFw Pointer to the mxl moca firmware struct
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : the bit mask for the firmware requested successfully
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_OsalGetFirmwareAndConfigData(uint32_t chipTypeIndex,
+ void *pDev,
+ const int8_t *pDevName,
+ MXL_MOCA_FIRMWARE_T *pFw,
+ int32_t *pFwBitMaskRet)
+{
+ MXL_MOCA_STATUS_E status = MXL_MOCA_OK;
+ int32_t i;
+ int8_t path[128];
+ static const int8_t *pChipSuffix[MXL_MOCA_SOC_TYPE_MAX] = {".jaws",
+ ".malaga",
+ ".cardiff",
+ ".leucadia",
+ ""};
+
+ static const int8_t *pFwFiles[MXL_MOCA_MAX_FW_IDX] = {"ccpu.elf",
+ "clink.bin",
+ "mcast.bin",
+ "rlapm.bin",
+ "endet.bin",
+ "sapm.bin",
+ "rssi.bin",
+ "platform.bin"};
+
+ MXL_ENTER_FUNCTION(TRACE_OSWP, "pDev = %p, pDevName = %s, pFw = %p", pDev, pDevName, pFw);
+
+ if ((pDev == NULL) || (pDevName == NULL) || (pFw == NULL) || (pFwBitMaskRet == NULL))
+ {
+ return MXL_MOCA_ERR;
+ }
+
+ *pFwBitMaskRet = 0;
+
+#ifdef SET_CD_FW_SUPPORT
+ if (!gGetFwViaIoctl)
+#endif
+ {
+ do
+ {
+ MxL_MoCA_OsalMemset(pFw, 0, sizeof(*pFw));
+
+ for (i = 0; i < MXL_MOCA_MAX_FW_IDX; i++)
+ {
+ if (i == MXL_MOCA_CCPU_IDX)
+ MxL_MoCA_OsalSnprintf(path, sizeof(path), "%s%s", pFwFiles[i], pChipSuffix[chipTypeIndex]);
+ else
+ MxL_MoCA_OsalSnprintf(path, sizeof(path), "%s/%s", pDevName, pFwFiles[i]);
+
+ if (request_firmware((const struct firmware **)&(pFw->fw_entry[i]), path, (struct device *)pDev))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_OSWP, L_ERR, "Can't load firmware %s\n", path);
+ status = MXL_MOCA_ERR;
+ break;
+ }
+ else
+ {
+ pFw->ret |= (1 << i);
+ }
+ }
+ *pFwBitMaskRet = pFw->ret;
+ }while (0);
+ }
+
+ MXL_EXIT_FUNCTION(TRACE_OSWP, "status (bitmask) = %#x", *pFwBitMask);
+
+ return status;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetResetMutex
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Get reset mutex
+ *
+ * IN PARAMS : None
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Pointer to reset mutex
+ *--------------------------------------------------------------------------------------*/
+
+void *MxL_MoCA_OsalGetResetMutex(void)
+{
+ return &reset_mutex;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalStrcpy
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Copy string from source to dstine
+ *
+ * IN PARAMS : dst Pointer destine string
+ * src Pointer source string
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Pointer to destine string
+ *--------------------------------------------------------------------------------------*/
+
+int8_t *MxL_MoCA_OsalStrcpy(int8_t *dst, const int8_t *src)
+{
+ return strcpy(dst, src);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalSnprintf
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Get parameters from argument buffer
+ *
+ * IN PARAMS : buf Pointer to created string
+ * size Length for bytes
+ * fmt Type for created string
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Length of created string
+ *--------------------------------------------------------------------------------------*/
+
+int32_t MxL_MoCA_OsalSnprintf(int8_t *buf, uint32_t size, const int8_t *fmt, ...)
+{
+ va_list args;
+ int32_t i;
+
+ va_start(args, fmt);
+ i=vsnprintf(buf,size,fmt,args);
+ va_end(args);
+
+ return i;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalHtons
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Host to network short
+ *
+ * IN PARAMS : n Host number
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Network short
+ *--------------------------------------------------------------------------------------*/
+
+uint16_t MxL_MoCA_OsalHtons(uint16_t n)
+{
+ return htons(n);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_OsalCheckImage
+ *
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Check the SoC ELF image
+ *
+ * IN PARAMS : elfData : Pointer to the ELF image data
+ * elfSize : Size of the ELF image
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE :
+ * \retval MXL_MOCA_OK Success
+ * \retval MXL_MOCA_ERR Failure
+ *
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_OsalCheckImage(uint8_t *elfData, uint32_t elfSize)
+{
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_ERR;
+
+ // MXL_ENTER_FUNCTION(TRACE_OSWP, "elfData = %p, elfSize = %u", elfData, elfSize);
+ MxL_MoCA_OsalPrintLog(TRACE_CD, L_DBG, "MxL_MoCA_OsalCheckImage::elfData = %p, elfSize = %u", elfData, elfSize);
+
+ if (elfData != NULL)
+ {
+ do
+ {
+ size_t length;
+ Elf32_Ehdr *ehdr = (Elf32_Ehdr*) elfData;
+
+ if (elfSize < sizeof(Elf32_Ehdr))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_CD, L_DBG, "elfSize %d < sizeof(Elf32_Ehdr) %d \n", elfSize, sizeof(Elf32_Ehdr) );
+ break;
+ }
+
+ if (elfSize < MxL_MoCA_OsalNtohl(ehdr->e_phoff))
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_CD, L_DBG, "elfSize < HTONL(ehdr->e_phoff)\n");
+ break;
+ }
+
+ length = MxL_MoCA_OsalNtohs(ehdr->e_phentsize) * MxL_MoCA_OsalNtohs(ehdr->e_phnum);
+
+ elfData += MxL_MoCA_OsalNtohl(ehdr->e_phoff);
+ elfSize -= MxL_MoCA_OsalNtohl(ehdr->e_phoff);
+
+ if (elfSize < length)
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_CD, L_ERR, "partial soc image used\n");
+ break;
+ }
+ ret = MXL_MOCA_OK;
+ } while(0);
+ }
+ else
+ {
+ MxL_MoCA_OsalPrintLog(TRACE_CD, L_DBG, "Invalid elfdata buff \n");
+ }
+
+ MXL_EXIT_FUNCTION(TRACE_OSWP, "status = %d", ret);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetFirstPhdr
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Get the first program header of the ELF image
+ *
+ * IN PARAMS :
+ * \param[in] elfData ELF image data
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Pointer to the first program header
+ *--------------------------------------------------------------------------------------*/
+
+void *MxL_MoCA_OsalGetFirstPhdr(uint8_t * elfData)
+{
+ void *phdr = 0;
+ Elf32_Ehdr *ehdr = (Elf32_Ehdr*) elfData;
+
+ MXL_ENTER_FUNCTION(TRACE_OSWP, "elfData = %p", elfData);
+
+ if (elfData != NULL)
+ {
+ elfData += MxL_MoCA_OsalNtohl(ehdr->e_phoff);
+ phdr = elfData;
+ }
+ MXL_EXIT_FUNCTION(TRACE_OSWP, "status = %d", MXL_MOCA_OK);
+
+ return phdr;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetNumOfProgHeader
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Get the first program header of the ELF image
+ *
+ * IN PARAMS :
+ * \param[in] elfData ELF image data
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Number of program header of the ELF image
+ *--------------------------------------------------------------------------------------*/
+
+uint32_t MxL_MoCA_OsalGetNumOfProgHeader(void *data)
+{
+ Elf32_Ehdr *pdata = (Elf32_Ehdr *)data;
+ uint32_t ret = 0;
+
+ DEBUG_PRINT(TRACE_CD, L_DBG, "pdata->e_phnum %d %d\n", pdata->e_phnum, MxL_MoCA_OsalNtohs(pdata->e_phnum));
+ if (data != NULL)
+ {
+ ret = MxL_MoCA_OsalNtohs(pdata->e_phnum);
+ }
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetProgHeaderPhyAddr
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Get the physical address of the program header
+ *
+ * IN PARAMS :
+ * \param[in] phdr Program header pointer
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Physical address of the program header
+ *--------------------------------------------------------------------------------------*/
+
+uint32_t MxL_MoCA_OsalGetProgHeaderPhyAddr(void *phdr)
+{
+ uint32_t ret = 0;
+ Elf32_Phdr *pdata = (Elf32_Phdr *)phdr;
+
+ DEBUG_PRINT(TRACE_CD, L_DBG, "pdata->p_paddr %x %x\n", pdata->p_paddr, MxL_MoCA_OsalNtohl(pdata->p_paddr));
+
+ if (phdr != NULL)
+ {
+ ret = (uint32_t)MxL_MoCA_OsalNtohl(pdata->p_paddr);
+ }
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetProgHeaderOffset
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Get offset of the program header
+ *
+ * IN PARAMS :
+ * \param[in] phdr Program header pointer
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Offset of the program header
+ *--------------------------------------------------------------------------------------*/
+
+uint32_t MxL_MoCA_OsalGetProgHeaderOffset(void *phdr)
+{
+ uint32_t ret = 0;
+ Elf32_Phdr * header = (Elf32_Phdr *)phdr;
+
+ DEBUG_PRINT(TRACE_CD, L_DBG, "header->p_offset %x %x\n", header->p_offset, MxL_MoCA_OsalNtohl(header->p_offset));
+
+ if (phdr != NULL)
+ {
+ ret = MxL_MoCA_OsalNtohl(header->p_offset);
+ }
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetProgHeaderFileSZ
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Get size of the segment
+ *
+ * IN PARAMS :
+ * \param[in] hdr Segment header pointer
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Size of the segment
+ *--------------------------------------------------------------------------------------*/
+
+uint32_t MxL_MoCA_OsalGetProgHeaderFileSZ(void *hdr)
+{
+ uint32_t ret = 0;
+ Elf32_Phdr * header = (Elf32_Phdr *)hdr;
+
+ DEBUG_PRINT(TRACE_CD, L_DBG, "header->p_filesz %x %x\n", header->p_filesz, MxL_MoCA_OsalNtohl(header->p_filesz));
+
+ if (hdr != NULL)
+ {
+ ret = MxL_MoCA_OsalNtohl(header->p_filesz);
+ }
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetProgHeaderFileSZ
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Get next program header
+ *
+ * IN PARAMS :
+ * \param[in] phdr Current program header pointer
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Next program header
+ *--------------------------------------------------------------------------------------*/
+
+void *MxL_MoCA_OsalNextProgHeader(void *phdr)
+{
+ Elf32_Phdr * header = (Elf32_Phdr *)phdr;
+
+ if (phdr != NULL)
+ {
+ ++header;
+
+ DEBUG_PRINT(TRACE_CD, L_DBG, "next header %x %x\n", header);
+ }
+
+ return (void*)header;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetFirstShdr
+ *
+ *
+ * DATE CREATED : Dec/14/2017
+ *
+ * DESCRIPTION : Get the first section header of the ELF image
+ *
+ * IN PARAMS :
+ * \param[in] elfData ELF image data
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Pointer to the first section header
+ *--------------------------------------------------------------------------------------*/
+
+void *MxL_MoCA_OsalGetFirstShdr(uint8_t * elfData)
+{
+ void *phdr = 0;
+ Elf32_Ehdr *ehdr = (Elf32_Ehdr*) elfData;
+
+ MXL_ENTER_FUNCTION(TRACE_OSWP, "elfData = %p", elfData);
+
+ if (elfData != NULL)
+ {
+ elfData += MxL_MoCA_OsalNtohl(ehdr->e_shoff);
+ phdr = elfData;
+ }
+
+ MXL_EXIT_FUNCTION(TRACE_OSWP, "status = %d", MXL_MOCA_OK);
+
+ return phdr;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetNumOfSecHeaders
+ *
+ *
+ * DATE CREATED : Dec/14/2017
+ *
+ * DESCRIPTION : Get the number of section headers of the ELF image
+ *
+ * IN PARAMS :
+ * \param[in] elfData ELF image data
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Number of program header of the ELF image
+ *--------------------------------------------------------------------------------------*/
+
+uint32_t MxL_MoCA_OsalGetNumOfSecHeaders(void *pData)
+{
+ Elf32_Ehdr *pdata = (Elf32_Ehdr *)pData;
+ uint32_t ret = 0;
+
+ if (pData != NULL)
+ {
+ ret = MxL_MoCA_OsalNtohs(pdata->e_shnum);
+ }
+
+ DEBUG_PRINT(TRACE_CD, L_DBG, "pdata->e_phnum %d %d\n", pdata->e_shnum, ret);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetSecIndexByName
+ *
+ *
+ * DATE CREATED : Mar/08/2018
+ *
+ * DESCRIPTION : Get the matching section index of the ELF image
+ *
+ * IN PARAMS :
+ * \param[in] elfData ELF image data
+ * \param[in] section name string
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : index of the matching section
+ *--------------------------------------------------------------------------------------*/
+
+uint32_t MxL_MoCA_OsalGetSecIndexByName(void *pData, char* pName)
+{
+ Elf32_Ehdr *pdata = (Elf32_Ehdr *)pData;
+ uint32_t ret = 0;
+ Elf32_Shdr *shdr = NULL;
+ uint32_t shoff = 0;
+ uint32_t shstrtab_off = 0;
+ uint32_t shnum = 0;
+ uint8_t i;
+ uint8_t *pStrData;
+
+ if (pData != NULL && pName != NULL)
+ {
+ shnum = MxL_MoCA_OsalGetNumOfSecHeaders(pData); // number of entries in the section header table
+ shoff = MxL_MoCA_OsalNtohl(pdata->e_shoff); // section header byte offset
+ shdr = (Elf32_Shdr*)(pData + shoff); // section header table base address
+ shstrtab_off = MxL_MoCA_OsalNtohl(shdr[shnum-1].sh_offset); // offset of the last section (string table)
+
+ for (i = 0; i < shnum; i++)
+ {
+ // Get the section name for each section and compare with requested name
+ pStrData = (uint8_t*)(pData + shstrtab_off + MxL_MoCA_OsalNtohl(shdr[i].sh_name));
+ DEBUG_PRINT (TRACE_CD, L_DBG, "%s\n", pStrData);
+
+ // If a match is found, return the section index. The caller can use the section index to extract the data.
+ if (strcmp(pStrData, pName) == 0)
+ {
+ DEBUG_PRINT (TRACE_CD, L_DBG, "Requested section index is %d\n", i);
+ ret = i;
+ break;
+ }
+ }
+ }
+
+ DEBUG_PRINT(TRACE_CD, L_DBG, "Requested section index = %d\n", ret);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalGetSecFileOffset
+ *
+ *
+ * DATE CREATED : Dec/14/2017
+ *
+ * DESCRIPTION : Get the byte offset from the beginning of the file to the first byte
+ * in the specified section. shdr[sectionId].sh_offset
+ *
+ * IN PARAMS :
+ * \param[in] data : ELF image data from Section header table file offset (e_shoff)
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Section file offset of the specified section.
+ *--------------------------------------------------------------------------------------*/
+
+uint32_t MxL_MoCA_OsalGetSecFileOffset(void *pData, uint32_t sectionId)
+{
+ Elf32_Shdr *pShdr = (Elf32_Shdr *)pData;
+ uint32_t offset = 0;
+
+ if (pData != NULL)
+ {
+ offset = MxL_MoCA_OsalNtohl(pShdr[sectionId].sh_offset);
+ }
+
+ DEBUG_PRINT(TRACE_CD, L_DBG, "pShdr[sectionId].sh_offset = %X\n", offset);
+
+ return offset;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalHtonl
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Host to network long
+ *
+ * IN PARAMS : n Host number
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Network long
+ *--------------------------------------------------------------------------------------*/
+
+uint32_t MxL_MoCA_OsalHtonl(uint32_t n)
+{
+ return htonl(n);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalNtohl
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Network to host long
+ *
+ * IN PARAMS : n Network long
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Host long
+ *--------------------------------------------------------------------------------------*/
+
+uint32_t MxL_MoCA_OsalNtohl(uint32_t n)
+{
+ return ntohl(n);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalNtohs
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Network to host short
+ *
+ * IN PARAMS : n Network short
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : Host short
+ *--------------------------------------------------------------------------------------*/
+
+uint16_t MxL_MoCA_OsalNtohs(uint16_t n)
+{
+ return ntohs(n);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalStrstr
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Find s2 in s1
+ *
+ * IN PARAMS : s1 The string expression to search
+ * s2 The string expression to find
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : 0 for failure, others for pointer in s1
+ *--------------------------------------------------------------------------------------*/
+
+int8_t *MxL_MoCA_OsalStrstr(int8_t *s1, int8_t *s2)
+{
+ return strstr(s1, s2);
+}
+
+#if defined(INCLUDE_PCI)
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalSetMacAddress
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Sets the MAC address in the OS
+ *
+ * IN PARAMS : devIndex - index of device
+ * mac - mac address
+ *
+ * OUT PARAMS : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalSetMacAddress(uint32_t devIndex, uint32_t *mac)
+{
+ MxL_MoCA_PCIeSetMgmtMAC(devIndex, mac);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalPcieAvailable
+ *
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Check if the device is available/ready to handle traffic
+ *
+ * IN PARAMS : devIndex : device index
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_STATUS_E code.
+ *
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_OsalPcieAvailable(int8_t devIndex)
+{
+ return MxL_MoCA_PCIeAvailable(devIndex);
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalPcieBusRead
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Read data via PCIe bus driver
+ *
+ * IN PARAMS : devIndex Device index
+ * addr Data address
+ * pData Pointer to data buffer
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : MXL_MOCA_OK for success, others for failure
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_OsalPcieBusRead(uint32_t devIndex,
+ uintptr_t addr, uint32_t *pData)
+{
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_ERR;
+
+ ret = MxL_MoCA_PCIeRead(devIndex, addr, pData);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalPcieBusWrite
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Write data to SoC memory via PCIe bus driver
+ *
+ * IN PARAMS : devIndex Device index
+ * addr Data address
+ * data Pointer to data buffer
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : MXL_MOCA_OK for success, others for failure
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_OsalPcieBusWrite(uint32_t devIndex,
+ uintptr_t addr,
+ uint32_t data)
+{
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_ERR;
+
+ ret = MxL_MoCA_PCIeWrite(devIndex, addr, data);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalDataPlaneIfRestart
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Restarts the data path
+ *
+ * IN PARAMS : devIndex Device index
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : MXL_MOCA_OK for success, others for failure
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_OsalDataPlaneIfRestart(uint32_t devIndex)
+{
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_ERR;
+
+ ret = MxL_MoCA_PCIeRestart(devIndex);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalDataPlaneResetSoC
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Resets SoC
+ *
+ * IN PARAMS : devIndex Device index
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : MXL_MOCA_OK for success, others for failure
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_OsalDataPlaneResetSoC(uint32_t devIndex)
+{
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_ERR;
+
+ ret = MxL_MoCA_PCIeGlobalResetSoC(devIndex);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_OsalDetectPCIeDevice
+ *
+ *
+ *
+ * DATE CREATED : Sep/20/2016
+ *
+ * DESCRIPTION : Begin searching for a PCI device by vendor/device id. Iterates through
+ * the list of known PCI devices. If a PCI device is found with a matching
+ * vendor and device, the reference count to the device is incremented and
+ * a pointer to its device structure is returned. Otherwise, NULL is
+ * returned. Before returning true, we will check if the driver was also
+ * loaded when the input flag is true.
+ *
+ * IN PARAMS : vendor - PCI vendor id to match, or PCI_ANY_ID to match all vendor ids
+ * device - PCI device id to match, or PCI_ANY_ID to match all device ids
+ * checkDriverLoad - checks if driver was loaded.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_OK - found , MXL_MOCA_ERR - not found
+ *
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_OsalDetectPCIeDevice(int32_t vendor, int32_t device, int8_t checkDriverLoad)
+{
+ struct pci_dev *p_pci_device;
+ MXL_MOCA_STATUS_E status = MXL_MOCA_ERR;
+
+ p_pci_device = pci_get_device(vendor, device, 0x0);
+
+ if (p_pci_device)
+ {
+ if (checkDriverLoad)
+ {
+ if (strcmp (p_pci_device->driver->name, MXL_MOCA_PCIE_DRV_NAME) == 0)
+ {
+ status = MXL_MOCA_OK;
+ }
+ }
+ else
+ {
+ status = MXL_MOCA_OK;
+ }
+ }
+ return status;
+}
+
+#endif
+
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalCreateLock
+ *
+ *
+ * DATE CREATED : Oct/06/2016
+ *
+ * DESCRIPTION : Create and initilize OSAL lock
+ *
+ * IN PARAMS : pLock --> Pointer to user created OSAL lock
+ *
+ * OUT PARAMS : pLock --> If return value is success then pLock will be a
+ * valid pointer to OSAL lock
+ *
+ * RETURN VALUE : MXL_MOCA_OK for success, others for failure
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_OsalCreateLock(MxL_OSAL_LOCK_T *pLock)
+{
+ MXL_MOCA_STATUS_E status = MXL_MOCA_ERR;
+
+ if (pLock)
+ {
+ // Initilize semaphore (binary semaphore)
+ sema_init(&pLock->mxlLock, 1);
+
+ status = MXL_MOCA_OK;
+
+ }
+ else
+ {
+ status = MXL_MOCA_INVALID_ARGUMENT_ERR;
+ }
+
+ return status;
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalDestroyLock
+ *
+ *
+ * DATE CREATED : Oct/06/2016
+ *
+ * DESCRIPTION : Destroy/De-Init OSAL lock
+ *
+ * IN PARAMS : pLock --> Pointer to user created OSAL lock
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalDestroyLock(MxL_OSAL_LOCK_T *pLock)
+{
+ // There is no explicit Destroy Semaphore in linux OS.
+ // If there is support to de-init or destroy semaphore then
+ // please update this function with OS supported API
+
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalLock
+ *
+ *
+ * DATE CREATED : Oct/06/2016
+ *
+ * DESCRIPTION : Acquire lock. If the Lock is not available, a caller thread will wait
+ * forever till the Lock is acquired and it enters sleep state.
+ *
+ * IN PARAMS : pLock --> Pointer to user created OSAL lock
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalLock(MxL_OSAL_LOCK_T *pLock)
+{
+ // down_interruptible would be a better solution since
+ // User-mode app can be interrupted by User while waiting on Lock
+
+ if (pLock)
+ {
+ // Acquire semaphore
+ down(&pLock->mxlLock);
+ }
+ else
+ {
+ // Error -- Invalid pointer Add some debug message instead of driver crash
+ }
+
+}
+
+/*----------------------------------------------------------------------------------------
+ * FUNCTION NAME : MxL_MoCA_OsalUnlock
+ *
+ *
+ * DATE CREATED : Oct/06/2016
+ *
+ * DESCRIPTION : Release previously acquired lock
+ *
+ * IN PARAMS : pLock --> Pointer to user created OSAL lock
+ *
+ * OUT PARAMS : None
+ * RETURN VALUE : None
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_OsalUnlock(MxL_OSAL_LOCK_T *pLock)
+{
+
+ if (pLock)
+ {
+ // Release semaphore
+ up(&pLock->mxlLock);
+ }
+ else
+ {
+ // Error -- Invalid pointer Add some debug message instead of driver crash
+ }
+
+}
+
diff --git a/drivers/net/phy/mxl371x/mxl_moca_osal_linux.h b/drivers/net/phy/mxl371x/mxl_moca_osal_linux.h
new file mode 100644
index 000000000000..020aba69555f
--- /dev/null
+++ b/drivers/net/phy/mxl371x/mxl_moca_osal_linux.h
@@ -0,0 +1,228 @@
+/*****************************************************************************************
+ *
+ * FILE NAME : mxl_moca_osal_linux.h
+ *
+ *
+ *
+ * DATE CREATED : Sep/30/2016
+ *
+ * LAST MODIFIED :
+ *
+ * DESCRIPTION : Header file for OSAL linux
+ *
+ *****************************************************************************************
+ * This file is licensed under GNU General Public license.
+ *
+ * This file is free software: you can redistribute and/or modify it under the
+ * terms of the GNU General Public License, Version 2, as published by the Free
+ * Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but AS-IS and
+ * WITHOUT ANY WARRANTY; without even the implied warranties of MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT. Redistribution,
+ * except as permitted by the GNU General Public License is prohibited.
+ *
+ * You should have received a copy of the GNU General Public License, Version 2
+ * along with this file; if not, see <http://www.gnu.org/licenses/>.
+ *
+ *****************************************************************************************
+ * Copyright (c) 2016 MaxLinear, Inc. All rights reserved.
+ ****************************************************************************************/
+
+#ifndef __MXL_MOCA_OSAL_LINUX_H__
+#define __MXL_MOCA_OSAL_LINUX_H__
+
+/*******************************************************************************
+ * Includes
+ ******************************************************************************/
+#include <linux/version.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)
+#include <generated/autoconf.h>
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)) && (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33))
+#include <linux/autoconf.h>
+#else
+#include <linux/config.h>
+#endif
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#ifdef INCLUDE_PCI
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#endif
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/spinlock.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/time.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>
+#include <linux/proc_fs.h>
+#include <linux/ctype.h>
+#include <linux/list.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <linux/kthread.h>
+#include <linux/mii.h>
+
+/*****************************************************************************************
+ * Macros
+ ****************************************************************************************/
+
+#define USEC_PER_MS 1000
+
+#ifndef init_MUTEX
+#define init_MUTEX(sem) sema_init(sem, 1)
+#endif
+
+#ifndef init_MUTEX_LOCKED
+#define init_MUTEX_LOCKED(sem) sema_init(sem, 0)
+#endif
+
+#ifndef DECLARE_MUTEX
+#define DECLARE_MUTEX(name) \
+ struct semaphore name = __SEMAPHORE_INITIALIZER(name, 1)
+#endif
+
+#define LOCK_MAGIC 0x4c4f434b ///< spells "LOCK"
+#define KMALLOC_MAX 65536
+
+// Host Print ForMaT string
+#define HPFMT "%s: %s"
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)
+#define UMH_WAIT_PROC 1
+#endif
+
+/*****************************************************************************************
+ * Type defines
+ ****************************************************************************************/
+
+typedef struct timer_list timer_list_t;
+typedef struct semaphore semaphore_t;
+
+/*!
+ * \brief Log strcture
+ */
+typedef struct
+{
+ int32_t log_mod; ///< used to verify the structure is initialized
+ int32_t log_lev;
+} osal_log_t ;
+
+
+/*!
+ * \brief Spinlock structure with added bells and whistles
+ *
+ * For locking purposes.
+ */
+typedef struct
+{
+ int32_t lock_magic; ///< used to verify the structure is initialized
+ unsigned long lock_irq_flags; ///< irq flags for restoring later
+ spinlock_t lock_spinlock;
+} osal_lock_t;
+
+/*!
+ * \brief Timer operations
+ *
+ * For linux this contains a struct timer_list.
+ */
+typedef struct
+{
+ struct timer_list ostimer ;
+} osal_timer_t ;
+
+/*!
+ * \brief Semaphore structure
+ *
+ * For linux this contains a struct semaphore
+ */
+typedef struct
+{
+ struct semaphore ossema ;
+} osal_sema_t ;
+
+
+typedef struct
+{
+
+ // Please do not change the variable name "mxlLock" as this
+ // name is used in MxLware.
+ // Just update "struct semaphore" to OS specific locking
+ // data structure.
+
+ struct semaphore mxlLock;
+
+} MxL_OSAL_LOCK_T ;
+
+/*!
+ * \brief Wait queue timer
+ *
+ * This structure contains everything necessary to
+ * use timers and wait queues from the !GPL side.
+ * You allocate one of these wqt_t things and then
+ * pass its pointer back on the various calls.
+ */
+
+typedef struct
+{
+ int32_t wqt_allocated ; ///< 0 = no, 1 = yes
+ struct timer_list wqt_timer;
+ wait_queue_head_t wqt_wq;
+} osal_wqt_t ;
+
+
+/*!
+ * \brief Thread operations
+ *
+ * For linux this contains kernel thread related information.
+ */
+typedef struct
+{
+ char name[20]; /*!< thread name */
+ int32_t threadID;
+ void (*func)(void *); /*!< thread internal function */
+ void *arg; /*!< argument to pass to kernel thread */
+} osal_kthread_t;
+
+/**
+ * \brief System time value
+ *
+ */
+typedef struct
+{
+ struct timeval timeVal ;
+} apposal_timeval_t;
+
+typedef struct ethtool_cmd apposal_ethtool_cmd_t;
+
+/*****************************************************************************************
+ * Global Variable Declarations
+ ****************************************************************************************/
+
+// Defined using DEVICE_ATTR(lof) and DEVICE_ATTR(link_status)
+extern struct device_attribute dev_attr_lof;
+extern struct device_attribute dev_attr_link_status;
+extern struct device_attribute dev_attr_adm_status;
+extern struct device_attribute dev_attr_bridge_ctrl_req_status;
+extern struct device_attribute dev_attr_net_proxy_req_status;
+extern struct device_attribute dev_attr_beacon_power_dist_status;
+extern struct device_attribute dev_attr_privacy_update_status;
+
+extern unsigned long volatile jiffies;
+extern int32_t major;
+
+/*****************************************************************************************
+ * Function Prototypes
+ ****************************************************************************************/
+
+#endif /* __MXL_MOCA_OSAL_LINUX_H__ */
+
diff --git a/drivers/net/phy/mxl371x/mxl_moca_osal_pcie.c b/drivers/net/phy/mxl371x/mxl_moca_osal_pcie.c
new file mode 100644
index 000000000000..1cc6fcb8b04b
--- /dev/null
+++ b/drivers/net/phy/mxl371x/mxl_moca_osal_pcie.c
@@ -0,0 +1,5677 @@
+/*****************************************************************************************
+ *
+ * FILE NAME : mxl_moca_osal_pcie.c
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * LAST MODIFIED : %Name% @ %%/%%/%%
+ *
+ * DESCRIPTION : Linux PCIe/Ethernet Driver. This file contains APIs that
+ * interface with the control path driver and to handle datapath
+ * packets to(tx) and from (rx) SoC.
+ *
+ *
+ *****************************************************************************************
+ * This file is licensed under GNU General Public license.
+ *
+ * This file is free software: you can redistribute and/or modify it under the
+ * terms of the GNU General Public License, Version 2, as published by the Free
+ * Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but AS-IS and
+ * WITHOUT ANY WARRANTY; without even the implied warranties of MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT. Redistribution,
+ * except as permitted by the GNU General Public License is prohibited.
+ *
+ * You should have received a copy of the GNU General Public License, Version 2
+ * along with this file; if not, see <http://www.gnu.org/licenses/>.
+ *
+ *****************************************************************************************
+ * Copyright (c) 2016 MaxLinear, Inc. All rights reserved.
+ ****************************************************************************************/
+
+/*----------------------------------------------------------------------------------------
+ * Includes
+ *--------------------------------------------------------------------------------------*/
+#include "mxl_moca_host_version.h"
+#include "mxl_moca_config.h"
+#include "mxl_moca_osal_pcie.h"
+
+/*----------------------------------------------------------------------------------------
+ * Command line arguments:
+ * Usage: sudo insmod mxl_moca_pcie.ko verbose=3 mac_addr="00:20:30:40:50:60"
+ * module_param - typesafe helper for a module/cmdline parameter
+ * @value: the variable to alter, and exposed parameter name.
+ * @type: the type of the parameter
+ * @perm: visibility in sysfs.
+ *--------------------------------------------------------------------------------------*/
+char *mac_addr = "00:09:8b:40:50:60";
+module_param(mac_addr, charp, 0);
+MODULE_PARM_DESC(mac_addr, "mac_addr=\"xx:xx:xx:xx:xx:xx\""); // stored in net_device
+
+int verbose = MXL_MOCA_PCIE_L_DEF;
+module_param(verbose, int, MXL_MOCA_MODULE_PARAM_PERM); // ( S_IRUSR | S_IWUSR) | S_IRGRP | S_IROTH )
+MODULE_PARM_DESC(verbose, "verbose=value where value ranges from 0-5, 0 is default");
+
+int intr_sel_type = PCIE_INTR_SEL_AUTO; // { PCIE_INTR_SEL_AUTO=0; PCIE_INTR_SEL_MSI=1; PCIE_INTR_SEL_INTA=2 }
+module_param(intr_sel_type, int, MXL_MOCA_MODULE_PARAM_PERM);
+MODULE_PARM_DESC(intr_sel_type, "0:sel AUTO(default); 1:sel MSI; 2:sel INTA.");
+
+// Set CONFIG_PCI_DEBUG=y in kernel config if you want the PCI core to produce a bunch of debug messages to the system log.
+/*----------------------------------------------------------------------------------------
+ * Global Data
+ *--------------------------------------------------------------------------------------*/
+static int gNumMocaPcieDevices = 0;
+
+// moduleInitError is used for auto-detection of PCIe/SGMII for the control path driver and ECA platforms.
+// When the PCIe device detection fails in module_init, we still return success to keep the module loaded.
+// Without this, the control path driver (mxl_moca_ctrl.ko) will not load due to static binding
+// to data path interfaces.
+#if MXLWARE_CONFIG_BOARD_ECA_9M_L3_NXP
+static uint32_t moduleInitError = 0;
+#endif
+
+static MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T* gpDevData[MXL_MOCA_PCIE_MAX_NUM_OF_PCIE_DEVICES];
+/* MXL_MOCA_PCIE_L_WARN: minimum level to include errors and warnings */
+static uint32_t MXL_MOCA_PCIE_HOST_PRINTLOG_THRESHOLD = MXL_MOCA_PCIE_L_INFO;
+
+/*----------------------------------------------------------------------------------------
+ * Supported devices, Vendor/Device table
+ *--------------------------------------------------------------------------------------*/
+static const struct pci_device_id __devinitdata gMxlMocaPciDevTbl[MXL_MOCA_PCIE_MAX_NUM_OF_PCIE_DEV_ID + 1] =
+{ // Vendor, device, subvendor, subdevice, class, mask, drv_data
+ { MXL_MOCA_PCIE_VENDOR_ID, MXL_MOCA_PCIE_DEV_ID_CARDIFF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+ { MXL_MOCA_PCIE_VENDOR_ID, MXL_MOCA_PCIE_DEV_ID_LEUCADIA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+ { }
+};
+
+MODULE_DEVICE_TABLE(pci, gMxlMocaPciDevTbl);
+
+/*----------------------------------------------------------------------------------------
+ * PCIe Device init and exit
+ *--------------------------------------------------------------------------------------*/
+static int __devinit MxL_MoCA_PCIeProbeOne (struct pci_dev *pDev, const struct pci_device_id *pEntry);
+static void __devexit MxL_MoCA_PCIeRemoveOne(struct pci_dev *pDev);
+
+/*----------------------------------------------------------------------------------------
+ * PCIe power management
+ * Set CONFIG_PCIEASPM_POWERSAVE=y and CONFIG_PM_RUNTIME=y in kernel .config
+ *--------------------------------------------------------------------------------------*/
+ int MxL_MoCA_PCIeDevPmSuspend(struct device *pDev);
+ int MxL_MoCA_PCIeDevPmResume(struct device *pDev);
+ int MxL_MoCA_PCIeDevPmIdle(struct device *pDev);
+
+/* pm-ops: assignments
+ .suspend = MxL_MoCA_PCIeDevPmSuspend
+ .resume = MxL_MoCA_PCIeDevPmResume
+ .freeze = MxL_MoCA_PCIeDevPmSuspend
+ .thaw = MxL_MoCA_PCIeDevPmResume
+ .poweroff = MxL_MoCA_PCIeDevPmSuspend
+ .restore = MxL_MoCA_PCIeDevPmResume
+ .runtime_suspend = MxL_MoCA_PCIeDevPmSuspend
+ .runtime_resume = MxL_MoCA_PCIeDevPmResume
+ .runtime_idle = MxL_MoCA_PCIeDevPmIdle
+*/
+
+// Use this ops for runtime PME
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31)
+UNIVERSAL_DEV_PM_OPS(pciDevPmOps, MxL_MoCA_PCIeDevPmSuspend, MxL_MoCA_PCIeDevPmResume, MxL_MoCA_PCIeDevPmIdle);
+//SIMPLE_DEV_PM_OPS(pciDevPmOps, MxL_MoCA_PCIeDevPmSuspend, MxL_MoCA_PCIeDevPmResume);
+#endif
+
+/*----------------------------------------------------------------------------------------
+ * PCIe Advanced Error Reporting (AER)
+ * Refer: https://lwn.net/Articles/162550/
+ * Set CONFIG_PCIEPORTBUS=y and CONFIG_PCIEAER = y in kernel .config
+ * To test errors, set CONFIG_PCIEAER_INJECT=y
+ *--------------------------------------------------------------------------------------*/
+
+/* PCI bus error detected on this device */
+pci_ers_result_t MxL_MoCA_PCIeAerErrorDetected(struct pci_dev *dev, enum pci_channel_state error);
+/* PCI Express link has been reset */
+pci_ers_result_t MxL_MoCA_PCIeAerLinkReset(struct pci_dev *dev);
+/* PCI slot has been reset */
+pci_ers_result_t MxL_MoCA_PCIeAerSlotReset(struct pci_dev *dev);
+/* Device driver may resume normal operations */
+void MxL_MoCA_PCIeAerResumeNormalOps(struct pci_dev *dev);
+
+static const struct pci_error_handlers pciErrHandlers =
+{
+ .error_detected = MxL_MoCA_PCIeAerErrorDetected,
+ .link_reset = MxL_MoCA_PCIeAerLinkReset,
+ .slot_reset = MxL_MoCA_PCIeAerSlotReset,
+ .resume = MxL_MoCA_PCIeAerResumeNormalOps,
+};
+
+/*----------------------------------------------------------------------------------------
+ * PCIe driver structure
+ *--------------------------------------------------------------------------------------*/
+
+static struct pci_driver gMxlMocaPCIeDrv =
+{
+name:
+ MXL_MOCA_PCIE_DRV_NAME,
+id_table:
+ gMxlMocaPciDevTbl,
+probe:
+ MxL_MoCA_PCIeProbeOne,
+remove:
+ __devexit_p(MxL_MoCA_PCIeRemoveOne),
+.driver =
+ {
+ .name = MXL_MOCA_PCIE_DRV_NAME,
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31)
+ .pm = &pciDevPmOps,
+#endif
+ },
+.err_handler = &pciErrHandlers
+};
+
+/*----------------------------------------------------------------------------------------
+ * Proc entry section
+ *--------------------------------------------------------------------------------------*/
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
+
+static int MxL_MoCA_PCIeReadProc(char *pUserBuf, char **ppStart, off_t offset, int count, int *pEof, void *pData);
+int MxL_MoCA_PCIeWriteProc(struct file *pFile, const char *pBuffer, unsigned long count, void *pData);
+
+#else // LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
+
+// Common buffer for all devices
+static int8_t gProcFsBuffer[MXL_MOCA_PROCFS_MAX_SIZE];
+
+static ssize_t MxL_MoCA_PCIeReadProc(struct file *pFile, char __user *pPage, size_t len, loff_t* pOffset);
+ssize_t MxL_MoCA_PCIeWriteProc(struct file *pFile, const char __user *pBuffer, size_t count, loff_t* pOffset);
+
+static const struct file_operations gMxlMocaProcFops =
+{
+ .read = MxL_MoCA_PCIeReadProc,
+ .write = MxL_MoCA_PCIeWriteProc,
+};
+
+#endif
+
+/*----------------------------------------------------------------------------------------
+ * Network device structure. Operations for the system to interact with
+ * the device.
+ *--------------------------------------------------------------------------------------*/
+
+ // net_device_ops
+int MxL_MoCA_PCIeNetDevOpen (struct net_device *pNetDev);
+int MxL_MoCA_PCIeNetDevClose(struct net_device *pNetDev);
+static int MxL_MoCA_PCIeNetDevStartXmit(struct sk_buff *skb, struct net_device *pNetDev);
+static struct net_device_stats *MxL_MoCA_PCIeNetDevGetStats(struct net_device *pNetDev);
+static void MxL_MoCA_PCIeNetDevSetRxMode(struct net_device *pNetDev);
+static void MxL_MoCA_PCIeNetDevTxTimeout(struct net_device *pNetDev);
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)
+static const struct net_device_ops gMxlMocaPcieNetDevOps =
+{
+ .ndo_open = MxL_MoCA_PCIeNetDevOpen,
+ .ndo_stop = MxL_MoCA_PCIeNetDevClose,
+ .ndo_start_xmit = MxL_MoCA_PCIeNetDevStartXmit,
+ .ndo_get_stats = MxL_MoCA_PCIeNetDevGetStats,
+ .ndo_set_rx_mode = MxL_MoCA_PCIeNetDevSetRxMode,
+ .ndo_tx_timeout = MxL_MoCA_PCIeNetDevTxTimeout,
+ .ndo_do_ioctl = 0,
+};
+#endif
+
+/*----------------------------------------------------------------------------------------
+ * Ethernet tool ops.
+ * ethtool -i en0
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeEthtoolGetDrvInfo(struct net_device *pNetDev, struct ethtool_drvinfo *drvinfo);
+unsigned int MxL_MoCA_PCIeEthtoolGetLink (struct net_device *pNetDev);
+
+// eth_tool_ops
+static const struct ethtool_ops gMxlMocaPcieEthtoolOps =
+{
+ .get_drvinfo = MxL_MoCA_PCIeEthtoolGetDrvInfo,
+ .get_link = MxL_MoCA_PCIeEthtoolGetLink,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
+ .get_sg = ethtool_op_get_sg,
+ .set_sg = ethtool_op_set_sg,
+#ifdef NETIF_F_TSO
+ .get_tso = ethtool_op_get_tso,
+#endif
+#endif
+};
+
+/*----------------------------------------------------------------------------------------
+ * - Data path functions - forward declarations
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeGetMgmtMAC(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc, unsigned int* mac);
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeAllocResources(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc);
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeAllocRxBuffers(void* pNetDev);
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeFreeRxBuffers(void* pNetDev);
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeResetTxQueue(void* pNetDev);
+static void MxL_MoCA_PCIeStartXmit(void* arg);
+static void MxL_MoCA_PCIeStopXmit(void* arg);
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeEnqueueRxBuffs(struct net_device *pNetDev);
+#if MXL_MOCA_PCIE_NAPI
+static int MxL_MoCA_PCIeNapiPoll(struct napi_struct *p_napi, int budget);
+#endif
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeStartXmitSkbs(struct net_device *pNetDev);
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeDataPathReset (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc, int8_t devIndex);
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeDataPathInit(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc, int8_t devIndex);
+
+/*----------------------------------------------------------------------------------------
+ * - ISR triggered by MSI or INTA(ASSERT)TLP from the EP
+ *--------------------------------------------------------------------------------------*/
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
+static irqreturn_t MxL_MoCA_PCIeISR(int irq, void *p_dev);
+#else
+static irqreturn_t MxL_MoCA_PCIeISR(int irq, void *p_dev, struct pt_regs *regs);
+#endif
+
+/*----------------------------------------------------------------------------------------
+ * - PCIe EP initialization functions
+ *--------------------------------------------------------------------------------------*/
+
+static int __init MxL_MoCA_PCIeModuleInit(void);
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeInitSoCIfc(unsigned int devIndex);
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeConfigInboundATU(unsigned int devIndex);
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeConfigOutboundATU(unsigned int devIndex);
+static void MxL_MoCA_PCIeSetEthToolVar(struct net_device *pNetDev);
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeFormatString
+ *
+ *
+ *
+ * DATE CREATED : 12/13/2016
+ *
+ * DESCRIPTION : Get parameters from argument buffer
+ *
+ * IN PARAMS : buf : Buffer to return created string
+ * size : max size in bytes of the buffer
+ * fmt : format specifier string
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : Length of created string
+ *
+ *--------------------------------------------------------------------------------------*/
+
+int32_t MxL_MoCA_PCIeFormatString(int8_t *buf, uint32_t size, const int8_t *fmt, ...)
+{
+ va_list args;
+ int32_t i;
+
+ va_start(args, fmt);
+ i=vsnprintf(buf,size,fmt,args);
+ va_end(args);
+
+ return i;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeDbgTrace
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Variable argument OS print
+ *
+ * For reference: Linux has these
+ *
+ * KERN_EMERG "<0>" Used for emergency messages, usually those that precede a crash.
+ * KERN_ALERT "<1>" A situation requiring immediate action.
+ * KERN_CRIT "<2>" Critical conditions, often related to serious hw/sw failures.
+ * KERN_ERR "<3>" Used to report error conditions; device drivers often use KERN_ERR
+ * to report hardware difficulties
+ * KERN_WARNING "<4>" Warnings about problematic situations that do not, in themselves,
+ * create serious problems with the system.
+ * KERN_NOTICE "<5>" Situations that are normal, but still worthy of note. A number
+ * of security-related conditions are reported at this level.
+ * KERN_INFO "<6>" Informational messages. Many drivers print information about
+ * the hardware they find at startup time at this level.
+ * KERN_DEBUG "<7>" Debugging messages.
+ *
+ * IN PARAMS : lev Severity level. See the MXL_MOCA_PCIE_L_* enum definitions listed.
+ * MXL_MOCA_PCIE_L_DEF "<0>" : defailt (same as 2)
+ * MXL_MOCA_PCIE_L_ERR "<1>" : error conditions
+ * MXL_MOCA_PCIE_L_WARN "<2>" : warning conditions
+ * MXL_MOCA_PCIE_L_INFO "<3>" : informational
+ * MXL_MOCA_PCIE_L_DBG1 "<4>" : debug messages (level1)
+ * MXL_MOCA_PCIE_L_DBG2 "<5>" : debug messages (level2)
+ * See MXL_MOCA_PCIE_HOST_OS_PRINTLOG_THRESHOLD
+ * fmt Printf format string.
+ * ... Printf format arguments (variable length)
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeDbgTrace(uint32_t lev, const int8_t *fmt, ...)
+{
+ va_list args;
+ int printLen;
+ static int8_t printkBuf[MXL_MOCA_PCIE_LOG_PRINT_BUFSIZE];
+
+ if (lev <= MXL_MOCA_PCIE_HOST_PRINTLOG_THRESHOLD)
+ {
+ /* Print argument data to buffer */
+ va_start(args, fmt);
+ printLen = vsnprintf(printkBuf, sizeof(printkBuf), fmt, args);
+ va_end(args);
+
+ if(printLen < 0)
+ {
+ printk(KERN_ERR "%s: %s", MXL_MOCA_PCIE_DRV_NAME, "vsnprintf failed!!\n");
+ return;
+ }
+
+ if (printLen < MXL_MOCA_PCIE_LOG_PRINT_BUFSIZE)
+ {
+ switch (lev)
+ {
+ case MXL_MOCA_PCIE_L_ERR:
+ printk(KERN_ERR "%s: %s", MXL_MOCA_PCIE_DRV_NAME, printkBuf);
+ break ;
+ case MXL_MOCA_PCIE_L_WARN:
+ printk(KERN_WARNING "%s: %s", MXL_MOCA_PCIE_DRV_NAME, printkBuf);
+ break ;
+ case MXL_MOCA_PCIE_L_INFO:
+ printk(KERN_INFO "%s: %s", MXL_MOCA_PCIE_DRV_NAME, printkBuf);
+ break ;
+ case MXL_MOCA_PCIE_L_DBG1:
+ printk(KERN_NOTICE "%s: %s", MXL_MOCA_PCIE_DRV_NAME, printkBuf);
+ break ;
+ case MXL_MOCA_PCIE_L_DBG2:
+ printk(KERN_DEBUG "%s: %s", MXL_MOCA_PCIE_DRV_NAME, printkBuf);
+ break ;
+ }
+ }
+ else
+ {
+ printk(KERN_ERR "%s: %s", MXL_MOCA_PCIE_DRV_NAME, "Not enough DEBUG print buffer!!\n");
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeAerErrorDetected
+ *
+ *
+ *
+ * DATE CREATED : 12/07/2016
+ *
+ * DESCRIPTION : PCI bus error detected on this device
+ *
+ * IN PARAMS : pDev : device pointer
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : pci_ers_result_t
+ *
+ *--------------------------------------------------------------------------------------*/
+
+pci_ers_result_t MxL_MoCA_PCIeAerErrorDetected(struct pci_dev *pDev, enum pci_channel_state error)
+{
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "PCIe Aer Error Detected handler called\n");
+ return PCI_ERS_RESULT_NEED_RESET;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeAerLinkReset
+ *
+ *
+ *
+ * DATE CREATED : 12/07/2016
+ *
+ * DESCRIPTION : PCI Express link has been reset
+ *
+ * IN PARAMS : pDev : device pointer
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : pci_ers_result_t
+ *
+ *--------------------------------------------------------------------------------------*/
+
+pci_ers_result_t MxL_MoCA_PCIeAerLinkReset(struct pci_dev *pDev)
+{
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "PCIe Aer Link Reset handler called\n");
+ return PCI_ERS_RESULT_RECOVERED;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeAerSlotReset
+ *
+ *
+ *
+ * DATE CREATED : 12/07/2016
+ *
+ * DESCRIPTION : PCI slot has been reset
+ *
+ * IN PARAMS : pDev : device pointer
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : pci_ers_result_t
+ *
+ *--------------------------------------------------------------------------------------*/
+
+pci_ers_result_t MxL_MoCA_PCIeAerSlotReset(struct pci_dev *pDev)
+{
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "PCIe Aer Slot Reset handler called\n");
+ return PCI_ERS_RESULT_RECOVERED;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeAerResumeNormalOps
+ *
+ *
+ *
+ * DATE CREATED : 12/07/2016
+ *
+ * DESCRIPTION : Device driver may resume normal operations
+ *
+ * IN PARAMS : pDev : device pointer
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_PCIeAerResumeNormalOps(struct pci_dev *pDev)
+{
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "PCIe Aer Resume Normal Ops handler called\n");
+ pci_cleanup_aer_uncorrect_error_status(pDev);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeDevPmSuspend
+ *
+ *
+ *
+ * DATE CREATED : 11/29/2016
+ *
+ * DESCRIPTION : PCIe power management ops
+ *
+ * IN PARAMS : pDev : device pointer
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : pci_ers_result_t
+ *
+ *--------------------------------------------------------------------------------------*/
+
+int MxL_MoCA_PCIeDevPmSuspend(struct device *pDev)
+{
+ struct pci_dev *pPCIeDev = to_pci_dev(pDev);
+ /* Other data can be accessed as follows
+ struct net_device *pNetDev = pci_get_drvdata(pPCIeDev);
+ struct MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = NETDEV_PRIV(pNetDev);
+ */
+
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Suspend\n");
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "current_state = %x\n", pPCIeDev->current_state);
+ pci_disable_device(pPCIeDev); // disable bus mastering
+ pci_set_power_state(pPCIeDev,PCI_D3hot); // device's power state
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "current_state = %x\n", pPCIeDev->current_state);
+ /* No more memory access after this point until device is brought back to D0 */
+ return 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeDevPmResume
+ *
+ *
+ *
+ * DATE CREATED : 11/29/2016
+ *
+ * DESCRIPTION : PCIe power management ops
+ *
+ * IN PARAMS : dev : device pointer
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : 0 on success
+ *
+ *--------------------------------------------------------------------------------------*/
+
+int MxL_MoCA_PCIeDevPmResume(struct device *pDev)
+{
+ struct pci_dev *pPCIeDev = to_pci_dev(pDev);
+
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Resume\n");
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "current_state = %x\n", pPCIeDev->current_state);
+ pci_set_power_state(pPCIeDev,PCI_D0);
+
+ if (pci_enable_device(pPCIeDev))
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_enable_device failed\n");
+ }
+
+ pci_pme_active (pPCIeDev, true);
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "current_state = %x\n", pPCIeDev->current_state);
+
+ return 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeDevPmIdle
+ *
+ *
+ *
+ * DATE CREATED : 11/29/2016
+ *
+ * DESCRIPTION : PCIe power management ops
+ *
+ * IN PARAMS : dev : device pointer
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : 0 on success
+ *
+ *--------------------------------------------------------------------------------------*/
+
+int MxL_MoCA_PCIeDevPmIdle(struct device *pDev)
+{
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Idle\n");
+ return 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeLockInit
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Initializes a spinlock
+ *
+ * IN PARAMS : pLock Pointer to a lock structure
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeLockInit(void *pLock)
+{
+ MXL_MOCA_PCIE_ETH_LOCK_T *lk = (MXL_MOCA_PCIE_ETH_LOCK_T *)pLock ;
+
+ if (!lk)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Error: invalid lock pointer\n");
+ }
+ else
+ {
+ spin_lock_init(&lk->lockSpinLock);
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeLockIrqSave
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Saves current interrupt context and waits for the lock.
+ * Pre-condition: The lock must be initialized.
+ *
+ * IN PARAMS : pLock Pointer to a lock structure
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeLockIrqSave(void *pLock)
+{
+ MXL_MOCA_PCIE_ETH_LOCK_T *lk = (MXL_MOCA_PCIE_ETH_LOCK_T *)pLock ;
+ spin_lock_irqsave(&lk->lockSpinLock, lk->lockIrqFlags);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeLock
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Waits for the lock.
+ * Pre-condition: The lock must be initialized.
+ *
+ * IN PARAMS : pLock Pointer to an initialized lock structure
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeLock(MXL_MOCA_PCIE_ETH_LOCK_T *pLock)
+{
+ MXL_MOCA_PCIE_ETH_LOCK_T *lk = (MXL_MOCA_PCIE_ETH_LOCK_T *)pLock ;
+
+ if (in_irq())
+ {
+ spin_lock(&lk->lockSpinLock);
+ }
+ else
+ {
+ spin_lock_irqsave(&lk->lockSpinLock, lk->lockIrqFlags);
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeUnLockIrqRestore
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Unlocks a lock and restores interrupt context
+ * Pre-condition: The lock must be initialized.
+ *
+ * IN PARAMS : pLock Pointer to an initialized lock structure
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeUnLockIrqRestore(void *pLock)
+{
+ MXL_MOCA_PCIE_ETH_LOCK_T *lk = (MXL_MOCA_PCIE_ETH_LOCK_T *)pLock ;
+ spin_unlock_irqrestore(&lk->lockSpinLock, lk->lockIrqFlags);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeUnLock
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Unlocks a lock
+ * Pre-condition: The lock must be initialized.
+ *
+ * IN PARAMS : pLock Pointer to an initialized lock structure
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeUnLock(MXL_MOCA_PCIE_ETH_LOCK_T *pLock)
+{
+ MXL_MOCA_PCIE_ETH_LOCK_T *lk = (MXL_MOCA_PCIE_ETH_LOCK_T *)pLock ;
+
+ if (in_irq())
+ {
+ spin_unlock(&lk->lockSpinLock);
+ }
+ else
+ {
+ spin_unlock_irqrestore(&lk->lockSpinLock, lk->lockIrqFlags);
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ * Low level PCIe read/write routines
+ *--------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeBusRead
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Low level PCIe read routine
+ *
+ * IN PARAMS : [addr] : address of SoC memory to read.
+ *
+ * OUT PARAMS : [*data] : pointer to read data.
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeBusRead(uintptr_t addr, uint32_t *pData)
+{
+ uint32_t rv ;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
+ rv = readl( (const volatile void *)addr );
+#else
+ rv = readl( addr ) ;
+#endif
+ *pData = rv;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeBusWrite
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Low level PCIe write routine
+ *
+ * IN PARAMS : [addr] : address of SoC memory.
+ * : [data] : data to write.
+ *
+ * OUT PARAMS : None.
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeBusWrite(uintptr_t addr, uint32_t data)
+{
+// MXL_MOCA_DBG2P3("%s: address = %x, data = %x\n", __FUNCTION__, addr, data);
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
+ writel( data, (volatile void *)addr );
+#else
+ writel( data, addr );
+#endif
+}
+
+/*---------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeCheckAddr
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Checks for validity of the memory address
+ *
+ * IN PARAMS : [addr] : address to validate
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : 0 if invalid address and 1 if valid address
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static bool MxL_MoCA_PCIeCheckAddr(uint32_t addr)
+{
+ if (addr < MXL_MOCA_PCIE_HIF_TC_DMEM_BASE)
+ {
+ MXL_MOCA_DBG2P2("%s: Invalid address %#010x (low)!!!\n", __FUNCTION__, addr);
+ return false;
+ }
+
+ if (addr > MXL_MOCA_PCIE_CCPU_CORE_BASE_MAX)
+ {
+ MXL_MOCA_DBG2P2("%s: Invalid address %#010x (high)!!!\n", __FUNCTION__, addr);
+ return false;
+ }
+ return true;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeApplyInboundBaseAddr
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Translates the addresses for datapath read/write routines. Host to SoC
+ * access
+ *
+ * IN PARAMS : [*pDdc] : driver data context
+ * : [addr] : data to apply the right mask.
+ *
+ * OUT PARAMS : None.
+ *
+ * RETURN VALUE : translated address
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void* MxL_MoCA_PCIeApplyInboundBaseAddr(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T* pDdc, uint32_t addr)
+{
+ uintptr_t base = (uintptr_t)pDdc->baseIoRemap1; // BAR1
+ void *pDst = 0;
+
+ uint32_t addrBase = (addr & MXL_MOCA_PCIE_CCPU_CORE_BASE);
+ uint32_t addrMask = (addr & MXL_MOCA_PCIE_BAR1_MASK);
+
+ if (addrBase != MXL_MOCA_PCIE_CCPU_CORE_BASE) // Did not match BAR1
+ {
+ // MXL_MOCA_DBG2P0( "did not match bar1\n");
+
+ base = (uintptr_t)pDdc->baseIoRemap0; // BAR0
+
+// MXL_MOCA_DBG2P1("base = 0x%08x\n", base);
+
+ addrBase = (addr & MXL_MOCA_PCIE_HIF_TC_DMEM_BASE);
+ addrMask = (addr & MXL_MOCA_PCIE_BAR0_MASK);
+
+ if (addrBase != MXL_MOCA_PCIE_HIF_TC_DMEM_BASE)
+ {
+ MXL_MOCA_DBG2P4("%s: address invalid: addr=0x%08x (CCPU BASE: 0x%08x, HIFTC BASE: 0x%08x)\n",
+ __FUNCTION__, addr, MXL_MOCA_PCIE_CCPU_CORE_BASE, MXL_MOCA_PCIE_HIF_TC_DMEM_BASE);
+ return 0;
+ }
+ else
+ {
+ // MXL_MOCA_DBG2P1("%s: Matches BAR0\n", __FUNCTION__);
+ }
+ }
+ else
+ {
+ // MXL_MOCA_DBG2P1("%s: Matches BAR1\n", __FUNCTION__);
+ }
+ if (base == 0)
+ {
+ MXL_MOCA_DBG2P1("%s: base is 0 (abort)\n", __FUNCTION__);
+ return 0;
+ }
+ pDst = (void*)(( addr & addrMask ) + base);
+
+// MXL_MOCA_DBG2P5("addr = 0x%x, base = 0x%x, addrBase = 0x%x, addrMask = 0x%x, pDst = 0x%x\n",
+// addr, base, addrBase, addrMask, pDst);
+
+ return(pDst);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeRead
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Reads from memory in the SoC hardware
+ *
+ * IN PARAMS : [devIndex] : device index
+ * : [addr] : The memory address to be read.
+ *
+ * OUT PARAMS : [*va]] : Pointer to return the data.
+ *
+ * RETURN VALUE : MXL_MOCA_STATUS_E
+ *
+ *--------------------------------------------------------------------------------------*/
+
+ // interface
+MXL_MOCA_STATUS_E MxL_MoCA_PCIeRead(int8_t devIndex, uintptr_t addr, uint32_t *val) //<<<
+{
+ bool goodAddr;
+ uint32_t *src;
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T*)gpDevData[devIndex];
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+
+ goodAddr = MxL_MoCA_PCIeCheckAddr(addr);
+
+ if (goodAddr == true)
+ {
+ src = MxL_MoCA_PCIeApplyInboundBaseAddr(pDdc, addr);
+ if (src != 0)
+ {
+ MxL_MoCA_PCIeLock(&pDdc->rwLock);
+ MxL_MoCA_PCIeBusRead((uintptr_t)src, val);
+ MxL_MoCA_PCIeUnLock(&pDdc->rwLock);
+ }
+ else
+ {
+ ret = MXL_MOCA_ERR;
+ }
+// MxL_MoCA_PCIeDbgTrace (MXL_MOCA_PCIE_L_INFO, "%s: addr = 0x%08x, val = 0x%08x\n", __FUNCTION__, addr, *val);
+ }
+ else
+ {
+ ret = MXL_MOCA_ERR;
+ }
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeWrite
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Reads from memory in the SoC hardware
+ *
+ * IN PARAMS : [devIndex] : device index
+ * : [addr] : The memory address to write
+ * : [va]] : data to write.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_STATUS_E
+ *
+ *--------------------------------------------------------------------------------------*/
+
+ // interface
+MXL_MOCA_STATUS_E MxL_MoCA_PCIeWrite(int8_t devIndex, uintptr_t addr, uint32_t val) //<<<
+{
+ uint32_t goodAddr;
+ uint32_t *pDst;
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *)gpDevData[devIndex];
+
+ goodAddr = MxL_MoCA_PCIeCheckAddr(addr);
+// MXL_MOCA_DBG2P2 ("%s: goodAddr = 0x%x\n", __FUNCTION__, goodAddr);
+
+ if (goodAddr)
+ {
+ pDst = MxL_MoCA_PCIeApplyInboundBaseAddr(pDdc, addr);
+ if (pDst != 0)
+ {
+ MxL_MoCA_PCIeLock(&pDdc->rwLock);
+ MxL_MoCA_PCIeBusWrite((uintptr_t)pDst, val);
+ MxL_MoCA_PCIeUnLock(&pDdc->rwLock);
+ }
+ else
+ {
+ ret = MXL_MOCA_ERR;
+ }
+ // MXL_MOCA_DBG2P3 ("%s: addr = 0x%08x, val = 0x%08x\n", __FUNCTION__, addr, val);
+ }
+ else
+ {
+ ret = MXL_MOCA_ERR;
+ }
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeConfigOutboundATU
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Program the upstream (outbound : to RC) iATU
+ *
+ * IN PARAMS : [devIndex] : device index
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_STATUS_E code
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeConfigOutboundATU(unsigned int devIndex)
+{
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *)gpDevData[devIndex];
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+
+ // Program the upstream (outbound : to RC) iATU
+ // There will be MXL_MOCA_PCIE_NUM_OUTBOUND_ATU_REGIONS
+
+ // REGION0 --
+ // 08204900 : iATU Index Register. REGION_DIR 0: outbound; 1 inbound
+ do
+ {
+ ret = MxL_MoCA_PCIeWrite(devIndex, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_INDEX_REG), 0x00000000); // 0x900: set outbound region 0 as the current region
+ if (MXL_MOCA_ERR == ret)
+ {
+ break;
+ }
+
+ // 0820490c : iATU Region Lower Base Address Register
+ ret = MxL_MoCA_PCIeWrite(devIndex, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_REG), MXL_MOCA_PCIE_OUTB_ATU_REGION0_BASE);
+ if (MXL_MOCA_ERR == ret)
+ {
+ break;
+ }
+
+ // 08204914 : iATU Region Limit Address Register (inbound)
+ ret = MxL_MoCA_PCIeWrite(devIndex, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_REGION_LIMIT_ADDR_REG), MXL_MOCA_PCIE_REGION0_MASK);
+ if (MXL_MOCA_ERR == ret)
+ {
+ break;
+ }
+
+ // 08204918 : iATU Region Lower Target Address Register. Correct target address register need to be specified by host
+ ret = MxL_MoCA_PCIeWrite(devIndex, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_REG), pDdc->target0OutATUAddrMask);
+ if (MXL_MOCA_ERR == ret)
+ {
+ break;
+ }
+
+ // 08204908 : iATU Region Control 2 Register - enable for addr match
+ ret = MxL_MoCA_PCIeWrite(devIndex, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_2_REG), 0x80000000);// REGION_EN = 1
+ if (MXL_MOCA_ERR == ret)
+ {
+ break;
+ }
+
+ // REGION1 --
+ // 08204900 : iATU Index Register
+ ret = MxL_MoCA_PCIeWrite(devIndex, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_INDEX_REG), 0x00000001); // set outbound region 1 as the current region
+ if (MXL_MOCA_ERR == ret)
+ {
+ break;
+ }
+
+ // 0820490c : iATU Region Lower Base Address Register
+ ret = MxL_MoCA_PCIeWrite(devIndex, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_REG), MXL_MOCA_PCIE_OUTB_ATU_REGION1_BASE);
+ if (MXL_MOCA_ERR == ret)
+ {
+ break;
+ }
+
+ // 08204914 : iATU Region Limit Address Register
+ ret = MxL_MoCA_PCIeWrite(devIndex, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_REGION_LIMIT_ADDR_REG), MXL_MOCA_PCIE_REGION1_MASK);
+ if (MXL_MOCA_ERR == ret)
+ {
+ break;
+ }
+
+ // 08204918 : iATU Region Lower Target Address Register. Correct target address register need to be specified by host
+ ret = MxL_MoCA_PCIeWrite(devIndex, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_REG), pDdc->target1OutATUAddrMask);
+ if (MXL_MOCA_ERR == ret)
+ {
+ break;
+ }
+
+ // 08204908 : iATU Region Control 2 Register - enable for addr match
+ ret = MxL_MoCA_PCIeWrite(devIndex, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_2_REG), 0x80000000); // REGION_EN = 1
+ if (MXL_MOCA_ERR == ret)
+ {
+ break;
+ }
+ } while (0);
+
+ if (MXL_MOCA_ERR == ret)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "PCIe Config Outbound ATU: Read/Write error!\n");
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Configuring outbound (SoC to Host mem access) iATUs...OK\n");
+ }
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeConfigInboundATU
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Program the downstream (inbound : from RC) iATU
+ *
+ * IN PARAMS : [devIndex] : device index
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_STATUS_E code
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeConfigInboundATU(unsigned int devIndex)
+{
+ // Program the downstream (inbound : from RC) iATU
+ // For downstream iATU: port logic registers start at base address 0x0820_4700 (PCI EP Core datasheet has offsets).
+ // MXL_MOCA_PCIE_EP_IATU_BASE 0x08204000 + (0x700 + 0x200)
+ // This has to be CfgWr since we cannot do Memory writes until the inbound ATU is setup.
+ // BAR0 --
+ uint32_t val = 0;
+ uint32_t ret = 0;
+ MXL_MOCA_STATUS_E err = MXL_MOCA_OK;
+
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDevData = (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *)gpDevData[devIndex];
+
+ do
+ {
+ // 08204900 : iATU Index Register. REGION_DIR 0: outbound; 1 inbound
+ if ((ret = pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_INDEX_OFFSET, 0x80000000)) != 0) // set inbound region 0 as the current region
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_write_config_dword failed: 0x%08x\n", MXL_MOCA_PCIE_EP_IATU_INDEX_OFFSET);
+ err = MXL_MOCA_ERR;
+ break;
+ }
+ if ((ret = pci_read_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_INDEX_OFFSET, &val)) == 0)
+ {
+ MXL_MOCA_DBG1P1( "BAR0:::::PCIE_EP_IATU_INDEX_OFFSET: 0x%08x\n", val);
+ }
+
+ // 08204904 : iATU Region Control 1 Register (inbound)
+ if ((ret = pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_1_OFFSET, 0)) != 0) // to define the type of the region to be MEM.
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_write_config_dword failed: 0x%08x\n", MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_1_OFFSET);
+ err = MXL_MOCA_ERR;
+ break;
+ }
+ if ((ret = pci_read_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_1_OFFSET, &val)) == 0)
+ {
+ MXL_MOCA_DBG1P1( "PCIE_EP_IATU_REGION_CTRL_1_OFFSET: 0x%08x\n", val);
+ }
+
+ // 0820490c : iATU Region Lower Base Address Register
+ if ((ret = pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_OFFSET, pDevData->baseIoAddr0)) != 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_write_config_dword failed: 0x%08x\n", MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_OFFSET);
+ err = MXL_MOCA_ERR;
+ break;
+ }
+ if ((ret = pci_read_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_OFFSET, &val)) == 0)
+ {
+ MXL_MOCA_DBG1P1( "PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_OFFSET: 0x%08x\n", val);
+ }
+
+ // 08204914 : iATU Region Limit Address Register (inbound)
+ if ((ret = pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_LIMIT_ADDR_OFFSET, (pDevData->baseIoAddr0 | MXL_MOCA_PCIE_BAR0_MASK))) != 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_write_config_dword failed: 0x%08x\n", MXL_MOCA_PCIE_EP_IATU_REGION_LIMIT_ADDR_OFFSET);
+ err = MXL_MOCA_ERR;
+ break;
+ }
+ if ((ret = pci_read_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_LIMIT_ADDR_OFFSET, &val)) == 0)
+ {
+ MXL_MOCA_DBG1P1( "PCIE_EP_IATU_REGION_LIMIT_ADDR_OFFSET: 0x%08x\n", val);
+ }
+
+ // 08204918 : iATU Region Lower Target Address Register
+ if ((ret = pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_OFFSET, MXL_MOCA_PCIE_HIF_TC_DMEM_BASE)) != 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_write_config_dword failed: 0x%08x\n", MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_OFFSET);
+ err = MXL_MOCA_ERR;
+ break;
+ }
+ if ((ret = pci_read_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_OFFSET, &val)) == 0)
+ {
+ MXL_MOCA_DBG1P1( "PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_OFFSET: 0x%08x\n", val);
+ }
+
+ // 08204908 : iATU Region Control 2 Register - enable for BAR match
+ if ((ret = pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_2_OFFSET, 0xC0000000)) != 0) // REGION_EN = 1, BAR0
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_write_config_dword failed: 0x%08x\n", MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_2_OFFSET);
+ err = MXL_MOCA_ERR;
+ break;
+ }
+ if ((ret = pci_read_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_2_OFFSET, &val)) == 0)
+ {
+ MXL_MOCA_DBG1P1( "PCIE_EP_IATU_REGION_CTRL_2_OFFSET: 0x%08x\n", val);
+ }
+
+ // BAR1 --
+ // 08204900 : iATU Index Register
+ if ((ret = pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_INDEX_OFFSET, 0x80000001)) != 0) // set inbound region 1 as the current region. 1 for second region
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_write_config_dword failed: 0x%08x\n", MXL_MOCA_PCIE_EP_IATU_INDEX_OFFSET);
+ err = MXL_MOCA_ERR;
+ break;
+ }
+ if ((ret = pci_read_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_INDEX_OFFSET, &val)) == 0)
+ {
+ MXL_MOCA_DBG1P1( "BAR1:::::PCIE_EP_IATU_INDEX_OFFSET: 0x%08x\n", val);
+ }
+
+ // 08204904 : iATU Region Control 1 Register
+ if ((ret = pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_1_OFFSET, 0)) != 0) // to define the type of the region to be MEM.
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_write_config_dword failed: 0x%08x\n", MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_1_OFFSET);
+ err = MXL_MOCA_ERR;
+ break;
+ }
+ if ((ret = pci_read_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_1_OFFSET, &val)) == 0)
+ {
+ MXL_MOCA_DBG1P1( "PCIE_EP_IATU_REGION_CTRL_1_OFFSET: 0x%08x\n", val);
+ }
+
+ // 0820490c : iATU Region Lower Base Address Register
+ if ((ret = pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_OFFSET, pDevData->baseIoAddr1)) != 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_write_config_dword failed: 0x%08x\n", MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_OFFSET);
+ err = MXL_MOCA_ERR;
+ break;
+ }
+ if ((ret = pci_read_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_OFFSET, &val)) == 0)
+ {
+ MXL_MOCA_DBG1P1( "PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_OFFSET: 0x%08x\n", val);
+ }
+
+ // 08204914 : iATU Region Limit Address Register
+ if ((ret = pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_LIMIT_ADDR_OFFSET, (pDevData->baseIoAddr1 | MXL_MOCA_PCIE_BAR1_MASK))) != 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_write_config_dword failed: 0x%08x\n", MXL_MOCA_PCIE_EP_IATU_REGION_LIMIT_ADDR_OFFSET);
+ err = MXL_MOCA_ERR;
+ break;
+ }
+ if ((ret = pci_read_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_LIMIT_ADDR_OFFSET, &val)) == 0)
+ {
+ MXL_MOCA_DBG1P1( "PCIE_EP_IATU_REGION_LIMIT_ADDR_OFFSET: 0x%08x\n", val);
+ }
+
+ // 08204918 : iATU Region Lower Target Address Register
+ if ((ret = pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_OFFSET, MXL_MOCA_PCIE_CCPU_CORE_BASE)) != 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_write_config_dword failed: 0x%08x\n", MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_OFFSET);
+ err = MXL_MOCA_ERR;
+ break;
+ }
+ if ((ret = pci_read_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_OFFSET, &val)) == 0)
+ {
+ MXL_MOCA_DBG1P1( "PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_OFFSET: 0x%08x\n", val);
+ }
+
+ // 08204908 : iATU Region Control 2 Register - enable for BAR match
+ if ((ret = pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_2_OFFSET, 0xC0000100)) != 0) // REGION_EN = 1, BAR1
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_write_config_dword failed: 0x%08x\n", MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_2_OFFSET);
+ err = MXL_MOCA_ERR;
+ break;
+ }
+ if ((ret = pci_read_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_2_OFFSET, &val)) == 0)
+ {
+ MXL_MOCA_DBG1P1( "PCIE_EP_IATU_REGION_CTRL_2_OFFSET: 0x%08x\n", val);
+ }
+ } while (0);
+
+ if (ret != 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "%s failed!!!\n", __FUNCTION__);
+ err = MXL_MOCA_ERR;
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Configuring inbound (Host to SoC mem access) iATUs...OK\n");
+ }
+
+ return err;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeGlobalResetSoC
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Generates a reset pulse to reset the chip via config space, link will
+ * not go down.
+ *
+ * IN PARAMS : [devIndex] : device index
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_OK or MXL_MOCA_ERR
+ *
+ *--------------------------------------------------------------------------------------*/
+
+ // interface
+MXL_MOCA_STATUS_E MxL_MoCA_PCIeGlobalResetSoC(int8_t devIndex)
+{
+ MXL_MOCA_STATUS_E status = MXL_MOCA_OK;
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDevData = (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *)gpDevData[devIndex];
+
+ MXL_MOCA_DBG2P1("%s...\n", __FUNCTION__);
+
+ do
+ {
+ if (pDevData->deviceId == MXL_MOCA_PCIE_DEVICE_ID_CARDIFF)
+ {
+ if (pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_CARDIFF_GLOBAL_RESETN,
+ MXL_MOCA_PCIE_EP_CARDIFF_GLOBAL_RESET_NO_LINK_DN) != 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "%s failed: 0x%08x\n",
+ __FUNCTION__, MXL_MOCA_PCIE_EP_CARDIFF_GLOBAL_RESETN);
+ status = MXL_MOCA_ERR;
+ break;
+ }
+ if (pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_CARDIFF_GLOBAL_RESETN,
+ MXL_MOCA_PCIE_EP_CARDIFF_GLOBAL_RESET_NO_LINK_DN_CLEAR) != 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "%s failed: 0x%08x\n",
+ __FUNCTION__, MXL_MOCA_PCIE_EP_CARDIFF_GLOBAL_RESETN);
+ status = MXL_MOCA_ERR;
+ break;
+ }
+ }
+ else if (pDevData->deviceId == MXL_MOCA_PCIE_DEVICE_ID_LEUCADIA)
+ {
+ if (pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_LEUCADIA_GLOBAL_RESETN,
+ MXL_MOCA_PCIE_EP_LEUCADIA_GLOBAL_RESET_NO_LINK_DN) != 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "%s failed: 0x%08x\n",
+ __FUNCTION__, MXL_MOCA_PCIE_EP_LEUCADIA_GLOBAL_RESETN);
+ status = MXL_MOCA_ERR;
+ break;
+ }
+ if (pci_write_config_dword(pDevData->pPCIeDev, MXL_MOCA_PCIE_EP_LEUCADIA_GLOBAL_RESETN,
+ MXL_MOCA_PCIE_EP_LEUCADIA_GLOBAL_RESET_NO_LINK_DN_CLEAR) != 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "%s failed: 0x%08x\n",
+ __FUNCTION__, MXL_MOCA_PCIE_EP_LEUCADIA_GLOBAL_RESETN);
+ status = MXL_MOCA_ERR;
+ break;
+ }
+ }
+ }while (0);
+
+ return status;
+}
+
+/*----------------------------------------------------------------------------------------
+ * utility functions
+ *--------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeAllocDmaMem
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Generates a reset pulse to reset the chip via config space, link will
+ * not go down.
+ *
+ * IN PARAMS : [pDdc] : Pointer to data context
+ * : [size] : Requested block size
+ * : [ppMemPa] : Pointer to place to return the Physical memory address.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : Virtual memory address (and Phys address), or NULL on failure
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void* MxL_MoCA_PCIeAllocDmaMem(void *pDdc, size_t size, void **ppMemPa)
+{
+ struct pci_dev *pDev= ((MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *)pDdc)->pPCIeDev;
+ dma_addr_t dma_buf;
+ void *pMemVa;
+
+ pMemVa = pci_alloc_consistent(pDev, size, &dma_buf);
+ *ppMemPa = (void *)(uintptr_t)dma_buf;
+
+ return (pMemVa);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeFreeDmaMem
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Free DMA-addressable memory.
+ *
+ * IN PARAMS : [pDdc] : Pointer to data context
+ * : [size] : Requested block size
+ * : [pMemVa] : Physical memory address returned by MxL_MoCA_PCIeAllocDmaMem()
+ * : [pMemPa] : Virtual memory address returned by MxL_MoCA_PCIeAllocDmaMem()
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : Virtual memory address (and Phys address), or NULL on failure
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeFreeDmaMem(void *pDdc, size_t size, void *pMemVa, void *pMemPa)
+{
+ struct pci_dev *pDev = ((MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *)pDdc)->pPCIeDev;
+
+ pci_free_consistent(pDev, size, pMemVa, (dma_addr_t)(uintptr_t)pMemPa);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeKMemAlloc
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Allocates memory. Function allocates size bytes of memory. If the
+ * allocation succeeds, a pointer to the block of memory is returned,
+ * otherwise a null pointer is returned.
+ *
+ * IN PARAMS : [size] : Size to allocate
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : Pointer to allocated block if successful, Null pointer otherwise
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void* MxL_MoCA_PCIeKMemAlloc(int size)
+{
+ void *pMem;
+
+ if (size < MXL_MOCA_PCIE_KMALLOC_MAX)
+ {
+ pMem = kmalloc(size, GFP_KERNEL /* | __GFP_DMA */);
+ }
+ else
+ {
+ pMem = (void *)__get_free_pages(GFP_KERNEL, get_order(size));
+ }
+ return (pMem);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeKMemFree
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Free memory.
+ *
+ * IN PARAMS : [pMem] : Allocation pointer from get free pages.
+ * : [size] : Requested block size.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeKMemFree(void *pMem, int size)
+{
+ if (size < MXL_MOCA_PCIE_KMALLOC_MAX)
+ kfree(pMem);
+ else
+ free_pages((unsigned long)pMem, get_order(size));
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeFreeResources
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Free all allocated resources.
+ *
+ * IN PARAMS : [pDdc] : Pointer to data context
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_OK or MXL_MOCA_ERR
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeFreeResources(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc)
+{
+ uint32_t sz;
+ MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *pDataPath;
+
+ pDataPath = (MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *)pDdc->pDpCtx;
+
+ if (!pDataPath)
+ {
+ MXL_MOCA_DBG1P1("%s NULL pointer\n", __FUNCTION__);
+ return MXL_MOCA_ERR;
+ }
+/// MXL_MOCA_DBG2P1("%s ...\n", __FUNCTION__);
+ if (pDataPath->txQueuePair.pDescQueue)
+ {
+ sz = MXL_MOCA_PCIE_TX_PTR_QUEUE_SIZE * sizeof(MXL_MOCA_PCIE_QUEUE_DESCR_T),
+ MxL_MoCA_PCIeFreeDmaMem(pDdc, sz,
+ pDataPath->txQueuePair.pDescQueue,
+ pDataPath->txQueuePair.pDescQueuePa);
+ }
+
+ if (pDataPath->rxQueuePair.pDescQueue)
+ {
+ sz = MXL_MOCA_PCIE_RX_PTR_QUEUE_SIZE * sizeof(MXL_MOCA_PCIE_QUEUE_DESCR_T),
+ MxL_MoCA_PCIeFreeDmaMem(pDdc, sz,
+ pDataPath->rxQueuePair.pDescQueue,
+ pDataPath->rxQueuePair.pDescQueuePa);
+ }
+
+ if (pDataPath->txQueuePair.pPktQueue)
+ {
+ sz = MXL_MOCA_PCIE_TX_PTR_QUEUE_SIZE * sizeof(MXL_MOCA_PCIE_QUEUE_PKT_T),
+ MxL_MoCA_PCIeFreeDmaMem(pDdc, sz,
+ pDataPath->txQueuePair.pPktQueue,
+ pDataPath->txQueuePair.pPktQueuePa);
+ }
+
+ if (pDataPath->rxQueuePair.pPktQueue)
+ {
+ sz = MXL_MOCA_PCIE_RX_PTR_QUEUE_SIZE * sizeof(MXL_MOCA_PCIE_QUEUE_PKT_T),
+ MxL_MoCA_PCIeFreeDmaMem(pDdc, sz,
+ pDataPath->rxQueuePair.pPktQueue,
+ pDataPath->rxQueuePair.pPktQueuePa);
+ }
+
+ MxL_MoCA_PCIeKMemFree(pDataPath, sizeof(MXL_MOCA_PCIE_DATAPATH_CONTEXT_T));
+ pDdc->pDpCtx = NULL;
+
+ return MXL_MOCA_OK;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeOpen
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Brings up the Ethernet interface.
+ *
+ * IN PARAMS : [kdev] : context structure with device pointer
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_PCIeOpen(void *kdev)
+{
+ struct net_device *pNetDev = (struct net_device *)kdev;
+
+ if ((pNetDev->flags & IFF_UP) == IFF_UP)
+ {
+ MxL_MoCA_PCIeNetDevOpen(pNetDev);
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeClose
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Shuts down the Ethernet interface.
+ *
+ * IN PARAMS : [*kdev] : context structure with device pointer
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_PCIeClose(void *kdev)
+{
+ struct net_device *pNetDev = (struct net_device *)kdev;
+
+ if ((pNetDev->flags & IFF_UP) == IFF_UP)
+ {
+ MxL_MoCA_PCIeNetDevClose(pNetDev);
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeDataPathInit
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Initializes the DP
+ *
+ * IN PARAMS : [*pDdc] : driver data context
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_OK for success, or MXL_MOCA_ERR on failure
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeDataPathInit(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc, int8_t devIndex)
+{
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+
+ MXL_MOCA_DBG2P1("%s: -- Data path init --\n", __FUNCTION__);
+
+ // Allocate and initialize host tx/rx lists and descriptors
+ ret = MxL_MoCA_PCIeAllocResources(pDdc); // memory alloc/init
+
+ if (MXL_MOCA_OK != ret)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "%s: Alloc resources failed!\n", __FUNCTION__);
+ }
+ else
+ {
+ // init the rxList and rxFreeList before MxL_MoCA_PCIeNetDevOpen is called
+ ret = MxL_MoCA_PCIeDataPathReset(pDdc, devIndex);
+ if (MXL_MOCA_OK != ret)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "%s: Data Path Reset failed!\n", __FUNCTION__);
+ }
+ MXL_MOCA_DBG2P2("NetDev, 0x%x, DevCtx: 0x%x\n", pDdc->pNetDev, pDdc);
+ MXL_MOCA_DBG2P1("line(%d): Datapath init done! \n", __LINE__);
+ }
+
+ return ret;
+}
+
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeTerminate
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Terminates the DP
+ *
+ * IN PARAMS : [pddp] : Pointer to driver data plane context.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_PCIeTerminate(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pddp)
+{
+ if (pddp == NULL)
+ {
+ MXL_MOCA_DBG1P0( "pddp is NULL\n");
+ return;
+ }
+ // Initialize hardware registers to reset device
+ // perform graceful shutdown if possible
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "MoCA PCIe device stopping\n");
+ MxL_MoCA_PCIeClose(pddp->pNetDev);
+ MXL_MOCA_DBG2P0( "MxL_MoCA_PCIeClose done\n");
+
+ if (MxL_MoCA_PCIeFreeResources(pddp) == MXL_MOCA_ERR)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "MxL_MoCA_PCIeTerminate failed\n");
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeDataPathClear
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Resets the DP (clears counters, if any; and statistics)
+ *
+ * IN PARAMS : [pddp] : Pointer to driver data plane context.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_PCIeDataPathClear(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc)
+{
+ memset(&pDdc->ethStats, 0, sizeof(MXL_MOCA_PCIE_ETH_STATS_T));
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeDataPathControl
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Controls the operation of the data path (place holder)
+ *
+ * IN PARAMS : [pddp] : Pointer to driver data plane context.
+ * : [cmd] : MxL MoCA IO command.
+ * : [val] : IO block pointer.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_OK or MXL_MOCA_ERR
+ *
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_PCIeDataPathControl(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc, unsigned int cmd, uintptr_t val)
+{
+ return (MXL_MOCA_OK);
+}
+
+#if MXL_MOCA_PCIE_PWR_MGMT
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIePowerManagementInit
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Function to init power management capabilities and control
+ *
+ * IN PARAMS : [devIndex] : device index
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : false or true
+ *
+ *--------------------------------------------------------------------------------------*/
+
+MXL_MOCA_STATUS_E MxL_MoCA_PCIePowerManagementInit(uint8_t devIndex)
+{
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T*)gpDevData[devIndex];
+
+ struct pci_dev *pDev = pDdc->pPCIeDev;
+ uint32_t pos, pos1;
+ uint16_t capability, control;
+ uint32_t status, lnkCap, lnkCtl, lnkStat, pmCap, pmCtrl;
+ uint16_t lnkCtrlWr;
+ bool bStatus;
+
+ // Power management capabilities
+ if ((pos = pci_find_capability(pDev, PCI_CAP_ID_EXP)) != 0)
+ {
+ pci_read_config_word(pDev, pos + PCI_EXP_DEVCAP, &capability);
+ pci_read_config_word(pDev, pos + PCI_EXP_DEVCTL, &control);
+
+ pci_read_config_dword(pDev, pos + PCI_EXP_DEVSTA, &status);
+ pci_read_config_dword(pDev, pos + PCI_EXP_LNKCAP, &lnkCap);
+ pci_read_config_dword(pDev, pos + PCI_EXP_LNKCTL, &lnkCtl);
+ pci_read_config_dword(pDev, pos + PCI_EXP_LNKSTA, &lnkStat);
+
+ if ((pos1 = pci_find_capability(pDev, PCI_CAP_ID_PM)) != 0)
+ {
+ pci_read_config_dword(pDev, pos1 + PCI_PM_PMC, &pmCap);
+ pci_read_config_dword(pDev, pos1 + PCI_PM_CTRL, &pmCtrl);
+ }
+ /*
+ PCIE_LINK_STATE_L0S 1
+ PCIE_LINK_STATE_L1 2
+ */
+ // Link Cap: ASPM (Active State Power Management) states
+ pDdc->lnkCapAspmSupport = (lnkCap & PCI_EXP_LNKCAP_ASPMS) >> 10;
+ MXL_MOCA_DBG1P2("LNKCAP:ASPM Support: L0s(%d); L1(%d)\n", \
+ (pDdc->lnkCapAspmSupport & PCIE_LINK_STATE_L0S) == PCIE_LINK_STATE_L0S,\
+ (pDdc->lnkCapAspmSupport & PCIE_LINK_STATE_L1) == PCIE_LINK_STATE_L1);
+
+ // Dev Cap: PME (Power Management Events) supported
+ pDdc->lnkCapPme = 0;
+
+ bStatus = pci_pme_capable(pDev, PCI_D0);
+ pDdc->lnkCapPme |= (bStatus == true) ? 1:0;
+
+ bStatus = pci_pme_capable(pDev, PCI_D1);
+ pDdc->lnkCapPme |= (bStatus == true) ? 1<<1:0;
+
+ bStatus = pci_pme_capable(pDev, PCI_D2);
+ pDdc->lnkCapPme |= (bStatus == true) ? 1<<2:0;
+
+ bStatus = pci_pme_capable(pDev, PCI_D3hot);
+ pDdc->lnkCapPme |= (bStatus == true) ? 1<<3:0;
+
+ bStatus = pci_pme_capable(pDev, PCI_D3cold);
+ pDdc->lnkCapPme |= (bStatus == true) ? 1<<4:0;
+
+ MXL_MOCA_DBG1P1("PME Capability(D3c,D3h,D2,D1,D0 = 0x%x)\n", pDdc->lnkCapPme);
+
+ /* Link Ctrl: ASPM (enable if needed)
+ PCI_EXP_LNKCTL_ASPMC 0x0003 // ASPM Control
+ - PCI_EXP_LNKCTL_ASPM_L0S 0x0001 // L0s Enable
+ - PCI_EXP_LNKCTL_ASPM_L1 0x0002 // L1 Enable
+ */
+ pDdc->lnkCtlAspmL1 = ((lnkCtl & PCI_EXP_LNKCTL_ASPM_L1) == PCI_EXP_LNKCTL_ASPM_L1);
+ if (PCI_EXP_LNKCTL_ASPM_L1 == (pDdc->lnkCapAspmSupport & PCI_EXP_LNKCTL_ASPM_L1)) /* ASPM Capable (L1) */
+ {
+ if (0 == pDdc->lnkCtlAspmL1)
+ {
+ MXL_MOCA_DBG1P0("ASPM Disabled!\n");
+ lnkCtrlWr = lnkCtl | PCI_EXP_LNKCTL_ASPM_L1; /* Enable */
+ pci_write_config_dword(pDev, pos + PCI_EXP_LNKCTL, lnkCtrlWr);
+ pci_read_config_dword(pDev, pos + PCI_EXP_LNKCTL, &lnkCtl); /* Update */
+ pDdc->lnkCtlAspmL1 = ((lnkCtl & PCI_EXP_LNKCTL_ASPM_L1) == PCI_EXP_LNKCTL_ASPM_L1);
+ }
+ }
+ else
+ {
+ MXL_MOCA_DBG1P0("ASPM: Link not capable of L1!\n");
+ }
+
+ ///* For TEST: */pci_write_config_dword(pDev, pos1 + PCI_PM_CTRL, pmCtrl | 0x3); // Capabilities::Status: D3
+
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "ASPM Enabled\n");
+
+ /* Enable or disable PCI device's PME# function */
+ if (pDdc->lnkCapPme)
+ {
+ pci_pme_active (pDev, true);
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Enabled PME generation.\n");
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_WARN, "Not PME capable\n");
+ }
+
+ pci_read_config_dword(pDev, pos + PCI_EXP_DEVSTA, &status);
+ pci_read_config_dword(pDev, pos + PCI_EXP_LNKCAP, &lnkCap);
+ pci_read_config_dword(pDev, pos + PCI_EXP_LNKCTL, &lnkCtl);
+ pci_read_config_dword(pDev, pos + PCI_EXP_LNKSTA, &lnkStat);
+
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "pDev->pm_cap=%d\n", pDev->pm_cap);
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG2, "capability=%x, control=%x, status=%x, lnkCap=%x, lnkCtl=%x, lnkStat=%x, pmCap=%x, pmCtrl=%x\n",
+ capability, control, status, lnkCap, lnkCtl, lnkStat, pmCap, pmCtrl);
+ }
+ return ret;
+}
+#endif
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeDataPathReset
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Resets the SoC hardware for the data path
+ *
+ * IN PARAMS : [*pDdc] : driver data context
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_OK or MXL_MOCA_ERR
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeDataPathReset(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc, int8_t devIndex)
+{
+ uint32_t mac[2] = {0,0};
+ uint32_t addr, i, v;
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+ MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *pDataPath = (MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *)pDdc->pDpCtx;
+
+ //Also called after SoC firmware is downloaded.
+
+ MXL_MOCA_DBG1P1( "%s ...\n", __FUNCTION__);
+
+ do
+ {
+ MxL_MoCA_PCIeStopXmit(pDdc->pNetDev);
+
+ MxL_MoCA_PCIeGetMgmtMAC(pDdc, mac);
+
+ addr = pDdc->dmemBaseAddr + (PCIE_TC_MGMT_IF_MAC_ADDR * 4);
+ ret = MxL_MoCA_PCIeWrite(devIndex, addr, mac[0]);
+ if (MXL_MOCA_OK != ret)
+ {
+ break;
+ }
+
+ ret = MxL_MoCA_PCIeWrite(devIndex, addr+4, mac[1]);
+ if (MXL_MOCA_OK != ret)
+ {
+ break;
+ }
+
+ // RX section
+ v = pDdc->dmemBaseAddr + (P_PCIE_HOST_RX_DESC_QUEUE * 4);
+ pDataPath->rxQueuePair.descQueueAddr = v;
+ addr = v;
+
+ ret = MxL_MoCA_PCIeWrite(devIndex, addr, (uintptr_t)pDataPath->rxQueuePair.pDescQueuePa);
+ if (MXL_MOCA_OK != ret)
+ {
+ break;
+ }
+
+ addr = pDdc->dmemBaseAddr + (P_PCIE_HOST_RX_DESC_Q_LEN * 4); // Rx desc queue len
+ ret = MxL_MoCA_PCIeWrite(devIndex, addr, MXL_MOCA_PCIE_RX_DESC_QUEUE_SIZE);
+ if (MXL_MOCA_OK != ret)
+ {
+ break;
+ }
+
+ // TX section
+ v = pDdc->dmemBaseAddr + (P_PCIE_HOST_TX_DESC_QUEUE * 4);
+ pDataPath->txQueuePair.descQueueAddr = v;
+ addr = v;
+
+ ret = MxL_MoCA_PCIeWrite(devIndex, addr, (uintptr_t)pDataPath->txQueuePair.pDescQueuePa);
+ if (MXL_MOCA_OK != ret)
+ {
+ break;
+ }
+
+ addr = pDdc->dmemBaseAddr + (P_PCIE_HOST_TX_DESC_Q_LEN * 4); // Tx desc queue len
+ ret = MxL_MoCA_PCIeWrite(devIndex, addr, MXL_MOCA_PCIE_TX_DESC_QUEUE_SIZE);
+ if (MXL_MOCA_OK != ret)
+ {
+ break;
+ }
+
+ pDataPath->txQueuePair.descQueueReadIdx = 0;
+ pDataPath->rxQueuePair.descQueueReadIdx = 0;
+ pDataPath->txQueuePair.descQueueWriteIdx = 0;
+ pDataPath->rxQueuePair.descQueueWriteIdx = 0;
+
+ pDataPath->rxQueuePair.descQueueSize = MXL_MOCA_PCIE_RX_DESC_QUEUE_SIZE;
+ pDataPath->txQueuePair.descQueueSize = MXL_MOCA_PCIE_TX_DESC_QUEUE_SIZE;
+
+ MxL_MoCA_PCIeFreeRxBuffers(pDdc->pNetDev);
+
+ for (i = 0; i < MXL_MOCA_PCIE_RX_PTR_QUEUE_SIZE; i++)
+ pDataPath->rxQueuePair.pDescQueue[i].dword0 = MXL_MOCA_PCIE_DESC_OWNER_HOST;
+
+ ret = MxL_MoCA_PCIeAllocRxBuffers(pDdc->pNetDev);
+ if (MXL_MOCA_OK != ret)
+ {
+ break;
+ }
+
+ MxL_MoCA_PCIeResetTxQueue(pDdc->pNetDev);
+
+ for(i = 0; i < MXL_MOCA_PCIE_TX_PTR_QUEUE_SIZE; i++)
+ pDataPath->txQueuePair.pDescQueue[i].dword0 = MXL_MOCA_PCIE_DESC_OWNER_HOST;
+
+ ret = MxL_MoCA_PCIeInitSoCIfc(devIndex);
+ if (MXL_MOCA_OK != ret)
+ {
+ break;
+ }
+
+ MxL_MoCA_PCIeStartXmit(pDdc->pNetDev);
+ } while (0);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeRestart
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Restarts the data path
+ *
+ * IN PARAMS : [devIndex] : device index
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_OK or MXL_MOCA_ERR
+ *
+ *--------------------------------------------------------------------------------------*/
+
+ // interface
+MXL_MOCA_STATUS_E MxL_MoCA_PCIeRestart(int8_t devIndex)
+{
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T*)gpDevData[devIndex];
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+
+ MXL_MOCA_DBG1P1( "%s...\n", __FUNCTION__);
+ ret = MxL_MoCA_PCIeConfigInboundATU(devIndex);
+ if (MXL_MOCA_OK != ret)
+ {
+ return MXL_MOCA_ERR;
+ }
+ return MxL_MoCA_PCIeDataPathReset(pDdc, devIndex);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeStop
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Stops the data path
+ *
+ * IN PARAMS : [devIndex] : device index
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+ // interface
+void MxL_MoCA_PCIeStop (int8_t devIndex)
+{
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T*)gpDevData[devIndex];
+
+ MxL_MoCA_PCIeStopXmit(pDdc->pNetDev);
+}
+
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeQueuePkt
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Queue packet in the descriptor (common for Tx and Rx queues)
+ *
+ * IN PARAMS : [*queuePair] : descriptor queue.
+ * : [*pPktElement] : physical address.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_OK or MXL_MOCA_ERR
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeQueuePkt(MXL_MOCA_PCIE_QUEUE_PAIR_T* queuePair, uint32_t pktLen, dma_addr_t mapping)
+{
+ uint32_t widx, descrDword0, descrDword1;
+
+ widx = queuePair->descQueueWriteIdx;
+
+ // Each PCIe Tx/Rx Desc Queue entry is 2dwords long.
+ if ((queuePair->pDescQueue[widx].dword0 & 0x03) != MXL_MOCA_PCIE_DESC_OWNER_HOST)
+ {
+ MXL_MOCA_DBG2P1("MXL_MOCA_NO_HOST_DESC_ERR, own=%x\n", (queuePair->pDescQueue[widx].dword0 & 0x03));
+ return MXL_MOCA_NO_HOST_DESC_ERR;
+ }
+
+ /* ToDo: We don't need the packet queue, just the ring buffer is enough Or use this and remove the ring */
+ queuePair->pPktQueue[widx].mapping = mapping;
+ queuePair->pPktQueue[widx].totalLen = pktLen;
+
+ /*****************************************************************************
+ * dword[1]::phy_addr : 32 //!< 31:0 - physical addr of the packet
+ * dword[0]::totalLen : 16 //!< 17:2 - total length of packet
+ * dword[0]::ownership : 2; //!< 1:0 - ownership: 1=SOC, 0=HOST, 2=PKT_DONE
+ ****************************************************************************/
+ descrDword0 = (pktLen << 2) | MXL_MOCA_PCIE_DESC_OWNER_SOC;
+ descrDword1 = mapping; /* physical addr (mapping) */
+
+ queuePair->pDescQueue[widx].dword1 = descrDword1;
+ queuePair->pDescQueue[widx].dword0 = descrDword0;
+
+ widx++;
+
+ if (widx >= queuePair->descQueueSize) // descriptors are 2 dwords
+ {
+ MXL_MOCA_DBG2P0( "wrap around!\n");
+ widx = 0;
+ }
+ queuePair->descQueueWriteIdx = widx;
+ return MXL_MOCA_OK;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeCheckOutOfBoundMapping
+ *
+ *
+ *
+ * DATE CREATED : 01/03/2017
+ *
+ * DESCRIPTION : Checks if the physical address mapping is outside the iATU window.
+ * This function must be effecient.
+ *
+ * IN PARAMS : [mapping] : physical address provided by the OS (pci_map_single call)
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_OK or MXL_MOCA_ERR
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeCheckOutOfBoundMapping(dma_addr_t mapping)
+{
+ /* NOTE: start_addr must be lowest of the target base addresses */
+ if (mapping >= MXL_MOCA_PCIE_OUTB_ATU_TARGET0_ADDR_MASK && mapping <= MXL_MOCA_PCIE_OUTB_ATU_TARGET1_ADDR_LIMIT)
+ {
+ return MXL_MOCA_OK;
+ }
+
+ //MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "mapping error (0x%p), out of range (%x, %x)\n",
+ // mapping,
+ // MXL_MOCA_PCIE_OUTB_ATU_TARGET0_ADDR_MASK,
+ // MXL_MOCA_PCIE_OUTB_ATU_TARGET1_ADDR_LIMIT);
+
+ return MXL_MOCA_ERR;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeDebugHandleRxReturnOwnership
+ *
+ *
+ *
+ * DATE CREATED : 10/20/2017
+ *
+ * DESCRIPTION : This is a DEBUG function. When enabled, it will not hand off the
+ * received packets to upper layers. See echo 'r 2' > /proc/%s/pcie
+ * command usage. MXL_MOCA_PCIE_DEBUG_DROP_RX must be enabled.
+ *
+ * IN PARAMS : [pDdc] : Pointer to driver data plane context.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+ #if MXL_MOCA_PCIE_DEBUG_DROP_RX
+static void MxL_MoCA_PCIeDebugHandleRxReturnOwnership(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc)
+{
+ MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *pDataPath = (MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *)pDdc->pDpCtx;
+ uint16_t index, num=0;
+ MXL_MOCA_PCIE_QUEUE_PAIR_T* queuePair;
+ uint32_t descrDword0 = 0;
+
+ queuePair = &pDataPath->rxQueuePair;
+
+ for (index = 0; index < queuePair->descQueueSize; index++)
+ {
+ if ((queuePair->pDescQueue[index].dword0 & 0x03) == MXL_MOCA_PCIE_DESC_OWNER_HOST)
+ {
+ num++;
+ pDdc->rxStats[0]++;
+ /*****************************************************************************
+ * dword[1]::phy_addr : 32 //!< 31:0 - physical addr of the packet
+ * dword[0]::totalLen : 16 //!< 17:2 - total length of packet
+ * dword[0]::ownership : 2; //!< 1:0 - ownership: 1=SOC, 0=HOST, 2=PKT_DONE
+ ****************************************************************************/
+ pDdc->rxStats[2]++; // proc stats
+ pDdc->netIfRxDropped++; // ifconfig
+ // Give the ownership back to SoC
+ descrDword0 = queuePair->pDescQueue[index].dword0;
+ descrDword0 &= 0xFFFFFFFC;
+ descrDword0 |= MXL_MOCA_PCIE_DESC_OWNER_SOC;
+ queuePair->pDescQueue[index].dword0 = descrDword0;
+ }
+ }
+ if (num)
+ {
+ pDdc->ethStats.rxPackets += num;
+ pDdc->ethStats.rxPacketsGood += num;
+ }
+}
+#endif
+
+/*----------------------------------------------------------------------------------------
+ * Interrupt handlers
+ *--------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeHandleRxData
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Handles the receive interrupt for the SoC hardware.
+ * Keep this function simple. No DBG print statements in release version
+ * since it will impact performance at high data rate.
+ *
+ * IN PARAMS : [pDdc] : Pointer to driver data plane context.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_PCIeHandleRxData(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc)
+{
+ MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *pDataPath = (MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *)pDdc->pDpCtx;
+
+ uint32_t num, max;
+ uint32_t ridx, pktLen, netif_rx_status;
+ MXL_MOCA_PCIE_QUEUE_PKT_T* pPktInfo;
+ struct net_device* pNetDev = pDdc->pNetDev;
+ dma_addr_t mapping;
+ struct sk_buff *skb;
+ MXL_MOCA_STATUS_E status;
+
+ MXL_MOCA_PCIE_QUEUE_PAIR_T* queuePair;
+
+ //MXL_MOCA_DBG2P1("%s\n", __FUNCTION__);
+
+ num = 0;
+ queuePair = &pDataPath->rxQueuePair;
+ ridx = queuePair->descQueueReadIdx;
+
+ max = MXL_MOCA_PCIE_MAX_RX_PACKETS_PER_INT; // Go one cycle of the descriptor array length
+ MXL_MOCA_DBG2P4("%s:queuePair->pDescQueue[%d].dword0/dword1 %x, %x\n",
+ __FUNCTION__, ridx, queuePair->pDescQueue[ridx].dword0, queuePair->pDescQueue[ridx].dword1);
+ for (num=0; num < max; num++)
+ {
+ // MXL_MOCA_PCIE_DESC_OWNER_HOST is the initial state (no allocations). DESC_OWNER_SOC is when packets are ready to be sent.
+ // MXL_MOCA_PCIE_DESC_OWNER_PKT_DONE is the state the SoC returns when packets are transferred and descriptor returned
+ MXL_MOCA_DBG2P4("queuePair->pDescQueue[%d].dword0 = %d, %x, %x\n", \
+ ridx, (queuePair->pDescQueue[ridx].dword0 & 0x03), \
+ queuePair->pDescQueue[ridx].dword0, queuePair->pDescQueue[ridx].dword1);
+
+ if ((queuePair->pDescQueue[ridx].dword0 & 0x03) == MXL_MOCA_PCIE_DESC_OWNER_HOST)
+ {
+ MXL_MOCA_DBG2P2("%s:*** (rx) ridx = %d\n", __FUNCTION__, ridx);
+ }
+ else if ( (queuePair->pDescQueue[ridx].dword0 & 0x03) == MXL_MOCA_PCIE_DESC_OWNER_SOC ) /* unused descriptor */
+ {
+ break;
+ }
+
+ pPktInfo = &queuePair->pPktQueue[ridx];
+
+ if (pPktInfo == NULL)
+ {
+ MXL_MOCA_DBG2P2("%s:pPktInfo is NULL at %d\n", __FUNCTION__, ridx);
+ }
+ else
+ {
+ pDdc->ethStats.rxBytes += pPktInfo->totalLen;
+ }
+ pDdc->rxStats[0]++;
+
+ if (ridx >= MXL_MOCA_PCIE_RX_RING_SIZE)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_WARN, "%s invalid packet id %d\n", pNetDev->name, ridx);
+ BUG();
+ continue;
+ }
+
+ if (pDdc->rxRing[ridx].skb != NULL)
+ {
+ skb = (struct sk_buff *)pDdc->rxRing[ridx].skb;
+ pktLen = queuePair->pDescQueue[ridx].dword0 >> 2;
+
+ MXL_MOCA_DBG2P2("rx callback (alloc): packetID = %3d, skb = %p\n", ridx, skb);
+
+ #if MXL_MOCA_ENABLE_DBG_MSG
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG2, "RX:(skb=%x) few pkt bytes(to stack) length=%x [%2x %2x %2x %2x %2x %2x %2x %2x\n %2x %2x %2x %2x %2x %2x %2x %2x\n %2x %2x %2x %2x %2x %2x %2x %2x\n %2x %2x %2x %2x %2x %2x %2x %2x\n %2x %2x]\n",
+ skb->data, skb->len,
+ skb->data[0], skb->data[1], skb->data[2], skb->data[3],
+ skb->data[4], skb->data[5], skb->data[6], skb->data[7],
+ skb->data[8], skb->data[9], skb->data[10], skb->data[11],
+ skb->data[12], skb->data[13], skb->data[14], skb->data[15],
+ skb->data[16], skb->data[17], skb->data[18], skb->data[19],
+ skb->data[20], skb->data[21], skb->data[22], skb->data[23],
+ skb->data[24], skb->data[25], skb->data[26], skb->data[27],
+ skb->data[28], skb->data[29], skb->data[30], skb->data[31],
+ skb->data[32], skb->data[33]);
+ #endif
+
+ /// unlock memory; may improve eg checksum speed
+ pci_unmap_single(pDdc->pPCIeDev, (dma_addr_t)pDdc->rxRing[ridx].mapping, MXL_MOCA_PCIE_MAX_ETH_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
+
+ if (pktLen > MXL_MOCA_PCIE_MAX_ETH_MTU_SIZE)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_WARN, "%s X large packet size %d(%#x)\n", pNetDev->name, pktLen, pktLen);
+
+ dev_kfree_skb_any(skb);
+ pDdc->netIfRxDropped++;
+ }
+ else
+ {
+ // we do not have CRC: pktLen -= 4; //strip 4B CRC
+ skb_put(skb,pktLen);
+
+ skb->protocol = eth_type_trans(skb, pNetDev);
+
+#if MXL_MOCA_PCIE_DEBUG_DROP_RX
+ if (1 == pDdc->dbg_drop_rx)
+ {
+ dev_kfree_skb_any(skb);
+ netif_rx_status = NET_RX_DROP;
+ }
+ else
+#endif // MXL_MOCA_PCIE_DEBUG_DROP_RX
+ {
+ // hand off the skb to upper layers
+#if MXL_MOCA_PCIE_NAPI
+ netif_rx_status = netif_receive_skb(skb);
+#else
+ netif_rx_status = netif_rx(skb);
+#endif
+ }
+
+ if (netif_rx_status == NET_RX_DROP) // DO NOT USE PRINT STATEMENTS
+ {
+ pDdc->rxStats[2]++; // proc stats
+ pDdc->netIfRxDropped++; // ifconfig
+ }
+ else
+ {
+ pDdc->rxStats[1]++;
+ }
+ pNetDev->last_rx = jiffies;
+ } /* end if !status */
+ }
+
+ // Alloc new skb
+ skb = dev_alloc_skb(MXL_MOCA_PCIE_MAX_ETH_RX_BUF_SIZE);
+ if (skb != NULL)
+ {
+ skb->dev = pNetDev;
+
+ pDdc->rxRing[ridx].skb = skb;
+
+ /// Ethernet header alignment.
+ skb_reserve(skb,0); // Do not use NET_IP_ALIGN
+
+ mapping = pci_map_single(pDdc->pPCIeDev, skb->data, MXL_MOCA_PCIE_MAX_ETH_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
+ if (unlikely(pci_dma_mapping_error(pDdc->pPCIeDev, mapping)))
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "HandleRxData: dma_mapping error!\n");
+ pDdc->mappingErr0++;
+ dev_kfree_skb_any(skb);
+ pDdc->rxRing[ridx].skb = NULL;
+ return;
+ }
+ else
+ {
+ if (MxL_MoCA_PCIeCheckOutOfBoundMapping(mapping) == MXL_MOCA_ERR)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "(0x%x)HandleRxData:out-of-bounds mapping error!\n", mapping);
+ pDdc->mappingErr0++;
+ dev_kfree_skb_any(skb);
+ pDdc->rxRing[ridx].skb = NULL;
+ return;
+ }
+ }
+ pDdc->rxRing[ridx].mapping = mapping;
+
+ status = MxL_MoCA_PCIeQueuePkt(&pDdc->pDpCtx->rxQueuePair, MXL_MOCA_PCIE_MAX_ETH_MTU_SIZE, mapping);
+
+ if (status != MXL_MOCA_OK)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_WARN, "%s attach rx failed packet id:%d\n", pNetDev->name, ridx);
+ dev_kfree_skb_any(skb);
+ }
+ }
+ else
+ {
+#if MXL_MOCA_ENABLE_DBG_MSG
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_WARN, "************** cannot alloc a skb\n");
+#endif
+ pDdc->skbAllocErr++;
+ pDdc->rxRing[ridx].skb = NULL; // Upadte RX RingBuf SKB pointer to be NULL.
+ // Do not increment ridx, exit loop. Breaks out of the loop to reduce ISR execution time.
+ // This section will enter only when oversubscribed and the host is resource limited.
+ break;
+ }
+ ridx++;
+
+ if (ridx >= MXL_MOCA_PCIE_RX_DESC_QUEUE_SIZE)
+ ridx = 0;
+ }
+
+ queuePair->descQueueReadIdx = ridx;
+
+ MXL_MOCA_DBG2P2("%s:num = %d\n", __FUNCTION__, num);
+
+#if MXL_MOCA_PCIE_NAPI
+ pDdc->napiWorkDone += num;
+#endif
+
+ if (num)
+ {
+ pDdc->ethStats.rxPackets += num;
+ pDdc->ethStats.rxPacketsGood += num;
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeHandleTxData
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Handles the transmit interrupt for the SoC hardware.
+ * Keep this function simple. No DBG print statements in release version
+ * since it will impact performance at high data rate.
+ *
+ * IN PARAMS : [pDdc] : Pointer to driver data plane context.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+void MxL_MoCA_PCIeHandleTxData(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc)
+{
+ uint32_t ridx;
+ MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *pDataPath = (MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *)pDdc->pDpCtx;
+ MXL_MOCA_PCIE_QUEUE_PAIR_T* queuePair;
+ MXL_MOCA_PCIE_QUEUE_PKT_T* pPktInfo;
+ uint32_t num, max;
+ struct sk_buff *skb;
+ dma_addr_t mapping;
+
+ queuePair = &pDataPath->txQueuePair;
+
+ num = 0;
+ ridx = queuePair->descQueueReadIdx;
+
+ MXL_MOCA_DBG2P2("%s:txQueuePair::descQueueReadIdx at %d \n", __FUNCTION__, ridx);
+
+ max = MXL_MOCA_PCIE_MAX_TX_PACKETS_PER_INT; // Go once cycle of the descriptor array length
+
+ MXL_MOCA_DBG2P4("%s:queuePair->pDescQueue[%d].dword0/dword1 %x, %x\n",
+ __FUNCTION__, ridx, queuePair->pDescQueue[ridx].dword0, queuePair->pDescQueue[ridx].dword1);
+
+ for (num = 0; num < max; num++)
+ {
+ // MXL_MOCA_PCIE_DESC_OWNER_HOST is the initial state (no allocations). MXL_MOCA_PCIE_MXL_MOCA_PCIE_DESC_OWNER_SOC is when packets are ready to be sent.
+ // MXL_MOCA_PCIE_DESC_OWNER_PKT_DONE is the state the SoC returns when packets are transferred and descriptor returned
+ if ((queuePair->pDescQueue[ridx].dword0 & 0x03) != MXL_MOCA_PCIE_DESC_OWNER_PKT_DONE)
+ {
+ MXL_MOCA_DBG2P2("%s:*** DESC_OWNER_PKT_DONE::ridx (break) = %d\n", __FUNCTION__, ridx);
+ break;
+ }
+ pPktInfo = &queuePair->pPktQueue[ridx];
+ // MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "%s:%d,%d\n", __FUNCTION__, pPktInfo->totalLen, queuePair->pDescQueue[ridx].dword0 >> 2);
+
+ queuePair->pDescQueue[ridx].dword1 = 0;
+ queuePair->pDescQueue[ridx].dword0 = MXL_MOCA_PCIE_DESC_OWNER_HOST;
+
+ pDdc->ethStats.txBytes += pPktInfo->totalLen;
+
+ if (ridx >= MXL_MOCA_PCIE_TX_MAPPING_SIZE)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "invalid xmitted packet id:0x%x\n", ridx);
+ }
+ else if ((skb = (struct sk_buff *)pDdc->txRing[ridx].skb) == NULL)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "invalid tx skb for packet id:%d\n", ridx);
+ }
+ else
+ {
+ pDdc->txStats[5]++;
+ pDdc->numPktsXmited++;
+ mapping = (dma_addr_t)pDdc->txRing[ridx].mapping;
+ pci_unmap_single(pDdc->pPCIeDev, mapping, skb->len, PCI_DMA_TODEVICE);
+ MXL_MOCA_DBG2P2("%s:freeing ring = %x\n", __FUNCTION__, ridx);
+ dev_kfree_skb_any(skb);
+ pDdc->txRing[ridx].skb = NULL;
+ }
+
+ ridx++;
+
+ if (ridx >= MXL_MOCA_PCIE_TX_DESC_QUEUE_SIZE)
+ ridx = 0;
+
+ }
+
+ queuePair->descQueueReadIdx = ridx;
+ queuePair->lastPktsCnt += num; //�Increment�tx�stats�for�ifconfig
+ MXL_MOCA_DBG2P3("%s ... num pkts = %d , descQueueReadIdx = %d\n", __FUNCTION__, num, queuePair->descQueueReadIdx);
+
+ if (num)
+ {
+ pDdc->ethStats.txPackets += num;
+ pDdc->ethStats.txPacketsGood += num;
+ }
+
+ netif_wake_queue(pDdc->pNetDev);
+
+ //transmit pkts if already queued.
+ MxL_MoCA_PCIeStartXmitSkbs(pDdc->pNetDev);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeAllocResources
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Initializes the data path (mem and queues)
+ *
+ * IN PARAMS : [pDdc] : Pointer to driver data plane context.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_OK for success, or MXL_MOCA_MEM_ALLOC_ERR for failure
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeAllocResources(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc)
+{
+ void *pMem, *pa;
+ uint32_t sz;
+ MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *pData;
+ uint32_t addr;
+ uint32_t i;
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+#if MXL_MOCA_PCIE_DEBUG_DESCR
+ MXL_MOCA_PCIE_QUEUE_DESCR_T* pDescr;
+#endif
+
+ MXL_MOCA_DBG2P1("%s: -- Alloc resources --\n", __FUNCTION__);
+
+ // Allocate the contexts
+ pDdc->pDpCtx = (MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *)MxL_MoCA_PCIeKMemAlloc(sizeof(MXL_MOCA_PCIE_DATAPATH_CONTEXT_T));
+ if (!pDdc->pDpCtx)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Failed to allocate MXL_MOCA_PCIE_DATAPATH_CONTEXT_T ... \n");
+ return MXL_MOCA_MEM_ALLOC_ERR;
+ }
+
+ do
+ {
+ pData = pDdc->pDpCtx;
+ pData->txQueuePair.descQueueReadIdx = 0;
+ pData->rxQueuePair.descQueueReadIdx = 0;
+ pData->txQueuePair.descQueueWriteIdx = 0;
+ pData->rxQueuePair.descQueueWriteIdx = 0;
+
+ pData->txQueuePair.pPktQueue = NULL;
+ pData->rxQueuePair.pPktQueue = NULL;
+
+ pData->txQueuePair.pDescQueue = NULL;
+ pData->rxQueuePair.pDescQueue = NULL;
+
+ sz = MXL_MOCA_PCIE_TX_PTR_QUEUE_SIZE * sizeof(MXL_MOCA_PCIE_QUEUE_DESCR_T),
+ pMem = MxL_MoCA_PCIeAllocDmaMem(pDdc, sz, (void **) &pa);
+ if (!pMem)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Failed to allocate PCIe Tx Desc Queue ... \n");
+ MxL_MoCA_PCIeTerminate(pDdc);
+ ret = MXL_MOCA_MEM_ALLOC_ERR;
+ break;
+ }
+
+ memset(pMem, 0, sz);
+ pData->txQueuePair.pDescQueue = (MXL_MOCA_PCIE_QUEUE_DESCR_T*) pMem;
+ pData->txQueuePair.pDescQueuePa = pa;
+
+ for (i = 0; i < MXL_MOCA_PCIE_TX_PTR_QUEUE_SIZE; i++)
+ {
+ pData->txQueuePair.pDescQueue[i].dword0 = MXL_MOCA_PCIE_DESC_OWNER_HOST;
+ }
+
+ sz = MXL_MOCA_PCIE_RX_PTR_QUEUE_SIZE * sizeof(MXL_MOCA_PCIE_QUEUE_DESCR_T),
+ pMem = MxL_MoCA_PCIeAllocDmaMem(pDdc, sz, (void **) &pa);
+ if (!pMem)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Failed to allocate PCIe Rx Desc Queue ... \n");
+ MxL_MoCA_PCIeTerminate(pDdc);
+ ret = MXL_MOCA_MEM_ALLOC_ERR;
+ break;
+ }
+
+ memset(pMem, 0, sz);
+ pData->rxQueuePair.pDescQueue = (MXL_MOCA_PCIE_QUEUE_DESCR_T*) pMem;
+ pData->rxQueuePair.pDescQueuePa = pa;
+
+ for(i = 0; i < MXL_MOCA_PCIE_RX_PTR_QUEUE_SIZE; i++)
+ {
+ pData->rxQueuePair.pDescQueue[i].dword0 = MXL_MOCA_PCIE_DESC_OWNER_HOST;
+ }
+
+ sz = MXL_MOCA_PCIE_TX_PTR_QUEUE_SIZE * sizeof(MXL_MOCA_PCIE_QUEUE_PKT_T);
+ pMem = MxL_MoCA_PCIeAllocDmaMem(pDdc, sz, (void **) &pa);
+
+ if (!pMem)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Failed to allocate PCIe Tx Ptr Queue ... \n");
+ MxL_MoCA_PCIeTerminate(pDdc);
+ ret = MXL_MOCA_MEM_ALLOC_ERR;
+ break;
+ }
+
+ memset(pMem, 0, sz);
+ pData->txQueuePair.pPktQueue = (MXL_MOCA_PCIE_QUEUE_PKT_T*) pMem;
+ pData->txQueuePair.pPktQueuePa = pa;
+
+ sz = MXL_MOCA_PCIE_RX_PTR_QUEUE_SIZE * sizeof(MXL_MOCA_PCIE_QUEUE_PKT_T);
+ pMem = MxL_MoCA_PCIeAllocDmaMem(pDdc, sz, (void **) &pa);
+ if (!pMem)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Failed to allocate PCIe Rx Ptr Queue ... \n");
+ MxL_MoCA_PCIeTerminate(pDdc);
+ ret = MXL_MOCA_MEM_ALLOC_ERR;
+ break;
+ }
+
+ memset(pMem, 0, sz);
+ pData->rxQueuePair.pPktQueue = (MXL_MOCA_PCIE_QUEUE_PKT_T*) pMem;
+ pData->rxQueuePair.pPktQueuePa = pa;
+
+ MXL_MOCA_DBG1P1("PCIe Rx Descr Queue Host Addr: 0x%x\n", pData->rxQueuePair.pDescQueuePa);
+ MXL_MOCA_DBG1P1("PCIe Tx Descr Queue Host Addr: 0x%x\n", pData->txQueuePair.pDescQueuePa);
+
+ MXL_MOCA_DBG1P1("PCIe Rx Packet Queue Host Addr: 0x%x\n", pData->rxQueuePair.pPktQueuePa);
+ MXL_MOCA_DBG1P1("PCIe Tx Packet Queue Host Addr: 0x%x\n", pData->txQueuePair.pPktQueuePa);
+
+#if MXL_MOCA_PCIE_DEBUG_DESCR
+ // print descriptors
+ pDescr = pData->rxQueuePair.pDescQueue;
+ for (i = 0; i < (MXL_MOCA_PCIE_RX_DESC_QUEUE_SIZE); i++)
+ {
+ MXL_MOCA_DBG1P3("rx descr[0x%x] = {0x%x, 0x%x}\n", i, pDescr[i].dword0, pDescr[i].dword1);
+ }
+ pDescr = pData->txQueuePair.pDescQueue;
+ for (i = 0; i < (MXL_MOCA_PCIE_TX_DESC_QUEUE_SIZE); i++)
+ {
+ MXL_MOCA_DBG1P3("tx descr[0x%x] = {0x%x, 0x%x}\n", i, pDescr[i].dword0, pDescr[i].dword1);
+ }
+#endif
+
+ addr = pDdc->dmemBaseAddr + (PCIE_NUM_OUTBOUND_REGIONS * 4);
+ ret = MxL_MoCA_PCIeWrite(0, addr, MXL_MOCA_PCIE_NUM_OUTBOUND_ATU_REGIONS);
+ if (MXL_MOCA_OK != ret)
+ {
+ break;
+ }
+
+ // Region
+ // ToDo: Change this to use region0/1OutATUAddrBase when CAR-1141 if fixed
+ addr = pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG0_BASE * 4);
+ pDdc->region0OutATUAddrBase = MXL_MOCA_PCIE_OUTB_ATU_REGION0_BASE;
+ ret = MxL_MoCA_PCIeWrite(0, addr, pDdc->region0OutATUAddrBase);
+ if (MXL_MOCA_OK != ret)
+ {
+ break;
+ }
+
+ addr = pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG1_BASE * 4);
+ pDdc->region1OutATUAddrBase = MXL_MOCA_PCIE_OUTB_ATU_REGION1_BASE;
+ ret = MxL_MoCA_PCIeWrite(0, addr, pDdc->region1OutATUAddrBase);
+ if (MXL_MOCA_OK != ret)
+ {
+ break;
+ }
+
+ // Target
+ addr = pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_TAR0_BASE * 4);
+ pDdc->target0OutATUAddrMask = MXL_MOCA_PCIE_OUTB_ATU_TARGET0_ADDR_MASK;
+ ret = MxL_MoCA_PCIeWrite(0, addr, pDdc->target0OutATUAddrMask);
+ if (MXL_MOCA_OK != ret)
+ {
+ break;
+ }
+
+ addr = pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_TAR1_BASE * 4);
+ pDdc->target1OutATUAddrMask = MXL_MOCA_PCIE_OUTB_ATU_TARGET1_ADDR_MASK;
+ ret = MxL_MoCA_PCIeWrite(0, addr, pDdc->target1OutATUAddrMask);
+ if (MXL_MOCA_OK != ret)
+ {
+ break;
+ }
+ } while(0);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeIsXmitOn
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Return TRUE if the device is available/ready to handle traffic
+ *
+ * IN PARAMS : [devIndex] : device index
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : false or true
+ *
+ *--------------------------------------------------------------------------------------*/
+
+ // interface
+int MxL_MoCA_PCIeIsXmitOn(unsigned int devIndex)
+{
+ int ret = false;
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *)gpDevData[devIndex];
+
+ if (pDdc)
+ ret = pDdc->active;
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeAvailable
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Return TRUE if the device is available/ready
+ *
+ * IN PARAMS : [devIndex] : device index
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_OK or MXL_MOCA_ERR
+ *
+ *--------------------------------------------------------------------------------------*/
+
+ // interface
+MXL_MOCA_STATUS_E MxL_MoCA_PCIeAvailable(int8_t devIndex)
+{
+ uint32_t val;
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *)gpDevData[devIndex];
+
+ ret = MxL_MoCA_PCIeRead(devIndex, MXL_MOCA_PROD_FAM_ID_ADDR, &val);
+
+ if (MXL_MOCA_OK == ret)
+ {
+ if (pDdc->deviceId != val)
+ {
+ ret = MXL_MOCA_ERR;
+ }
+ }
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeInitSoCIfc
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Local function to init the SoC ifc
+ *
+ * IN PARAMS : [devIndex] : device index
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_STATUS_E code
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeInitSoCIfc(unsigned int devIndex) // need to check for failures
+{
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *)gpDevData[devIndex];
+ uint32_t val = 0, addr;
+ int8_t loop;
+ uint32_t endianCheckVal = 1;
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+
+ uint8_t *pByte = (uint8_t*)&endianCheckVal;
+ uint32_t hostEndian = (pByte[0] == 1)?0:1; // hostEndian result: 0 = little; 1 = big
+
+ MXL_MOCA_DBG1P0("#### Outbound ATU Regions (DMEM) ####\n");
+
+ do
+ {
+ ret = MxL_MoCA_PCIeRead (devIndex, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG0_BASE * 4), &val);
+ MXL_MOCA_DBG1P2("PCIE_OUTBOUND_ATU_REG0_BASE(0x%x)=0x%8x\n", pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG0_BASE * 4), val);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ ret = MxL_MoCA_PCIeRead (devIndex, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG1_BASE * 4), &val);
+ MXL_MOCA_DBG1P2("PCIE_OUTBOUND_ATU_REG1_BASE(0x%x)=0x%8x\n", pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG1_BASE * 4), val);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ /* Address translation for outbound */
+ ret = MxL_MoCA_PCIeConfigOutboundATU(devIndex);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+ } while (0);
+
+ // DEBUG Info
+ MXL_MOCA_DBG1P0("#### Outbound ATU values (EP) ####\n");
+
+ for (loop = 0; loop < MXL_MOCA_PCIE_NUM_OUTBOUND_ATU_REGIONS; loop++)
+ {
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ ret = MxL_MoCA_PCIeWrite(devIndex, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_INDEX_REG), loop);
+ MXL_MOCA_DBG1P1("EP_IATU_INDEX_REG(0x08204900)=0x%x\n", loop);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ ret = MxL_MoCA_PCIeRead(devIndex, (uintptr_t)MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_2_REG, &val);
+ MXL_MOCA_DBG1P1("EP_IATU_REGION_CTRL_2_REG(0x08204908)=0x%x\n", val);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ ret = MxL_MoCA_PCIeRead(devIndex, (uintptr_t)MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_REG, &val);
+ MXL_MOCA_DBG1P1("EP_IATU_REGION_LOWER_BASE_ADDR_REG(0x0820490C)=0x%x\n", val);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ ret = MxL_MoCA_PCIeRead(devIndex, (uintptr_t)MXL_MOCA_PCIE_EP_IATU_REGION_LIMIT_ADDR_REG, &val);
+ MXL_MOCA_DBG1P1("EP_IATU_REGION_LIMIT_ADDR_REG(0x08204914)=0x%x\n", val);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ ret = MxL_MoCA_PCIeRead(devIndex, (uintptr_t)MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_REG, &val);
+ MXL_MOCA_DBG1P1("EP_IATU_REGION_LOWER_TARGET_ADDR_REG(0x08204918)=0x%x\n\n", val);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+ }
+
+ do
+ {
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ // Update DMEM region:
+ addr = pDdc->dmemBaseAddr + (PCIE_NUM_OUTBOUND_REGIONS * 4);
+ ret = MxL_MoCA_PCIeWrite(devIndex, addr, MXL_MOCA_PCIE_NUM_OUTBOUND_ATU_REGIONS);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+ // ToDo: Change these to region0OutATUAddrBase when CAR-1141 if fixed
+ // Region
+ addr = pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG0_BASE * 4);
+ ret = MxL_MoCA_PCIeWrite(devIndex, addr, pDdc->region0OutATUAddrBase);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ addr = pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG1_BASE * 4);
+ ret = MxL_MoCA_PCIeWrite(devIndex, addr, pDdc->region1OutATUAddrBase);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ // target
+ // Target
+ addr = pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_TAR0_BASE * 4);
+ ret = MxL_MoCA_PCIeWrite(0, addr, pDdc->target0OutATUAddrMask);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ addr = pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_TAR1_BASE * 4);
+ ret = MxL_MoCA_PCIeWrite(0, addr, pDdc->target1OutATUAddrMask);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ ret = MxL_MoCA_PCIeWrite(devIndex,(pDdc->dmemBaseAddr + (PCIE_DEVCTL_MAX_PAYLOAD_SIZE * 4)), pDdc->devCtlMaxPayloadSz);
+ /* NOTE: The RC is sending completion TLPs larger than the RCB setting (not conforming to spec.).
+ This is ok as long as there are no issues seen on the SoC side. If a host system is always going
+ to send TLPs of RCB length (64 or 128 bytes), we should set the LargeRdAXIBurst to RCB length
+ instead of MaxReadReq. This is done by enabling pDdc->lnkCtlRCB below.
+ */
+ ret = MxL_MoCA_PCIeWrite(devIndex,(pDdc->dmemBaseAddr + (PCIE_LNKCTL_RCB * 4)), pDdc->devCtlMaxReadReqSz/*pDdc->lnkCtlRCB*/);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ // DEBUG Info
+ MXL_MOCA_DBG1P0("#### DMEM values (SoC) ####\n");
+ ret = MxL_MoCA_PCIeRead (devIndex, pDdc->dmemBaseAddr + (PCIE_HOST_STATUS * 4), &val);
+ MXL_MOCA_DBG1P2("W_HIF_PCIE_HOST_STATUS(0x%x)=0x%x\n", pDdc->dmemBaseAddr + (PCIE_HOST_STATUS * 4), val);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ ret = MxL_MoCA_PCIeRead (devIndex, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG0_BASE * 4), &val);
+ MXL_MOCA_DBG1P2("PCIE_OUTBOUND_ATU_REG0_BASE(0x%x)=0x%x\n", pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG0_BASE * 4), val);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ ret = MxL_MoCA_PCIeRead (devIndex, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG1_BASE * 4), &val);
+ MXL_MOCA_DBG1P2("PCIE_OUTBOUND_ATU_REG1_BASE(0x%x)=0x%x\n", pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG1_BASE * 4), val);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ ret = MxL_MoCA_PCIeRead (devIndex, (pDdc->dmemBaseAddr + (PCIE_DEVCTL_MAX_PAYLOAD_SIZE * 4)), &val);
+ MXL_MOCA_DBG1P2("PCIE_DEVCTL_MAX_PAYLOAD_SIZE(0x%x)=0x%x\n", (pDdc->dmemBaseAddr + (PCIE_DEVCTL_MAX_PAYLOAD_SIZE * 4)), val);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ ret = MxL_MoCA_PCIeRead (devIndex, (pDdc->dmemBaseAddr + (PCIE_LNKCTL_RCB * 4)), &val);
+ MXL_MOCA_DBG1P2("PCIE_LNKCTL_RCB(0x%x)=0x%x\n", (pDdc->dmemBaseAddr + (PCIE_LNKCTL_RCB * 4)), val);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ // Activate CCPU periodic interrupts to prevent missed/overlap interrupt scenarios
+ MXL_MOCA_DBG1P2("Setting PCIE_EN_CCPU_TIMER_INTR (0x%x) to %d \n", (pDdc->dmemBaseAddr + (PCIE_EN_CCPU_TIMER_INTR * 4)), MXL_MOCA_PCIE_EN_CCPU_TIMER_INTR);
+ ret = MxL_MoCA_PCIeWrite(devIndex,(pDdc->dmemBaseAddr + (PCIE_EN_CCPU_TIMER_INTR * 4)), (uint32_t)MXL_MOCA_PCIE_EN_CCPU_TIMER_INTR);
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ // DMA access byte order
+ MXL_MOCA_DBG1P2("Setting PCIE_DMA_DATA_ACCESS_BYTE_ORDER (0x%x) to %d \n", (pDdc->dmemBaseAddr + (PCIE_DMA_DATA_ACCESS_BYTE_ORDER * 4)), hostEndian);
+ ret = MxL_MoCA_PCIeWrite(devIndex,(pDdc->dmemBaseAddr + (PCIE_DMA_DATA_ACCESS_BYTE_ORDER * 4)), hostEndian);
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Host byte order:%s\n", (hostEndian==1)?"big-endian":"little-endian");
+ if (ret == MXL_MOCA_ERR)
+ {
+ break;
+ }
+
+ // Done with Init: TC code can start running now.
+ MXL_MOCA_DBG1P1("Setting PCIE_HOST_STATUS (0x%x) to RUNNING \n", (pDdc->dmemBaseAddr + (PCIE_HOST_STATUS * 4)));
+ ret = MxL_MoCA_PCIeWrite(devIndex,(pDdc->dmemBaseAddr + (PCIE_HOST_STATUS * 4)), (uint32_t)PCIE_HOST_STATUS_RUNNING);
+ } while (0);
+
+ if (ret == MXL_MOCA_ERR)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "PCIe Init SoC Ifc: Read/Write error!\n");
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Initializing PCIe interface of MoCA SoC...OK\n");
+ }
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeGetSocName
+ *
+ *
+ *
+ * DATE CREATED : 07/26/2017
+ *
+ * DESCRIPTION : Queries the family ID and bond option and return the chip name string
+ *
+ * IN PARAMS : [devIndex] : Device index of the PCI device.
+ *
+ * OUT PARAMS : [pChipName]: pointer to return MoCA SoC skuName string or 'Unknown'.
+ *
+ * RETURN VALUE : return MXL_MOCA_INVALID_PARAM_ERR, MXL_MOCA_OK or MXL_MOCA_ERR
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeGetSocName(int8_t devIndex, char **pChipName)
+{
+ uint32_t productFamilyId;
+ uint32_t bondOpt;
+ uint32_t arrayLen;
+ uint32_t i = 0;
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+ static const char const *UnknownStr = "Unknown";
+ static const struct skuNameArray
+ {
+ uint32_t familyId;
+ uint32_t bondOption;
+ char *skuName;
+ } skuArray[] = {
+ {0x3700, 0x2f, "MXL3700"},
+ {0x3700, 0x3f, "MXL3701"},
+ {0x3700, 0x2e, "MXL3702"},
+ {0x3700, 0x2d, "MXL3705"},
+ {0x3700, 0x3d, "MXL3706"},
+ {0x3700, 0x2c, "MXL3707"},
+ {0x3710, 0x2d, "MXL3710"},
+ {0x3710, 0x3d, "MXL3711"},
+ {0x3710, 0x2c, "MXL3712"},
+ };
+
+ if (NULL == pChipName)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Invalid pointer passed for chip name\n");
+ return MXL_MOCA_INVALID_PARAM_ERR;
+ }
+
+ arrayLen = sizeof(skuArray)/sizeof(skuArray[0]);
+
+ do
+ {
+ ret = MxL_MoCA_PCIeRead(devIndex, MXL_MOCA_PROD_FAM_ID_ADDR, &productFamilyId);
+ if (MXL_MOCA_OK == ret)
+ {
+ ret = MxL_MoCA_PCIeRead(devIndex, MXL_MOCA_SYS_RES_EXT_CONFIG_STAT_ADDR, &bondOpt);
+ if (MXL_MOCA_OK == ret)
+ {
+ bondOpt = (bondOpt & MXL_MOCA_BOND_OPT_SKU_MASK) >> MXL_MOCA_BOND_OPT_OFFSET;
+
+ for (i = 0; i < arrayLen; i++)
+ {
+ if ((skuArray[i].familyId == productFamilyId) &&
+ (skuArray[i].bondOption == bondOpt))
+ {
+ *pChipName = (char *)skuArray[i].skuName;
+ break;
+ }
+ }
+ }
+ }
+
+ // Can't find the valid SKU from skuArray
+ if (MXL_MOCA_ERR == ret || (i == arrayLen))
+ {
+ *pChipName = (char*)UnknownStr;
+ if (MXL_MOCA_ERR == ret)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Failed to read device ID of MoCA SoC.\n");
+ }
+ }
+ } while (0);
+
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeProbeOne
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Initializes an instance of clink ethernet driver.
+ * Initializes an adapter identified by a pci_dev structure.
+ * The OS initialization, configuring of the adapter private structure,
+ * and a hardware reset occur.
+ *
+ * IN PARAMS : [pdev] : Pointer to the PCI device.
+ * : [pEntry] : Pointer to the PCI device ID.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : return 0 if successful, <0 (Linux error code) if error
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static int __devinit MxL_MoCA_PCIeProbeOne(struct pci_dev *pdev, const struct pci_device_id *pEntry)
+{
+ struct net_device *pNetDev;
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDrvData, *pDdc;
+ uint16_t err, index;
+ struct proc_dir_entry *pProcEntry;
+ uint32_t val, bar0;
+ uint16_t valShort;
+
+ uint32_t bar1, pos;
+ uint16_t control, capability, status;
+ uint32_t configValue;
+ uint32_t tmp[2];
+ uint32_t seq;
+ uint8_t myMacAddr[6];
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+ MXL_MOCA_PCIE_ERROR_OUT_E errorOut = MXL_MOCA_PCIE_ERROR_OUT_NONE;
+ char* pChipName = NULL;
+ static const int8_t *pLinkSpeed[4] = {
+ "Invalid",
+ "2.5GT/s",
+ "5.0GT/s",
+ "8.0GT/s"
+ };
+
+ MXL_MOCA_DBG1P1("pdev: 0x%p\n", pdev);
+
+ do
+ {
+ /* Enable PCIe Device: Initialize device before it's used by a driver.
+ * Ask low-level code to enable I/O and memory
+ */
+ if (pci_enable_device(pdev))
+ {
+ MXL_MOCA_DBG2P0("pci_enable_device failed\n");
+ return -ENODEV;
+ }
+
+ // Set DMA Mask so we work on 32-bit and 64-bit systems
+ err = pci_set_dma_mask(pdev, 0xffffffff);
+ if (err)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_set_dma_mask failed: %d\n", err);
+ pci_disable_device(pdev);
+ return -ENODEV;
+ }
+
+ err = pci_set_consistent_dma_mask(pdev, 0xffffffff);
+ if (err)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_set_consistent_dma_mask failed: %d\n", err);
+ pci_disable_device(pdev);
+ return -ENODEV;
+ }
+
+ /// allocate an aligned and zeroed private driver structure
+ /// the structure is
+ /// net_device with eth_dev tacked on the end
+ /// net_device->priv points at the eth_dev
+ pNetDev = alloc_etherdev(sizeof(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T));
+
+ if (!pNetDev)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "alloc_etherdev failed\n");
+ pci_disable_device(pdev);
+ return -ENOMEM;
+ }
+ memset(pNetDev->broadcast, 0xFF, MAX_ADDR_LEN);
+
+ strcpy(pNetDev->name, MXL_MOCA_PCIE_DEV_NAME); // en%d
+
+ /// Initialize the owner field in net device
+ SET_MODULE_OWNER(pNetDev);
+
+ /* Reserve PCI I/O and memory resources (owner is MXL_MOCA_PCIE_DRV_NAME) */
+ if (pci_request_regions(pdev, MXL_MOCA_PCIE_DRV_NAME))
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "pci_request_regions failed\n");
+ errorOut = MXL_MOCA_PCIE_ERROR_OUT_FREE_NETDEV;
+ break;
+ }
+
+ /// Store net device in PCI device structure
+ pci_set_drvdata(pdev, pNetDev); /// pci_dev -> driver_data = net_device : Set private driver data pointer for a pci_dev
+
+ /// init the driver data context
+ pDrvData = NETDEV_PRIV(pNetDev);
+
+ MxL_MoCA_PCIeLockInit(&pDrvData->ethTxLock);
+
+ // BAR0
+ pDrvData->baseIoAddr0 = pci_resource_start(pdev, 0);
+ pDrvData->baseIoLen0 = pci_resource_len(pdev, 0);
+
+ /* map bus memory into CPU space */
+ pDrvData->baseIoRemap0 = (uintptr_t)ioremap_nocache(pDrvData->baseIoAddr0, pDrvData->baseIoLen0);
+ if (pDrvData->baseIoRemap0 == 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "ioremap_nocache failed for BAR1 (vmalloc too small) - abort!\n");
+ return -ENOMEM;
+ }
+
+ // BAR1
+ pDrvData->baseIoAddr1 = pci_resource_start(pdev, 1);
+ pDrvData->baseIoLen1 = pci_resource_len(pdev, 1);
+
+ /* map bus memory into CPU space */
+ pDrvData->baseIoRemap1 = (uintptr_t)ioremap_nocache(pDrvData->baseIoAddr1, pDrvData->baseIoLen1);
+
+ if (pDrvData->baseIoRemap1 == 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "ioremap_nocache failed for BAR1 (vmalloc too small) - abort!\n");
+ return -ENOMEM;
+ }
+
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG1, "baseIoAddr0: 0x%08x\n", pDrvData->baseIoAddr0);
+
+ MXL_MOCA_DBG1P1("baseIoLen0 : 0x%08x\n", pDrvData->baseIoLen0);
+ MXL_MOCA_DBG1P1("baseIoRemap0: 0x%x\n", pDrvData->baseIoRemap0);
+
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG1, "baseIoAddr1: 0x%08x\n", pDrvData->baseIoAddr1);
+
+ MXL_MOCA_DBG1P1("baseIoLen1 : 0x%08x\n", pDrvData->baseIoLen1);
+ MXL_MOCA_DBG1P1("baseIoRemap1: 0x%x\n", pDrvData->baseIoRemap1);
+
+ if (pDrvData->baseIoAddr0 == pDrvData->baseIoAddr1)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Error: baseIoAddr0(0x%x) and baseIoAddr1(0x%x) are same!\n", pDrvData->baseIoAddr0, pDrvData->baseIoAddr1);
+ }
+
+ pDrvData->pPCIeDev = pdev;
+ pNetDev->base_addr = pDrvData->baseIoAddr0;
+
+ pDrvData->deviceId = MXL_MOCA_PCIE_DEVICE_ID_UNKNOWN;
+
+ if (pci_read_config_word(pdev, PCI_DEVICE_ID, &valShort))
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Cannot read vendor ID from the PCIe device!\n");
+ errorOut = MXL_MOCA_PCIE_ERROR_OUT_FREE_ALLOC;
+ break;
+ }
+ else
+ {
+ pDrvData->deviceId = (MXL_MOCA_PCIE__DEVICE_ID_E)valShort;
+
+ if (pDrvData->deviceId == MXL_MOCA_PCIE_DEVICE_ID_CARDIFF)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Reading config space(PCI_DEVICE_ID) = 0x%08x (Cardiff)\n", valShort);
+ pDrvData->dmemBaseAddr = MXL_MOCA_PCIE_HIF_TC0_DMEM_BASE;
+ }
+ else if (pDrvData->deviceId == MXL_MOCA_PCIE_DEVICE_ID_LEUCADIA)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Reading config space(PCI_DEVICE_ID) = 0x%08x (Leucadia)\n", valShort);
+ pDrvData->dmemBaseAddr = MXL_MOCA_PCIE_HIF_TC1_DMEM_BASE;
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Device unknown!\n");
+ pDrvData->dmemBaseAddr = 0;
+ }
+ }
+
+ // A few debug prints
+ // Let us read a few config registers here for debug.
+ pci_read_config_dword(pdev, PCI_VENDOR_ID, &val);
+ MXL_MOCA_DBG2P1("Config rd(0): 0x%08x\n", val);
+ pci_read_config_word(pdev, PCI_COMMAND, &valShort);
+ MXL_MOCA_DBG2P1("Config rd(4): 0x%08x\n", valShort);
+ val |= 0x400;
+ pci_write_config_word(pdev, PCI_COMMAND, valShort);
+ pci_read_config_word(pdev, PCI_COMMAND, &valShort);
+ MXL_MOCA_DBG2P1("Config rd(4) - disable INT_A: 0x%08x\n", val);
+
+ // Read the BAR0 size.
+ pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &bar0);
+ MXL_MOCA_DBG2P1("Config rd(0x10) BAR0: 0x%08x\n", bar0);
+ if (0 == bar0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "BAR0 value(0x%x) is invalid!\n", bar0);
+ }
+ pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0xFFFFFFFF);
+ pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &val);
+ MXL_MOCA_DBG2P1("Config rd(0x10) BAR0 size = 0x%08x\n", (~(val & 0xFFFFFFF0)) + 1 );
+ pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, bar0);
+
+ // Read the BAR1 size.
+ pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &bar1);
+ MXL_MOCA_DBG2P1("Config rd(0x10) BAR1: 0x%08x\n", bar1);
+ if (0 == bar1)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "BAR1 value(0x%x) is invalid!\n", bar1);
+ }
+ pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, 0xFFFFFFFF);
+ pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &val);
+ MXL_MOCA_DBG2P1("Config rd(0x10) BAR1 size = 0x%08x\n", (~(val & 0xFFFFFFF0)) + 1 );
+ pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, bar1);
+
+ for (index = 0; index < MXL_MOCA_PCIE_MAX_NUM_OF_PCIE_DEVICES; index++)
+ {
+ if (gpDevData[index] == NULL)
+ {
+ pDrvData->devIndex = index;
+ gpDevData[index] = pDrvData;
+ break;
+ }
+ }
+
+ index++;
+ if (index > gNumMocaPcieDevices)
+ gNumMocaPcieDevices = index;
+
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG1, "MoCA PCIe Device 0x%02x\n", gNumMocaPcieDevices);
+
+ /// create dcp contexts
+ pDdc = pDrvData;
+ MxL_MoCA_PCIeLockInit(&pDdc->rwLock);
+ pDdc->busy = 0;
+
+ /* Program Inbound ATU */
+ if (MXL_MOCA_OK != MxL_MoCA_PCIeConfigInboundATU(0))
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Inbound ATU not configured\n");
+ errorOut = MXL_MOCA_PCIE_ERROR_OUT_FREE_NETDEV;
+ break;
+ }
+
+ /* Inbound ATU programmed: Host can access SoC memory */
+ ret = MxL_MoCA_PCIeGetSocName(pDrvData->devIndex, &pChipName);
+ if (MXL_MOCA_ERR == ret)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Cannot read from chip\n");
+ errorOut = MXL_MOCA_PCIE_ERROR_OUT_FREE_NETDEV;
+ break;
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "MoCA SoC: %s\n", pChipName);
+ }
+
+ // -------------------------------- MSI/INTA Section ----------------------------------------
+ // NOTE: MSI is the preferred inband interrupt type. There are several advantages such as interupt not being shared,
+ // Single TLP is sent from EP to RC for interrupt. With INTx, there are 3: ASSERT, DEASSERT_REQ(from host), DEASSERT TLP.
+ pDdc->inbandIntrType = PCIE_INTR_TYPE_MSI;
+
+ // { Command line options(intr_sel_type=): PCIE_INTR_SEL_AUTO=0; PCIE_INTR_SEL_MSI=1; PCIE_INTR_SEL_INTA=2 }
+ // If MSI has not been disabled by the command-line option pci=nomsi or CONFIG_PCI_MSI is defined and enabled,
+ // pci_msi_enabled() will return TRUE. MSI section is also entered, if command line param = PCIE_INTR_SEL_MSI
+ // If PCIE_INTR_SEL_AUTO, and the host device is capable of MSI and INTx, MSI has preference and driver will
+ // configure endpoint (EP) for MSI.
+ // Run: modinfo mxl_moca_pcie.ko to print command line options.
+
+ // If system is capable of both MSI and INTx, specify PCIE_INTR_SEL_INTA in cmd line to prefer INTx over MSI for interrupts.
+ // If system is NOT capable of MSI, make sure the kernel is built without CONFIG_PCI_MSI option.
+ // When CONFIG_PCI_MSI is not defined by kernel,
+ // specifying either PCIE_INTR_SEL_AUTO or PCIE_INTR_SEL_INTA in cmd line will configure the EP for INTx.
+
+ if ( (PCIE_INTR_SEL_MSI == intr_sel_type || pci_msi_enabled()) &&
+ (PCIE_INTR_SEL_INTA != intr_sel_type) )
+ {
+ // MSI section
+ if ((pos = pci_find_capability(pdev, PCI_CAP_ID_MSI)) != 0) // MSI capable
+ {
+ pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
+ MXL_MOCA_DBG1P1("PCI_MSI_FLAGS = %x\n", control);
+ if ((control & PCI_MSI_FLAGS_ENABLE) != 1);
+ {
+ MXL_MOCA_DBG1P0("setting PCI_MSI_FLAGS_ENABLE\n");
+ control |= PCI_MSI_FLAGS_ENABLE;
+ }
+ pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, control);
+ MXL_MOCA_DBG1P1("pos + PCI_MSI_FLAGS = %x\n", pos+PCI_MSI_FLAGS);
+
+ // verify
+ pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
+ MXL_MOCA_DBG1P1("PCI_MSI_FLAGS = %x\n", control);
+
+ if (!pci_enable_msi(pdev)) // allocates ONE interrupt to the device
+ {
+ // Register interrupt handler
+ MXL_MOCA_DBG1P2("%s: IRQ: %i\n", __FUNCTION__, pdev->irq);
+ pNetDev->irq = pdev->irq;
+ err = request_irq(pdev->irq, MxL_MoCA_PCIeISR, IRQF_SHARED, pNetDev->name, pNetDev);
+
+ if (err)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "MSI: IRQ request failed!\n");
+ }
+ else
+ {
+ pci_intx(pdev, 0); // lspci:DisINTx+
+ pDdc->inbandIntrType = PCIE_INTR_TYPE_MSI;
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Configuring interrupt(MSI)...OK\n");
+ }
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Configuring interrupt(MSI)...failed!\n");
+ }
+
+ pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO, &configValue);
+ MXL_MOCA_DBG2P1("pos + PCI_MSI_ADDRESS_LO val = %x\n", configValue);
+ MXL_MOCA_DBG2P1("pos + PCI_MSI_DATA_32 = %x\n", pos+PCI_MSI_DATA_64);
+ }
+ }
+ else if ( (PCIE_INTR_SEL_INTA == intr_sel_type || (!pci_msi_enabled())) &&
+ (PCIE_INTR_SEL_MSI != intr_sel_type) )
+ {
+ // INTA section
+ // Kernel not built with CONFIG_PCI_MSI (pci_msi_enabled will return 0) or user specified to use INTA only
+ // INTA section is also entered if command line param was specified with PCIE_INTR_SEL_INTA
+ pci_disable_msi(pdev); // Resets cfg_msi_en in EHI reg space for SoC FW. lspci: Capability::MSI: Enable-
+ pci_intx(pdev, 1); // Enable INTx. lspci:DisINTx-
+
+ // Configure for INTx
+ // Register interrupt handler
+ MXL_MOCA_DBG1P2("%s: IRQ: %i\n", __FUNCTION__, pdev->irq);
+ pNetDev->irq = pdev->irq;
+ // Uses pre-assigned IOAPIC
+ err = request_irq(pdev->irq, MxL_MoCA_PCIeISR, IRQF_SHARED, pNetDev->name, pNetDev);
+ if (err)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "INT_A: IRQ request failed!\n");
+ }
+ else
+ {
+ pDdc->inbandIntrType = PCIE_INTR_TYPE_INTA;
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Configuring interrupt(INT_A)...OK\n");
+ }
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Interrupts are not configured!!!");
+ }
+
+ // -------------------------------------------------------------------------------------
+ // Clear TX/RX ring buffers
+ for (index = 0; index < MXL_MOCA_PCIE_TX_MAPPING_SIZE; index++)
+ {
+ pDdc->txRing[index].skb = NULL;
+ }
+
+ pDdc->txRingWrIndex = 0;
+ pDdc->txRingRdIndex = 0;
+
+ for (index = 0; index < MXL_MOCA_PCIE_RX_RING_SIZE; index++)
+ {
+ pDdc->rxRing[index].skb = NULL;
+ }
+
+ // -------------------------------- PCIe capabilities ----------------------------------
+ // PCIe express capabilities
+ MXL_MOCA_DBG1P0("-- PCI Express cap/ctl/sta--\n");
+
+ if ((pos = pci_find_capability(pdev, PCI_CAP_ID_EXP)) != 0)
+ {
+ /* Read Device MaxPayload capability and setting */
+ pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &control);
+ pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &capability);
+ /*
+ PCI_EXP_DEVCTL_READRQ_128B 0x0000 // 128 Bytes
+ PCI_EXP_DEVCTL_READRQ_256B 0x1000 // 256 Bytes
+ PCI_EXP_DEVCTL_READRQ_512B 0x2000 // 512 Bytes
+ PCI_EXP_DEVCTL_READRQ_1024B 0x3000 // 1024 Bytes
+ */
+ pDdc->devCapMaxPayloadSz = 1 << ( (capability & PCI_EXP_DEVCAP_PAYLOAD) + 7 );
+ MXL_MOCA_DBG1P2("PCI_EXP_DEVCAP[0x%x]MaxPayLoadSize = %d\n", capability, pDdc->devCapMaxPayloadSz);
+
+ pDdc->devCtlMaxPayloadSz = 1 << ( ((control & PCI_EXP_DEVCTL_PAYLOAD)>> 5) + 7 );
+ pDdc->devCtlMaxReadReqSz = 1 << ( ((control & PCI_EXP_DEVCTL_READRQ) >> 12) + 7 );
+ MXL_MOCA_DBG1P3("PCI_EXP_DEVCTL[0x%x]MaxPayLoadSize = %d, MaxReadReq = %d\n", \
+ control, pDdc->devCtlMaxPayloadSz, pDdc->devCtlMaxReadReqSz);
+ /*
+ PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 // LNKCAP2 SLS Vector bit 0
+ PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 // LNKCAP2 SLS Vector bit 1
+ */
+ pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &control);
+ pci_read_config_word(pdev, pos + PCI_EXP_LNKCAP, &capability);
+ /* Supported Link Speeds, Maximum Link Width
+ * PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 // LNKCAP2 SLS Vector bit 0
+ * PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 // LNKCAP2 SLS Vector bit 1
+ */
+ pDdc->lnkCapMaxLnkSpeed = (capability & PCI_EXP_LNKCAP_SLS); // SLS = Supported Link Speed
+ pDdc->lnkCapMaxLinkWidth = (capability & PCI_EXP_LNKCAP_MLW) >> 4;
+
+ if (pDdc->lnkCapMaxLnkSpeed > 3)
+ {
+ pDdc->lnkCapMaxLnkSpeed = 0;
+ }
+
+ MXL_MOCA_DBG1P3("PCI_EXP_LNKCAP[0x%x]MaxLinkSpeed(1=2.5GT/s, 2=5GT/s) = %d, MaxLinkWidth = x%d\n", \
+ capability, pDdc->lnkCapMaxLnkSpeed, pDdc->lnkCapMaxLinkWidth);
+ // Read Completion Boundary
+ pDdc->lnkCtlRCB = 64 * ( ((control & PCI_EXP_LNKCTL_RCB) >> 3) + 1 );
+ MXL_MOCA_DBG1P2("PCI_EXP_LNKCTL[0x%x]RCB = %d\n", control, pDdc->lnkCtlRCB);
+
+ pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, &status);
+
+ // Current Link Speed, Negotiated Link Width
+ pDdc->lnkStaMaxLnkSpeed = (status & PCI_EXP_LNKSTA_CLS); // CLS = Current Link Speed
+ pDdc->lnkStaMaxLinkWidth = (status & PCI_EXP_LNKSTA_NLW) >> 4;
+
+ if (pDdc->lnkStaMaxLnkSpeed > 3)
+ {
+ pDdc->lnkStaMaxLnkSpeed = 0;
+ }
+
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Supported Link Speed : %s, Current Link Speed : %s\n", pLinkSpeed[pDdc->lnkCapMaxLnkSpeed], pLinkSpeed[pDdc->lnkStaMaxLnkSpeed]);
+
+ MXL_MOCA_DBG1P3("PCI_EXP_LNKSTA[0x%x]MaxLinkSpeed(1=2.5GT/s, 2=5GT/s, 3=8GT/s) = %d, MaxLinkWidth = x%d\n", \
+ capability, pDdc->lnkStaMaxLnkSpeed, pDdc->lnkStaMaxLinkWidth);
+ }
+ pDrvData->pPCIeDev = pdev;
+#if MXL_MOCA_PCIE_PWR_MGMT
+ MxL_MoCA_PCIePowerManagementInit(gNumMocaPcieDevices-1);
+#endif
+ if (pci_enable_pcie_error_reporting(pdev) == 0)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO,"Advanced Error Reporting (AER) enable...OK\n");
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Advanced Error Reporting (AER) enable...failed!\n");
+ }
+
+ // -------------------------------------------------------------------------------------
+ /// initialize default handlers
+ ether_setup(pNetDev);
+
+ /// Initialize net device for Ethernet
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)
+ pNetDev->netdev_ops = &gMxlMocaPcieNetDevOps;
+#else
+ pNetDev->open = MxL_MoCA_PCIeNetDevOpen;
+ pNetDev->stop = MxL_MoCA_PCIeNetDevClose;
+ pNetDev->hard_start_xmit = MxL_MoCA_PCIeNetDevStartXmit;
+ pNetDev->do_ioctl = 0;
+ pNetDev->get_stats = MxL_MoCA_PCIeNetDevGetStats;
+ pNetDev->set_multicast_list = MxL_MoCA_PCIeNetDevSetRxMode;
+ pNetDev->tx_timeout = MxL_MoCA_PCIeNetDevTxTimeout;
+#endif
+ pNetDev->watchdog_timeo = MXL_MOCA_PCIE_TX_TIMEOUT;
+ pNetDev->tx_queue_len = MXL_MOCA_PCIE_TX_MAPPING_SIZE; /* reflects in ifconfig */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 4)
+ MxL_MoCA_PCIeSetEthToolVar(pNetDev);
+#endif
+
+#if MXL_MOCA_PCIE_NAPI
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Config NAPI...\n");
+ netif_napi_add(pNetDev, &pDrvData->napi, MxL_MoCA_PCIeNapiPoll, MXL_MOCA_PCIE_MAX_NAPI_WEIGHT);
+ napi_enable(&pDdc->napi);
+#endif
+
+ for (val = 0; val < 6; val++)
+ {
+ int8_t c1 = mac_addr[val*3];
+ int8_t c2 = mac_addr[val*3+1];
+
+ if (val != 5 && mac_addr[val*3+2] != ':') break;
+
+ if (!isxdigit(c1) || !isxdigit(c2)) break;
+
+ c1 = isdigit(c1) ? c1 - '0' : tolower(c1) - 'a' + 10;
+ c2 = isdigit(c2) ? c2 - '0' : tolower(c2) - 'a' + 10;
+ myMacAddr[val] = (uint8_t) c1 * 16 + (uint8_t) c2;
+ }
+ // 00:20:30:40:50:60
+ // tmp[0] = 0x00203040;
+ // tmp[1] = 0x50600000;
+ tmp[0] = (uint32_t)myMacAddr[0];
+ tmp[0] <<= 8;
+ tmp[0] |= (uint32_t)myMacAddr[1];
+ tmp[0] <<= 8;
+ tmp[0] |= (uint32_t)myMacAddr[2];
+ tmp[0] <<= 8;
+ tmp[0] |= (uint32_t)myMacAddr[3];
+ //--
+ tmp[1] = (uint32_t)myMacAddr[4];
+ tmp[1] <<= 8;
+ tmp[1] |= (uint32_t)myMacAddr[5];
+ tmp[1] <<= 16;
+
+ MxL_MoCA_PCIeSetMgmtMAC(0, tmp);
+
+ pci_set_master(pdev);
+ /// Register Linux net device
+ /// Note: MxL_MoCA_PCIeNetDevGetStats (and possibly others) is called from inside register_netdev
+ if (register_netdev(pNetDev))
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "register_netdev failed\n");
+ errorOut = MXL_MOCA_PCIE_ERROR_OUT_FREE_UNMAP;
+ break;
+ }
+
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Registering network device(%s)...OK\n", pNetDev->name);
+
+ seq = simple_strtoul(pNetDev->name+2,0, 10);
+
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG1, "mac_addr: %02x %02x %02x %02x %02x %02x\n",
+ pNetDev->dev_addr[0], pNetDev->dev_addr[1], pNetDev->dev_addr[2],
+ pNetDev->dev_addr[3], pNetDev->dev_addr[4], pNetDev->dev_addr[5]);
+
+ pDrvData->netIfRxDropped = 0;
+ pDrvData->txIntrCount = 0;
+ pDrvData->readProcMode = 0;
+#if MXL_MOCA_PCIE_DEBUG_DROP_RX
+ pDrvData->dbg_drop_rx = 0;
+#endif
+#if MXL_MOCA_PCIE_DEBUG_DROP_TX
+ pDrvData->dbg_drop_tx = 0;
+#endif
+
+ pDrvData->skbAllocErr = 0;
+
+#if MXL_MOCA_PCIE_NAPI
+ pDrvData->napiDisableIntr = 0;
+#endif
+
+ if (gNumMocaPcieDevices > 0)
+ {
+ MxL_MoCA_PCIeFormatString(pDrvData->procDirName,
+ MXL_MOCA_PCIE_PROC_NAME_LEN_MAX,
+ MXL_MOCA_PCIE_PROC_DIR_NAME,
+ gNumMocaPcieDevices-1); // en%d
+
+ pDrvData->pProcDir = proc_mkdir(pDrvData->procDirName, NULL);
+
+ if (pDrvData->pProcDir)
+ {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
+ pProcEntry = create_proc_entry(MXL_MOCA_PCIE_PROC_ENTRY_NAME, (S_IFREG|S_IRUGO|S_IWUGO), pDrvData->pProcDir);
+ if (pProcEntry != NULL)
+ {
+ pProcEntry->read_proc = MxL_MoCA_PCIeReadProc;
+ pProcEntry->write_proc = MxL_MoCA_PCIeWriteProc;
+ }
+#else
+ pProcEntry = proc_create(MXL_MOCA_PCIE_PROC_ENTRY_NAME, (S_IFREG|S_IRUGO|S_IWUGO), pDrvData->pProcDir, &gMxlMocaProcFops);
+#endif
+ if (pProcEntry == NULL)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Creating proc failed!\n");
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Creating proc(directory: %s, entry: %s)...OK\n", pDrvData->procDirName, MXL_MOCA_PCIE_PROC_ENTRY_NAME);
+ }
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "proc_mkdir failed!\n");
+ }
+ }
+
+ pDdc->pNetDev = pNetDev;
+
+ if (MxL_MoCA_PCIeDataPathInit(pDdc, gNumMocaPcieDevices-1) != MXL_MOCA_OK)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Data path init failed\n");
+ errorOut = MXL_MOCA_PCIE_ERROR_OUT_FREE_ALLOC;
+ break;
+ }
+ /* Outbound ATU configured: SoC can access host memory via PCIe link for DMA transfers */
+ printk("%s: PCIe driver init done!\n\n", MXL_MOCA_PCIE_DRV_NAME);
+ }while (0);
+
+ // Handle error conditions before returning
+ switch (errorOut)
+ {
+ case MXL_MOCA_PCIE_ERROR_OUT_NONE:
+ return MXL_MOCA_OK;
+
+ case MXL_MOCA_PCIE_ERROR_OUT_FREE_ALLOC:
+ MXL_MOCA_DBG2P0( "err_out_free_alloc\n");
+ pDrvData = NETDEV_PRIV(pNetDev);
+ /* Free any allocations here */
+ // fall-through
+
+ case MXL_MOCA_PCIE_ERROR_OUT_FREE_UNMAP:
+ // unmap/un-register
+ MXL_MOCA_DBG2P0( "err_out_free_umap\n");
+ /// Unregister Linux net device
+ free_irq(pdev->irq, pNetDev);
+ pci_disable_msi(pdev);
+ unregister_netdev(pNetDev);
+
+ // Free the net device
+ pci_disable_device(pdev);
+
+ // Release reserved PCI I/O and memory resources
+ pci_release_regions(pdev);
+
+ iounmap((void*)pDrvData->baseIoRemap0);
+ iounmap((void*)pDrvData->baseIoRemap1);
+ // fall-through
+
+ case MXL_MOCA_PCIE_ERROR_OUT_FREE_NETDEV:
+ // release the net device and data
+ MXL_MOCA_DBG2P0( "err_out_free_netdev\n");
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
+ /// pNetDev is not the allocation address anymore, can't use kfree() directly.
+ free_netdev(pNetDev);
+#else
+ kfree(pNetDev);
+#endif
+ pci_set_drvdata(pdev, NULL);
+ break;
+
+ default:
+ break;
+ }
+
+ return -ENODEV;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeRemoveOne
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Remove or uninstall the driver.
+ *
+ * IN PARAMS : [pdev] : Pointer to the PCI device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : return 0 if successful, <0 (Linux error code) if error
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void __devexit MxL_MoCA_PCIeRemoveOne(struct pci_dev *pdev)
+{
+ int8_t i;
+ struct net_device *pNetDev = pci_get_drvdata(pdev);
+
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = NETDEV_PRIV(pNetDev);
+
+ MXL_MOCA_DBG1P2("%s: pdev: 0x%p\n", __FUNCTION__, pdev);
+
+#if MXL_MOCA_PCIE_NAPI
+ napi_disable(&pDdc->napi);
+#endif
+
+ if (pDdc->pProcDir)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Removing proc entry\n");
+ remove_proc_entry(MXL_MOCA_PCIE_PROC_ENTRY_NAME, pDdc->pProcDir);
+ remove_proc_entry(pDdc->procDirName, NULL);
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 10, 0)
+ proc_remove(pDdc->pProcDir);
+#endif
+ pDdc->pProcDir = NULL;
+ }
+
+ for (i = 0; i < gNumMocaPcieDevices; i++)
+ {
+ if (gpDevData[i] == pDdc)
+ {
+ gpDevData[i] = NULL;
+ MXL_MOCA_DBG1P1("Removed MoCA-Ethernet board #%d.\n", i);
+
+ break;
+ }
+ }
+
+ /// Get the net device from the PCI device structure
+ if (!pNetDev)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "Net device is NULL\n");
+ return;
+ }
+
+ MXL_MOCA_DBG2P0( "Un-register IRQ handler\n");
+
+ /// Unregister interrupt handler
+ free_irq(pdev->irq, pNetDev);
+ //MXL_MOCA_DBG2P0( "done\n");
+
+ // Disable MSI
+ pci_disable_msi(pdev); // moved up // kernel BUG at /build/buildd/linux-2.6.31/drivers/pci/msi.c:668!
+ MXL_MOCA_DBG2P0( "pci_disable_msi done\n");
+
+ /// Unregister Linux net device
+ unregister_netdev(pNetDev);
+ MXL_MOCA_DBG2P0( "unregister_netdev done\n");
+
+ /// Free the net device
+ pci_disable_device(pdev);
+ MXL_MOCA_DBG2P0( "pci_disable_device done\n");
+
+ iounmap((void *)pDdc->baseIoRemap0);
+ iounmap((void *)pDdc->baseIoRemap1);
+ MXL_MOCA_DBG2P0( "iounmap done\n");
+
+ pci_release_regions(pdev);
+ MXL_MOCA_DBG2P0( "pci_release_regions done\n");
+
+ /// Terminate the Common Ethernet Module
+ MxL_MoCA_PCIeTerminate(pDdc);
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
+ /// pNetDev is not the allocation address anymore, can't use kfree() directly.
+ free_netdev(pNetDev);
+ MXL_MOCA_DBG2P0( "free_netdev done\n");
+#else
+ kfree(pNetDev);
+ MXL_MOCA_DBG2P0( "kfree done\n");
+#endif
+
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Done.\n\n");
+
+ ////// pci_set_drvdata(pdev, NULL);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeDumpQueues
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Dumps the rx or tx descriptor wueues. Useful for debugging.
+ *
+ * IN PARAMS : [idx] : device index.
+ * [type] : 0 = rx only; 1 = tx only; 2 = rx and tx .
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeDumpQueues(unsigned int idx, unsigned int type)
+{
+ int16_t i;
+ MXL_MOCA_PCIE_DATAPATH_CONTEXT_T* pDataPath;
+ MXL_MOCA_PCIE_QUEUE_PAIR_T* queuePair;
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T* pDdc;
+
+ pDdc = gpDevData[idx];
+ pDataPath = (MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *)pDdc->pDpCtx;
+
+ if (type == 0 || type == 2)
+ {
+ printk("============================ RX Queue ======================\n");
+ queuePair = &pDataPath->rxQueuePair;
+
+ printk("ridx = %d, widx = %d, lastPktsCnt = %d\n",
+ queuePair->descQueueReadIdx,
+ queuePair->descQueueWriteIdx,
+ queuePair->lastPktsCnt);
+
+ for (i = 0; i < (queuePair->descQueueSize); i++)
+ {
+ printk("[%04d]: w0=0x%x w1=0x%x plen=0x%x\n", i, (queuePair->pDescQueue[i].dword0 & 0x03),
+ queuePair->pDescQueue[i].dword1,
+ queuePair->pPktQueue[i].totalLen);
+
+ }
+ }
+
+ if (type == 1 || type == 2)
+ {
+ printk("============================ TX Queue ======================\n");
+ queuePair = &pDataPath->txQueuePair;
+
+ printk("ridx = %d, widx = %d, lastPktsCnt = %d\n",
+ queuePair->descQueueReadIdx,
+ queuePair->descQueueWriteIdx,
+ queuePair->lastPktsCnt);
+
+ for (i = 0; i < (queuePair->descQueueSize); i++) // descriptors are two dwords
+ {
+ printk("[%04d]: w0=0x%x w1=0x%x plen=0x%x\n", i, (queuePair->pDescQueue[i].dword0 & 0x03),
+ queuePair->pDescQueue[i].dword1,
+ queuePair->pPktQueue[i].totalLen);
+
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeWriteProc
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Proc Read operations.
+ * Proc read/write commands (usage from user space):
+ *
+ * DEBUG:
+ * ======
+ * 0)
+ * > echo 'h' > /proc/en%d/pcie
+ * Display usage
+ *
+ * 1)
+ * > echo 'd 0' > /proc/en%d/pcie
+ * Revert back to displaying tx and rx counters
+ * > cat /proc/en%d/pcie
+ * Display the tx/rx counters
+ *
+ * 2)
+ * > echo 'd 1' > /proc/en%d/pcie
+ * To clear rx counters
+ * > cat /proc/en%d/pcie
+ * Display the tx/rx counters (rx counts are reset)
+ *
+ * 3)
+ * > echo 'd 2' > /proc/en%d/pcie
+ * To clear tx counters
+ * > cat /proc/en%d/pcie
+ * Display the tx/rx counters (tx counts are reset)
+ *
+ * 4)
+ * > echo 'd 3' > /proc/en%d/pcie
+ * To clear tx and rx counters
+ * > cat /proc/en%d/pcie
+ * Display the tx/rx counters (tx and rx counts are reset)
+ *
+ * 5)
+ * > echo 'd 4' > /proc/en%d/pcie
+ * To output Rx descr queue info.
+ * > cat /proc/en%d/pcie
+ * > dmesg
+ * Displays the Rx descr queue
+ *
+ * 6)
+ * > echo 'd 5' > /proc/en%d/pcie
+ * To output Tx descr queue info.
+ * > cat /proc/en%d/pcie
+ * > dmesg
+ * Displays the Tx descr queue
+ *
+ * 7)
+ * > echo 'd 6' > /proc/en%d/pcie
+ * To displays the DMEM fixed locations
+ * > cat /proc/en%d/pcie
+ * > dmesg
+ * Displays the DMEM fixed locations (Host-to-SoC DMEM interface)
+ *
+ * 8)
+ * > echo 'd 7' > /proc/en%d/pcie
+ * Output outbound (EP to RC) iATU configurations
+ * > cat /proc/en%d/pcie
+ * > dmesg
+ * Displays the outbound iATU configurations
+ *
+ * << values 8 and 9 are reserved >>
+ *
+ * INFO:
+ * =====
+ * 1)
+ * > echo 'i 1' > /proc/en%d/pcie
+ * Display EP info.
+ * > dmesg
+ * Displays the capabilities and key config info (vendor/device ID).
+ *
+ *
+ *--------------------------------------------------------------------------------------*/
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
+static int MxL_MoCA_PCIeReadProc(char *pUserBuf, char **ppStart, off_t offset, int count, int *pEof, void *data) // old kernel
+{
+#else
+static ssize_t MxL_MoCA_PCIeReadProc(struct file *pFile, char __user *pPage, size_t len, loff_t* pOffset)
+{
+#endif
+ int8_t idx, loop;
+ uint32_t regions;
+ unsigned int* p;
+ MXL_MOCA_PCIE_DATAPATH_CONTEXT_T* pDataPath;
+ MXL_MOCA_PCIE_QUEUE_PAIR_T* queuePair;
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T* pDdc;
+ uint32_t val = 0;
+ int16_t num = 0;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
+#else
+ char* pUserBuf = gProcFsBuffer;
+#endif
+
+#if MXL_MOCA_PCIE_NAPI
+ const int8_t intrModeStr[] = "[NAPI]";
+ const int8_t intrHandlerStr[] = "[NAPI Polls]";
+#else
+ const int8_t intrModeStr[] = " "; // non-NAPI
+ const int8_t intrHandlerStr[] = "Interrupts]";
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
+ static int finished = 0;
+#endif
+
+ idx=0;
+ for (idx = 0; idx < gNumMocaPcieDevices; idx++)
+ {
+ pDdc = gpDevData[idx];
+ pDataPath = (MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *)pDdc->pDpCtx;
+
+ switch (pDdc->readProcMode)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ {
+ p = (unsigned int*) &pDdc->rxStats;
+
+ num += sprintf(pUserBuf + num, "\n === ingress ==>\n");
+ num += sprintf(pUserBuf + num, "|--------| |----------------| |-----------|\n");
+ num += sprintf(pUserBuf + num, "| |------>|RX Host TX|------->| |\n");
+ num += sprintf(pUserBuf + num, "| Upper | | MxL PCIe | PCIe | MxL37xx |\n");
+ num += sprintf(pUserBuf + num, "| layers | | EP Drv | Link | (PCIe EP) | <=Coax=>\n");
+ num += sprintf(pUserBuf + num, "| |<------|TX RX|<-------| |\n");
+ num += sprintf(pUserBuf + num, "|--------| |----------------| |-----------|\n");
+ num += sprintf(pUserBuf + num, " <== egress ====\n\n");
+ num += sprintf(pUserBuf + num, "RX Stats:-----------------------------\n");
+ num += sprintf(pUserBuf + num, "%sRX(egress) Pkts Good : %u\n%sTX(egress) Pkts Good : %u\n%sTX(egress) Pkts Dropped: %u\n",
+ intrModeStr, p[0], " ", p[1], " ", p[2]);
+
+ num += sprintf(pUserBuf + num, "TX Stats:-----------------------------\n");
+
+
+ p = (unsigned int*) &pDdc->txStats;
+ val = 0;
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (PCIE_TX_NUM_PKTS * 4), &val);
+ num += sprintf(pUserBuf + num, "%sRX(ingress) Pkts Good : %u\n%sTX(ingress) Pkts Good : %u\n%sTX(ingress) Pkts Dropped: %u\n", " ", p[0], " ", val, " ", p[2]);
+ num += sprintf(pUserBuf + num, "--------------------------------------\n");
+#if MXL_MOCA_PCIE_NAPI
+ num += sprintf(pUserBuf + num, "%s: %u \n", intrHandlerStr, pDdc->polls);
+ num += sprintf(pUserBuf + num, "%s: %u \n", (pDdc->inbandIntrType == PCIE_INTR_TYPE_MSI)?"[MSI]":"[INTA]", pDdc->interrupts);
+#else
+ num += sprintf(pUserBuf + num, "%s%s: %u \n", (pDdc->inbandIntrType == PCIE_INTR_TYPE_MSI)?"[MSI/":"[INTA/", intrHandlerStr, pDdc->interrupts);
+#endif
+ queuePair = &pDataPath->rxQueuePair;
+ num += sprintf(pUserBuf + num, "RX (ridx, widx) = (%d, %d) \n",
+ queuePair->descQueueReadIdx, queuePair->descQueueWriteIdx);
+
+ queuePair = &pDataPath->txQueuePair;
+ num += sprintf(pUserBuf + num, "TX (ridx, widx) = (%d, %d) \n",
+ queuePair->descQueueReadIdx, queuePair->descQueueWriteIdx);
+ num += sprintf(pUserBuf + num, "Mapping errors: Rx(%u), Q(%u), Tx(%u). skb alloc errors: %u\n",
+ pDdc->mappingErr0, pDdc->mappingErr1, pDdc->mappingErr2, pDdc->skbAllocErr);
+ }
+ break;
+
+ case 4:
+ MxL_MoCA_PCIeDumpQueues(idx, 0);
+ break;
+
+ case 5:
+ MxL_MoCA_PCIeDumpQueues(idx, 1);
+ break;
+
+ case 6:
+ {
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (P_PCIE_HOST_RX_DESC_QUEUE * 4), &val);
+ num += sprintf(pUserBuf + num, "P_PCIE_HOST_RX_DESC_QUEUE[0x%x](0x%x)=0x%x\n", P_PCIE_HOST_RX_DESC_QUEUE, pDdc->dmemBaseAddr + (P_PCIE_HOST_RX_DESC_QUEUE * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (P_PCIE_HOST_RX_DESC_Q_LEN * 4), &val);
+ num += sprintf(pUserBuf + num, "P_PCIE_HOST_RX_DESC_Q_LEN[0x%x](0x%x)=0x%x\n", P_PCIE_HOST_RX_DESC_Q_LEN, pDdc->dmemBaseAddr + (P_PCIE_HOST_RX_DESC_Q_LEN * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (P_PCIE_HOST_TX_DESC_QUEUE * 4), &val);
+ num += sprintf(pUserBuf + num, "P_PCIE_HOST_TX_DESC_QUEUE[0x%x](0x%x)=0x%x\n", P_PCIE_HOST_TX_DESC_QUEUE, pDdc->dmemBaseAddr + (P_PCIE_HOST_TX_DESC_QUEUE * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (P_PCIE_HOST_TX_DESC_Q_LEN * 4), &val);
+ num += sprintf(pUserBuf + num, "P_PCIE_HOST_TX_DESC_Q_LEN[0x%x](0x%x)=0x%x\n", P_PCIE_HOST_TX_DESC_Q_LEN, pDdc->dmemBaseAddr + (P_PCIE_HOST_TX_DESC_Q_LEN * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (PCIE_TC_MGMT_IF_MAC_ADDR * 4), &val);
+ num += sprintf(pUserBuf + num, "PCIE_TC_MGMT_IF_MAC_ADDR0[0x%x](0x%x)=0x%x\n", PCIE_TC_MGMT_IF_MAC_ADDR, pDdc->dmemBaseAddr + (PCIE_TC_MGMT_IF_MAC_ADDR * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + ((PCIE_TC_MGMT_IF_MAC_ADDR+1) * 4), &val);
+ num += sprintf(pUserBuf + num, "PCIE_TC_MGMT_IF_MAC_ADDR1[0x%x](0x%x)=0x%x\n", PCIE_TC_MGMT_IF_MAC_ADDR, pDdc->dmemBaseAddr + ((PCIE_TC_MGMT_IF_MAC_ADDR+1) * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (PCIE_NUM_OUTBOUND_REGIONS * 4), &val);
+ num += sprintf(pUserBuf + num, "PCIE_NUM_OUTBOUND_REGIONS[0x%x](0x%x)=0x%x\n", PCIE_NUM_OUTBOUND_REGIONS, pDdc->dmemBaseAddr + (PCIE_NUM_OUTBOUND_REGIONS * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG0_BASE * 4), &val);
+ num += sprintf(pUserBuf + num, "PCIE_OUTBOUND_ATU_REG0_BASE[0x%x](0x%x)=0x%x\n", PCIE_OUTBOUND_ATU_REG0_BASE, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG0_BASE * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG1_BASE * 4), &val);
+ num += sprintf(pUserBuf + num, "PCIE_OUTBOUND_ATU_REG1_BASE[0x%x](0x%x)=0x%x\n", PCIE_OUTBOUND_ATU_REG1_BASE, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG1_BASE * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG2_BASE * 4), &val);
+ num += sprintf(pUserBuf + num, "PCIE_OUTBOUND_ATU_REG2_BASE[0x%x](0x%x)=0x%x\n", PCIE_OUTBOUND_ATU_REG2_BASE, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG2_BASE * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG3_BASE * 4), &val);
+ num += sprintf(pUserBuf + num, "PCIE_OUTBOUND_ATU_REG3_BASE[0x%x](0x%x)=0x%x\n", PCIE_OUTBOUND_ATU_REG3_BASE, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_REG3_BASE * 4), val);
+
+ // ToDo: Add TARGET addresses here when CAR-1141 is fixed.
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_TAR0_BASE * 4), &val);
+ num += sprintf(pUserBuf + num, "PCIE_OUTBOUND_ATU_TAR0_BASE[0x%x](0x%x)=0x%x\n", PCIE_OUTBOUND_ATU_TAR0_BASE, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_TAR0_BASE * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_TAR1_BASE * 4), &val);
+ num += sprintf(pUserBuf + num, "PCIE_OUTBOUND_ATU_TAR1_BASE[0x%x](0x%x)=0x%x\n", PCIE_OUTBOUND_ATU_TAR1_BASE, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_TAR1_BASE * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_TAR2_BASE * 4), &val);
+ num += sprintf(pUserBuf + num, "PCIE_OUTBOUND_ATU_TAR2_BASE[0x%x](0x%x)=0x%x\n", PCIE_OUTBOUND_ATU_TAR2_BASE, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_TAR2_BASE * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_TAR3_BASE * 4), &val);
+ num += sprintf(pUserBuf + num, "PCIE_OUTBOUND_ATU_TAR3_BASE[0x%x](0x%x)=0x%x\n", PCIE_OUTBOUND_ATU_TAR3_BASE, pDdc->dmemBaseAddr + (PCIE_OUTBOUND_ATU_TAR3_BASE * 4), val);
+
+ // Capabilities
+ MxL_MoCA_PCIeRead (idx, (pDdc->dmemBaseAddr + (PCIE_DEVCTL_MAX_PAYLOAD_SIZE * 4)), &val);
+ num += sprintf(pUserBuf + num, "PCIE_DEVCTL_MAX_PAYLOAD_SIZE[0x%x](0x%x)=0x%x\n", PCIE_DEVCTL_MAX_PAYLOAD_SIZE, pDdc->dmemBaseAddr + (PCIE_DEVCTL_MAX_PAYLOAD_SIZE * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, (pDdc->dmemBaseAddr + (PCIE_LNKCTL_RCB * 4)), &val);
+ num += sprintf(pUserBuf + num, "PCIE_LNKCTL_RCB[0x%x](0x%x)=0x%x\n", PCIE_LNKCTL_RCB, pDdc->dmemBaseAddr + (PCIE_LNKCTL_RCB * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, (pDdc->dmemBaseAddr + (PCIE_EN_CCPU_TIMER_INTR * 4)), &val);
+ num += sprintf(pUserBuf + num, "PCIE_EN_CCPU_TIMER_INTR[0x%x](0x%x)=0x%x\n", PCIE_EN_CCPU_TIMER_INTR, pDdc->dmemBaseAddr + (PCIE_EN_CCPU_TIMER_INTR * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, (pDdc->dmemBaseAddr + (PCIE_DMA_DATA_ACCESS_BYTE_ORDER * 4)), &val);
+ num += sprintf(pUserBuf + num, "PCIE_DMA_DATA_ACCESS_BYTE_ORDER[0x%x](0x%x)=0x%x\n", PCIE_DMA_DATA_ACCESS_BYTE_ORDER, pDdc->dmemBaseAddr + (PCIE_DMA_DATA_ACCESS_BYTE_ORDER * 4), val);
+
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (PCIE_HOST_STATUS * 4), &val);
+ num += sprintf(pUserBuf + num, "PCIE_HOST_STATUS[0x%x](0x%x)=0x%x\n", PCIE_HOST_STATUS, pDdc->dmemBaseAddr + (PCIE_HOST_STATUS * 4), val);
+ }
+ break;
+
+ case 7:
+ {
+ MxL_MoCA_PCIeRead (idx, pDdc->dmemBaseAddr + (PCIE_NUM_OUTBOUND_REGIONS * 4), &regions);
+
+ if (regions > 4)
+ {
+ regions = 4;
+ }
+
+ for (loop = 0; loop < regions; loop++)
+ {
+ MxL_MoCA_PCIeWrite(idx, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_INDEX_REG), loop); // 0x900
+ num += sprintf(pUserBuf + num, "PCIE_EP_IATU_INDEX_REG=0x%x\n", loop);
+
+ // 0820490c : iATU Region Lower Base Address Register
+ MxL_MoCA_PCIeRead(idx, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_REG), &val);
+ num += sprintf(pUserBuf + num, "PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_REG=0x%x\n", val);
+
+ // 08204914 : iATU Region Limit Address Register (inbound)
+ MxL_MoCA_PCIeRead(idx, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_REGION_LIMIT_ADDR_REG), &val);
+ num += sprintf(pUserBuf + num, "PCIE_EP_IATU_REGION_LIMIT_ADDR_REG=0x%x\n", val);
+
+ // 08204918 : iATU Region Lower Target Address Register. Correct target address register need to be specified by host
+ MxL_MoCA_PCIeRead(idx, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_REG), &val);
+ num += sprintf(pUserBuf + num, "PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_REG=0x%x\n", val);
+
+ // 08204908 : iATU Region Control 2 Register - enable for addr match
+ MxL_MoCA_PCIeRead(idx, (uintptr_t)(MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_2_REG), &val);// REGION_EN = 1
+ num += sprintf(pUserBuf + num, "PCIE_EP_IATU_REGION_CTRL_2_REG=0x%x\n", val);
+ }
+ // Constants
+ num += sprintf(pUserBuf + num, "iATU region addresses:\nOUTB_ATU_TARGET0_ADDR_START =0x%x\n", MXL_MOCA_PCIE_OUTB_ATU_TARGET0_ADDR_MASK);
+ num += sprintf(pUserBuf + num, "OUTB_ATU_TARGET0_ADDR_END =0x%x\n", MXL_MOCA_PCIE_OUTB_ATU_TARGET0_ADDR_LIMIT);
+ num += sprintf(pUserBuf + num, "OUTB_ATU_TARGET1_ADDR_START=0x%x\n", MXL_MOCA_PCIE_OUTB_ATU_TARGET1_ADDR_MASK);
+ num += sprintf(pUserBuf + num, "OUTB_ATU_TARGET1_ADDR_END =0x%x\n", MXL_MOCA_PCIE_OUTB_ATU_TARGET1_ADDR_LIMIT);
+ }
+ break;
+
+#if MXL_MOCA_PCIE_EN_PROC_DBG
+ case 8: /* for debug - add any function call or print statement here. See MxL_MoCA_PCIeWriteProc() to enable this case */
+ MxL_MoCA_PCIeDevPmSuspend(&(pDdc->pPCIeDev->dev));
+ break;
+
+ case 9:
+ MxL_MoCA_PCIeDevPmResume(&(pDdc->pPCIeDev->dev));
+ break;
+#endif
+
+ default:
+ break;
+ }
+ }
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
+ return num;
+#else
+ /*
+ * We return 0 to indicate end of file, that we have
+ * no more information. Otherwise, processes will
+ * continue to read from us in an endless loop.
+ */
+ if ( finished )
+ {
+ finished = 0;
+ return 0;
+ }
+
+ finished = 1;
+
+ /*
+ * We use put_to_user to copy the string from the kernel's
+ * memory segment to the memory segment of the process
+ * that called us. get_from_user, BTW, is used for the reverse.
+ */
+ if ( copy_to_user(pPage, gProcFsBuffer, num) ) // pDst, src
+ {
+ return -EFAULT;
+ }
+ return num; /* Return the number of bytes "read" */
+#endif
+}
+
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeWriteProc
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Proc Write operations.
+ * Proc commands (usage from user space):
+ * ( See description section of MxL_MoCA_PCIeReadProc)
+ *
+ *
+ *--------------------------------------------------------------------------------------*/
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
+int MxL_MoCA_PCIeWriteProc(struct file *pFile, const char *pBuffer, unsigned long count, void *data) // old kernel
+{
+#else
+ssize_t MxL_MoCA_PCIeWriteProc(struct file *pFile, const char __user *pBuffer, size_t count, loff_t* pOffset) // new kernel
+{
+ int num = 0;
+#endif
+ int8_t debug;
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T*)gpDevData[0];
+ MXL_MOCA_PCIE_DATAPATH_CONTEXT_T* pDataPath;
+ uint32_t* p;
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
+ if (!count)
+ return 0;
+#else
+ if ( count > MXL_MOCA_PROCFS_MAX_SIZE )
+ {
+ num = MXL_MOCA_PROCFS_MAX_SIZE;
+ }
+ else
+ {
+ num = count;
+ }
+#endif
+
+ if (pBuffer[0] == 'd') /* Debug commands */
+ {
+ debug = simple_strtol(pBuffer+2, 0, 10);
+
+#if MXL_MOCA_PCIE_EN_PROC_DBG
+ if (debug > 9)
+#else
+ if (debug > 13)
+#endif
+ {
+ printk("invalid debug param: %d\n", debug);
+ debug = 0;
+ }
+ pDdc->readProcMode = debug;
+
+ pDataPath = (MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *)pDdc->pDpCtx;
+
+ switch(debug)
+ {
+ case 1:
+ p = (uint32_t*) &pDdc->rxStats;
+ p[0] = p[1] = p[2] = p[3] = 0;
+ break;
+
+ case 2:
+ p = (uint32_t*) &pDdc->txStats;
+ p[0] = p[1] = p[2] = p[3] = p[4] = p[5] = 0;
+ MxL_MoCA_PCIeWrite(0, pDdc->dmemBaseAddr + (PCIE_TX_NUM_PKTS * 4), 0); // devIndex = 0, assuming a single device
+ break;
+
+ case 3:
+ p = (uint32_t*) &pDdc->rxStats;
+ p[0] = p[1] = p[2] = p[3] = 0;
+ p = (uint32_t*) &pDdc->txStats; // was unsigned int
+ p[0] = p[1] = p[2] = p[3] = p[4] = p[5] = 0;
+ MxL_MoCA_PCIeWrite(0, pDdc->dmemBaseAddr + (PCIE_TX_NUM_PKTS * 4), 0);
+ pDdc->interrupts = 0;
+#if MXL_MOCA_PCIE_NAPI
+ pDdc->polls = 0;
+#endif
+ break;
+
+ default:
+ break;
+ }
+ }
+ else if (pBuffer[0] == 'i') /* Info commands */
+ {
+ printk ("PCI_EXP_DEVCAP:MaxPayLoadSize = %d\n", pDdc->devCapMaxPayloadSz);
+ printk ("PCI_EXP_DEVCTL:MaxPayLoadSize = %d, MaxReadReq = %d\n", pDdc->devCtlMaxPayloadSz, pDdc->devCtlMaxReadReqSz);
+
+ /* Supported Link Speeds, Maximum Link Width */
+ printk ("PCI_EXP_LNKCAP:MaxLinkSpeed(1=2.5GT/s, 2=5GT/s, 4=8GT/s) = %d, MaxLinkWidth = x%d\n",
+ pDdc->lnkCapMaxLnkSpeed, pDdc->lnkCapMaxLinkWidth);
+
+ /* Read Completion Boundary */
+ printk ("PCI_EXP_LNKCTL:RCB = %d\n", pDdc->lnkCtlRCB);
+
+ /* Current Link Speed, Negotiated Link Width */
+ printk ("PCI_EXP_LNKSTA:MaxLinkSpeed(1=2.5GT/s, 2=5GT/s, 3=8GT/s) = %d, MaxLinkWidth = x%d\n\n",
+ pDdc->lnkStaMaxLnkSpeed, pDdc->lnkStaMaxLinkWidth);
+ }
+ else if (pBuffer[0] == 't') /* tx */
+ {
+ debug = simple_strtol(pBuffer+2, 0, 10);
+ switch (debug)
+ {
+ case 0:
+ case 1:
+#if MXL_MOCA_PCIE_DEBUG_DROP_TX
+ printk ("Drop TX flag = %d:\n", debug);
+ pDdc->dbg_drop_tx = debug;
+#else
+ printk("TX pkt drop debug code is not enabled!\n");
+#endif
+ break;
+
+ default:
+ break;
+ }
+
+ }
+ else if (pBuffer[0] == 'r') /* rx */
+ {
+ debug = simple_strtol(pBuffer+2, 0, 10);
+ switch (debug)
+ {
+ case 0:
+ case 1:
+ case 2:
+#if MXL_MOCA_PCIE_DEBUG_DROP_RX
+ printk ("Drop RX flag = %d:\n", debug);
+ pDdc->dbg_drop_rx = debug;
+#else
+ printk("RX pkt drop debug code is not enabled!\n");
+#endif
+ break;
+
+ default:
+#if MXL_MOCA_PCIE_DEBUG_DROP_RX
+ pDdc->dbg_drop_rx = 0;
+#endif
+ break;
+ }
+ }
+ else if (pBuffer[0] == 'h') /* help */
+ {
+ printk ("DEBUG:\n");
+ printk ("======\n");
+ printk ("> echo 'd 0' > /proc/%s/pcie\n" \
+ "Revert back to displaying tx and rx counters\n" \
+ "> cat /proc/%s/pcie\n" \
+ "Display the tx/rx counters\n\n", pDdc->procDirName, pDdc->procDirName);
+
+ printk ("> echo 'd 1' > /proc/%s/pcie\n" \
+ "To clear rx counters\n" \
+ "> cat /proc/%s/pcie\n" \
+ "Display the tx/rx counters (rx counts are reset)\n\n", pDdc->procDirName, pDdc->procDirName);
+
+ printk ("> echo 'd 2' > /proc/%s/pcie\n" \
+ "To clear tx counters\n" \
+ "> cat /proc/%s/pcie\n" \
+ "Display the tx/rx counters (tx counts are reset)\n\n", pDdc->procDirName, pDdc->procDirName);
+
+ printk ("> echo 'd 3' > /proc/%s/pcie\n" \
+ "To clear tx and rx counters\n" \
+ "> cat /proc/%s/pcie\n" \
+ "Display the tx/rx counters (tx and rx counts are reset)\n\n", pDdc->procDirName, pDdc->procDirName);
+
+ printk ("> echo 'd 4' > /proc/%s/pcie\n" \
+ "To output Rx descr queue info.\n" \
+ "> cat /proc/%s/pcie\n" \
+ "> dmesg\n" \
+ "Displays the Rx descr queue\n\n", pDdc->procDirName, pDdc->procDirName);
+
+ printk ("> echo 'd 5' > /proc/%s/pcie\n" \
+ "To output Tx descr queue info.\n" \
+ "> cat /proc/%s/pcie\n" \
+ "> dmesg\n" \
+ "Displays the Tx descr queue\n\n", pDdc->procDirName, pDdc->procDirName);
+
+ printk ("> echo 'd 6' > /proc/%s/pcie\n" \
+ "To displays the DMEM fixed locations\n" \
+ "> cat /proc/%s/pcie\n" \
+ "> dmesg\n" \
+ "Displays the DMEM fixed locations (Host-to-SoC DMEM interface)\n\n", pDdc->procDirName, pDdc->procDirName);
+
+ printk ("> echo 'd 7' > /proc/%s/pcie\n" \
+ "Output outbound (EP to RC) iATU configurations\n" \
+ "> cat /proc/%s/pcie\n" \
+ "> dmesg\n" \
+ "Displays the outbound iATU configurations\n\n", pDdc->procDirName, pDdc->procDirName);
+
+ // << values 8 and 9 are reserved for internal use >>
+
+ // "Allow 1 packet every 32 packets (received from upper layers) in TX (Host to SoC) direction\n"
+ // "Set the second param to 1 to enable drop packets\n"
+ printk ("> echo 't 0' > /proc/%s/pcie\nor\n" \
+ "> echo 't 1' > /proc/%s/pcie\n" \
+ "0: (default)Allow all packets in TX (received from upper layers) in TX (Host to SoC) direction\n" \
+ "1: Drop all packets in TX (received from upper layers) in TX (Host to SoC) direction\n" \
+ "> dmesg\n" \
+ "Displays the flag was set\n\n", pDdc->procDirName, pDdc->procDirName);
+
+ // "Allow 1 packet every 32 packets in RX (SoC to Host) direction (not sending to upper layers)\n"
+ // "Set the second param to 1 to enable drop packets\n"
+ printk ("> echo 'r 0' > /proc/%s/pcie\nor\n" \
+ "> echo 'r 1' > /proc/%s/pcie\n" \
+ "> echo 'r 2' > /proc/%s/pcie\n" \
+ "0: (default)Allow all packets in RX (SoC to Host) direction (not sending to upper layers)\n" \
+ "1: Drop all packets in RX (SoC to Host) direction (not sending to upper layers but freeing and re-allocating skb)\n" \
+ "2: Drop all packets in RX (SoC to Host) direction (not sending to upper layers and not releasing the skb)\n" \
+ "> dmesg\n" \
+ "Displays the flag was set\n\n", pDdc->procDirName, pDdc->procDirName, pDdc->procDirName);
+
+ printk ("INFO:\n");
+ printk ("=====\n");
+ printk ("> echo 'i 1' > /proc/%s/pcie\n" \
+ "Display EP info.\n" \
+ "> dmesg\n" \
+ "Displays the capabilities and key config info (vendor/device ID).\n\n", pDdc->procDirName);
+ }
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
+ return count;
+#else
+ printk(KERN_INFO "procfs_write: write %d bytes\n", num);
+ return num;
+#endif
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeGetMgmtMAC
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Get the stored management MAC address from the net_device
+ *
+ * IN PARAMS : [*pDdc]: Device driver context.
+ *
+ * OUT PARAMS : [*mac] : pointer to array of 2 DWORDs to return the MAC address.
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeGetMgmtMAC(MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc, uint32_t* pMac)
+{
+ if (pDdc != 0)
+ {
+ pMac[0] = pDdc->mgmtIfMacAddr[0];
+ pMac[1] = pDdc->mgmtIfMacAddr[1];
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "NULL Pointer (pDdc)\n");
+ }
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeSetMgmtMAC
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Specify the device MAC address
+ *
+ * IN PARAMS : [devIndex] : device index.
+ * [*mac] : array of 2 DWORDs to provide the MAC address.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+ // interface
+void MxL_MoCA_PCIeSetMgmtMAC(int8_t devIndex, uint32_t* pMac)
+{
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = (MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T*)gpDevData[devIndex];
+ struct net_device *pNetDev = pci_get_drvdata(pDdc->pPCIeDev); // pNetDev ?
+ unsigned int macHigh, macLow;
+
+ macHigh = pDdc->mgmtIfMacAddr[0] = pMac[0];
+ macLow = pDdc->mgmtIfMacAddr[1] = pMac[1];
+
+ // shift out the hi and low words to be endian-agnostic
+ pNetDev->dev_addr[0] = (uint8_t) ((macHigh >> 24) & 0xff);
+ pNetDev->dev_addr[1] = (uint8_t) ((macHigh >> 16) & 0xff);
+ pNetDev->dev_addr[2] = (uint8_t) ((macHigh >> 8) & 0xff);
+ pNetDev->dev_addr[3] = (uint8_t) ((macHigh ) & 0xff);
+ pNetDev->dev_addr[4] = (uint8_t) ((macLow >> 24) & 0xff);
+ pNetDev->dev_addr[5] = (uint8_t) ((macLow >> 16) & 0xff);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeStopXmit
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Stop transmit
+ *
+ * IN PARAMS : [*arg] : pointer to net_device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeStopXmit(void* arg)
+{
+ struct net_device *pNetDev;
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc;
+ MXL_MOCA_DBG1P0("**** MxL_MoCA_PCIeStopXmit ....\n");
+
+ pNetDev = (struct net_device *)arg;
+
+ pDdc = NETDEV_PRIV(pNetDev);
+
+ MxL_MoCA_PCIeLockIrqSave(&pDdc->ethTxLock);
+ pDdc->active = 0;
+ MxL_MoCA_PCIeUnLockIrqRestore(&pDdc->ethTxLock);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeStartXmit
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Start transmit
+ *
+ * IN PARAMS : [*arg] : pointer to net_device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeStartXmit(void* arg)
+{
+ struct net_device *pNetDev;
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc;
+ pNetDev = (struct net_device *)arg;
+
+ pDdc = NETDEV_PRIV(pNetDev);
+
+ MxL_MoCA_PCIeLockIrqSave(&pDdc->ethTxLock);
+ pDdc->active = 1;
+ MxL_MoCA_PCIeUnLockIrqRestore(&pDdc->ethTxLock);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeResetTxQueue
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Reset Tx queue
+ *
+ * IN PARAMS : [*arg] : pointer to net_device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_STATUS_E
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeResetTxQueue(void* arg)
+{
+ struct net_device *pNetDev;
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc;
+ uint16_t index;
+
+ pNetDev = (struct net_device *)arg;
+
+ MXL_MOCA_DBG1P0("Reseting TxQueue ...\n");
+
+ pDdc = NETDEV_PRIV(pNetDev);
+
+ MxL_MoCA_PCIeLockIrqSave(&pDdc->ethTxLock);
+
+ pDdc->txRingWrIndex = 0;
+ pDdc->txRingRdIndex = 0;
+
+ for (index = 0; index < MXL_MOCA_PCIE_TX_MAPPING_SIZE; index++)
+ {
+ if (pDdc->txRing[index].skb)
+ {
+ pci_unmap_single(pDdc->pPCIeDev, pDdc->txRing[index].mapping,
+ MXL_MOCA_PCIE_MAX_ETH_MTU_SIZE, PCI_DMA_TODEVICE);
+ //dev_kfree_skb(pDdc->txRing[index].skb);
+ dev_kfree_skb_any(pDdc->txRing[index].skb);
+ pDdc->txRing[index].skb = NULL;
+ }
+ }
+
+ MxL_MoCA_PCIeUnLockIrqRestore(&pDdc->ethTxLock);
+
+ return MXL_MOCA_OK;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeAllocRxBuffers
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Allocate static Rx buffers
+ *
+ * IN PARAMS : [*arg] : pointer to the struct net_device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_STATUS_E
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeAllocRxBuffers(void* arg)
+{
+ //MXL_MOCA_DBG2P0( "======= MxL_MoCA_PCIeAllocRxBuffers ...\n");
+ return MxL_MoCA_PCIeEnqueueRxBuffs((struct net_device *)arg);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeFreeRxBuffers
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Free RX buffers
+ *
+ * IN PARAMS : [*arg] : pointer to the struct net_device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeFreeRxBuffers(void* arg)
+{
+ struct net_device *pNetDev = (struct net_device *) arg;
+
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = NETDEV_PRIV(pNetDev);
+
+ unsigned int packetID;
+
+ //MXL_MOCA_DBG2P0( "======= MxL_MoCA_PCIeFreeRxBuffers ...\n");
+ for (packetID = 0; packetID < MXL_MOCA_PCIE_RX_RING_SIZE; packetID++)
+ {
+ if (pDdc->rxRing[packetID].skb)
+ {
+ pci_unmap_single(pDdc->pPCIeDev, pDdc->rxRing[packetID].mapping,
+ MXL_MOCA_PCIE_MAX_ETH_MTU_SIZE, PCI_DMA_FROMDEVICE);
+ //dev_kfree_skb(pDdc->rxRing[packetID].skb);
+ dev_kfree_skb_any(pDdc->rxRing[packetID].skb);
+ pDdc->rxRing[packetID].skb = NULL;
+ }
+ }
+
+ return MXL_MOCA_OK;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeEnqueueRxBuffs
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Allocates initial RX Queue buffers. These are required to be available
+ * since the packets are pushed from the SoC side (egress) as soon as the
+ * firmware starts running and packets are pending.
+ *
+ * IN PARAMS : [*pNetDev] : pointer to the struct net_device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_STATUS_E (MXL_MOCA_MEM_ALLOC_ERR, MXL_MOCA_OK, MXL_MOCA_ERR)
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeEnqueueRxBuffs(struct net_device *pNetDev)
+{
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = NETDEV_PRIV(pNetDev);
+ uint16_t loop;
+ struct sk_buff *skb;
+ dma_addr_t mapping;
+ int packetID;
+ MXL_MOCA_STATUS_E ret = MXL_MOCA_OK;
+
+ packetID = 0;
+
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG1, "Allocating Rx Queue buffers...\n");
+
+ for (loop = 0; loop < MXL_MOCA_PCIE_RX_RING_SIZE; loop++)
+ {
+ if (!(skb = dev_alloc_skb(MXL_MOCA_PCIE_MAX_ETH_RX_BUF_SIZE)))
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "%s: dev_alloc_skb failed\n", __FUNCTION__);
+ return MXL_MOCA_MEM_ALLOC_ERR; // Cause: -ENOMEM
+ }
+
+ pDdc->rxRing[packetID].skb = skb;
+ skb->dev = pNetDev;
+
+ /// Ethernet header alignment
+ skb_reserve(skb,0); // Do not use NET_IP_ALIGN
+
+ mapping = pci_map_single(pDdc->pPCIeDev, skb->data, MXL_MOCA_PCIE_MAX_ETH_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
+ if (unlikely(pci_dma_mapping_error(pDdc->pPCIeDev, mapping)))
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "EnqueueRxBuffs: dma_mapping error!\n");
+ pDdc->mappingErr1++;
+ dev_kfree_skb_any(skb);
+ pDdc->rxRing[packetID].skb = NULL;
+ ret = MXL_MOCA_ERR;
+ break;
+ }
+
+ pDdc->rxRing[packetID].mapping = mapping;
+ ret = MxL_MoCA_PCIeQueuePkt(&pDdc->pDpCtx->rxQueuePair, MXL_MOCA_PCIE_MAX_ETH_MTU_SIZE, mapping);
+
+ if (ret != MXL_MOCA_OK)
+ {
+ pci_unmap_single(pDdc->pPCIeDev, mapping, MXL_MOCA_PCIE_MAX_ETH_MTU_SIZE, PCI_DMA_FROMDEVICE);
+
+ dev_kfree_skb_any(skb);
+ pDdc->rxRing[packetID].skb = NULL;
+
+ break;
+ }
+ packetID++;
+ }
+ return ret;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeNetDevOpen
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Brings up the Ethernet interface. This is one of the net_device_ops.
+ *
+ * IN PARAMS : [*pNetDev] : pointer to the struct net_device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : return 0 if successful, <0 (Linux error code) if error
+ *
+ *--------------------------------------------------------------------------------------*/
+
+int MxL_MoCA_PCIeNetDevOpen(struct net_device *pNetDev)
+{
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = NETDEV_PRIV(pNetDev);
+
+ MXL_MOCA_DBG2P2("%s: %s\n", __FUNCTION__, pNetDev->name);
+
+ MxL_MoCA_PCIeLockIrqSave(&pDdc->ethTxLock);
+
+ /// Start Linux net interface
+ netif_carrier_on(pNetDev);
+ netif_start_queue(pNetDev);
+
+ pDdc->firstTime = true;
+ MxL_MoCA_PCIeUnLockIrqRestore(&pDdc->ethTxLock);
+
+ return (0);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeNetDevClose
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Shuts down the Ethernet interface. This is one of the net_device_ops
+ *
+ * IN PARAMS : [*pNetDev] : pointer to the struct net_device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : return 0 if successful, <0 (Linux error code) if error
+ *
+ *--------------------------------------------------------------------------------------*/
+
+int MxL_MoCA_PCIeNetDevClose(struct net_device *pNetDev)
+{
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = NETDEV_PRIV(pNetDev);
+ uint16_t packetID;
+ uint16_t index;
+
+ /*************************************************************************
+ * NEED TO STOP SOC FIRST
+ ************************************************************************/
+
+ MXL_MOCA_DBG2P2("%s: %s\n", __FUNCTION__, pNetDev->name);
+
+ MxL_MoCA_PCIeLockIrqSave(&pDdc->ethTxLock);
+ /// Stop Linux net interface
+ netif_stop_queue(pNetDev);
+
+ for(packetID = 0; packetID < MXL_MOCA_PCIE_RX_RING_SIZE; packetID++)
+ {
+ if (pDdc->rxRing[packetID].skb)
+ {
+ pci_unmap_single(pDdc->pPCIeDev, pDdc->rxRing[packetID].mapping,
+ MXL_MOCA_PCIE_MAX_ETH_MTU_SIZE, PCI_DMA_FROMDEVICE);
+ dev_kfree_skb_any(pDdc->rxRing[packetID].skb);
+ pDdc->rxRing[packetID].skb = NULL;
+ }
+ }
+
+ for(index = 0; index < MXL_MOCA_PCIE_TX_MAPPING_SIZE; index++)
+ {
+ if (pDdc->txRing[index].skb)
+ {
+ pci_unmap_single(pDdc->pPCIeDev, pDdc->txRing[index].mapping,
+ MXL_MOCA_PCIE_MAX_ETH_MTU_SIZE, PCI_DMA_TODEVICE);
+ //dev_kfree_skb(pDdc->txRing[index].skb);
+ dev_kfree_skb_any(pDdc->txRing[index].skb);
+ pDdc->txRing[index].skb = NULL;
+ }
+ }
+
+ MxL_MoCA_PCIeUnLockIrqRestore(&pDdc->ethTxLock);
+ return (0);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeNapiPoll
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : NAPI Poll function. Called by Kernel.
+ *
+ * IN PARAMS : [*p_napi] : pointer to the mapi struct.
+ * : [budget] : budget or unit of work to handle.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : pDdc->napiWorkDone
+ *
+ *--------------------------------------------------------------------------------------*/
+
+#if MXL_MOCA_PCIE_NAPI
+static int MxL_MoCA_PCIeNapiPoll(struct napi_struct *p_napi, int budget)
+{
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc;
+
+ pDdc = container_of(p_napi, MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T, napi);
+
+ pDdc->napiWorkDone = 0;
+
+#if MXL_MOCA_PCIE_DEBUG_DROP_RX
+ if (2 == pDdc->dbg_drop_rx)
+ {
+ MxL_MoCA_PCIeDebugHandleRxReturnOwnership(pDdc);
+ }
+ else
+#endif // MXL_MOCA_PCIE_DEBUG_DROP_RX
+ {
+ MxL_MoCA_PCIeHandleRxData(pDdc); /* will update pDdc->napiWorkDone */
+ }
+ MXL_MOCA_DBG2P3("%s %d %d\n", __FUNCTION__, budget, pDdc->napiWorkDone);
+
+ pDdc->polls++;
+
+ if (pDdc->napiWorkDone < budget)
+ {
+ /* Turn off polling */
+ napi_complete(p_napi);
+ pDdc->napiDisableIntr = 0;
+ }
+ else
+ {
+ MXL_MOCA_DBG2P0( "********* pDdc->napiWorkDone >= budget ********\n");
+ }
+ return pDdc->napiWorkDone;
+}
+#endif
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeStartXmitSkbs
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Sends a packet over the Ethernet interface. Invoked by stack.
+ *
+ * IN PARAMS : [*pNetDev] : Pointer to the net device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : MXL_MOCA_STATUS_E code.
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static MXL_MOCA_STATUS_E MxL_MoCA_PCIeStartXmitSkbs(struct net_device *pNetDev)
+{
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = NETDEV_PRIV(pNetDev);
+ dma_addr_t mapping;
+ uint16_t i, j;
+ MXL_MOCA_STATUS_E status = MXL_MOCA_OK;
+ struct sk_buff *skb;
+
+ MXL_MOCA_DBG2P2("%s: %s\n", __FUNCTION__, pNetDev->name);
+
+ i = pDdc->txRingRdIndex;
+ for (j = 0; j < MXL_MOCA_PCIE_TX_MAPPING_SIZE; i++, j++)
+ {
+ if (i >= MXL_MOCA_PCIE_TX_MAPPING_SIZE) i = 0;
+
+ if (i == pDdc->txRingWrIndex) break;
+
+ skb = pDdc->txRing[i].skb;
+ mapping = pDdc->txRing[i].mapping;
+
+ //MXL_MOCA_DBG2P3("xmit_skbs: packetID = %d, txRingWrIndex = %d, skb = %p\n", i, pDdc->txRingWrIndex, (long)skb);
+
+ // Should not happen.
+ if (skb == NULL)
+ {
+ MXL_MOCA_DBG2P2("*** MxL_MoCA_PCIeStartXmitSkbs: i = %d, txRingIndex = %d\n", i, pDdc->txRingWrIndex);
+
+ BUG();
+ break;
+ }
+
+ if (skb->len < MXL_MOCA_PCIE_MIN_ETH_MTU_SIZE_NO_FCS)
+ {
+ memset(skb->data+skb->len, 0, (MXL_MOCA_PCIE_MIN_ETH_MTU_SIZE_NO_FCS-skb->len));
+ status = MxL_MoCA_PCIeQueuePkt(&pDdc->pDpCtx->txQueuePair, MXL_MOCA_PCIE_MIN_ETH_MTU_SIZE_NO_FCS, mapping);
+ }
+ else
+ {
+ status = MxL_MoCA_PCIeQueuePkt(&pDdc->pDpCtx->txQueuePair, skb->len, mapping);
+ }
+
+ MXL_MOCA_DBG2P3("MxL_MoCA_PCIeStartXmitSkbs: packetID = %d, txRingWrIndex = %d, status = %d\n", i, pDdc->txRingWrIndex, status);
+
+ if (status == MXL_MOCA_NO_HOST_DESC_ERR)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "StartXmitSkbs: Out-of-descriptors\n");
+ break;
+ }
+
+ pDdc->txIntrCount++;
+ pDdc->txStats[4]++;
+ }
+
+ pDdc->txRingRdIndex = i;
+
+ pNetDev->trans_start = jiffies;
+
+ return status;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeNetDevStartXmit
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Sends a packet over the Ethernet interface. Called�by�the�protocol�stack.
+ * Declared�by�attaching�to�the�netdev�structure. This is one of the
+ * net_device_ops.
+ *
+ * IN PARAMS : [*skb] : Pointer to the socket buffer to send.
+ * : [*pNetDev] : Pointer to the net device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : return 0 if successful, <0 (Linux error code) if error
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static int MxL_MoCA_PCIeNetDevStartXmit(struct sk_buff *skb, struct net_device *pNetDev)
+{
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = NETDEV_PRIV(pNetDev);
+ dma_addr_t mapping;
+
+#if MXL_MOCA_PCIE_DEBUG_DROP_TX
+ if (1 == pDdc->dbg_drop_tx)
+ {
+ pDdc->txStats[0]++; // recieved from stack
+ pDdc->txStats[1]++;
+ pDdc->txStats[2]++; // dropped
+ dev_kfree_skb_any(skb);
+ return NETDEV_TX_OK;
+ }
+ else
+#endif
+ {
+ if (unlikely(skb->len <= 0) || (pDdc->busy == 1))
+ {
+ pDdc->txStats[1]++;
+ dev_kfree_skb_any(skb);
+ pDdc->txStats[2]++; // dropped
+ return NETDEV_TX_OK;
+ }
+ }
+
+ pDdc->txStats[0]++;
+
+ //�Map�a�tx�packet�ready�for�DMA
+ mapping = pci_map_single(pDdc->pPCIeDev, skb->data, skb->len, PCI_DMA_TODEVICE);
+ if (unlikely(pci_dma_mapping_error(pDdc->pPCIeDev, mapping)))
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "DevStartXmit: dma_mapping error!\n");
+ pDdc->mappingErr2++;
+ dev_kfree_skb_any(skb);
+ pDdc->txStats[2]++; // dropped
+ return NETDEV_TX_OK;
+ }
+ else
+ {
+ if (MxL_MoCA_PCIeCheckOutOfBoundMapping(mapping) == MXL_MOCA_ERR)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "(0x%x)DevStartXmit:out-of-bounds mapping error!\n", mapping);
+ pDdc->mappingErr2++;
+ dev_kfree_skb_any(skb);
+ pDdc->txStats[2]++; // dropped
+ return NETDEV_TX_OK;
+ }
+ }
+
+#if MXL_MOCA_ENABLE_DBG_MSG
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG2, "TX:(skb=%x) mapping = %x, few pkt bytes(from stack) length=%x [%2x %2x %2x %2x %2x %2x %2x %2x %2x %2x %2x %2x %2x %2x %2x %2x %2x %2x %2x %2x]\n",
+ skb->data, mapping, skb->len,
+ skb->data[0], skb->data[1], skb->data[2], skb->data[3],
+ skb->data[4], skb->data[5], skb->data[6], skb->data[7],
+ skb->data[8], skb->data[9], skb->data[10], skb->data[11],
+ skb->data[12], skb->data[13], skb->data[14], skb->data[14],
+ skb->data[15], skb->data[15], skb->data[17], skb->data[18]);
+#endif
+
+ MxL_MoCA_PCIeLockIrqSave(&pDdc->ethTxLock);
+
+ if (unlikely(pDdc->txRing[pDdc->txRingWrIndex].skb != NULL) ||
+ unlikely(!pDdc->active))
+ {
+ pDdc->txStats[2]++;
+ pDdc->ethStats.txDroppedErrs++;
+ pci_unmap_single(pDdc->pPCIeDev, mapping, skb->len, PCI_DMA_TODEVICE);
+ dev_kfree_skb(skb);
+ MxL_MoCA_PCIeUnLockIrqRestore(&pDdc->ethTxLock);
+
+ MXL_MOCA_DBG2P1("NETDEV_TX_OK txRingWrIndex (busy) = %d\n", pDdc->txRingWrIndex);
+ // pDdc->busy = 1; // For DEBUG
+
+ return NETDEV_TX_OK;
+ }
+ pDdc->txRing[pDdc->txRingWrIndex].skb = skb;
+ pDdc->txRing[pDdc->txRingWrIndex].mapping = mapping;
+
+ MXL_MOCA_DBG2P2("MxL_MoCA_PCIeNetDevStartXmit: txRingIndex = %d, skb = %p\n", pDdc->txRingWrIndex, (long)skb);
+
+ pDdc->txRingWrIndex++;
+ if (pDdc->txRingWrIndex >= MXL_MOCA_PCIE_TX_MAPPING_SIZE)
+ pDdc->txRingWrIndex = 0;
+
+ //MXL_MOCA_DBG2P4("%s: index = %d, txRingIndex = %d, skb = %p\n", __FUNCTION__, index, pDdc->txRingWrIndex, (long)skb);
+
+ pDdc->numPktsQueued++;
+ pDdc->txStats[3]++;
+
+ MxL_MoCA_PCIeStartXmitSkbs(pNetDev);
+ MxL_MoCA_PCIeUnLockIrqRestore(&pDdc->ethTxLock);
+
+ return NETDEV_TX_OK;
+}
+
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeNetDevTxTimeout
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Transmission Timeouts callback place holder. This is one of the
+ * net_device_ops
+ *
+ * IN PARAMS : [*skb] : Pointer to the socket buffer to send.
+ * : [*pNetDev] : Pointer to the net device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeNetDevTxTimeout(struct net_device *pNetDev)
+{
+ MXL_MOCA_DBG2P2("%s: %s\n", __FUNCTION__, pNetDev->name);
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeISR
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Interrupt service routine (MSI type) called by the kernel when
+ * a MSI is issued by the EP. Keep this function simple. No print statements.
+ *
+ * IN PARAMS : [irq] : Interrrupt number.
+ * : [p_dev_instance] : Pointer to a network interface device structure.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
+static irqreturn_t MxL_MoCA_PCIeISR(int irq, void *pNetDev)
+#else
+static irqreturn_t MxL_MoCA_PCIeISR(int irq, void *pNetDev, struct pt_regs *regs)
+#endif
+{
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = NETDEV_PRIV(pNetDev);
+ uint16_t valShort;
+
+ MXL_MOCA_PCIE_ETH_LOCK_T *lk = &pDdc->ethTxLock;
+
+ // MXL_MOCA_DBG2P1("%s: IRQ recieved!!!!\n", __FUNCTION__);
+
+ spin_lock(&lk->lockSpinLock);
+
+ /* Check if it is INTx and skip if it was not ASSERTED by our device */
+ if (pDdc->inbandIntrType == PCIE_INTR_TYPE_INTA)
+ {
+ pci_read_config_word(pDdc->pPCIeDev, PCI_STATUS, &valShort);
+ if (0 == (valShort & PCI_STATUS_INTERRUPT))
+ {
+ spin_unlock(&lk->lockSpinLock);
+ return IRQ_NONE;
+ }
+ }
+
+#if MXL_MOCA_PCIE_NAPI
+ if (pDdc->active)
+ {
+ MxL_MoCA_PCIeHandleTxData(pDdc);
+ if (pDdc->napiDisableIntr == 0)
+ {
+ // MXL_MOCA_DBG1P0("napi_schedule\n");
+ napi_schedule(&pDdc->napi);
+ // We increment polls count in MxL_MoCA_PCIeNapiPoll
+ pDdc->napiDisableIntr = 1;
+ }
+ }
+#else
+ /// call RX interrupt routine
+ if (pDdc->active)
+ {
+ // MXL_MOCA_DBG2P1( "No NAPI %d\n", pDdc->active);
+#if MXL_MOCA_PCIE_DEBUG_DROP_RX
+ if (2 == pDdc->dbg_drop_rx)
+ {
+ MxL_MoCA_PCIeDebugHandleRxReturnOwnership(pDdc);
+ }
+ else
+#endif // MXL_MOCA_PCIE_DEBUG_DROP_RX
+ {
+ MxL_MoCA_PCIeHandleRxData(pDdc);
+ }
+ MxL_MoCA_PCIeHandleTxData(pDdc);
+ }
+#endif
+ pDdc->interrupts++;
+
+ if (pDdc->inbandIntrType == PCIE_INTR_TYPE_INTA)
+ {
+ MxL_MoCA_PCIeWrite(pDdc->devIndex, MXL_MOCA_PCIE_EHI_CTRL_STAT_REG0, MXL_MOCA_PCIE_EHI_CTRL_STAT_REG0_INTX_DEASSERT);
+ }
+
+ spin_unlock(&lk->lockSpinLock);
+
+ return IRQ_HANDLED;
+}
+
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeNetDevSetRxMode
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Network rx mode setting function. This is one of the net_device_ops
+ *
+ * IN PARAMS : [*pNetDev] : Pointer to the struct net_device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeNetDevSetRxMode(struct net_device *pNetDev)
+{
+ pNetDev = pNetDev;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeNetDevGetStats
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Network device statistics gatherer. ifconfig from user space calls this.
+ * This is one of the net_device_ops.
+ *
+ * IN PARAMS : [*pNetDev] : Pointer to the struct net_device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static struct net_device_stats* MxL_MoCA_PCIeNetDevGetStats(struct net_device *pNetDev)
+{
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = NETDEV_PRIV(pNetDev);
+ MXL_MOCA_PCIE_ETH_STATS_T ethStats;
+
+ memcpy((void *)&ethStats, (void *)&pDdc->ethStats, sizeof(MXL_MOCA_PCIE_ETH_STATS_T));
+
+ /// then, update driver stats structure
+ pDdc->stats.rx_packets = ethStats.rxPackets; /** total packets received */
+ pDdc->stats.tx_packets = ethStats.txPackets; /** total packets transmitted */
+ pDdc->stats.rx_bytes = ethStats.rxBytes; /** total bytes received */
+ pDdc->stats.tx_bytes = ethStats.txBytes; /** total bytes transmitted */
+ pDdc->stats.rx_errors = ethStats.rxPacketErrs;
+ //+ ethStats.rxCrc32Errs; /* bad packets received */
+ pDdc->stats.tx_errors = ethStats.txPacketErrs; /** packet transmit problems */
+ //pDdc->stats.rx_dropped = ethStats.rxDroppedErrs; /** no space in linux buffers */
+ pDdc->stats.rx_dropped = pDdc->netIfRxDropped; /** no space in linux buffers */
+ pDdc->stats.tx_dropped = ethStats.txDroppedErrs;
+ pDdc->stats.multicast = ethStats.rxMulticastPackets; /** multicast packets received */
+ pDdc->stats.rx_length_errors = ethStats.rxLengthErrs;
+ pDdc->stats.rx_over_errors = 0;
+ pDdc->stats.rx_crc_errors = ethStats.rxCrc32Errs; /** recved pkt with crc error */
+ pDdc->stats.rx_frame_errors = ethStats.rxFrameHeaderErrs; /** recv'd frame alignment error */
+ pDdc->stats.rx_fifo_errors = ethStats.rxFifoFullErrs; /** recv'r fifo overrun */
+ pDdc->stats.tx_aborted_errors = ethStats.txCrc32Errs;
+ pDdc->stats.tx_fifo_errors = ethStats.txFifoFullErrs;
+
+ return &pDdc->stats;
+}
+
+/* ethtool ops */
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : netdev_ethtool_ioctl
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : ethtool handler
+ *
+ * IN PARAMS : [*pNetDev] : Pointer to the struct net_device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 4)
+int netdev_ethtool_ioctl(struct net_device *pNetDev, void *pUserAddr)
+{
+ u32 ethCmd;
+
+ MXL_MOCA_DBG2P0("ioctl codes here\n");
+
+ if (copy_from_user(&ethCmd, pUserAddr, sizeof(ethCmd)))
+ return -EFAULT;
+
+ switch (ethCmd)
+ {
+ case ETHTOOL_GDRVINFO:
+ {
+ struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO};
+ memcpy(info.driver, MXL_MOCA_PCIE_DRV_NAME, sizeof(MXL_MOCA_PCIE_DRV_NAME));
+ memcpy(info.version, VERSION_HOST_STR, sizeof(VERSION_HOST_STR));
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
+ /* slot_name does not exist on 2.6 */
+ info.bus_info[0] = 0;
+#else
+ {
+ MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T *pDdc = NETDEV_PRIV(pNetDev);
+ memcpy(info.bus_info, pDdc->pdev->slot_name, sizeof(pDdc->pdev->slot_name));
+ }
+#endif
+ if (copy_to_user(pUserAddr, &info, sizeof(info)))
+ return -EFAULT;
+
+ return 0;
+ }
+ } /* end switch */
+
+ return -EOPNOTSUPP;
+}
+
+#else /* 2.6.4 */
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeEthtoolGetDrvInfo
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : ethtool get link status
+ *
+ * IN PARAMS : [pNetDev] : Pointer to the struct net_device.
+ * [pDrvInfo] : Pointer to return the driver information
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+///After 2.6.4, it supports ethtool_ops, ethtool.h to check ethtool_ops struct
+// ethtool_ops
+static void MxL_MoCA_PCIeEthtoolGetDrvInfo(struct net_device *pNetDev,
+ struct ethtool_drvinfo *pDrvInfo)
+{
+ strncpy(pDrvInfo->driver, MXL_MOCA_PCIE_DRV_NAME, 32);
+ strncpy(pDrvInfo->version, VERSION_HOST_STR, 32);
+ strcpy(pDrvInfo->fw_version, "N/A");
+ pDrvInfo->bus_info[0] = 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeEthtoolGetLink
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : ethtool get link status
+ *
+ * IN PARAMS : [p_dev] : Pointer to the struct net_device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+// ethtool_ops
+unsigned int MxL_MoCA_PCIeEthtoolGetLink(struct net_device *pNetDev)
+{
+ return netif_carrier_ok(pNetDev) ? 1 : 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeSetEthToolVar
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : setup default ethtool ops
+ *
+ * IN PARAMS : [*pNetDev] : Pointer to the struct net_device.
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void MxL_MoCA_PCIeSetEthToolVar(struct net_device *pNetDev)
+{
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0)
+ SET_ETHTOOL_OPS(pNetDev, (struct ethtool_ops *)&gMxlMocaPcieEthtoolOps);
+#else
+ netdev_set_default_ethtool_ops(pNetDev, (struct ethtool_ops *)&gMxlMocaPcieEthtoolOps);
+#endif
+}
+
+#endif /* 2.6.4 */
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeModuleInit
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Driver main entry point. Called when driver load (insmod)
+ * Will call MxL_MoCA_PCIeProbeOne
+ *
+ * Vendor IDs:
+ * -----------
+ * MxL3701/MxL3706/MxL3609 : Cardiff
+ * Access - MxL3609.
+ * MoCA - MxL3701/MxL3706
+ *
+ * MxL3711/MxL3619" : Leucadia
+ * Access - MxL3619.
+ * MoCA - MxL3711
+ *
+ * IN PARAMS : None
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : 0 Registration was successful. !0 Registration failed
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static int __init MxL_MoCA_PCIeModuleInit(void)
+{
+ int ret_code;
+ uint8_t index, devNum;
+ uint32_t levelBackup = MXL_MOCA_PCIE_HOST_PRINTLOG_THRESHOLD;
+ struct pci_dev *p_pci_device = 0;
+ uint8_t found = 0;
+ static const int8_t *pErrorLevelStr[MXL_MOCA_PCIE_L_END] = {
+ "DEF",
+ "ERR",
+ "WARN",
+ "INFO",
+ "DBG_1",
+ "DBG_2"
+ };
+
+ MXL_MOCA_PCIE_HOST_PRINTLOG_THRESHOLD = MXL_MOCA_PCIE_L_DBG2;
+
+ for(index = 0; index < MXL_MOCA_PCIE_MAX_NUM_OF_PCIE_DEVICES; index++)
+ gpDevData[index] = NULL;
+
+ for (devNum = 0; devNum < MXL_MOCA_PCIE_MAX_NUM_OF_PCIE_DEVICES; devNum++)
+ {
+ p_pci_device = pci_get_device(MXL_MOCA_PCIE_VENDOR_ID, PCI_ANY_ID, p_pci_device);
+
+ if (p_pci_device == NULL)
+ {
+ break;
+ }
+ else
+ {
+ found++;
+ }
+ }
+
+ if (0 == found)
+ {
+ MxL_MoCA_PCIeDbgTrace( MXL_MOCA_PCIE_L_ERR, "No MoCA PCIe device(s) found!\n");
+#if MXLWARE_CONFIG_BOARD_ECA_9M_L3_NXP
+ moduleInitError = 1;
+ // NOTE: Return 0 to indicate success to avoid unknown symbols issue when control path driver is loaded.
+ // This is essential to support runtime ECA type detection.
+
+ return 0;
+#else // MVL platform: returning -1 will cause insmod to abort loading the driver
+ return -1;
+#endif
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "%d device(s) found\n", found);
+ }
+
+#if defined(__LP64__) || defined(_LP64)
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Host system type: 64 bits\n");
+#else
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Host system type: 32 bits\n");
+#endif
+
+#if MXL_MOCA_PCIE_NAPI
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "NAPI enabled\n");
+#else
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "NAPI not enabled\n");
+#endif
+
+ /* Command line set verbose level takes effect from here */
+ if (verbose >= MXL_MOCA_PCIE_L_END)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Verbose option range: %d - %d\n",
+ MXL_MOCA_PCIE_L_DEF, MXL_MOCA_PCIE_L_DBG2);
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Setting level=%s\n", pErrorLevelStr[MXL_MOCA_PCIE_L_INFO]);
+ MXL_MOCA_PCIE_HOST_PRINTLOG_THRESHOLD = levelBackup;
+ }
+ else if (verbose == MXL_MOCA_PCIE_L_DEF) /* Only errors and warnings */
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Setting default debug level(%s)\n", pErrorLevelStr[MXL_MOCA_PCIE_L_INFO]);
+ MXL_MOCA_PCIE_HOST_PRINTLOG_THRESHOLD = MXL_MOCA_PCIE_L_INFO;
+ }
+ else
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Setting debug level(%s)\n", pErrorLevelStr[verbose]);
+ MXL_MOCA_PCIE_HOST_PRINTLOG_THRESHOLD = verbose;
+ }
+
+ ret_code = pci_register_driver(&gMxlMocaPCIeDrv); /* Calls MxL_MoCA_PCIeProbeOne */
+
+ if (ret_code)
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_ERR, "%s: Module init failed: %d\n", MXL_MOCA_PCIE_DRV_NAME, ret_code);
+ }
+
+ return ret_code;
+}
+
+/*----------------------------------------------------------------------------------------
+ *
+ * FUNCTION NAME : MxL_MoCA_PCIeModuleExit
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * DESCRIPTION : Driver exit point. Called when driver unload (rmmod).
+ * Will call MxL_MoCA_PCIeRemoveOne
+ *
+ * IN PARAMS : None
+ *
+ * OUT PARAMS : None
+ *
+ * RETURN VALUE : None
+ *
+ *--------------------------------------------------------------------------------------*/
+
+static void __exit MxL_MoCA_PCIeModuleExit(void)
+{
+ if (MXL_MOCA_PCIE_HOST_PRINTLOG_THRESHOLD == MXL_MOCA_PCIE_L_DEF)
+ {
+ /* Report errors and warnings */
+ MXL_MOCA_PCIE_HOST_PRINTLOG_THRESHOLD = MXL_MOCA_PCIE_L_INFO;
+ }
+
+#if MXLWARE_CONFIG_BOARD_ECA_9M_L3_NXP
+ if (1 == moduleInitError) // Nothing to unregister
+ {
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "%s %s Unloaded\n", MXL_MOCA_PCIE_DRV_NAME, VERSION_HOST_STR);
+ return;
+ }
+#endif
+
+ MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_INFO, "Removing PCIe driver\n");
+ pci_unregister_driver(&gMxlMocaPCIeDrv);
+}
+
+/*******************************************************************************
+ * Control Plane Interface Function
+ ******************************************************************************/
+EXPORT_SYMBOL(MxL_MoCA_PCIeRead);
+EXPORT_SYMBOL(MxL_MoCA_PCIeWrite);
+EXPORT_SYMBOL(MxL_MoCA_PCIeAvailable);
+EXPORT_SYMBOL(MxL_MoCA_PCIeRestart);
+EXPORT_SYMBOL(MxL_MoCA_PCIeStop);
+EXPORT_SYMBOL(MxL_MoCA_PCIeSetMgmtMAC);
+EXPORT_SYMBOL(MxL_MoCA_PCIeGlobalResetSoC);
+
+/*******************************************************************************
+ * Kernel mode driver init and exit
+ ******************************************************************************/
+module_init(MxL_MoCA_PCIeModuleInit);
+module_exit(MxL_MoCA_PCIeModuleExit);
+
+/*******************************************************************************
+ * Kernel module identifications
+ ******************************************************************************/
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("MaxLinear SW Development Team");
+MODULE_DESCRIPTION("MxL37xx PCIe Driver"); // MxL3701 is Cardiff, MxL3711 is Leucadia
+
diff --git a/drivers/net/phy/mxl371x/mxl_moca_osal_pcie.h b/drivers/net/phy/mxl371x/mxl_moca_osal_pcie.h
new file mode 100644
index 000000000000..9f16f67b6ef4
--- /dev/null
+++ b/drivers/net/phy/mxl371x/mxl_moca_osal_pcie.h
@@ -0,0 +1,722 @@
+/*****************************************************************************************
+ *
+ * FILE NAME : mxl_moca_osal_pcie.h
+ *
+ *
+ *
+ * DATE CREATED : 03/25/2016
+ *
+ * LAST MODIFIED : %Name% @ %%/%%/%%
+ *
+ * DESCRIPTION : Linux PCIe/Ethernet Driver. This file contains constants and API
+ * definitions.
+ *
+ *
+ *****************************************************************************************
+ * This file is licensed under GNU General Public license.
+ *
+ * This file is free software: you can redistribute and/or modify it under the
+ * terms of the GNU General Public License, Version 2, as published by the Free
+ * Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but AS-IS and
+ * WITHOUT ANY WARRANTY; without even the implied warranties of MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT. Redistribution,
+ * except as permitted by the GNU General Public License is prohibited.
+ *
+ * You should have received a copy of the GNU General Public License, Version 2
+ * along with this file; if not, see <http://www.gnu.org/licenses/>.
+ *
+ *****************************************************************************************
+ * Copyright (c) 2016 MaxLinear, Inc. All rights reserved.
+ ****************************************************************************************/
+
+#ifndef __MXL_MOCA_OSAL_PCIE_H__
+#define __MXL_MOCA_OSAL_PCIE_H__
+
+/*******************************************************************************
+ * Includes
+ ******************************************************************************/
+#include <linux/version.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)
+//#include <linux/autoconf.h>
+#else
+#include <linux/config.h>
+#endif
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/pci_regs.h>
+#include <linux/pci-aspm.h>
+#include <linux/interrupt.h>
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31)
+#include <linux/pm.h>
+#include <linux/pm_wakeup.h>
+#include <linux/pm_runtime.h>
+#endif
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/spinlock.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/aer.h>
+#include <linux/pcieport_if.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>
+#include <linux/proc_fs.h>
+#include <linux/ctype.h>
+#include <linux/list.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+
+
+// Macros
+/*****************************************************************************************
+ * ECA specific
+ *****************************************************************************************/
+#ifndef MXLWARE_CONFIG_BOARD_ECA_9M_L3_NXP
+#define MXLWARE_CONFIG_BOARD_ECA_9M_L3_NXP 0
+#endif
+
+/*****************************************************************************************
+ * Debug
+ *****************************************************************************************/
+#define MXL_MOCA_PCIE_DEBUG_DESCR 0
+#define MXL_MOCA_PCIE_DEBUG_DROP_TX 0 // Enable this to test TX packet drop feature
+#define MXL_MOCA_PCIE_DEBUG_DROP_RX 0 // Enable this to test RX packet drop feature
+
+
+/*****************************************************************************************
+ * Driver
+ *****************************************************************************************/
+#define MXL_MOCA_PCIE_DRV_NAME "mxl_moca_pcie"
+#define MXL_MOCA_PCIE_DEV_NAME "en%d"
+#define MXL_MOCA_PCIE_PROC_DIR_NAME "en%d"
+#define MXL_MOCA_PCIE_PROC_ENTRY_NAME "pcie"
+#define MXL_MOCA_MODULE_PARAM_PERM (0644) // ( S_IRUSR | S_IWUSR) | S_IRGRP | S_IROTH )
+
+#define MXL_MOCA_PCIE_PROC_NAME_LEN_MAX 30
+
+#define MXL_MOCA_PCIE_NAPI 1
+
+#define MXL_MOCA_PCIE_PWR_MGMT 0
+
+#define MXL_MOCA_ENABLE_DBG_MSG 0 /* Keep this 0 for release builds */
+
+#define MXL_MOCA_PCIE_MAX_NUM_OF_PCIE_DEVICES 1
+
+#define MXL_MOCA_PCIE_MAX_NUM_OF_PCIE_DEV_ID 2
+
+#define MXL_MOCA_PCIE_DMA_MASK_BITS 32
+
+#define MXL_MOCA_PCIE_EN_PROC_DBG 0 /* Keep this 0 for release builds */
+
+/* Enabled feature in CCPU to issue periodic MSIs when there is active traffic. Interval is 160msec.
+ * This can be used as a DEBUG feature as well.
+ */
+#define MXL_MOCA_PCIE_EN_CCPU_TIMER_INTR 1
+
+#define MXL_MOCA_PROCFS_MAX_SIZE 4096
+
+#define MXL_MOCA_PCIE_VENDOR_ID 0x17e6
+#define MXL_MOCA_PCIE_DEV_ID_CARDIFF 0x3700
+#define MXL_MOCA_PCIE_DEV_ID_LEUCADIA 0x3710
+
+#define MXL_MOCA_PCIE_CTL_CD_CMD 0x0100000
+#define MXL_MOCA_PCIE_CTL_DP_CMD 0x0020000
+
+#define PCIE_INTR_SEL_AUTO 0 // Detect MSI, if not found, use INTA
+#define PCIE_INTR_SEL_MSI 1 // use MSI
+#define PCIE_INTR_SEL_INTA 2 // use INTA
+
+#define PCIE_INTR_TYPE_MSI 1 // use MSI
+#define PCIE_INTR_TYPE_INTA 2 // use INTA
+
+// Outbound ATU (RC <-- EP)
+#define MXL_MOCA_PCIE_NUM_OUTBOUND_ATU_REGIONS 2 // Maximum num regions are 4
+/* If MXL_MOCA_PCIE_NUM_OUTBOUND_ATU_REGIONS is changed,
+ * update MxL_MoCA_PCIeConfigOutboundATU and MxL_MoCA_PCIeCheckOutOfBoundMapping
+ */
+/* Example of iATU:
+ * Update the numbers in the table below if any updates to related #define constants
+ * The region addresses, when programmed, must be in ascending order from region 0 - thru region 3
+ * The number of valid regions are defined by MXL_MOCA_PCIE_NUM_OUTBOUND_ATU_REGIONS
+ |----------------------------------|
+ | Region 0 |
+ |----------------------------------|
+ | Target addr | Region base addr | // Target addr range: 0x0 - 0x3FFF_FFFF
+ | 0x0000_0000 | 0x4000_0000 | // MXL_MOCA_PCIE_OUTB_ATU_REGION0_BASE
+ |----------------------------------|
+ | Region 1 |
+ |----------------------------------|
+ | Target addr | Region base addr | // Target addr range: 0x4000_0000 - 0xBFFF_FFFF
+ | 0x4000_0000 | 0x8000_0000 | // MXL_MOCA_PCIE_OUTB_ATU_REGION1_BASE
+ |----------------------------------|
+ | Region 2 |
+ |----------------------------------|
+ | Target addr | Region base addr | // Unused target or region base addresses will be 0 (default)
+ | 0xXXXX_XXXX | 0xXXXX_XXXX |
+ |----------------------------------|
+ | Region 3 |
+ |----------------------------------|
+ | Target addr | Region base addr | // Unused target or region base addresses will be 0 (default)
+ | 0xXXXX_XXXX | 0xXXXX_XXXX |
+ |---------------|------------------|
+*/
+#define MXL_MOCA_PCIE_REGION0_MASK 0x7FFFFFFF // 1GB : 0x40000000 - 1
+#define MXL_MOCA_PCIE_REGION1_MASK 0xFFFFFFFF // 2GB : 0x80000000 - 1
+
+/* Defaults */
+#if defined(__LP64__) || defined(_LP64)
+#if MXLWARE_CONFIG_BOARD_ECA_9M_L3_NXP
+#define MXL_MOCA_PCIE_OUTB_ATU_TARGET0_ADDR_MASK 0x40000000 // 0x4000_0000 - 0x7FFF_FFFF (1GB)
+#define MXL_MOCA_PCIE_OUTB_ATU_TARGET0_ADDR_LIMIT 0x7FFFFFFF
+#define MXL_MOCA_PCIE_OUTB_ATU_TARGET1_ADDR_MASK 0x80000000 // 0x8000_0000 - 0xFFFF_FFFF (2GB)
+#define MXL_MOCA_PCIE_OUTB_ATU_TARGET1_ADDR_LIMIT 0xFFFFFFFF
+#else // PC specific
+#define MXL_MOCA_PCIE_OUTB_ATU_TARGET0_ADDR_MASK 0x30000000 // 0x3000_0000 - 0x6FFF_FFFF (1GB)
+#define MXL_MOCA_PCIE_OUTB_ATU_TARGET0_ADDR_LIMIT 0x6FFFFFFF
+#define MXL_MOCA_PCIE_OUTB_ATU_TARGET1_ADDR_MASK 0x70000000 // 0x7000_0000 - 0xEFFF_FFFF (2GB)
+#define MXL_MOCA_PCIE_OUTB_ATU_TARGET1_ADDR_LIMIT 0xEFFFFFFF
+#endif
+#else // 32-bits
+#define MXL_MOCA_PCIE_OUTB_ATU_TARGET0_ADDR_MASK 0x0 // 0x0000_0000 - 0x3FFF_FFFF (1GB)
+#define MXL_MOCA_PCIE_OUTB_ATU_TARGET0_ADDR_LIMIT 0x3FFFFFFF
+#define MXL_MOCA_PCIE_OUTB_ATU_TARGET1_ADDR_MASK 0x40000000 // 0x4000_0000 - 0xBFFF_FFFF (2GB)
+#define MXL_MOCA_PCIE_OUTB_ATU_TARGET1_ADDR_LIMIT 0xBFFFFFFF
+#endif
+
+#define MXL_MOCA_PCIE_OUTB_ATU_REGION0_BASE 0x40000000
+#define MXL_MOCA_PCIE_OUTB_ATU_REGION1_BASE 0x80000000
+
+
+// Inbound ATU (RC --> EP)
+/*
+ |---------------------------|
+ | Region 0 |
+ |---------------------------|
+ | BAR0 match | Target addr |
+ | | 0x0800_0000 | // MXL_MOCA_PCIE_HIF_TC_DMEM_BASE (Range: 0x800_0000-0x83F_FFFF)
+ |---------------------------|
+ | Region 1 |
+ |---------------------------|
+ | BAR1 match | Target addr |
+ | | 0x0C00_0000 | // MXL_MOCA_PCIE_CCPU_CORE_BASE (Range: 0xC00_0000-0xCFF_FFFF)
+ |---------------------------|
+*/
+#define MXL_MOCA_PCIE_BAR0_MASK 0x003FFFFF // 4MB : 0x400000 - 1
+#define MXL_MOCA_PCIE_BAR1_MASK 0x00FFFFFF // 16MB : 0x1000000 - 1
+// --
+
+// The product family of the Cardiff Chip: Cardiff: 3700, Leucadia: 3710
+#define MXL_MOCA_PROD_FAM_ID_ADDR 0x08200000
+#define MXL_MOCA_SYS_RES_EXT_CONFIG_STAT_ADDR 0x0820000c
+#define MXL_MOCA_BOND_OPT_SKU_MASK 0x003f0000
+#define MXL_MOCA_BOND_OPT_OFFSET 16
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
+ #define __devinitdata
+ #define __devinit
+ #define __devexit
+
+#if defined(MODULE) || defined(CONFIG_HOTPLUG)
+ #define __devexit_p(x) x
+#else
+ #define __devexit_p(x) NULL
+#endif
+
+#endif // LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
+
+#ifndef IRQF_SHARED
+ #define IRQF_SHARED SA_SHIRQ
+#endif
+
+#ifndef DMA_BIT_MASK
+ #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
+#endif
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22)
+ #undef ETHTOOL_GPERMADDR
+ #undef SET_MODULE_OWNER
+ #define SET_MODULE_OWNER(dev) do { } while (0)
+#endif
+
+#define MXL_MOCA_PCIE_TX_TIMEOUT (4*HZ) ///< for watchdog
+#define MXL_MOCA_PCIE_MAX_ETH_MTU_SIZE 1536
+#define MXL_MOCA_PCIE_MIN_ETH_MTU_SIZE_NO_FCS 60
+
+#define MXL_MOCA_PCIE_MAX_TX_PACKETS_PER_INT 32 // do not modify this.
+#define MXL_MOCA_PCIE_MAX_RX_PACKETS_PER_INT 32 // do not modify this.
+
+#define MXL_MOCA_PCIE_MAX_NAPI_WEIGHT MXL_MOCA_PCIE_MAX_RX_PACKETS_PER_INT // Change to a value <= MXL_MOCA_PCIE_MAX_RX_PACKETS_PER_INT
+
+
+// At least +2 due to our Ethernet header misalignment.
+#define MXL_MOCA_PCIE_MAX_ETH_RX_BUF_SIZE ((MXL_MOCA_PCIE_MAX_ETH_MTU_SIZE) + 2) // Our NET_IP_ALIGN is 0 for cardiff/leuc
+
+/*----------------------------------------------------------------------------------------
+ * Debug macros (MXL_MOCA_PCIE_L_DBG1 or MXL_MOCA_PCIE_L_DBG2 level must be set)
+ *--------------------------------------------------------------------------------------*/
+
+#if MXL_MOCA_ENABLE_DBG_MSG
+
+#define MXL_MOCA_DBG1P0(msg) MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG1, msg)
+#define MXL_MOCA_DBG1P1(msg, p0) MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG1, msg, p0)
+#define MXL_MOCA_DBG1P2(msg, p0, p1) MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG1, msg, p0, p1)
+#define MXL_MOCA_DBG1P3(msg, p0, p1, p2) MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG1, msg, p0, p1, p2)
+#define MXL_MOCA_DBG1P4(msg, p0, p1, p2, p3) MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG1, msg, p0, p1, p2, p3)
+#define MXL_MOCA_DBG1P5(msg, p0, p1, p2, p3, p4) MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG1, msg, p0, p1, p2, p3, p4)
+
+#define MXL_MOCA_DBG2P0(msg) MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG2, msg)
+#define MXL_MOCA_DBG2P1(msg, p0) MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG2, msg, p0)
+#define MXL_MOCA_DBG2P2(msg, p0, p1) MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG2, msg, p0, p1)
+#define MXL_MOCA_DBG2P3(msg, p0, p1, p2) MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG2, msg, p0, p1, p2)
+#define MXL_MOCA_DBG2P4(msg, p0, p1, p2, p3) MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG2, msg, p0, p1, p2, p3)
+#define MXL_MOCA_DBG2P5(msg, p0, p1, p2, p3, p4) MxL_MoCA_PCIeDbgTrace(MXL_MOCA_PCIE_L_DBG2, msg, p0, p1, p2, p3, p4)
+
+#else /* Expand to nothing */
+
+#define MXL_MOCA_DBG1P0(msg)
+#define MXL_MOCA_DBG1P1(msg, p0)
+#define MXL_MOCA_DBG1P2(msg, p0, p1)
+#define MXL_MOCA_DBG1P3(msg, p0, p1, p2)
+#define MXL_MOCA_DBG1P4(msg, p0, p1, p2, p3)
+#define MXL_MOCA_DBG1P5(msg, p0, p1, p2, p3, p4)
+
+#define MXL_MOCA_DBG2P0(msg)
+#define MXL_MOCA_DBG2P1(msg, p0)
+#define MXL_MOCA_DBG2P2(msg, p0, p1)
+#define MXL_MOCA_DBG2P3(msg, p0, p1, p2)
+#define MXL_MOCA_DBG2P4(msg, p0, p1, p2, p3)
+#define MXL_MOCA_DBG2P5(msg, p0, p1, p2, p3, p4)
+
+#endif
+
+
+/*******************************************************************************
+ * Constants (Host-to-SoC DMEM interface) : Common to Leuc and Cardiff
+ ******************************************************************************/
+// DMEM addr offsets
+// Datapath descriptors storage
+#define P_PCIE_HOST_RX_DESC_QUEUE 0x00000301
+#define P_PCIE_HOST_RX_DESC_Q_LEN 0x00000302
+#define P_PCIE_HOST_TX_DESC_QUEUE 0x00000305
+#define P_PCIE_HOST_TX_DESC_Q_LEN 0x00000306
+
+#define PCIE_TC_MGMT_IF_MAC_ADDR 0x00000309
+
+// iATU: Outbound settings - region base
+#define PCIE_NUM_OUTBOUND_REGIONS 0x0000030b
+#define PCIE_OUTBOUND_ATU_REG0_BASE 0x0000030c
+#define PCIE_OUTBOUND_ATU_REG1_BASE 0x0000030d
+#define PCIE_OUTBOUND_ATU_REG2_BASE 0x0000030e
+#define PCIE_OUTBOUND_ATU_REG3_BASE 0x0000030f
+
+// PCIe capabilities settings
+#define PCIE_DEVCTL_MAX_PAYLOAD_SIZE 0x00000310 // MTU size. Set LargeWrAXIBurst to ((this_value/4) - 1)
+#define PCIE_LNKCTL_RCB 0x00000311 // Read Completion Boundary. Set LargeRdAXIBurst to ((this_value/4) - 1)
+
+// Handshake
+#define PCIE_HOST_STATUS 0x00000312 // W_HIF_PCIE_HOST_STATUS in TC
+
+// Periodic CCPU interrupts (Enabled with MXL_MOCA_PCIE_EN_CCPU_TIMER_INTR) option DMEM addr offsets
+#define PCIE_EN_CCPU_TIMER_INTR 0x00000313 // W_HIF_PCIE_EN_CCPU_TIMER_INTR in TC : Enables optional periodic timer interrupts (MSI) from CCPU
+#define PCIE_CCPU_INTR_COUNT 0x00000314 // W_HIF_PCIE_INTR_TIMER_TICK in TC : MSI timer tick/counter from Ecl
+
+// iATU: Outbound settings - target base
+#define PCIE_OUTBOUND_ATU_TAR0_BASE 0x00000315
+#define PCIE_OUTBOUND_ATU_TAR1_BASE 0x00000316
+#define PCIE_OUTBOUND_ATU_TAR2_BASE 0x00000317
+#define PCIE_OUTBOUND_ATU_TAR3_BASE 0x00000318
+
+// DMA/transfer config - read/write port access byte order.
+#define PCIE_DMA_DATA_ACCESS_BYTE_ORDER 0x00000319 // Location to pass host endianess. 1 = big endian. 0 = little endian (default)
+
+#define PCIE_RX_NUM_PKTS 0x0000031A // No of Eth frames transferred to the Host from the SHMEM Mem
+#define PCIE_TX_NUM_PKTS 0x0000031B // No of Eth frames transferred to the SHMEM from the Host Mem
+
+#define PCIE_DEBUG_MEM_ADDR 0x0000031C // Temporary debug
+
+// Status value
+#define PCIE_HOST_STATUS_RUNNING 0x00000001
+
+#define MXL_MOCA_PCIE_KMALLOC_MAX 65536
+
+/*******************************************************************************
+ * Macros
+ ******************************************************************************/
+
+#undef MXL_MOCA_PCIE_TX_MAPPING_SIZE
+
+#define MXL_MOCA_PCIE_TX_QUEUE_SIZE 1024
+#define MXL_MOCA_PCIE_RX_QUEUE_SIZE 256
+
+#define MXL_MOCA_PCIE_TX_MAPPING_SIZE MXL_MOCA_PCIE_TX_QUEUE_SIZE //Must match the desc queue size in SoC
+#define MXL_MOCA_PCIE_RX_RING_SIZE MXL_MOCA_PCIE_RX_QUEUE_SIZE //Must match the desc queue size in SoC
+
+#define MXL_MOCA_PCIE_HIF_TC0_DMEM_BASE 0x08000000 // Cardiff
+#define MXL_MOCA_PCIE_HIF_TC1_DMEM_BASE 0x08040000 // Leucadia
+
+// Match the TX/RX descriptor sizes in SoC
+#define MXL_MOCA_PCIE_TX_PTR_QUEUE_SIZE MXL_MOCA_PCIE_TX_QUEUE_SIZE
+#define MXL_MOCA_PCIE_RX_PTR_QUEUE_SIZE MXL_MOCA_PCIE_RX_QUEUE_SIZE
+
+// Match the TX/RX descriptor sizes in SoC
+#define MXL_MOCA_PCIE_TX_DESC_QUEUE_SIZE MXL_MOCA_PCIE_TX_QUEUE_SIZE
+#define MXL_MOCA_PCIE_RX_DESC_QUEUE_SIZE MXL_MOCA_PCIE_RX_QUEUE_SIZE
+
+#define MXL_MOCA_PCIE_DESC_OWNER_HOST 0 /* host */
+#define MXL_MOCA_PCIE_DESC_OWNER_SOC 1
+#define MXL_MOCA_PCIE_DESC_OWNER_PKT_DONE 2
+
+#define MXL_MOCA_PCIE_LOG_PRINT_BUFSIZE 1024
+
+
+/*******************************************************************************
+ * Public Function Definitions
+ ******************************************************************************/
+typedef enum
+{
+ MXL_MOCA_PCIE_DEVICE_ID_UNKNOWN = 0x0,
+ MXL_MOCA_PCIE_DEVICE_ID_CARDIFF = MXL_MOCA_PCIE_DEV_ID_CARDIFF,
+ MXL_MOCA_PCIE_DEVICE_ID_LEUCADIA = MXL_MOCA_PCIE_DEV_ID_LEUCADIA
+} MXL_MOCA_PCIE__DEVICE_ID_E;
+
+typedef enum
+{
+ MXL_MOCA_PCIE_ERROR_OUT_NONE = 0x0,
+ MXL_MOCA_PCIE_ERROR_OUT_FREE_ALLOC = 0x1,
+ MXL_MOCA_PCIE_ERROR_OUT_FREE_UNMAP = 0x2,
+ MXL_MOCA_PCIE_ERROR_OUT_FREE_NETDEV = 0x3
+} MXL_MOCA_PCIE_ERROR_OUT_E;
+
+enum
+{
+ MXL_MOCA_PCIE_L_DEF = 0, /* same as level 2 (include only err and warn) */
+ MXL_MOCA_PCIE_L_ERR = 1,
+ MXL_MOCA_PCIE_L_WARN = 2,
+ MXL_MOCA_PCIE_L_INFO = 3,
+ MXL_MOCA_PCIE_L_DBG1 = 4, /* Primarily used to print entry, exits to/from functions */
+ MXL_MOCA_PCIE_L_DBG2 = 5, /* Used for messages inside tx/rx packet handlers */
+ MXL_MOCA_PCIE_L_END = 6
+};
+
+#define MXL_MOCA_PCIE_HIF_TC_DMEM_BASE 0x08000000
+#define MXL_MOCA_PCIE_CCPU_CORE_BASE 0x0c000000
+#define MXL_MOCA_PCIE_CCPU_CORE_BASE_MAX 0x0cffffff
+
+#define MXL_MOCA_PCIE_EP_BASE 0x08204000 // 0x08204700 + 0x200
+
+#define MXL_MOCA_PCIE_EHI_CTRL_STAT_REG0 0x08205000
+#define MXL_MOCA_PCIE_EHI_CTRL_STAT_REG1 0x08205004
+#define MXL_MOCA_PCIE_EHI_CTRL_STAT_REG2 0x08205008
+
+
+#define MXL_MOCA_PCIE_EHI_CTRL_STAT_REG0_INTX_ASSERT 0x0000E809
+#define MXL_MOCA_PCIE_EHI_CTRL_STAT_REG0_INTX_DEASSERT 0x0000E808
+
+
+// Global reset
+#define MXL_MOCA_PCIE_EP_LEUCADIA_GLOBAL_RESETN (0x708) // Leucadia
+#define MXL_MOCA_PCIE_EP_CARDIFF_GLOBAL_RESETN (0x814) // Cardiff
+
+
+// Only offsets are used in config rd/wr
+#define MXL_MOCA_PCIE_EP_IATU_INDEX_OFFSET (0x900)
+#define MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_1_OFFSET (0x904)
+#define MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_2_OFFSET (0x908)
+#define MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_OFFSET (0x90C)
+#define MXL_MOCA_PCIE_EP_IATU_REGION_LIMIT_ADDR_OFFSET (0x914)
+#define MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_OFFSET (0x918)
+
+
+// base address + offsets are used for memory rd/wr
+#define MXL_MOCA_PCIE_EP_IATU_INDEX_REG (MXL_MOCA_PCIE_EP_BASE + MXL_MOCA_PCIE_EP_IATU_INDEX_OFFSET)
+#define MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_1_REG (MXL_MOCA_PCIE_EP_BASE + MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_1_OFFSET)
+#define MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_2_REG (MXL_MOCA_PCIE_EP_BASE + MXL_MOCA_PCIE_EP_IATU_REGION_CTRL_2_OFFSET)
+#define MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_REG (MXL_MOCA_PCIE_EP_BASE + MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_BASE_ADDR_OFFSET)
+#define MXL_MOCA_PCIE_EP_IATU_REGION_LIMIT_ADDR_REG (MXL_MOCA_PCIE_EP_BASE + MXL_MOCA_PCIE_EP_IATU_REGION_LIMIT_ADDR_OFFSET)
+#define MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_REG (MXL_MOCA_PCIE_EP_BASE + MXL_MOCA_PCIE_EP_IATU_REGION_LOWER_TARGET_ADDR_OFFSET)
+
+// Global reset
+// Leucadia
+/*
+ pcie_global_resetn - Bit 22: It is 1 by-default and SW needs to write 0 to issue the request for global reset.
+ pcie_global_resetn_disable : Bit 23: It is 0 by-default and implies that when pcie_global_resetn bit is set to 0,
+ then it will reset the entire SoC including PCIe
+*/
+#define MXL_MOCA_PCIE_EP_LEUCADIA_GLOBAL_RESET_NO_LINK_DN 0x07800004
+#define MXL_MOCA_PCIE_EP_LEUCADIA_GLOBAL_RESET_NO_LINK_DN_CLEAR 0x07C00004
+
+/*
+ pcie_global_resetn - Bit 0: It is 1 by-default and SW needs to write 0 to issue the request for global reset.
+ pcie_global_resetn_disable : Bit 1: It is 0 by-default and implies that when pcie_global_resetn bit is set to 0,
+ then it will reset the entire SoC including PCIe
+*/
+// Cardiff
+#define MXL_MOCA_PCIE_EP_CARDIFF_GLOBAL_RESET_NO_LINK_DN 0x00000002
+#define MXL_MOCA_PCIE_EP_CARDIFF_GLOBAL_RESET_NO_LINK_DN_CLEAR 0x00000003
+
+
+/*******************************************************************************
+ * Public/Private Data
+ ******************************************************************************/
+/*!
+ * \brief Spinlock structure with added bells and whistles
+ *
+ * For locking purposes.
+ */
+typedef struct
+{
+ unsigned long lockIrqFlags;
+ spinlock_t lockSpinLock;
+} MXL_MOCA_PCIE_ETH_LOCK_T;
+
+/*!
+ * \brief Semaphore structure
+ */
+typedef struct
+{
+ struct semaphore osSema;
+} MXL_MOCA_PCIE_ETH_SEMA_T;
+
+
+/*!
+ * \brief Packet element structure
+ */
+typedef struct
+{
+ uint32_t totalLen; // Packet length. DECLARE_PCI_UNMAP_LEN(totalLen)
+ dma_addr_t mapping; // sk_buff physical addr/mapping. DECLARE_PCI_UNMAP_ADDR(mapping)
+} MXL_MOCA_PCIE_QUEUE_PKT_T;
+
+typedef struct
+{
+ uint32_t dword0; /* length and ownership. length[17:2], ownership[1:0] */
+ uint32_t dword1; /* dma physical addr of the packet */
+} MXL_MOCA_PCIE_QUEUE_DESCR_T;
+
+typedef struct
+{
+ void* pPktQueuePa; // Pointer queue physical addr (MxL_MoCA_PCIeAllocDmaMem-->pa)
+ MXL_MOCA_PCIE_QUEUE_PKT_T* pPktQueue; // Packet : 32 packets (same as descriptors length) (MxL_MoCA_PCIeAllocDmaMem-->va)
+
+ void* pDescQueuePa;
+ MXL_MOCA_PCIE_QUEUE_DESCR_T* pDescQueue; // Desc Queue in host : 32x2 descriptors
+
+ uint32_t descQueueAddr; // Host descr queue addr value: host will write the physical base address of the queue here using MemWrite
+ uint32_t descQueueSize; // Desc Queue size (in host memory)
+
+ uint32_t descQueueReadIdx; // Read index for the host descr
+ uint32_t descQueueWriteIdx; // Write index for the host descr
+
+ uint32_t lastPktsCnt; // last counter for # of pkts processed. There is a proc entry for tx/rx stats.
+} MXL_MOCA_PCIE_QUEUE_PAIR_T;
+
+/*!
+ * \brief DP Structure
+ *
+ */
+typedef struct
+{
+ MXL_MOCA_PCIE_QUEUE_PAIR_T txQueuePair;
+ MXL_MOCA_PCIE_QUEUE_PAIR_T rxQueuePair;
+} MXL_MOCA_PCIE_DATAPATH_CONTEXT_T;
+
+
+// MxL MoCA Ethernet Statistics Structure
+typedef struct
+{
+ // Driver stats
+ uint32_t drvSwRevNum;
+ uint32_t embSwRevNum;
+ uint32_t upTime;
+ uint32_t linkUpTime;
+
+ // Transmit and recieve stats
+ uint32_t rxPackets; // Total packets received
+ uint32_t txPackets; // Total packets transmitted
+ uint32_t rxBytes; // Total bytes received
+ uint32_t txBytes; // Total bytes transmitted
+ uint32_t rxPacketsGood; // Packet receive with no errors
+ uint32_t txPacketsGood; // Packet transmitted with no errors
+ uint32_t rxPacketErrs; // Packets received with errors
+ uint32_t txPacketErrs; // Packets transmitted with errors
+ uint32_t rxDroppedErrs; // Packets dropped with no host buffers
+ uint32_t txDroppedErrs; // Packet dropped with no host buffers
+ uint32_t rxMulticastPackets; // Total multicast packets received
+ uint32_t txMulticastPackets; // Total multicast packets transmitted
+ uint32_t rxMulticastBytes; // Total multicast bytes received
+ uint32_t txMulticastBytes; // Total multicast bytes transmitted
+
+ // Detailed receive errors
+ uint32_t rxLengthErrs;
+ uint32_t rxCrc32Errs; // Packets rx'd with CRC-32 errors
+ uint32_t rxFrameHeaderErrs; // Packets rx'd with frame header errors
+ uint32_t rxFifoFullErrs; // Packets rx'd with FIFO full
+ uint32_t rxListHaltErr[3];
+
+ // Detailed transmit errors
+ uint32_t txCrc32Errs; // Packets tx'd with CRC-32 errors
+ uint32_t txFrameHeaderErrs; // Packets tx'd with frame header errors
+ uint32_t txFifoFullErrs; // Packets tx'd with FIFO full
+ uint32_t txFifoHaltErr[8];
+} MXL_MOCA_PCIE_ETH_STATS_T;
+
+/*!
+ * \brief Ring info data structure
+ *
+ */
+typedef struct __ring_info
+{
+ struct sk_buff *skb;
+ dma_addr_t mapping;
+} MXL_MOCA_PCIE_RING_INFO_T;
+
+/*!
+ * \brief eth_dev data structure
+ *
+ * This structure is instantiated at probe time by allocation of the net_device.
+ * It exists at the end of the net_device and is pointed to by the priv member
+ * of the net_device.
+ */
+typedef struct
+{
+ // Device data
+ struct pci_dev *pPCIeDev; // pointer to pci_dev
+ struct net_device *pNetDev; // pointer to net_dev
+ MXL_MOCA_PCIE_DATAPATH_CONTEXT_T *pDpCtx; // pointer to data path structure
+
+ // Identification
+ MXL_MOCA_PCIE__DEVICE_ID_E deviceId;
+ uint32_t devIndex;
+ uint32_t mgmtIfMacAddr[2];
+
+ // Stack interface
+ MXL_MOCA_PCIE_RING_INFO_T rxRing[MXL_MOCA_PCIE_RX_RING_SIZE];
+ MXL_MOCA_PCIE_RING_INFO_T txRing[MXL_MOCA_PCIE_TX_MAPPING_SIZE];
+
+ // skb management
+ int32_t txRingWrIndex;
+ int32_t txRingRdIndex;
+
+ // NAPI support
+#if MXL_MOCA_PCIE_NAPI
+ struct napi_struct napi;
+ int32_t napiDisableIntr;
+ int32_t polls;
+ int32_t napiWorkDone;
+#endif
+
+ // Device capabilities/control/status
+ int32_t devCapMaxPayloadSz;
+ int32_t devCtlMaxPayloadSz;
+ int32_t devCtlMaxReadReqSz;
+ int32_t lnkCapMaxLnkSpeed;
+ int32_t lnkCapMaxLinkWidth;
+ int32_t lnkCapAspmSupport; /* ASPM support */
+ int32_t lnkCapPme; /* PME# support */
+ int32_t lnkCtlAspmL1;
+ int32_t lnkCtlRCB;
+ int32_t lnkStaMaxLnkSpeed;
+ int32_t lnkStaMaxLinkWidth;
+
+ // iATU
+ uint32_t dmemBaseAddr; // Depends on Chip ID
+ uint32_t region0OutATUAddrBase;
+ uint32_t region1OutATUAddrBase;
+ uint32_t region2OutATUAddrBase; // reserved
+ uint32_t region3OutATUAddrBase; // reserved
+
+ uint32_t target0OutATUAddrMask;
+ uint32_t target1OutATUAddrMask;
+ uint32_t target2OutATUAddrMask; // reserved
+ uint32_t target3OutATUAddrMask; // reserved
+
+ // Interrupts counter
+ int32_t interrupts; // MSI/INTx issued by SoC FW
+
+ // PCIe config space
+ /* We have two BARs */
+ // 4MB: Use for L2 space access
+ uintptr_t baseIoAddr0; // physical address
+ uint32_t baseIoLen0;
+ uintptr_t baseIoRemap0;// virtual address
+
+ // 16MB: Use for Fusion4 access
+ uintptr_t baseIoAddr1; // physical address
+ uint32_t baseIoLen1;
+ uintptr_t baseIoRemap1;// virtual address
+
+ // flags
+ uint32_t active; // datapath up/down
+ uint32_t firstTime; // first-time up indicator
+ uint32_t busy; // for DEBUG
+ uint32_t inbandIntrType; // MSI/INTx
+#if MXL_MOCA_PCIE_DEBUG_DROP_TX
+ uint32_t dbg_drop_tx;
+#endif
+#if MXL_MOCA_PCIE_DEBUG_DROP_RX
+ uint32_t dbg_drop_rx;
+#endif
+ // rx stats
+ uint32_t netIfRxDropped;
+ uint32_t rxStats[4]; // for DEBUG). See Proc read/write
+
+ // tx stats
+ uint32_t numPktsQueued;
+ uint32_t numPktsXmited;
+ uint32_t txIntrCount; // interrupts from stack
+ uint32_t txStats[6]; // for DEBUG). See Proc read/write
+
+ // errors
+ uint32_t mappingErr0;
+ uint32_t mappingErr1;
+ uint32_t mappingErr2;
+ uint32_t skbAllocErr;
+
+ MXL_MOCA_PCIE_ETH_STATS_T ethStats; // /sys/class/net/en0/statistics
+ struct net_device_stats stats; // net device statistics
+
+ // proc entry
+ uint32_t readProcMode;
+ int8_t procDirName[MXL_MOCA_PCIE_PROC_NAME_LEN_MAX+1];
+ struct proc_dir_entry *pProcDir;
+
+ // Synchronizing objects
+ MXL_MOCA_PCIE_ETH_LOCK_T ethTxLock; ///< xmit spin lock: avoid recursive interrupts and for net_dev_ops
+ MXL_MOCA_PCIE_ETH_LOCK_T rwLock; ///< For PCI address read/write spin lock
+} MXL_MOCA_PCIE_DEV_DATA_CONTEXT_T;
+
+/*!
+ * \brief Driver kernel context.
+ *
+ */
+typedef struct net_device MXL_MOCA_PCIE_KERNEL_CONTEXT_T;
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)
+ #define NETDEV_PRIV(dev) netdev_priv(dev)
+#else
+ #define NETDEV_PRIV(dev) (dev)->priv
+#endif
+
+/*******************************************************************************
+ * Function Definitions
+ ******************************************************************************/
+MXL_MOCA_STATUS_E MxL_MoCA_PCIeRestart(int8_t devIndex);
+void MxL_MoCA_PCIeSetMgmtMAC(int8_t devIndex, uint32_t* pMac);
+MXL_MOCA_STATUS_E MxL_MoCA_PCIeAvailable(int8_t devIndex);
+void MxL_MoCA_PCIeStop (int8_t devIndex);
+MXL_MOCA_STATUS_E MxL_MoCA_PCIeRead(int8_t devIndex, uintptr_t addr, uint32_t *pVal);
+MXL_MOCA_STATUS_E MxL_MoCA_PCIeWrite(int8_t devIndex, uintptr_t addr, uint32_t pVal);
+MXL_MOCA_STATUS_E MxL_MoCA_PCIeGlobalResetSoC(int8_t devIndex);
+
+#endif /* __MXL_MOCA_OSAL_PCIE_H__ */
+
diff --git a/drivers/net/phy/mxl371x/mxl_moca_soc_cmd.h b/drivers/net/phy/mxl371x/mxl_moca_soc_cmd.h
new file mode 100644
index 000000000000..84a5139c2fb3
--- /dev/null
+++ b/drivers/net/phy/mxl371x/mxl_moca_soc_cmd.h
@@ -0,0 +1,3050 @@
+/*****************************************************************************************
+ *
+ * FILE NAME : mxl_moca_soc_cmd.h
+ *
+ *
+ *
+ * DATE CREATED : Sep/14/2016
+ *
+ * LAST MODIFIED :
+ *
+ * DESCRIPTION : This file contains all MoCA SOC commands and the corresponding
+ * response data that shall be used in communication with MxL Host
+ * driver
+ *
+ *****************************************************************************************
+ * MaxLinear, Inc. retains all right, title and interest (including all intellectual
+ * property rights) in and to this computer program, which is protected by applicable
+ * intellectual property laws. Unless you have obtained a separate written license from
+ * MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., you are not authorized
+ * to utilize all or a part of this computer program for any purpose (including
+ * reproduction, distribution, modification, and compilation into object code), and you
+ * must immediately destroy or return all copies of this computer program. If you are
+ * licensed by MaxLinear, Inc. or an authorized licensee of MaxLinear, Inc., your rights
+ * to utilize this computer program are limited by the terms of that license.
+ *
+ * This computer program contains trade secrets owned by MaxLinear, Inc. and, unless
+ * authorized by MaxLinear, Inc. in writing, you agree to maintain the confidentiality
+ * of this computer program and related information and to not disclose this computer
+ * program and related information to any other person or entity.
+ *
+ * Misuse of this computer program or any information contained in it may results in
+ * violations of applicable law. MaxLinear, Inc. vigorously enforces its copyright,
+ * trade secret, patent, contractual, and other legal rights.
+ *
+ * THIS COMPUTER PROGRAM IS PROVIDED "AS IS" WITHOUT ANY WARRANTIES, AND
+ * MAXLINEAR, INC.EXPRESSLY DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE
+ * WARRANTIES OF MERCHANTIBILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND
+ * NONINFRINGEMENT.
+ *
+ ****************************************************************************************
+ * Copyright (c) 2021, MaxLinear, Inc.
+ ****************************************************************************************/
+
+#ifndef __MXL_MOCA_SOC_CMD_H__
+#define __MXL_MOCA_SOC_CMD_H__
+
+
+/*****************************************************************************************
+ Include Header Files
+ (No absolute paths - paths handled by make file)
+ ****************************************************************************************/
+#ifndef __KERNEL__
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+#include "mxl_data_types.h"
+#include "mxl_moca_ioctl_cmd.h"
+#include "mxl_moca_config.h"
+
+
+/*****************************************************************************************
+ Macros
+ ****************************************************************************************/
+#define CONFIG_PARAM_VERSION 0x20 /* Change this to the actual version when feature complete */
+
+#define MXL_MOCA_SOC_CMD 0x0010000
+#define MXL_MOCA_DRV_CMD 0x0020000
+#define MXL_MOCA_DBG_CMD 0x0040000
+#define CMD_RESPONSE 0x1000000
+#define CMD_NO_RESPONSE 0x2000000
+
+#define CLNK_CMD_DST_MASK 0x03f0000
+#define CLNK_CMD_RESPONSE_MASK 0xf000000 // private bitmask
+
+#define CLNK_CMD_BYTE_MASK (0x000000ff)
+#define CLNK_CTL_VERSION 0x01
+
+#define CCPU_MAGIC_NUM0_REG 0x0c107080
+#define RESET_CNT_MASK 0x0000ffff
+#define RESET_EC_OFFSET 24
+#define RESET_LINE_MASK 0xffffff
+
+/*
+ * MxL MoCA SoC commands
+ */
+
+#define MXL_MOCA_SOC_GET_SOC_STATUS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0001) /* HI_TXNTYPE_GET_SOC_STATUS */
+#define MXL_MOCA_SOC_GET_IMAGE_INFO (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0002) /* HI_TXNTYPE_GET_IMAGE_INFO */
+#define MXL_MOCA_SOC_SET_INIT_PARAM_V2 (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0004) /* HI_TXNTYPE_SET_INIT_PARAM_V2 */
+#define MXL_MOCA_SOC_SET_INIT_RLAPM (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0005) /* HI_TXNTYPE_SET_INIT_RLAPM */
+#define MXL_MOCA_SOC_SET_INIT_SAPM (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0006) /* HI_TXNTYPE_SET_INIT_SAPM */
+#define MXL_MOCA_SOC_SET_INIT_START (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0007) /* HI_TXNTYPE_SET_INIT_START */
+#define MXL_MOCA_SOC_SET_BCN_POWER (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0008) /* HI_TXNTYPE_SET_BCN_POWER */
+#define MXL_MOCA_SOC_GET_BCN_POWER (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0009) /* HI_TXNTYPE_GET_BCN_POWER */
+#define MXL_MOCA_SOC_SET_INIT_PARAM_V25 (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x000A) /* HI_TXNTYPE_SET_INIT_PARAM_V25 */
+#define MXL_MOCA_SOC_GET_DATA_STATS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x000B) /* HI_TXNTYPE_GET_DATA_STATS */
+#define MXL_MOCA_SOC_GET_AGGR_STATS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0010) /* HI_TXNTYPE_GET_AGGR_STATS */
+#define MXL_MOCA_SOC_GET_BRIDGE_STATS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0011) /* HI_TXNTYPE_GET_BRIDGE_STATS */
+#define MXL_MOCA_SOC_GET_BRIDGE_TABLE (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0012) /* HI_TXNTYPE_GET_BRIDGE_TABLE */
+#define MXL_MOCA_SOC_GET_EPHY_STATS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0013) /* HI_TXNTYPE_GET_EPHY_STATS */
+#define MXL_MOCA_SOC_GET_FRAME_STATS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0014) /* HI_TXNTYPE_GET_FRAME_STATS */
+#define MXL_MOCA_SOC_GET_LOCAL_INFO (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0015) /* HI_TXNTYPE_GET_LOCAL_INFO */
+#define MXL_MOCA_SOC_GET_NET_INFO (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0016) /* HI_TXNTYPE_GET_NET_INFO */
+#define MXL_MOCA_SOC_SET_MULTICAST_INFO (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0018) /* HI_TXNTYPE_SET_MULTICAST_INFO */
+#define MXL_MOCA_SOC_REQUEST_HANDOFF (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0019) /* HI_TXNTYPE_REQUEST_HANDOFF */
+#define MXL_MOCA_SOC_REQUEST_LMO (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x001A) /* HI_TXNTYPE_REQUEST_LMO */
+#define MXL_MOCA_SOC_REQUEST_NMS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x001B) /* HI_TXNTYPE_REQUEST_NMS */
+#define MXL_MOCA_SOC_REQUEST_SPECTRUM (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x001C) /* HI_TXNTYPE_REQUEST_SPECTRUM */
+#define MXL_MOCA_SOC_GET_FMR_INFO (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x001D) /* HI_TXNTYPE_REQUEST_FMR */
+#define MXL_MOCA_SOC_GET_DD_INFO (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x001E) /* HI_TXNTYPE_GET_DD_INFO */
+#define MXL_MOCA_SOC_REQUEST_BCNPWR_PIE (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x001F) /* HI_TXNTYPE_REQUEST_ BCNPWR_PIE*/
+#define MXL_MOCA_SOC_GET_PHY_TX_PROFILE (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0020) /* HI_TXNTYPE_GET_PHY_TX_PROFILE */
+#define MXL_MOCA_SOC_GET_PHY_RX_PROFILE (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0021) /* HI_TXNTYPE_GET_PHY_RX_PROFILE */
+#define MXL_MOCA_SOC_GET_PHY_NODE (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0022) /* HI_TXNTYPE_GET_PHY_NODE */
+#define MXL_MOCA_SOC_GET_PHY_EVM (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0023) /* HI_TXNTYPE_GET_PHY_EVM */
+#define MXL_MOCA_SOC_GET_PHY_MISC (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0024) /* HI_TXNTYPE_GET_PHY_MISC */
+#define MXL_MOCA_SOC_GET_PHY_OFDMA (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0025) /* HI_TXNTYPE_GET_PHY_OFDMA */
+#define MXL_MOCA_SOC_GET_RETX_STATS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0026) /* HI_TXNTYPE_GET_RETX_STATS */
+#define MXL_MOCA_SOC_GET_MULTICAST_MODE (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0027) /* HI_TXNTYPE_GET_MULTICAST_MODE */
+#define MXL_MOCA_SOC_SET_MULTICAST_MODE (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0028) /* HI_TXNTYPE_SET_MULTICAST_MODE */
+#define MXL_MOCA_SOC_SET_PHY_MOD_BITMASK (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0029) /* HI_TXNTYPE_SET_PHY_MOD_BITMASK*/
+#define MXL_MOCA_SOC_SLEEP (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0030) /* HI_TXNTYPE_SLEEP */
+#define MXL_MOCA_SOC_WAKE (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0031) /* HI_TXNTYPE_WAKE */
+#define MXL_MOCA_SOC_GET_PM_CAPS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0032) /* HI_TXNTYPE_GET_PM_CAPS */
+#define MXL_MOCA_SOC_QUERY_PM_STATE (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0033) /* HI_TXNTYPE_QUERY_PM_STATE */
+#define MXL_MOCA_SOC_GET_PM_EVENTS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0034) /* HI_TXNTYPE_GET_PM_EVENTS */
+#define MXL_MOCA_SOC_HOST_IF_READY (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0035) /* HI_TXNTYPE_HOST_IF_READY */
+#define MXL_MOCA_SOC_CREATE_FLOW (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0040) /* HI_TXNTYPE_CREATE_FLOW */
+#define MXL_MOCA_SOC_UPDATE_FLOW (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0041) /* HI_TXNTYPE_UPDATE_FLOW */
+#define MXL_MOCA_SOC_DELETE_FLOW (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0042) /* HI_TXNTYPE_DELETE_FLOW */
+#define MXL_MOCA_SOC_LIST_FLOW (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0043) /* HI_TXNTYPE_LIST_FLOW */
+#define MXL_MOCA_SOC_QUERY_FLOW (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0044) /* HI_TXNTYPE_QUERY_FLOW */
+#define MXL_MOCA_SOC_GET_FLOW_STATS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0045) /* HI_TXNTYPE_GET_FLOW_STATS */
+#define MXL_MOCA_SOC_GET_SEC_PASSWORD (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0050) /* HI_TXNTYPE_GET_SEC_PASSWORD */
+#define MXL_MOCA_SOC_GET_SEC_INFO (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0051) /* HI_TXNTYPE_GET_SEC_INFO */
+#define MXL_MOCA_SOC_GET_SEC_STATS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0052) /* HI_TXNTYPE_GET_SEC_STATS */
+#define MXL_MOCA_SOC_GET_FRAG_STATS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0054) /* HI_TXNTYPE_GET_FRAG_STATS */
+#define MXL_MOCA_SOC_MOCA_RESET (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0055) /* HI_TXNTYPE_MOCA_RESET */
+#define MXL_MOCA_SOC_GET_L2ME_STATS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0056) /* HI_TXNTYPE_GET_L2ME_STATS */
+#define MXL_MOCA_SOC_GET_ACTIVE_RLAPM_V2 (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0057) /* HI_TXNTYPE_GET_ACTIVE_RLAPM_V2*/
+#define MXL_MOCA_SOC_GET_ACTIVE_SAPM_V2 (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0058) /* HI_TXNTYPE_GET_ACTIVE_SAPM_V2 */
+#define MXL_MOCA_SOC_GET_ENDET_STATUS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0059) /* HI_TXNTYPE_GET_ENDET_STATUS */
+#define MXL_MOCA_SOC_GET_SEC_EP_PASSWORD (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x005E) /* HI_TXNTYPE_GET_SEC_EP_PASSWORD*/
+#define MXL_MOCA_SOC_GET_EP_SEC_INFO (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x005F) /* HI_TXNTYPE_GET_EP_SEC_INFO */
+#define MXL_MOCA_SOC_SET_MCAST_PARAM (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0061) /* HI_TXNTYPE_SET_MCAST_PARAM */
+#define MXL_MOCA_SOC_GET_OFDMA_SC_DEF (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0062) /* HI_TXNTYPE_GET_OFDMA_SC_DEF */
+#define MXL_MOCA_SOC_GET_OFDMA_SC_ASSIGN (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0063) /* HI_TXNTYPE_GET_OFDMA_SC_ASSIGN*/
+#define MXL_MOCA_SOC_GET_OFDMA_PARAMS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0064) /* HI_TXNTYPE_GET_OFDMA_PARAMS */
+#define MXL_MOCA_SOC_GET_OFDMA_TX_PROFILE (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0065) /* HI_TXNTYPE_GET_OFDMA_TX_PROFILE*/
+#define MXL_MOCA_SOC_GET_OFDMA_RX_PROFILE (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0066) /* HI_TXNTYPE_GET_OFDMA_RX_PROFILE*/
+#define MXL_MOCA_SOC_SET_GET_TX_PWR_VAR (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0067) /* HI_TXNTYPE_SET_GET_TX_PWR_VAR */
+#define MXL_MOCA_SOC_DO_TEST_CMD (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0070) /* HI_TXNTYPE_DO_TEST_CMD */
+#define MXL_MOCA_SOC_GET_SWITCH_TABLE (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0071) /* HI_TXNTYPE_GET_SWITCH_TABLE */
+#define MXL_MOCA_SOC_GET_SWITCH_STATS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0072) /* HI_TXNTYPE_GET_SWITCH_STATS */
+#define MXL_MOCA_SOC_GET_SWITCH_CONFIG (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0073) /* HI_TXNTYPE_GET_SWITCH_CONFIG */
+#define MXL_MOCA_SOC_RESET_SWITCH_CONFIG (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0074) /* HI_TXNTYPE_RESET_SWITCH_CONFIG */
+#define MXL_MOCA_SOC_SET_SWITCH_TMO (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0075) /* HI_TXNTYPE_SET_SWITCH_TMO */
+#define MXL_MOCA_SOC_ENA_SWTICH_VLAN_CHECK (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0076) /* HI_TXNTYPE_ENA_SWTICH_VLAN_CHECK */
+#define MXL_MOCA_SOC_DIS_SWTICH_VLAN_CHECK (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0077) /* HI_TXNTYPE_DIS_SWTICH_VLAN_CHECK */
+#define MXL_MOCA_SOC_ENA_SWTICH_VLAN_STRIP (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0078) /* HI_TXNTYPE_ENA_SWTICH_VLAN_STRIP */
+#define MXL_MOCA_SOC_DIS_SWTICH_VLAN_STRIP (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0079) /* HI_TXNTYPE_DIS_SWTICH_VLAN_STRIP */
+#define MXL_MOCA_SOC_SET_SWTICH_VLAN_PVID (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x007A) /* HI_TXNTYPE_SET_SWTICH_VLAN_PVID */
+#define MXL_MOCA_SOC_ADD_SWTICH_VLAN_ID (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x007B) /* HI_TXNTYPE_ADD_SWTICH_VLAN_ID */
+#define MXL_MOCA_SOC_DEL_SWTICH_VLAN_ID (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x007C) /* HI_TXNTYPE_DEL_SWTICH_VLAN_ID */
+#define MXL_MOCA_SOC_SET_SWITCH_MGMT_MAC (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x007D) /* HI_TXNTYPE_SET_SWTICH_MGMT_MAC */
+#define MXL_MOCA_SOC_GET_MAC_DATA_STATS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x007E) /* HI_TXNTYPE_GET_MAC_DATA_STATS */
+#define MXL_MOCA_SOC_GET_M25_PHY_MISC (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x007F) /* HI_TXNTYPE_GET_M25_PHY_MISC */
+// Network Proxy
+#define MXL_MOCA_SOC_NET_PROXY_PKT_SEND_REQ (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0081) /* HI_TXNTYPE_NET_PROXY_PKT_SEND_REQ */
+#define MXL_MOCA_SOC_NET_PROXY_PKT_RCV_RSP (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0082) /* HI_TXNTYPE_NET_PROXY_PKT_RCV_RSP */
+#define MXL_MOCA_SOC_NET_PROXY_PKT_RCV_REQ (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0083) /* HI_TXNTYPE_NET_PROXY_PKT_RCV_REQ */
+#define MXL_MOCA_SOC_NET_PROXY_PKT_SEND_RSP (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0084) /* HI_TXNTYPE_NET_PROXY_PKT_SEND_RSP */
+// Bridge detection
+#define MXL_MOCA_SOC_GET_NETWORK_NAME_REC (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0085) /* HI_TXNTYPE_GET_NETWORK_NAME_REC */
+#define MXL_MOCA_SOC_GET_NETWORK_NAME_PAYLOAD (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0086) /* HI_TXNTYPE_GET_NETWORK_NAME_PAYLOAD */
+#define MXL_MOCA_SOC_ME_NETWORK_IE_PAYLOAD_TX (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0087) /* HI_TXNTYPE_ME_NETWORK_IE_PAYLOAD_TX */
+#define MXL_MOCA_SOC_ME_NETWORK_IE_PAYLOAD_RX (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0088) /* HI_TXNTYPE_ME_NETWORK_IE_PAYLOAD_RX */
+#define MXL_MOCA_SOC_ME_NETWORK_JOIN (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0089) /* HI_TXNTYPE_ME_NETWORK_JOIN */
+#define MXL_MOCA_SOC_ME_NETWORK_JOIN_CFG (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x008A) /* HI_TXNTYPE_ME_NETWORK_JOIN_CFG */
+// Traffic Permission
+#define MXL_MOCA_SOC_SET_TRAFFIC_PERMIT_CFG (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x008B) /* HI_TXNTYPE_SET_TRAFFIC_PERMIT_CFG */
+#define MXL_MOCA_SOC_GET_TRAFFIC_PERMIT_STS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x008C) /* HI_TXNTYPE_GET_TRAFFIC_PERMIT_STS */
+#define MXL_MOCA_SOC_GET_ETHER_TYPE_INFO (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x008D) /* HI_TXNTYPE_GET_ETHER_TYPE_INFO */
+
+// Network Proxy Response Enable - controls the response to a NetProxy SET or GET
+// If the DCAP test mode is turned ON, the node in response to receiving a MIB Management GET or SET request message replies
+// with a MIB Management GET or SET response message respectively.
+#define MXL_MOCA_SOC_NET_PROXY_TEST_MODE_CFG (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x008F) /* HI_TXNTYPE_NET_PROXY_TEST_MODE_CFG */
+
+// MPS
+#define MXL_MOCA_SOC_SET_MPS_TRIGGER (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0090) /* HI_TXNTYPE_SET_MPS_TRIGGER */
+#define MXL_MOCA_SOC_GET_MPS_REPORT (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0091) /* HI_TXNTYPE_GET_MPS_REPORT */
+#define MXL_MOCA_SOC_GET_MPS_STATE (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0092) /* HI_TXNTYPE_GET_MPS_REPORT */
+
+#define MXL_MOCA_SOC_GET_ECB_STATS (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0093) /* HI_TXNTYPE_GET_ECB_STATS */
+// Port Configure
+#define MXL_MOCA_SOC_SET_SWITCH_PORT_CONFIG (CMD_RESPONSE | MXL_MOCA_SOC_CMD | 0x0094) /* HI_TXNTYPE_SET_SWITCH_PORT_CONFIG */
+
+/*
+ * MxL MoCA Driver commands
+ */
+
+#define MXL_MOCA_DRV_SET_OTP (MXL_MOCA_DRV_CMD | 0x01) // Set OTP parameter
+#define MXL_MOCA_DRV_GET_CFG_AND_FW_DIR (MXL_MOCA_DRV_CMD | 0x02) // Get config dir and fw dir
+#define MXL_MOCA_DRV_RESET_DEVICE (MXL_MOCA_DRV_CMD | 0x04) // Reset the SoC.
+#define MXL_MOCA_DRV_STOP_DEVICE (MXL_MOCA_DRV_CMD | 0x05) // Stop the SoC.
+#define MXL_MOCA_DRV_GET_DAEMON_INFO (MXL_MOCA_DRV_CMD | 0x06) // Get Daemon Information
+#define MXL_MOCA_DRV_SET_BOOT_SOC (MXL_MOCA_DRV_CMD | 0x07) // Set socBooted and open Eth interface.
+#define MXL_MOCA_DRV_SET_MAC_ADDR (MXL_MOCA_DRV_CMD | 0x08) // Sets MAC address in the Driver subsystem.
+#ifdef SET_CD_FW_SUPPORT
+#define MXL_MOCA_DRV_SET_CD_FIRMWARE (MXL_MOCA_DRV_CMD | 0x09) // Set the MXL_MOCA_FIRMWARE_T in Clink Daemon
+#endif
+#define MXL_MOCA_DRV_SET_DATA_PLANE_VARS (MXL_MOCA_DRV_CMD | 0x0A) // Set Data Plane Variables.
+#define MXL_MOCA_DRV_GET_CHIP_TYPE (MXL_MOCA_DRV_CMD | 0x0B) // Gets the current Chip type of Soc.
+#define MXL_MOCA_DRV_START_DAEMON (MXL_MOCA_DRV_CMD | 0x0C) // Start daemon thread.
+#define MXL_MOCA_DRV_HW_RESET (MXL_MOCA_DRV_CMD | 0x0D) // Hardware reset
+#define MXL_MOCA_DRV_SW_RESET (MXL_MOCA_DRV_CMD | 0x0E) // Software reset
+#define MXL_MOCA_DRV_DEV_LOW_PWR_WITH_ESWITCH_ON (MXL_MOCA_DRV_CMD | 0x0F) // Standalone low power mode with eSwitching active
+
+#define MXL_MOCA_DRV_SET_APPLICATION_TRACE (MXL_MOCA_DRV_CMD | 0x10) // Send the Application clnktrace notification on/off to driver
+
+/*
+ * MxL MoCA Debug commands
+ */
+
+#define MXL_MOCA_DBG_GET_MEM (MXL_MOCA_DBG_CMD | 0x01) // Perform extended SoC memory read operation.
+#define MXL_MOCA_DBG_SET_MEM (MXL_MOCA_DBG_CMD | 0x02) // Perform extended SoC memory write operation.
+
+/*****************************************************************************************
+ User-Defined Types (Typedefs)
+ ****************************************************************************************/
+
+typedef struct
+{
+ uint32_t result;
+ int8_t str[MAX_PASSWORD_LENGTH_PADDED];
+} MXL_MOCA_SEC_PASSWORD_T; //SecPassword_t;
+
+/** Represents an address in the MaxLinear SoC FW */
+typedef unsigned int MXL_SOCFW_ADDR_T; //En2710_CcpuAddr_t;
+
+typedef struct
+{
+ uint32_t address; // MoCA SOC internal memory address
+ uint32_t *pBuf; // Pointer to user buffer
+ uint32_t bufsize;
+} MXL_MOCA_SOC_MEMORY_INFO_T;
+
+typedef struct
+{
+ uint32_t cmdBytes;
+ uint32_t cmdArray[1000]; // must adjust MAX_MBX_MSG to match this
+ uint32_t opId;
+ uint32_t resId;
+ uint32_t rspBytes;
+ uint32_t rspArray[1000]; // must adjust MAX_MBX_MSG to match this
+} MXL_MOCA_SOC_IOCTL_SEND_RCV_MBX;
+
+typedef struct
+{
+ uint32_t trapInfoSize; // Trap info area size in bytes
+ uint32_t errCode; // Error code
+ uint32_t errFileId; // Error file ID (see Diag_FileId.h)
+ uint32_t errLine; // Error line number
+ uint32_t bootStatus; // Boot status
+ uint32_t bootFileId; // Boot file ID (see Diag_FileId.h)
+ uint32_t bootLine; // Boot line number
+ uint32_t epc; // Exception program counter
+ uint32_t sp; // Stack pointer (CPU register)
+ uint32_t lr; // Link register (CPU register)
+ uint32_t threadName; // Thread's name
+ uint32_t threadRunCount; // Thread's run counter
+ uint32_t threadStackPtr; // Thread's stack pointer
+ uint32_t threadStackStart; // Stack starting address
+ uint32_t threadStackEnd; // Stack ending address
+ uint32_t threadStackSize; // Stack size
+ uint32_t threadPriority; // Priority of thread (0-1023)
+ uint32_t threadState; // Thread's execution state
+ uint32_t stackDump[16]; // Stack dump
+} MXL_MOCA_SOC_TRAP_INFO_T;
+
+/****************************************************************************************
+ Try to list all data types documented in SoC HI.docx
+ ****************************************************************************************/
+
+// MXL_MOCA_SOC_GET_SOC_STATUS / HI_TXNTYPE_GET_SOC_STATUS
+
+typedef struct
+{
+ uint32_t status;
+ uint32_t fatalCode;
+ uint32_t state;
+ uint32_t dbg;
+ uint32_t bbTemp;
+ uint32_t rfTemp;
+} MXL_MOCA_SOC_GET_SOC_STATUS_RSP_T; /* Hi_TxnGetSocStatusRsp_t*/
+
+// MXL_MOCA_SOC_GET_IMAGE_INFO / HI_TXNTYPE_GET_IMAGE_INFO
+
+typedef struct
+{
+ uint32_t messageVersion;
+ uint32_t hi;
+ uint32_t ecl;
+ uint32_t lc;
+ uint32_t mac;
+ uint32_t phyCtl;
+ uint32_t sws;
+ uint32_t hal;
+ uint32_t reserved0;
+ uint32_t reserved1;
+ uint32_t tcDic;
+ uint32_t tcCpc;
+ uint32_t tcHif;
+ uint32_t compile;
+ uint32_t socVerStr[MAX_VERSION_STR_SIZE / 4];
+} MXL_MOCA_SOC_GET_IMAGE_INFO_RSP_T; /* Hi_TxnGetImageInfoRsp_t */
+
+// MXL_MOCA_SOC_SET_INIT_START / HI_TXNTYPE_SET_INIT_START
+
+typedef struct
+{
+ uint32_t accepted;
+ uint32_t initStatusWord;
+ uint32_t initExceptionWord;
+ uint32_t initDataWord;
+} MXL_MOCA_SOC_INIT_SYSTEM_START_RSP_T; /* Hi_TxnSetInitSystemStartRsp_t */
+
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_SOC_GET_AGGR_STATS_CMD_T; /* Hi_TxnGetAggrStatsCmd_t */
+
+// MXL_MOCA_SOC_GET_AGGR_STATS / HI_TXNTYPE_GET_AGGR_STATS
+
+typedef struct
+{
+ uint32_t txAggNone;
+ uint32_t txAggP2[MAX_AGGR_FRAMES_V25-1];
+ uint32_t rxAggNone;
+ uint32_t rxAggP2[MAX_AGGR_FRAMES_V25-1];
+} MXL_MOCA_SOC_GET_AGGR_STATS_RSP_T; /* Hi_TxnGetAggrStatsRsp_t */
+
+// MXL_MOCA_SOC_GET_BRIDGE_STATS / HI_TXNTYPE_GET_BRIDGE_STATS
+
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_SOC_GET_BRIDGE_STATS_CMD_T; /* Hi_TxnGetBridgeStatsCmd_t */
+
+typedef struct
+{
+ uint32_t ucastDestEntries;
+ uint32_t mcastDestEntries;
+ uint32_t pqosDestEntries;
+ uint32_t ucastSrcEntries;
+ uint32_t mcastSrcEntries;
+ uint32_t totalHits;
+ uint32_t totalMisses;
+} MXL_MOCA_SOC_GET_BRIDGE_STATS_RSP_T; /* Hi_TxnGetBridgeStatsRsp_t */
+
+// MXL_MOCA_SOC_GET_BRIDGE_TABLE / HI_TXNTYPE_GET_BRIDGE_TABLE
+
+typedef struct
+{
+ uint32_t type;
+ uint32_t startIndex;
+} MXL_MOCA_SOC_GET_BRIDGE_TABLE_CMD_T; /* Hi_TxnGetBridgeTableCmd_t*/
+
+typedef struct
+{
+ uint32_t macAddrHi;
+ uint32_t macAddrLoIds;
+} MXL_MOCA_SOC_BRIDGE_ENTRY_T; /* Hi_TxnBridgeEntry_t */
+
+typedef struct
+{
+ uint32_t maxEntries;
+ MXL_MOCA_SOC_BRIDGE_ENTRY_T entry[32];
+} MXL_MOCA_SOC_GET_BRIDGE_TABLE_RSP_T; /* Hi_TxnGetBridgeTableRsp_t */
+
+// MXL_MOCA_SOC_GET_EPHY_STATS / HI_TXNTYPE_GET_EPHY_STATS
+
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_SOC_GET_EPHY_STATS_CMD_T; /* Hi_TxnGetEphyStatsCmd_t */
+
+// MXL_MOCA_SOC_GET_ECB_STATS / HI_TXNTYPE_GET_ECB_STATS
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_SOC_GET_ECB_STATS_CMD_T; /* Hi_TxnGetEcbStatsCmd_t */
+
+typedef struct
+{
+ uint32_t miiPausePriLvl;
+ uint32_t miiSpeed;
+ uint32_t rxGood[2];
+ uint32_t rxDrop[2];
+ uint32_t rxError[2];
+ uint32_t txGood[2];
+ uint32_t txDrop[2];
+ uint32_t txError[2];
+} MXL_MOCA_SOC_GET_EPHY_STATS_RSP_T; /* Hi_TxnGetEphyStatsRsp_t */
+
+typedef struct
+{
+ uint32_t sgmii0Rx;
+ uint32_t sgmii0Tx;
+ uint32_t pcieRx;
+ uint32_t pcieTx;
+ uint32_t sgmii1Rx;
+ uint32_t sgmii1Tx;
+ uint32_t mocaRx;
+ uint32_t mocaTx;
+ uint32_t debug0;
+ uint32_t debug1;
+ uint32_t debug2;
+ uint32_t debug3;
+ uint32_t debug4;
+ uint32_t debug5;
+ uint32_t debug6;
+ uint32_t debug7;
+ uint32_t debug8;
+ uint32_t debug9;
+ uint32_t debug10;
+ uint32_t debug11;
+ uint32_t debug12;
+ uint32_t debug13;
+ uint32_t debug14;
+ uint32_t debug15;
+ uint32_t debug16;
+
+} MXL_MOCA_SOC_GET_ECB_STATS_RSP_T; /* Hi_TxnGetEphyStatsRsp_t */
+
+// MXL_MOCA_SOC_GET_RETX_STATS / HI_TXNTYPE_GET_RETX_STATS
+
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_SOC_GET_RETRANS_STATS_CMD_T; /* Hi_TxnGetRetxStatsCmd_t */
+
+typedef struct
+{
+ uint32_t retxFrames[16];
+ uint32_t txTimeout[16];
+} MXL_MOCA_SOC_GET_RETRANS_STATS_RSP_T;
+
+// MXL_MOCA_SOC_GET_FRAG_STATS / HI_TXNTYPE_GET_FRAG_STATS
+
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_SOC_GET_FRAG_STATS_CMD_T;
+
+typedef struct
+{
+ uint32_t rxFragFrames;
+ uint32_t txFragFrames;
+} MXL_MOCA_SOC_GET_FRAG_STATS_RSP_T;
+
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_SOC_GET_DATA_STATS_CMD_T;
+
+typedef struct
+{
+ uint64_t txTotalPkts;
+ uint64_t txTotalBytes;
+ uint64_t txDroppedPkts;
+ uint64_t txBcastPkts;
+ uint64_t txBcastBytes;
+ uint64_t txMcastPkts;
+ uint64_t txMcastBytes;
+ uint64_t txUcastPkts[MAX_NUM_NODES];
+ uint64_t txUcastBytes[MAX_NUM_NODES];
+ uint64_t txGoodPktsInLast60s[MAX_NUM_NODES];
+ uint64_t txDroppedPktsInLast60s[MAX_NUM_NODES];
+ uint64_t rxTotalPkts;
+ uint64_t rxTotalBytes;
+ uint64_t rxDroppedPkts;
+ uint64_t rxBcastPkts[MAX_NUM_NODES];
+ uint64_t rxBcastBytes[MAX_NUM_NODES];
+ uint64_t rxMcastPkts[MAX_NUM_NODES];
+ uint64_t rxMcastBytes[MAX_NUM_NODES];
+ uint64_t rxUcastPkts[MAX_NUM_NODES];
+ uint64_t rxUcastBytes[MAX_NUM_NODES];
+ uint64_t rxGoodPktsInLast60s[MAX_NUM_NODES];
+ uint64_t rxBadPktsInLast60s[MAX_NUM_NODES];
+} MXL_MOCA_SOC_GET_DATA_STATS_RSP_T;
+
+// MXL_MOCA_SOC_GET_L2ME_STATS / HI_TXNTYPE_GET_L2ME_STATS
+
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_SOC_GET_L2ME_STATS_CMD_T;
+
+typedef struct
+{
+ uint32_t l2meIssuedTxns;
+ uint32_t l2meSuccessfulTxns;
+ uint32_t l2meTimedOutCycles;
+ uint32_t l2meFailedTxns;
+} MXL_MOCA_SOC_GET_L2ME_STATS_RSP_T;
+
+// MXL_MOCA_SOC_GET_MULTICAST_MODE / HI_TXNTYPE_SET_MULTICAST_MODE
+
+typedef struct
+{
+ uint32_t mode;
+} MXL_MOCA_SOC_GET_MCAST_MODE_RSP_T; /* Hi_TxnGetMcastModeRsp_t */
+
+// MXL_MOCA_SOC_SET_MULTICAST_MODE / HI_TXNTYPE_SET_MULTICAST_MODE
+
+typedef struct
+{
+ uint32_t mode;
+} MXL_MOCA_SOC_SET_MCAST_MODE_CMD_T; /* Hi_TxnSetMcastModeCmd_t */
+
+typedef struct
+{
+ uint32_t result;
+} MXL_MOCA_SOC_SET_MCAST_MODE_RSP_T; /* Hi_TxnSetMcastModeRsp_t */
+
+// MXL_MOCA_SOC_SET_GET_TX_PWR_VAR / HI_TXNTYPE_SET_GET_TX_PWR_VAR
+
+typedef struct
+{
+ uint32_t set; // If true, set to new value before get
+ uint32_t nodeId;
+ uint32_t txPwrVariation; // New value if 'set' is true
+} MXL_MOCA_SOC_SET_GET_TXPWR_VAR_CMD_T; /* Hi_TxnSetGetTxPwrVarCmd_t */
+
+typedef struct
+{
+ uint32_t txPwrVariation; // Current Tx power variation value
+} MXL_MOCA_SOC_SET_GET_TXPWR_VAR_RSP_T; /* Hi_TxnSetGetTxPwrVarRsp_t */
+
+// MXL_MOCA_SOC_SET_PHY_MOD_BITMASK / HI_TXNTYPE_SET_PHY_MOD_BITMASK
+
+typedef struct
+{
+ uint32_t nodeId;
+ uint32_t type;
+ uint32_t value;
+} MXL_MOCA_SOC_SET_PHYMODE_BITMASK_CMD_T; /* Hi_TxnSetPhyModBitmaskCmd_t */
+
+typedef struct
+{
+ uint32_t result;
+} MXL_MOCA_SOC_SET_PHYMODE_BITMASK_RSP_T; /* Hi_TxnSetPhyModBitmaskRsp_t */
+
+// MXL_MOCA_SOC_SET_MULTICAST_INFO / HI_TXNTYPE_SET_MULTICAST_INFO
+
+typedef struct
+{
+ uint32_t macAddrHi;
+ uint32_t macAddrLo;
+ uint32_t mode;
+} MXL_MOCA_SOC_SET_MULTICAST_FILTER_CMD_T;
+
+typedef struct
+{
+ uint32_t result;
+} MXL_MOCA_SOC_SET_MULTICAST_FILTER_RSP_T;
+
+typedef struct
+{
+ /**
+ * The exclusive set of multicast MAC address allowed to pass
+ * from MoCA to host when filter mode is set to Enabled. When
+ * filter mode is set to DfidOnly, then the following list of
+ * MAC addresses are only filtered by MAP DFID and not by
+ * precise MAC Address. This is only useful for internal
+ * testing.
+ *
+ * The first array entry with a 0 in macAddrHi indicates that it
+ * and all following array entries do not contain a valid entry.
+ */
+ uint32_t macAddrHi[48];
+ uint32_t macAddrLo[48];
+ /**
+ * The filter mode enables or disables multicast filtering
+ * for the MoCA device.
+ *
+ * The values for filter mode are: Disabled (0), Enabled (1),
+ * and DfidOnly (2).
+ */
+ uint32_t mode;
+} MXL_MOCA_SOC_SET_MULTICAST_CFG_CMD_T; //Hi_TxnSetMultiCastCfgCmd_t
+
+typedef struct
+{
+ uint32_t result;
+} MXL_MOCA_SOC_SET_MULTICAST_CFG_RSP_T;
+
+///3.5 Link
+
+// MXL_MOCA_SOC_REQUEST_HANDOFF / HI_TXNTYPE_REQUEST_HANDOFF
+
+typedef struct
+{
+ uint32_t nodeId;
+ uint32_t isBnc;
+} MXL_MOCA_SOC_REQ_HANDOFF_CMD_T;
+
+typedef struct
+{
+ uint32_t status;
+} MXL_MOCA_SOC_REQ_HANDOFF_RSP_T;
+
+// MXL_MOCA_SOC_REQUEST_LMO / HI_TXNTYPE_REQUEST_LMO
+
+typedef struct
+{
+ uint32_t type; //!< LMO type
+
+ union
+ {
+ struct
+ {
+ uint32_t type; //!< Assessment type 0 - Quiet , 1 - EVM
+ uint32_t channel;
+ uint32_t srcNodeId;
+ uint32_t dstNodeMask;
+ } aca;
+
+ struct
+ {
+ uint32_t nodeId; //!< OOO lmo node ID
+ } ooo;
+
+ struct
+ {
+ uint32_t type; //!< 0 - Unicast, 1 OFDMA
+ uint32_t nodeMask; //!< Mask of nodes involved
+ } upr;
+
+ struct
+ {
+ uint32_t nodeId; //!< Tx node Id
+ uint32_t probeId; //!< Pre-Defined Probe identifier
+ } rdp;
+
+ struct
+ {
+ uint32_t timeSlots;
+ } silent;
+
+ struct
+ {
+ uint32_t timeSlots;
+ } loopBack;
+
+ } data;
+} MXL_MOCA_SOC_REQ_LMO_CMD_T;
+
+typedef struct
+{
+ uint32_t type;
+ uint32_t nodeId;
+ uint32_t result;
+
+ union
+ {
+ struct
+ {
+ uint32_t type; //!< Assessment type 0 - Quiet , 1 - EVM
+ uint32_t txStatus;
+ uint32_t status;
+ uint32_t power;
+ uint32_t relativePower;
+ uint8_t powerProfile[LMO_ACA_RPT_PWR_PRFL_SZ];
+ } aca;
+ } data;
+} MXL_MOCA_SOC_REQ_LMO_RSP_T;
+
+// MXL_MOCA_SOC_MOCA_RESET / HI_TXNTYPE_MOCA_RESET
+
+typedef struct
+{
+ uint32_t lof;
+ uint32_t nodemask;
+ uint32_t seconds;
+} MXL_MOCA_SOC_MOCA_RESET_CMD_T; /* Hi_TxnMocaResetRequest_t */
+
+typedef struct
+{
+ uint32_t mrCode;
+ uint32_t issuedNodemask;
+ uint32_t topLastResetStatus;
+ uint32_t nodeLastResetStatus[MAX_NODES];
+ uint32_t nodeLastResponseCode[MAX_NODES];
+} MXL_MOCA_SOC_MOCA_RESET_RSP_T; /* Hi_TxnMocaResetResponse_t */
+
+// MXL_MOCA_SOC_GET_FRAME_STATS / HI_TXNTYPE_GET_FRAME_STATS
+
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_SOC_GET_FRAME_STATS_CMD_T; /* Hi_TxnGetFrameStatsCmd_t */
+
+typedef struct
+{
+ uint64_t totalMap;
+ uint64_t totalRr;
+ uint64_t totalLc;
+ uint64_t totalBcn;
+ uint64_t totalAcf;
+ uint64_t totalProbe;
+ uint64_t totalEth;
+ uint64_t totalOfdmaRr;
+ uint64_t totalOfdmaEvm;
+} MXL_MOCA_SOC_CATEGORY_T; /* Hi_Category_t */
+
+typedef struct
+{
+ MXL_MOCA_SOC_CATEGORY_T txGood;
+ MXL_MOCA_SOC_CATEGORY_T txError;
+ MXL_MOCA_SOC_CATEGORY_T txDropped;
+ MXL_MOCA_SOC_CATEGORY_T rxGood;
+ MXL_MOCA_SOC_CATEGORY_T rxError;
+ MXL_MOCA_SOC_CATEGORY_T rxDropped;
+} MXL_MOCA_SOC_GET_FRAME_STATS_RSP_T; /* Hi_TxnGetFrameStatsRsp_t */
+
+
+// MXL_MOCA_SOC_GET_LOCAL_INFO / HI_TXNTYPE_GET_LOCAL_INFO
+
+typedef struct
+{
+ uint32_t nodeId;
+ uint32_t ncNodeId;
+ uint32_t nextNcNodeId;
+ uint32_t backupNodeId;
+ uint32_t lmoNodeId;
+ uint32_t linkStatus;
+ uint32_t lastAdmStatus;
+ uint32_t beaconRxPwrLevel; /* Beacon Rx power level (dBm) */
+ uint32_t role;
+ uint32_t netState;
+ uint32_t resetCnt;
+ uint32_t mocaVer;
+ uint32_t activeMask;
+ uint32_t sleepM1NodeBitmask;
+ uint32_t sleepM2NodeBitmask;
+ uint32_t sleepM3NodeBitmask;
+ uint32_t tabooMask;
+ uint32_t tabooOffset;
+ uint32_t priChnOffset;
+ uint32_t secChnOffset;
+ uint32_t pqosFlowPolicingFlag;
+ uint32_t socVersionStr[MAX_VERSION_STR_SIZE / 4];
+ uint32_t reqStatus;
+ uint32_t customBandProfCGapMode;
+} MXL_MOCA_SOC_GET_LOCAL_INFO_RSP_T; /* Hi_TxnGetLocalInfoRsp_t */
+
+// MXL_MOCA_SOC_GET_NET_INFO / HI_TXNTYPE_GET_NET_INFO
+
+typedef struct
+{
+ uint32_t nodeId;
+} MXL_MOCA_SOC_GET_NET_INFO_CMD_T; /* Hi_TxnGetNetInfoCmd_t */
+
+typedef struct
+{
+ uint32_t guidHi;
+ uint32_t guidLo;
+ uint32_t state;
+ uint32_t protoSupport;
+ uint32_t mocaVer;
+ uint64_t txCtlFrameGood; // Number of MoCA Ctl Frames / Probes successfully TXed
+ uint64_t txCtlFrameError; // Number of MoCA Ctl Frames / Probes that errored out (Tx Late) during TX
+ uint64_t txCtlFrameDropped; // Number of MoCA Ctl Frames / Probes that were dropped
+ uint64_t rxCtlFrameGood; // Number of MoCA Ctl Frames / Probes successfully RXed
+ uint64_t rxCtlFrameError; // Number of MoCA Ctl Frames / Probes that errored out (Rx Late, CRC Err) during RX
+ uint64_t rxCtlFrameDropped; // Number of MoCA Ctl Frames / Probes that were dropped
+ uint64_t txDataFrameGood; // Number of MoCA Data Frames successfully TXed
+ uint64_t txDataFrameDropped; // Number of MoCA Data Frames dropped (TX Data Late)
+ uint64_t rxDataFrameGood; // Number of MoCA Data Frames successfully RXed
+ uint64_t rxDataFrameBad; // Number of MoCA Data Frames with errors / drops during RX (RX Data Late, MPDU HDR CRC Err, APDU HDR CRC Err, BD Failure, PDU CRC Err)
+} MXL_MOCA_SOC_GET_NET_INFO_RSP_T; /* Hi_TxnGetNetInfoRsp_t */
+
+// MXL_MOCA_SOC_GET_FMR_INFO / HI_TXNTYPE_REQUEST_FMR
+
+typedef struct
+{
+ uint32_t nodeMask;
+ uint32_t fmrVer;
+} MXL_MOCA_SOC_GET_FMR_INFO_CMD_T;
+
+typedef struct
+{
+ uint32_t rsp[104];
+} MXL_MOCA_SOC_GET_FMR_INFO_RSP_T;
+
+// MXL_MOCA_SOC_GET_DD_INFO / HI_TXNTYPE_GET_DD_INFO
+
+typedef struct
+{
+ uint32_t nodeMask;
+} MXL_MOCA_SOC_GET_DD_INFO_CMD_T; // Device Discovery Info
+
+typedef struct
+{
+ uint32_t rsp[100];
+} MXL_MOCA_SOC_GET_DD_INFO_RSP_T;
+
+// MXL_MOCA_SOC_REQUEST_NMS / HI_TXNTYPE_REQUEST_NMS
+
+typedef struct
+{
+ uint32_t reserved; //!< Reserved
+} MXL_MOCA_SOC_REQ_NMS_CMD_T;
+
+//! NMS response information
+typedef struct
+{
+ uint32_t result;
+} MXL_MOCA_SOC_REQ_NMS_RSP_T;
+
+// MXL_MOCA_SOC_REQUEST_SPECTRUM / HI_TXNTYPE_REQUEST_SPECTRUM
+
+typedef struct
+{
+ uint32_t request;
+} MXL_MOCA_SOC_REQ_SPECTRUM_CMD_T;
+
+typedef struct
+{
+ uint32_t result;
+} MXL_MOCA_SOC_REQ_SPECTRUM_RSP_T;
+
+// MXL_MOCA_SOC_GET_PHY_TX_PROFILE / HI_TXNTYPE_GET_PHY_TX_PROFILE
+
+typedef struct
+{
+ uint32_t nodeId;
+ uint32_t profileId;
+ uint32_t getBitloading;
+} MXL_MOCA_SOC_GET_PHY_TX_PROFILE_CMD_T; /* Hi_TxnGetPhyTxProfileCmd_t */
+
+typedef struct
+{
+ uint32_t txProfileValid;
+ uint32_t iqTxCoef;
+ uint32_t iqTxDelay;
+ uint32_t iqTxDslope_AB;
+ uint32_t iqTxDslope_CD;
+ uint32_t txCpLen;
+ uint32_t txNumSymbols;
+ uint32_t txBitsPerSymbol;
+ uint32_t txChnUsable;
+ uint32_t txPreamble;
+ uint32_t txTpcBackoff;
+ uint32_t txKLdpcMax;
+ uint32_t txPhyrate;
+ uint32_t seqNum;
+ uint32_t nodeMask;
+ uint32_t txBitloading[64];
+} MXL_MOCA_SOC_GET_PHY_TX_PROFILE_RSP_T; /* Hi_TxnGetPhyTxProfileRsp_t */
+
+// MXL_MOCA_SOC_GET_PHY_RX_PROFILE / HI_TXNTYPE_GET_PHY_RX_PROFILE
+
+typedef struct
+{
+ uint32_t nodeId;
+ uint32_t profileId;
+ uint32_t getBitloading;
+} MXL_MOCA_SOC_GET_PHY_RX_PROFILE_CMD_T; /* Hi_TxnGetPhyRxProfileCmd_t */
+
+typedef struct
+{
+ uint32_t rxProfileValid;
+ uint32_t iqRxCoef;
+ uint32_t iqRxDelay;
+ uint32_t iqRxDslope_AB;
+ uint32_t iqRxDslope_CD;
+ uint32_t rxCpLen;
+ uint32_t rxChnPrecurBias;
+ uint32_t agc_b8_f8_digi16;
+ uint32_t agc_b8_f8_digi3_16;
+ uint32_t rxNumSymbols;
+ uint32_t rxBitsPerSymbol;
+ uint32_t rxChnUsable;
+ uint32_t rxPreamble;
+ uint32_t rxTpcBackoff;
+ uint32_t rxKLdpcMax;
+ uint32_t rxPhyrate;
+ uint32_t rxPwrLevel;
+ uint32_t seqNum;
+ uint32_t rxBitloading[64];
+ uint32_t rxChnSnr;
+} MXL_MOCA_SOC_GET_PHY_RX_PROFILE_RSP_T; /* Hi_TxnGetPhyRxProfileRsp_t */
+
+// MXL_MOCA_SOC_GET_PHY_NODE / HI_TXNTYPE_GET_PHY_NODE
+
+typedef struct
+{
+ uint32_t nodeId;
+} MXL_MOCA_SOC_GET_PHY_NODE_CMD_T; /* Hi_TxnGetPhyNodeCmd_t */
+
+typedef struct
+{
+ uint32_t valid;
+ uint32_t freqOffset;
+ uint32_t rangeValid;
+ uint32_t nodeDelay;
+ uint32_t validTxProf;
+} MXL_MOCA_SOC_GET_PHY_NODE_RSP_T; /* Hi_TxnGetPhyNodeRsp_t */
+
+// MXL_MOCA_SOC_GET_PHY_EVM / HI_TXNTYPE_GET_PHY_EVM
+
+typedef struct
+{
+ uint32_t nodeId;
+ uint32_t profileId;
+} MXL_MOCA_SOC_GET_PHY_EVM_CMD_T; /* Hi_TxnGetPhyEvmCmd_t */
+
+typedef struct
+{
+ uint32_t rxProfileValid;
+ uint32_t rxEvm[128];
+} MXL_MOCA_SOC_GET_PHY_EVM_RSP_T; /* Hi_TxnGetPhyEvmRsp_t */
+
+// MXL_MOCA_SOC_GET_PHY_MISC / HI_TXNTYPE_GET_PHY_MISC
+
+typedef struct
+{
+ uint32_t temperature;
+ uint32_t currentOperatingFrequency;
+} MXL_MOCA_SOC_GET_PHY_MISC_RSP_T; /* Hi_TxnGetPhyMiscRsp_t */
+
+// MXL_MOCA_SOC_GET_M25_PHY_MISC / HI_TXNTYPE_GET_M25_PHY_MISC
+
+typedef struct
+{
+ uint32_t temperature;
+ uint32_t currentOperatingFrequency;
+ uint32_t firstChannelFrequency;
+ uint32_t numberM25Channels;
+} MXL_MOCA_SOC_GET_M25_PHY_MISC_RSP_T; /* Hi_TxnGetM25PhyMiscRsp_t*/
+
+// MXL_MOCA_SOC_GET_OFDMA_SC_DEF / HI_TXNTYPE_GET_OFDMA_SC_DEF
+
+typedef struct
+{
+ struct
+ {
+ uint32_t subchanDefID;
+ uint32_t nodeBitmask;
+ uint32_t bitsPerSubchanelPerSym;
+ uint32_t gapOfdma;
+ uint32_t numSubchan;
+ } profile[MAX_OFDMA_PROFILES];
+} MXL_MOCA_SOC_GET_PHY_OFDMA_DEF_RSP_T; /* Hi_TxnGetPhyOfdmaDefRsp_t */
+
+// MXL_MOCA_SOC_GET_OFDMA_SC_ASSIGN / HI_TXNTYPE_GET_OFDMA_SC_ASSIGN
+
+typedef struct
+{
+ struct
+ {
+ uint32_t frameID;
+ uint32_t subchanDefID;
+ uint32_t numSubchan;
+ uint32_t nodeBitmask;
+ uint32_t cpLen;
+ } profile[MAX_OFDMA_PROFILES];
+} MXL_MOCA_SOC_GET_PHY_OFDMA_ASSIGN_RSP_T; /* Hi_TxnGetPhyOfdmaAssignRsp_t */
+
+// MXL_MOCA_SOC_GET_OFDMA_PARAMS / HI_TXNTYPE_GET_OFDMA_PARAMS
+
+typedef struct
+{
+ int32_t result;
+ uint32_t ofdmaGrps;
+ uint32_t m2NodeMask;
+ uint32_t ofdmaNodeMask;
+} MXL_MOCA_SOC_GET_OFDMA_PARAMS_RSP_T; /* Hi_TxnGetOfdmaParamsRsp_t */
+
+// MXL_MOCA_SOC_GET_OFDMA_TX_PROFILE / HI_TXNTYPE_GET_OFDMA_TX_PROFILE
+
+typedef struct
+{
+ int32_t result;
+ uint32_t usedProfileTypeMask;
+ uint32_t numAsgnTbls;
+ uint32_t blt[64];
+ uint32_t phyFrameId;
+ uint32_t preambleType;
+ uint32_t cpLen;
+ uint32_t kLdpcMax;
+ uint32_t rrUnitLength;
+ uint32_t rateMultNi;
+ uint32_t bitsPerSymbol;
+ int32_t TPC;
+ uint32_t propDelay;
+ int32_t propDelayOffset;
+ uint32_t propDelayMax;
+ int32_t freqOffset;
+ int32_t txIq[2];
+} MXL_MOCA_SOC_GET_OFDMA_TX_PROFILE_RSP_T; /* Hi_TxnGetOfdmaTxProfileRsp_t */
+
+// MXL_MOCA_SOC_GET_OFDMA_RX_PROFILE / HI_TXNTYPE_GET_OFDMA_RX_PROFILE
+
+typedef struct
+{
+ int32_t result;
+ uint32_t numAsgnTbls;
+ uint32_t sumNi;
+ uint32_t blt[64];
+ uint32_t contextId[64];
+ uint32_t phyFrameId;
+ uint32_t clNodeMask;
+ uint32_t preambleType;
+ uint32_t cpLen;
+ uint32_t kLdpcMax;
+ uint32_t rrUnitLength;
+ uint32_t rateMultNi[8];
+ uint32_t bitsPerSymbolPerNi;
+ int32_t TPC[8];
+ uint32_t digitalGain;
+ uint32_t analogGain;
+ uint32_t feGain;
+ uint32_t beGain;
+ int32_t powerLevel;
+ uint32_t propDelayMax;
+ int32_t rxIq[2];
+ int32_t rxIdDslope[4];
+} MXL_MOCA_SOC_GET_OFDMA_RX_PROFILE_RSP_T; /* Hi_TxnGetOfdmaRxProfileRsp_t */
+
+// MXL_MOCA_SOC_GET_OFDMA_TX_PROFILE / HI_TXNTYPE_GET_OFDMA_TX_PROFILE
+
+typedef struct
+{
+ uint32_t role; // Either NC or BNC
+ uint32_t asgnTblIdx; // Index of assignment table that you want access
+} MXL_MOCA_SOC_GET_OFDMA_TX_PROFILE_CMD_T; /* Hi_TxnGetOfdmaTxProfileCmd_t*/
+
+// MXL_MOCA_SOC_GET_OFDMA_RX_PROFILE / HI_TXNTYPE_GET_OFDMA_RX_PROFILE
+typedef struct
+{
+ uint32_t profileNum;
+ uint32_t asgnTblIdx; // Index of assignment table that you want access
+} MXL_MOCA_SOC_GET_OFDMA_RX_PROFILE_CMD_T; /* Hi_TxnGetOfdmaRxProfileCmd_t */
+
+// Power Management
+
+// MXL_MOCA_SOC_SLEEP / HI_TXNTYPE_SLEEP
+
+typedef struct
+{
+ uint32_t requestedState;
+} MXL_MOCA_SOC_POWER_SLEEP_CMD_T; /* Hi_TxnPowerSleepCmd_t */
+
+typedef struct
+{
+ uint32_t actualState;
+ uint32_t result;
+} MXL_MOCA_SOC_POWER_SLEEP_RSP_T; /* Hi_TxnPowerSleepRsp_t */
+
+// MXL_MOCA_SOC_WAKE / HI_TXNTYPE_WAKE
+
+typedef struct
+{
+ uint32_t nodeId;
+} MXL_MOCA_SOC_POWER_WAKE_CMD_T; /* Hi_TxnPowerWakeCmd_t */
+
+
+typedef struct
+{
+ uint32_t actualState;
+ uint32_t result;
+} MXL_MOCA_SOC_POWER_WAKE_RSP_T; /* Hi_TxnPowerWakeRsp_t */
+
+// MXL_MOCA_SOC_GET_PM_CAPS / HI_TXNTYPE_GET_PM_CAPS
+
+typedef struct
+{
+ uint32_t capsMask;
+ uint32_t result;
+} MXL_MOCA_SOC_GET_PM_CAPS_RSP_T; /* Hi_TxnGetPmCapsRsp_t */
+
+// MXL_MOCA_SOC_QUERY_PM_STATE / HI_TXNTYPE_QUERY_PM_STATE
+
+typedef struct
+{
+ uint32_t nodeId;
+} MXL_MOCA_SOC_QUERY_PM_STATE_CMD_T; /* Hi_TxnQueryPmStateCmd_t */
+
+typedef struct
+{
+ uint32_t powerState;
+ uint32_t lastHbIvSecs;
+ int32_t ncHbIvExpiresInSecs;
+ uint32_t clStartedHbIvTimerCount;
+} MXL_MOCA_SOC_QUERY_PM_STATE_RSP_T; /* Hi_TxnQueryPmStateRsp_t */
+
+// MXL_MOCA_SOC_GET_PM_EVENTS / HI_TXNTYPE_GET_PM_EVENTS
+
+typedef struct
+{
+ uint32_t clearEvent;
+} MXL_MOCA_SOC_GET_PM_EVENT_CMD_T; /* Hi_TxnGetPmEventCmd_t */
+
+typedef struct
+{
+ uint32_t nodeId;
+ uint32_t isLocal;
+ uint32_t state;
+} MXL_MOCA_SOC_PM_SLEEP_EVENT_DATA_T; /* Hi_PmSleepEventData_t */
+
+typedef struct
+{
+ uint32_t nodeId;
+ uint32_t isLocal;
+} MXL_MOCA_SOC_PM_WAKE_EVENT_DATA_T; /* Hi_PmWakeEventData_t */
+
+typedef struct
+{
+ uint32_t nodeId;
+ uint32_t isLocal;
+} MXL_MOCA_SOC_PM_WOM_EVENT_DATA_T; /* Hi_PmWomEventData_t */
+
+
+typedef union
+{
+ MXL_MOCA_SOC_PM_SLEEP_EVENT_DATA_T sleep;
+ MXL_MOCA_SOC_PM_WAKE_EVENT_DATA_T wake;
+ MXL_MOCA_SOC_PM_WOM_EVENT_DATA_T wom;
+} MXL_MOCA_SOC_PM_EVENT_DATA_T; /* Hi_PmEventData_t */
+
+typedef struct
+{
+ int32_t event; // -1 if no event
+ MXL_MOCA_SOC_PM_EVENT_DATA_T eventData;
+ uint32_t result;
+} MXL_MOCA_SOC_GET_PM_EVENT_RSP_T; /* Hi_TxnGetPmEventRsp_t */
+
+// MXL_MOCA_SOC_HOST_IF_READY / HI_TXNTYPE_HOST_IF_READY
+
+typedef struct
+{
+ uint32_t result;
+} MXL_MOCA_SOC_HOST_IF_READY_RSP_T; /* Hi_TxnHostIfReadyRsp_t */
+
+
+///QOS
+
+typedef struct
+{
+ uint32_t hi;
+ uint32_t lo;
+} MXL_MOCA_MAC_ADDR_T;
+
+typedef uint32_t MXL_MOCA_SOC_FLOWCODE_T;
+
+typedef struct
+{
+ MXL_MOCA_MAC_ADDR_T flowId; //!< PQoS flow ID
+ uint32_t tPktSize; //!< Traffic packet size
+ MXL_MOCA_MAC_ADDR_T ingressGuid; //!< Ingress GUID
+ MXL_MOCA_MAC_ADDR_T egressGuid; //!< Egress GUID
+ uint32_t flowTag; //!< Flow tag
+ MXL_MOCA_MAC_ADDR_T packetDa; //!< Packet destination address
+ uint32_t tPeakDataRateKbps; //!< Traffic peak data rate
+ uint32_t tLeaseTimeSec; //!< Traffic lease time
+ uint32_t tBurstSize; //!< Traffic burst size
+ uint32_t maxLatencyMs; //!< M2: Maximum latency
+ uint32_t stAvgRatio; //!< M2: Short term average ratio
+ uint32_t maxNumRetry; //!< M2: Maximum number of retx attempts
+ uint32_t flowPer; //!< M2: Flow PER (NPER or VLPER)
+ uint32_t inOrderDeliver; //!< M2, no query: In order delivery recommendation
+ uint32_t tProtocol; //!< M2, no query: Traffic protocol
+ uint32_t ingressClass; //!< M2: Ingress classification rule
+ uint32_t vlanTag; //!< M2: VLAN tag
+ uint32_t dscpMoca; //!< M2: DSCP MoCA value
+} MXL_MOCA_SOC_PFP_CMD_T; /* Hi_PFP_t */
+
+// MXL_MOCA_SOC_CREATE_FLOW / HI_TXNTYPE_CREATE_FLOW
+// MXL_MOCA_SOC_UPDATE_FLOW / HI_TXNTYPE_UPDATE_FLOW
+
+typedef struct
+{
+ MXL_MOCA_SOC_FLOWCODE_T flowCode; //!< Response code, encodes DECISION
+ uint32_t postStps; //!< W1REQ: POST_STPS
+ uint32_t postTxps; //!< W1REQ: POST_TXPS
+ uint32_t dfid; //!< W1REQ: DFID
+ uint32_t maxRetryNum; //!< W1REQ: Maximum allowed retry number
+ uint32_t maxShortTermAvRatio;//!< W1REQ: Maximum allowed short term avg ratio
+ uint32_t remainKbps; //!< W1REQ: MAX_PEAK_DATA_RATE
+ uint32_t remainBurst; //!< W1REQ: MAX_BURST_SIZE
+ uint32_t decision; //!< W1REQ: DECISION
+ uint32_t bwLimitInfo; //!< W1REQ: BW_LIMIT_INFO
+ uint32_t isIngressLimited; //!< W1REQ: BW_LIMIT_INFO(3)
+ uint32_t isEgressLimited; //!< W1REQ: BW_LIMIT_INFO(3)
+ uint32_t isAggrStpsLimited; //!< W1REQ: BW_LIMIT_INFO(1)
+ uint32_t isAggrTxpsLimited; //!< W1REQ: BW_LIMIT_INFO(0)
+ uint32_t currMaxStps; //!< Estimate of current max MOCA STPS
+ uint32_t currMaxTxps; //!< Estimate of current max MOCA TXPS
+} MXL_MOCA_SOC_FLOW_CREATE_OR_UPDATE_RSP_T; /* Hi_FlowCURsp_t */
+
+// MXL_MOCA_SOC_DELETE_FLOW / HI_TXNTYPE_DELETE_FLOW
+
+//! Flow delete response
+typedef struct
+{
+ MXL_MOCA_SOC_FLOWCODE_T flowCode; //!< Response
+ uint32_t numNodesDelRsrc; //!< Number of nodes that deleted something
+} MXL_MOCA_SOC_FLOW_DELETE_RSP_T; /* Hi_FlowDeleteRsp_t */
+
+// MXL_MOCA_SOC_LIST_FLOW / HI_TXNTYPE_LIST_FLOW
+
+//! Flow list request.
+typedef struct
+{
+ MXL_MOCA_MAC_ADDR_T ingressGuid; //!< Queried node
+ uint32_t flowStartIndex; //!< First flow index to return in logical table
+ uint32_t flowMaxReturn; //!< Maximum number of flows to return
+} MXL_MOCA_SOC_FLOW_LIST_CMD_T; /* Hi_FlowListReq_t */
+
+//! Flow list response.
+typedef struct
+{
+ MXL_MOCA_SOC_FLOWCODE_T flowCode; //!< Response
+ uint32_t flowUpdateCount; //!< Event for each flow change at node
+ uint32_t totalFlowIdCount; //!< Flows for which node is Ingress
+ uint32_t numReturnedFlowIds; //!< Num flows populated in table below
+ MXL_MOCA_MAC_ADDR_T returnedFlowId[MAX_FLOWS_IN_LIST];
+} MXL_MOCA_SOC_FLOW_LIST_RSP_T; /* Hi_FlowListRsp_t */
+
+typedef struct
+{
+ MXL_MOCA_SOC_FLOWCODE_T flowCode; //!< Response code, encodes W1REQ DECISION
+ uint32_t leaseTimeLeft; //!< Lease time left (seconds)
+ MXL_MOCA_SOC_PFP_CMD_T pfp; //!< Parameters for PQoS Flow
+ uint32_t dfid; //!< DFID, 8 bit routing number
+} MXL_MOCA_SOC_FLOW_QUERY_RSP_T; /* Hi_FlowQueryRsp_t */
+
+// MXL_MOCA_SOC_GET_FLOW_STATS / HI_TXNTYPE_GET_FLOW_STATS
+
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_SOC_GET_FLOW_STATS_CMD_T; /* Hi_TxnGetFlowStatsCmd_t */
+
+//! Flow statistics
+typedef struct
+{
+ /** Number of times that this node has seen other nodes admit and drop */
+ uint32_t countTopologyChanged;
+ /** Number of times that this node has been the ingress for a creation,
+ * update, or deletion of a Flow. */
+ uint32_t countIngressFlowChanged;
+ /** Number of times a PQoS maintenance cycle has reported that Flows
+ * in the network are at risk due to changing topology or bandwidth
+ * availability. */
+ uint32_t countBwExceeded;
+ /** Number of times this node has detected that a change in the network
+ * version has occurred. This directly corresponds to events that cause
+ * network-wide PQoS guarantee changes. */
+ uint32_t countNwVersionChange;
+ /** Node's estimate of maximum STPS possible in the network, may differ from
+ * the NC's version. */
+ uint32_t currentMaxStps;
+ /** Node's estimate of maximum TXPS possible in the network, may differ from
+ * the NC's version. */
+ uint32_t currentMaxTxps;
+ /** Flow Maintenance: several fields update every PQoS maintenance cycle- this
+ * field increments every maintenance. */
+ uint32_t fmUpdateCount;
+ /** Flow Maintenance: cache of the IOC_NODEMASK value during the last
+ * maintenance. Represents which nodeIds are over ingress commitment */
+ uint32_t fmIocNodemask;
+ /** Flow Maintenance: cache of the ALLOCATED_STPS value during the last
+ * maintenance. Represents networkwide allocation of slot times. */
+ uint32_t fmAllocatedStps;
+ /** Flow Maintenance: cache of the ALLOCATED_TXPS value during the last
+ * maintenance. Represents networkwide allocation of transmissions. */
+ uint32_t fmAllocatedTxps;
+} MXL_MOCA_SOC_FLOW_STATS_RSP_T; /* Hi_FlowStats_t */
+
+///SEC
+//
+
+// MXL_MOCA_SOC_GET_SEC_PASSWORD / HI_TXNTYPE_GET_SEC_PASSWORD
+
+typedef struct
+{
+ uint32_t result;
+ uint32_t password[5];
+} MXL_MOCA_SOC_GET_SEC_PASSWD_RSP_T;
+
+// MXL_MOCA_SOC_GET_SEC_INFO / HI_TXNTYPE_GET_SEC_INFO
+
+typedef struct
+{
+ uint32_t state;
+ uint32_t mmk[2]; ///TODO 07/12/2011 API is of size 2*sizeof(uint32_t) SoC Hi is of sizeof(uint32_t)
+ uint32_t pmkInit[2]; ///TODO 07/12/2011 API is of size 2*sizeof(uint32_t) SoC Hi is of sizeof(uint32_t)
+ uint32_t pmk0[2];
+ uint32_t pmk1[2];
+ uint32_t activePmk;
+ uint32_t tek0[2];
+ uint32_t tek1[2];
+ uint32_t activeTek;
+ uint32_t ammk[4];
+ uint32_t apmkInit[4];
+ uint32_t apmk0[4];
+ uint32_t apmk1[4];
+ uint32_t activeApmk;
+ uint32_t atek0[4];
+ uint32_t atek1[4];
+ uint32_t activeAtek;
+ uint32_t permSalt[3];
+} MXL_MOCA_SOC_GET_SEC_INFO_RSP_T;
+
+// MXL_MOCA_SOC_GET_SEC_STATS / HI_TXNTYPE_GET_SEC_STATS
+
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_SOC_GET_SEC_STATS_CMD_T;
+
+typedef struct
+{
+ uint32_t txNoSec;
+ uint32_t txPmkInit;
+ uint32_t txMmk;
+ uint32_t txPmk;
+ uint32_t txTek;
+ uint32_t txApmkInit;
+ uint32_t txAmmk;
+ uint32_t txApmk;
+ uint32_t txAtek;
+} MXL_MOCA_SOC_GET_SEC_STATS_RSP_T;
+
+// MXL_MOCA_SOC_DO_TEST_CMD / HI_TXNTYPE_DO_TEST_CMD
+
+typedef struct
+{
+ uint32_t dcapId;
+ uint32_t param[64];
+ uint32_t paramLen;
+} MXL_MOCA_SOC_TEST_CMD_T;
+
+typedef struct
+{
+ uint32_t result;
+ uint32_t param[64];
+ uint32_t paramLen;
+} MXL_MOCA_SOC_TEST_RSP_T;
+
+//! RLAPM configuration
+
+typedef struct
+{
+ uint32_t chn_index;
+} MXL_MOCA_SOC_GET_ACTIVE_RLAPM_CMD_T;
+
+typedef struct
+{
+ //! RLAPM mode
+ uint32_t rlapmMode;
+ //! RLAPM tables
+ struct
+ {
+ //! The frequency for the PHY margin table
+ uint32_t freq;
+ //! Added PHY margin table
+ uint8_t
+ phyMargin[MAX_RX_LEVELS_PADDED];
+ } tbl;
+} MXL_MOCA_SOC_GET_ACTIVE_RLAPM_RSP_T;
+
+//! SAPM configuration
+
+typedef struct
+{
+ uint32_t chn_index;
+} MXL_MOCA_SOC_GET_ACTIVE_SAPM_CMD_T;
+
+typedef struct
+{
+ //! SAPM mode
+ uint32_t sapmMode;
+ //! Added PHY margin table
+ uint8_t phyMargin[FFT_LENGTH];
+
+ //! Threshold and frequency
+ uint16_t frequency;
+ uint8_t threshold;
+ uint8_t pad;
+} MXL_MOCA_SOC_GET_ACTIVE_SAPM_RSP_T;
+
+// ! Energy detection result
+typedef struct
+{
+ uint32_t rawDetectedServiceBitmask;
+ uint8_t channelInfo50MhzBandE[7];
+ uint8_t channelInfo50MhzBandF[8];
+ uint8_t channelInfo50MhzBandD[21];
+ uint8_t channelInfo100MhzBandE[5];
+ uint8_t channelInfo100MhzBandF[6];
+ uint8_t channelInfo100MhzBandD[19];
+ uint8_t pad[2];
+
+ uint32_t bandEF50MhzEnergyBitmask;
+ uint32_t bandD50MhzEnergyBitmask;
+ uint32_t bandEF100MhzEnergyBitmask;
+ uint32_t bandD100MhzEnergyBitmask;
+} MXL_MOCA_SOC_ENDET_STATUS_RSP_T;
+
+// MXL_MOCA_SOC_GET_SWITCH_STATS / HI_TXNTYPE_GET_SWITCH_STATS
+
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_SOC_GET_SWITCH_STATS_CMD_T; /* Hi_TxnGetSwitchStatsCmd_t */
+
+typedef struct
+{
+ uint32_t rxGood[4];
+ uint32_t rxDrop[4];
+ uint32_t rxError[4];
+ uint32_t txGood[4];
+ uint32_t txDrop[4];
+ uint32_t txError[4];
+} MXL_MOCA_SOC_GET_SWITCH_STATS_RSP_T; /* Hi_TxnGetSwitchStatsRsp_t */
+
+// MXL_MOCA_SOC_GET_SWITCH_CONFIG / HI_TXNTYPE_GET_SWITCH_CONFIG
+
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_GET_SWITCH_CONFIG_CMD_T; /* Hi_TxnGetSwitchConfigCmd_t */
+
+// MXL_MOCA_SOC_SET_SWITCH_CONFIG / HI_TXNTYPE_SET_SWITCH_CONFIG
+
+/* eSwitch config:
+ * ---------------
+ * eSwitch port control eSwitchPortConfig[2:0]
+ * A value of 0 in a given bit position indicates disable. Default value is 111'b
+ * Bit0 EPHY0(RGMII)
+ * Bit1 EPHY1(SGMII)
+ * Bit2 MoCA ifc.
+ * Other bits are reserved
+ */
+typedef struct
+{ uint32_t eSwitchPortConfig;
+} MXL_MOCA_SOC_SET_SWITCH_PORT_CONFIG_CMD_T; /* Hi_TxnSetSwitchPortConfigCmd_t */
+
+typedef struct
+{ uint32_t status;
+} MXL_MOCA_SOC_SET_SWITCH_PORT_CONFIG_RSP_T; /* Hi_TxnSetSwitchPortConfigRsp_t */
+
+
+/* == Bridge Detection == */
+typedef struct
+{
+ uint32_t reset; // resets the event
+} MXL_MOCA_SOC_GET_NETWORK_NAME_REC_CMD_T; /* Hi_TxnGetNetworkNameRecCmd_t */
+// MXL_MOCA_SOC_GET_NETWORK_NAME_REC / HI_TXNTYPE_GET_NETWORK_NAME_REC
+
+typedef struct
+{
+ uint32_t networkNameRecRsp;
+} MXL_MOCA_SOC_GET_NETWORK_NAME_REC_RSP_T; /* Hi_TxnGetNetworkNameRecRsp_t */
+
+//
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_GET_NETWORK_NAME_PAYLOAD_CMD_T; /* Hi_TxnGetNetworkNamePayloadRecCmd_t */
+// MXL_MOCA_SOC_GET_NETWORK_NAME_PAYLOAD / HI_TXNTYPE_GET_NETWORK_NAME_PAYLOAD_REC
+
+typedef struct
+{
+ uint8_t vendorInfo[MAX_NW_NAME_LEN+1];
+ uint32_t networkNameRec;
+} MXL_MOCA_SOC_GET_NETWORK_NAME_PAYLOAD_RSP_T; /* Hi_TxnGetNetworkNamePayloadRecRsp_t */
+
+typedef struct
+{
+ uint8_t vendorInfo[MOCA25_ME_IE_RSP_MBOX_SIZE_BYTES];
+ uint32_t set; // 1= set (use the vendor info from cmd); 0 = get (return in response structure)
+} MXL_MOCA_SOC_ME_NETWORK_IE_PAYLOAD_TX_CMD_T; /* Hi_TxnSetMeIEPayloadTxCmd_t */
+// MXL_MOCA_SOC_ME_NETWORK_IE_PAYLOAD_TX / HI_TXNTYPE_SET_ME_IE_PAYLOAD_TX
+
+typedef struct
+{
+ uint8_t vendorInfo[MOCA25_ME_IE_RSP_MBOX_SIZE_BYTES];
+} MXL_MOCA_SOC_ME_NETWORK_IE_PAYLOAD_TX_RSP_T; /* Hi_TxnSetMeIEPayloadTxRsp_t */
+
+typedef struct
+{
+ uint8_t vendorInfo[MOCA25_ME_IE_REQ_MBOX_SIZE_BYTES];
+ uint32_t set; // 1= set (use the vendor info from cmd); 0 = get (return in response structure)
+} MXL_MOCA_SOC_ME_NETWORK_IE_PAYLOAD_RX_CMD_T; /* Hi_TxnGetMeIEPayloadRxCmd_t */
+// MXL_MOCA_SOC_ME_NETWORK_IE_PAYLOAD_RX / HI_TXNTYPE_GET_ME_IE_PAYLOAD_RX
+
+typedef struct
+{
+ uint8_t vendorInfo[MOCA25_ME_IE_REQ_MBOX_SIZE_BYTES];
+ uint32_t meIEPayloadRec;
+} MXL_MOCA_SOC_ME_NETWORK_IE_PAYLOAD_RX_RSP_T; /* Hi_TxnGetMeIEPayloadRxRsp_t */
+
+typedef struct /* combined with Join Cfg */
+{
+ uint32_t networkJoin;
+} MXL_MOCA_SOC_ME_NETWORK_JOIN_CMD_T; /* Hi_TxnSetNetworkJoinCmd_t */
+// MXL_MOCA_SOC_ME_NETWORK_JOIN / HI_TXNTYPE_SET_ME_NETWORK_JOIN
+
+typedef struct
+{
+ uint32_t networkJoinRsp;
+} MXL_MOCA_SOC_ME_NETWORK_JOIN_RSP_T; /* Hi_TxnSetNetworkJoinRsp_t */
+
+// Network Management Proxy
+// Send pkt
+typedef struct
+{
+ uint8_t pkt[MOCA_MAX_PACKET_SIZE];
+ uint32_t length;
+} MXL_MOCA_SOC_NET_PROXY_PKT_SEND_REQ_CMD_T; /* Hi_TxnNetProxyPktSendCmd_t */
+
+typedef struct
+{
+ uint32_t status;
+} MXL_MOCA_SOC_NET_PROXY_PKT_RCV_RSP_T; /* Hi_TxnNetProxyPktSendRsp_t */
+
+// Pkt response
+typedef struct
+{
+ uint32_t token; // reserved
+} MXL_MOCA_SOC_NET_PROXY_PKT_REPLY_CMD_T; /* Hi_TxnNetProxyPktReplyCmd_t */
+
+typedef struct
+{
+ uint32_t status;
+ uint8_t pkt[MOCA_MAX_PACKET_SIZE];
+ uint32_t length;
+} MXL_MOCA_SOC_NET_PROXY_PKT_REPLY_RSP_T; /* Hi_TxnNetProxyPktReplyRsp_t */
+
+// dcap136
+typedef struct
+{
+ uint32_t enable;
+} MXL_MOCA_SOC_NET_PROXY_TEST_MODE_CTRL_CMD_T; /* Hi_TxnNetProxyTestModeCtrlCmd_t */
+
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_NET_PROXY_TEST_MODE_CTRL_RSP_T; /* Hi_TxnNetProxyTestModeCtrlRsp_t */
+
+typedef struct
+{
+ uint32_t macHi;
+ uint32_t macLo;
+ uint32_t tmo;
+ uint32_t vlanCheck[2];
+ uint32_t vlanStrip[2];
+ uint32_t vlanPvid[2];
+ uint32_t vlanId[2][SWITCH_PORT_MAX_VLAN_IDS];
+} MXL_MOCA_SOC_GET_SWITCH_CONFIG_RSP_T; /* Hi_TxnGetSwitchConfigRsp_t */
+
+// MXL_MOCA_SOC_RESET_SWITCH_CONFIG / HI_TXNTYPE_RESET_SWITCH_CONFIG
+
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_RESET_SWITCH_CONFIG_CMD_T; /* Hi_TxnResetSwitchConfigCmd_t */
+
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_RESET_SWITCH_CONFIG_RSP_T; /* Hi_TxnResetSwitchConfigRsp_t */
+
+// MXL_MOCA_SOC_SET_SWITCH_TMO / HI_TXNTYPE_SET_SWITCH_TMO
+
+typedef struct
+{
+ uint32_t tmo;
+} MXL_MOCA_SOC_SET_SWITCH_TMO_CMD_T; /* Hi_TxnSetSwitchTmoCmd_t */
+
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_SET_SWITCH_TMO_RSP_T; /* Hi_TxnSetSwitchTmoRsp_t */
+
+// MXL_MOCA_SOC_ENA_SWTICH_VLAN_CHECK / HI_TXNTYPE_ENA_SWTICH_VLAN_CHECK
+
+typedef struct
+{
+ int32_t port;
+} MXL_MOCA_SOC_ENA_SWITCH_VLAN_CHECK_CMD_T; /* Hi_TxnEnaSwitchVlanCheckCmd_t */
+
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_ENA_SWITCH_VLAN_CHECK_RSP_T; /* Hi_TxnEnaSwitchVlanCheckRsp_t*/
+
+// MXL_MOCA_SOC_DIS_SWTICH_VLAN_CHECK / HI_TXNTYPE_DIS_SWTICH_VLAN_CHECK
+
+typedef struct
+{
+ int32_t port;
+} MXL_MOCA_SOC_DIS_SWITCH_VLAN_CHECK_CMD_T; /* Hi_TxnDisSwitchVlanCheckCmd_t*/
+
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_DIS_SWITCH_VLAN_CHECK_RSP_T; /* Hi_TxnDisSwitchVlanCheckRsp_t*/
+
+// MXL_MOCA_SOC_ENA_SWTICH_VLAN_STRIP / HI_TXNTYPE_ENA_SWTICH_VLAN_STRIP
+
+typedef struct
+{
+ int32_t port;
+} MXL_MOCA_SOC_ENA_SWITCH_VLAN_STRIP_CMD_T; /* Hi_TxnEnaSwitchVlanStripCmd_t*/
+
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_ENA_SWITCH_VLAN_STRIP_RSP_T; /* Hi_TxnEnaSwitchVlanStripRsp_t*/
+
+// MXL_MOCA_SOC_DIS_SWTICH_VLAN_STRIP / HI_TXNTYPE_DIS_SWTICH_VLAN_STRIP
+
+typedef struct
+{
+ int32_t port;
+} MXL_MOCA_SOC_DIS_SWITCH_VLAN_STRIP_CMD_T; /* Hi_TxnDisSwitchVlanStripCmd_t */
+
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_DIS_SWITCH_VLAN_STRIP_RSP_T; /* Hi_TxnDisSwitchVlanStripRsp_t */
+
+// MXL_MOCA_SOC_SET_SWTICH_VLAN_PVID / HI_TXNTYPE_SET_SWTICH_VLAN_PVID
+
+typedef struct
+{
+ int32_t port;
+ uint32_t pvid;
+} MXL_MOCA_SOC_SET_SWITCH_VLAN_PVID_CMD_T; /* Hi_TxnSetSwitchVlanPvidCmd_t */
+
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_SET_SWITCH_VLAN_PVID_RSP_T; /* Hi_TxnSetSwitchVlanPvidRsp_t */
+
+// MXL_MOCA_SOC_ADD_SWTICH_VLAN_ID / HI_TXNTYPE_ADD_SWTICH_VLAN_ID
+
+typedef struct
+{
+ int32_t port;
+ uint32_t vid;
+} MXL_MOCA_SOC_ADD_SWITCH_VLANID_CMD_T; /* Hi_TxnAddSwitchVlanIdCmd_t */
+
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_ADD_SWITCH_VLANID_RSP_T; /* Hi_TxnAddSwitchVlanIdRsp_t */
+
+// MXL_MOCA_SOC_DEL_SWTICH_VLAN_ID / HI_TXNTYPE_DEL_SWTICH_VLAN_ID
+
+typedef struct
+{
+ int32_t port;
+ uint32_t vid;
+} MXL_MOCA_SOC_DEL_SWITCH_VLANID_CMD_T; /* Hi_TxnDelSwitchVlanIdCmd_t */
+
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_DEL_SWITCH_VLANID_RSP_T; /* Hi_TxnDelSwitchVlanIdRsp_t */
+
+// MXL_MOCA_SOC_SET_SWITCH_MGMT_MAC / HI_TXNTYPE_SET_SWTICH_MGMT_MAC
+
+typedef struct
+{
+ uint32_t macHi;
+ uint32_t macLo;
+} MXL_MOCA_SOC_SET_SWITCH_MGMT_MAC_CMD_T; /* Hi_TxnSetSwitchMgmtMacCmd_t */
+
+typedef struct
+{
+ uint32_t reserved;
+} MXL_MOCA_SOC_SET_SWITCH_MGMT_MAC_RSP_T; /* Hi_TxnSetSwitchMgmtMacRsp_t */
+
+// MXL_MOCA_SOC_GET_MAC_DATA_STATS / HI_TXNTYPE_GET_MAC_DATA_STATS
+
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_SOC_GET_MACDATA_STATS_CMD_T; /* Hi_TxnGetMacDataStatsCmd_t */
+
+typedef struct
+{
+ uint32_t pktsTx2Node[MAX_NUM_NODES];
+} MXL_MOCA_SOC_GET_MACDATA_STATS_RSP_T; /* Hi_TxnGetMacDataStatsRsp_t */
+
+// MXL_MOCA_SOC_SET_INIT_PARAM_V2 / HI_TXNTYPE_SET_INIT_PARAM_V2
+
+typedef struct
+{
+ uint8_t confVersion; //!< The config version to indicate the changes history of structure.
+ uint8_t testMode; //!< The test mode for the MoCA device.
+ uint8_t turboModeMask; //!< The turbo mode for each band for the MoCA device.
+ uint8_t clnkLedMode; //!< The CLINK LED mode (on or flash, 0 or 1)
+ uint32_t testParam1; //!< The test parameter 1 for the MoCA device.
+ uint32_t testParam2; //!< The test parameter 2 for the MoCA device.
+ uint32_t testParam3; //!< The test parameter 3 for the MoCA device.
+ uint32_t testParam4; //!< The test parameter 4 for the MoCA device.
+ uint32_t clinkGuidHi; //!< The MoCA GUID high.
+ uint32_t clinkGuidLo; //!< The MoCA GUID low.
+ uint32_t mpaMacAddrHi; //!< Upper 4 bytes of MPA destination MAC Address
+ uint16_t mpaMacAddrLo; //!< 2 bytes of MPA destination MAC Address
+ uint16_t mpaPktFilter; //!< 2 bytes for MPA MoCA packet filter
+ uint8_t traceEnable; //!< Trace type enable/disable.
+ uint8_t traceLevel; //!< Minimum trace level.
+ uint8_t traceModule; //!< Trace module enable/disable.
+ uint8_t traceDest; //!< Trace destination enable/disable.
+} MXL_MOCA_INIT_SYSTEM_V2_T;
+
+typedef struct
+{
+ uint16_t miiPausePriorityLevel; //!< The MII pause priority level specifies the MoCA priority level
+ uint8_t policingModeMask; //!< The policing mode for each band for the MoCA device.
+ uint8_t pqosClassificationMode; //!< The PQoS classification mode specifies the classification mode
+ uint32_t miiSpeed; //!< The MII speed for the MoCA device.
+ uint32_t retransmissionPriority; //!< The priorities to enable retransmission on the transmit side.
+ uint32_t transmissionPriorityPer; //!< The PER profile to use for each priority on the transmit side.
+ uint8_t datapathMode; //!< The data path mode for the MoCA device.
+ uint8_t mcastMode; //!< The multicast mode for the MoCA device.
+ uint16_t reserved2;
+ uint32_t mcastAddrHi[48]; //!< The multicast MAC address high. There are a total of 48 MAC addresses.
+ uint32_t mcastAddrLo[48]; //!< The multicast MAC address high. There are a total of 48 MAC addresses.
+ uint32_t rgmiiClkDelayCfg;
+ uint32_t stripVlanTag; //!< Bit 31 enable, LS 12 bit vlan id.
+ uint32_t macAddrAgingTimeInSecs; //!< E-MAC Address Aging time out.
+} MXL_MOCA_INIT_DATA_V2_T;
+
+typedef struct
+{
+ uint8_t failoverMode : 1, //!< bit 7 - The failover mode for the MoCA device.
+ handoffMode : 1, //!< bit 6 - The handoff mode for the MoCA device.
+ preferredNcMode : 1, //!< bit 5 - The preferred NC mode for the MoCA device.
+ networkSearchMode : 2, //!< bit 4:3 - The network search mode for the MoCA device.
+ lofUpdateMode : 1, //!< bit 2 - The LOF update mode for the MoCA device.
+ channelBondEn : 1, //!< bit 1 - Control Channel Bonding when start up.
+ reserved1 : 1; // bit 0
+ uint8_t initialRole; //!< The role is the initial role used to form or join the MoCA network
+ uint8_t lmoMode; //!< The LMO mode for the MoCA device.
+ uint8_t securityModeMask; //!< The security mode for each band for the MoCA device.
+ uint8_t mocaPassword[MAX_BANDS][MAX_PASSWORD_LENGTH_PADDED];
+ uint16_t mocaResetSeqNum[MAX_BANDS]; //!< The MoCA reset sequence number.
+ uint16_t lof; //!< The last operating frequency (LOF) in MHz.
+ uint8_t reserved2;
+ uint8_t bandMask; //!< The frequency band mask defines the frequency bands
+ uint64_t scanMask[MAX_BANDS]; //!< The scan mask defines the channels that the user has selected to scan.
+ uint8_t scanOffset[MAX_BANDS]; //!< The scan offset is the offset in 25MHz steps starting from 0 MHz for
+ //!< the scan mask.
+ uint64_t priChnAboveMask[MAX_BANDS]; //!< The primary channel above mask is a mask to indicate whether the center
+ //!< frequency of the primary channel is 25MHz above the beacon channel.
+ uint64_t priChnBelowMask[MAX_BANDS]; //!< The primary channel below mask is a mask to indicate whether the center
+ //!< frequency of the primary channel is 25MHz below the beacon channel.
+ uint64_t secChnAboveMask[MAX_BANDS]; //!< The secondary channel above mask is a mask to indicate whether the center
+ //!< frequency of the secondary channel is 125MHz above the primary channel.
+ uint64_t secChnBelowMask[MAX_BANDS]; //!< The secondary channel above mask is a mask to indicate whether the center
+ //!< frequency of the secondary channel is 125MHz below the primary channel.
+ uint32_t tabooMask : 24, //!< bits 31:8 - The taboo information defines the off-limits channels above
+ //!< and below the active channel which the NC will advertise
+ //!< to all nodes scanning to join a network.
+ //!< The taboo mask is a mask of the channels for the taboo info.
+ tabooOffset : 8; //!< bits 7:0 - The taboo offset is the offset from the beacon frequency for
+ //!< the taboo information.
+ uint8_t tlpMin[MAX_BANDS]; //!< The minimum time (in seconds) a node stays in listening phase of
+ //!< network search.
+ uint8_t tlpMax[MAX_BANDS]; //!< The maximum time (in seconds) a node stays in listening phase of
+ //!< network search.
+ uint8_t firstChannelOffset[MAX_BANDS]; //!< The offset of first channel's center frequency below the center
+ //!< frequency of the Primary Channel, the valid values range is 0-4.
+ uint8_t numberOfChannels[MAX_BANDS]; //!< The maximum number of 100MHz channels, the valid values range is 3-5.
+} MXL_MOCA_INIT_CONTROL_V2_T;
+
+typedef struct
+{
+ uint8_t beaconTxPwr; //!< The beacon transmit power for the MoCA device when TPC is enabled.
+ uint8_t maxTxPwr; //!< The maximum transmit power (except beacons) for the MoCA device
+ uint16_t reserved1;
+ uint32_t encWdLenNper; //!< The encoding word length (kLDPCmax) for the NPER profile.
+ uint32_t encWdLenVlper; //!< The encoding work length (kLDPCmax) for the VLPER profile.
+ uint32_t featureEnFlags; //!< The PHY feature enable flags.
+ uint8_t phyMargin50[MAX_BANDS]; //!< The PHY margin controls the margin (in dB) used above the measured
+ //!< RX noise floor to accommodate variations due to return loss on
+ //!< the receive side for the 50MHz channel
+ uint8_t phyMarginNper[MAX_BANDS]; //!< The PHY margin controls the margin (in dB) used above the measured
+ //!< RX noise floor to accommodate variations due to return loss on
+ //!< the receive side for the 100MHz NPER channel
+ uint8_t phyMarginVlper[MAX_BANDS]; //!< The PHY margin controls the margin (in dB) used above the measured
+ //!< RX noise floor to accommodate variations due to return loss on
+ //!< the receive side for the 100MHz VLPER channel
+ uint16_t tpcMode; //!< The TPC mode enables/disables TPC from all other nodes to this node.
+ uint16_t tgtP2p50Rate; //!< The TPC target PHY rate for transmissions on the 50MHz channel from
+ //!< all other nodes to this node when TPC mode is enabled.
+ uint16_t tgtP2pNperRate; //!< The TPC target PHY rate for transmissions on the 100MHz NPER channel
+ //!< from all other nodes to this node when TPC mode is enabled.
+ uint16_t tgtP2pVlperRate; //!< The TPC target PHY rate for transmissions on the 100MHz VLPER channel
+ //!< from all other nodes to this node when TPC mode is enabled.
+ uint32_t phyModBitmaskUcast50; //!< The PHY modulation bitmask for the 50MHz unicast channel.
+ uint32_t phyModBitmaskUcast100; //!< The PHY modulation bitmask for the 100MHz unicast channel.
+ uint32_t phyModBitmaskBcast50; //!< The PHY modulation bitmask for the 50MHz broadcast channel.
+ uint32_t phyModBitmaskBcast100; //!< The PHY modulation bitmask for the 100MHz broadcast channel.
+ uint32_t diplexerCalWord; //!< The diplexer calibration word.
+ uint32_t hwCfgWord; //!< The hardware configuration word.
+ uint32_t loadingCaps; //!< The load capacitors configraion for the xtal.
+} MXL_MOCA_INIT_PHY_V2A_T;
+
+typedef struct
+{
+ MXL_MOCA_INIT_SYSTEM_V2_T initSystemV2; // System, was Hi_InitSystem_t initSystem;
+ MXL_MOCA_INIT_DATA_V2_T initDataV2; // ECL, was Hi_InitEcl_t initEcl;
+ MXL_MOCA_INIT_CONTROL_V2_T initControlV2; // LC, was Hi_InitLc_t initLc;
+ MXL_MOCA_INIT_PHY_V2A_T initPhyV2A; // PHY, was Pcl_HostCfg_t initPhy;
+} MXL_MOCA_SOC_SET_INIT_PARAM_CMD_T; /* Hi_TxnSetInitParamCmd_t */
+
+// MXL_MOCA_SOC_SET_INIT_RLAPM / HI_TXNTYPE_SET_INIT_RLAPM
+
+typedef struct
+{
+ uint8_t rlapmModeMask; //!< The RLAPM mode for each band for the MoCA device.
+ uint8_t reserved2;
+ uint16_t reserved3;
+ uint16_t rlapmFreq[MAX_RLAPM_FREQS]; //!< The frequency for the RLAPM tables.
+ uint8_t rlapmMargin[MAX_RLAPM_FREQS][MAX_RX_LEVELS_PADDED]; //!< The added PHY margin for the RLAPM tables.
+ struct
+ {
+ uint16_t lowerbandstart; // Lower band start signal
+ uint16_t upperbandstart; // Upper band start signal
+ uint16_t lowerGap[MAX_ATSC_CATV_GAPS];
+ uint16_t upperGap[MAX_ATSC_CATV_GAPS];
+ uint16_t validChBitMask; // Valid channel bitmask
+ uint16_t reserved;
+ } atscTbl[MAX_ATSC_CATV_FREQS];
+
+ struct
+ {
+ uint16_t lowerbandstart; // Lower band start signal
+ uint16_t upperbandstart; // Upper band start signal
+ uint16_t lowerGap[MAX_ATSC_CATV_GAPS];
+ uint16_t upperGap[MAX_ATSC_CATV_GAPS];
+ uint16_t validChBitMask; // Valid channel bitmask
+ uint16_t reserved;
+ } catvTbl[MAX_ATSC_CATV_FREQS];
+
+ uint8_t atscwtHit; // WT_HIT value
+ uint8_t atscwtMiss; // WT_MISS value
+ uint8_t atscloPenalty; // LO_PENALTY
+ uint8_t atschiPenalty; // HI_PENALTY
+ uint8_t atscminCnt; // MIN_CNT
+ uint8_t atscmaxCnt; // MAX_CNT
+ uint16_t reserved4;
+ uint16_t atscrxLvlMin; // RX_LVL_MIN
+ uint16_t atscrxLvlScale; // RX_LVL_SCALE
+ uint8_t atscchwt[MAX_WEIGHTS]; // Channel weight (WT0...WT3)
+ uint32_t atscthreshold;
+ uint8_t catvwtHit; // WT_HIT value
+ uint8_t catvwtMiss; // WT_MISS value
+ uint8_t catvloPenalty; // LO_PENALTY
+ uint8_t catvhiPenalty; // HI_PENALTY
+ uint8_t catvminCnt; // MIN_CNT
+ uint8_t catvmaxCnt; // MAX_CNT
+ uint16_t reserved5;
+ uint16_t catvrxLvlMin; // RX_LVL_MIN
+ uint16_t catvrxLvlScale; // RX_LVL_SCALE
+ uint8_t catvchwt[MAX_WEIGHTS]; // Channel weight (WT0...WT3)
+ uint32_t catvthreshold;
+ struct
+ {
+ uint16_t btscsscvalue[MAX_BTS_CSS_VALUES]; // Channel measurement C1-C5
+ uint16_t btscssnvalue[MAX_BTS_CSS_VALUES]; // Narrow gap measurements N1-N5
+ } btsCssTbl[MAX_BTS_CSS_FREQS];
+
+ uint16_t btsRxLvlMin; // RX_LVL_MIN
+ uint16_t btsRxLvlScale; // RX_LVL_SCALE
+ uint8_t btseChWt[MAX_WEIGHTS]; // BTS even channel weight
+ uint8_t btsoChWt[MAX_WEIGHTS]; // BTS odd channel weight
+ uint8_t btseWtHt; // BTS even WT_HIT
+ uint8_t btsoWtHt; // BTS odd WT_HIT
+ uint8_t btseWtMiss; // BTS even WT_MISS
+ uint8_t btsoWtMiss; // BTS odd WT_MISS
+ uint8_t btseMinCnt; // BTS even MIN_CNT
+ uint8_t btsoMinCnt; // BTS odd MIN_CNT
+ uint8_t btseMaxCnt; // BTS even MAX_CNT
+ uint8_t btsoMaxCnt; // BTS odd MAX_CNT
+ uint8_t btseLoPenalty; // BTS even LO_PENALTY
+ uint8_t btsoLoPenalty; // BTS odd LO_PENALTY
+ uint8_t btseHiPenalty; // BTS even HI_PENALTY
+ uint8_t btsoHiPenalty; // BTS odd HI_PENALTY
+ uint8_t btse1ValidChnList; // Valid BTSe1 channel list
+ uint8_t btse2ValidChnList; // Valid BTSe2 channel list
+ uint8_t btso1ValidChnList; // Valid BTSo1 channel list
+ uint8_t btso2ValidChnList; // Valid BTSo2 channel list
+ uint32_t btsThreshold;
+ uint16_t cssRxLvlMin; // RX_LVL_MIN
+ uint16_t cssRxLvlScale; // RX_LVL_SCALE
+ uint8_t acssChWt[MAX_WEIGHTS]; // aCss channel weight
+ uint8_t dcssChWt[MAX_WEIGHTS]; // dCss channel weight
+ uint8_t acssWtHt; // Analog CSS WT_HIT
+ uint8_t dcssWtHt; // Digital CSS WT_HIT
+ uint8_t acssWtMiss; // Analog CSS WT_MISS
+ uint8_t dcssWtMiss; // Digital CSS WT_MISS
+ uint8_t acssMinCnt; // Analog CSS MIN_CNT
+ uint8_t dcssMinCnt; // Digital CSS MIN_CNT
+ uint8_t acssMaxCnt; // Analog CSS MAX_CNT
+ uint8_t dcssMaxCnt; // Digital CSS MAX_CNT
+ uint8_t acssLoPenalty; // Analog CSS LO_PENALTY
+ uint8_t dcssLoPenalty; // Digital CSS LO_PENALTY
+ uint8_t acssHiPenalty; // Analog CSS HI_PENALTY
+ uint8_t dcssHiPenalty; // Digital CSS HI_PENALTY
+ uint8_t acssValidChnList; // Valid analog CSS channel list
+ uint8_t dcss1ValidChnList; // Valid digital CSS1 channel list
+ uint8_t dcss2ValidChnList; // Valid digital CSS2 channel list
+ uint8_t reserved6;
+ uint32_t cssThreshold;
+ uint32_t bandEUsabilityThreshold;
+ uint32_t bandFUsabilityThreshold;
+ uint32_t bandDUsabilityThreshold;
+ uint32_t bandEEnergyThreshold;
+ uint32_t bandFEnergyThreshold;
+ uint32_t bandDEnergyThreshold;
+} MXL_MOCA_SOC_SET_INIT_RLAPM_CMD_T; /* Hi_TxnSetInitRlapmCmd_t */
+
+// MXL_MOCA_SOC_SET_INIT_SAPM / HI_TXNTYPE_SET_INIT_SAPM
+
+typedef struct
+{
+ uint8_t sapmModeMask; //!< The SAPM mode for each band for the MoCA device.
+ uint8_t reserved4;
+ uint16_t reserved5;
+ uint16_t sapmFreq[MAX_SAPM_FREQS]; //!< The frequency for the SAPM tables.
+ uint8_t sapmThreshold[MAX_SAPM_FREQS]; //!< The threshold for the SAPM tables.
+ int16_t sapmSubcarrierStart[MAX_SAPM_FREQS]; //!< The starting subcarrier for the SAPM tables.
+ uint8_t miniSapmMargin[MAX_SAPM_FREQS][MAX_MINI_SAPM_MARGIN_LEN]; //!< The added PHY margin for the SAPM tables.
+ int8_t rssiFreqCompTbl[MAX_RSSI_LEN]; //!< The RSSI frequency compensation table.
+} MXL_MOCA_SOC_SET_INIT_SAPM_CMD_T; /* Hi_TxnSetInitSapmCmd_t */
+
+// MXL_MOCA_SOC_SET_INIT_PARAM_V25 / HI_TXNTYPE_SET_INIT_PARAM_V25
+
+typedef struct
+{
+ /* Beacon Power */
+ uint8_t bcnPwrConfigEn; //!< ENABLED/ DISABLED
+ int8_t bcnPwrDist; //!< Absolute Beacon Power for Distribution -10dbm to +7dbm
+ int8_t bcnPwrLocal; //!< The beacon transmit power for the c.LINK device when TPC is enabled.
+ uint8_t hoToLowerMoCAVer; //!< The configurtion for hand off to lower MoCA Version
+
+ /* MPS */
+ uint16_t mpsPrivacyDown;
+ uint16_t mpsPrivacyReceive;
+ uint32_t mpsUnPairedTime;
+ uint32_t mpsWalkTime;
+
+ /* Enhanced Privacy */
+ uint8_t privacySupported; //!< Lower 3 bits used for Privacy Supported
+ uint8_t pad1[3];
+ uint8_t mocaEPPassword[MAX_MOCA_EP_PASSWORD_LEN_PADDED]; //!< 12 to 64 ASCII printable characters
+
+ /* Bridge Detection */
+ uint8_t networkName[MAX_NW_NAME_LEN]; //!< Network name updated from Host
+ uint32_t networkNameAdmitCfg; //!< Network Name Admit cfg
+ uint8_t meNetworkIePayloadTx[MAX_ME_NW_IE_PAYLOAD_LEN];
+ uint32_t meNetworkIeRespTimeout;
+ uint32_t meNetworkJoinEn;
+ //! MAC Link Authentication params
+ struct
+ {
+ uint16_t reserved;
+ uint16_t etherType; //!< Ethernet Type
+ uint16_t bitmask[MAX_NUM_NODES]; //!< unicast traffics permission bitmasks
+ } defaultAuthLink;
+} MXL_MOCA_SOC_SET_INIT_PARAM_V25_CMD_T;
+
+typedef struct
+{
+ //! The frequency for the PHY margin table
+ uint32_t freq;
+
+ //! Added PHY margin table
+ uint8_t phymargin[MAX_RX_LEVELS_PADDED];
+} MXL_MOCA_RLAPM_TABLE_V2_T; // was ClnkLib_RlapmTableV2_t;
+
+typedef struct
+{
+ //! RLAPM mode
+ uint32_t rlapmmode;
+
+ //! RLAPM tables
+ MXL_MOCA_RLAPM_TABLE_V2_T tbl;
+} MXL_MOCA_RLAPM_ACTIVE_CFG_V2_T; // ClnkLib_RlapmActiveCfgV2_t;
+
+typedef struct
+{
+ /**
+ * The exclusive set of multicast MAC address allowed to pass
+ * from MoCA to host when filter mode is set to Enabled. When
+ * filter mode is set to DfidOnly, then the following list of
+ * MAC addresses are only filtered by MAP DFID and not by
+ * precise MAC Address. This is only useful for internal
+ * testing.
+ *
+ * The first array entry with a 0 in macAddrHi indicates that it
+ * and all following array entries do not contain a valid entry.
+ */
+ uint32_t macAddrHi[48];
+ uint32_t macAddrLo[48];
+ /**
+ * The filter mode enables or disables multicast filtering
+ * for the MoCA device.
+ *
+ * The values for filter mode are: Disabled (0), Enabled (1),
+ * and DfidOnly (2).
+ */
+ int32_t mode;///defval is 0;
+} MXL_MOCA_MCAST_CFG_T;
+
+// CATV and ATSC
+typedef struct
+{
+ uint8_t wtHit; // WT_HIT value
+ uint8_t wtMiss; // WT_MISS value
+ uint8_t loPenalty; // LO_PENALTY
+ uint8_t hiPenalty; // HI_PENALTY
+ uint8_t minCnt; // MIN_CNT
+ uint8_t maxCnt; // MAX_CNT
+ uint16_t reserved;
+ uint16_t rxLvlMin; // RX_LVL_MIN
+ uint16_t rxLvlScale; // RX_LVL_SCALE
+ uint8_t chwt[MAX_WEIGHTS]; // Channel weight (WT0...WT3)
+ uint32_t threshold;
+} MXL_MOCA_ATSC_CATV_WEIGHT_T; // AtscCatvWeight_t;
+
+// Summing over 25 subcarriers for Ui and Li, each one separate by 31. i.e. U2 = U1+31
+// ATSC and CATV table
+// E2, EE3, F3, F7
+typedef struct
+{
+ uint16_t lowerbandstart; // Lower band start signal
+ uint16_t upperbandstart; // Upper band start signal
+ uint16_t lowerGap[MAX_ATSC_CATV_GAPS];
+ uint16_t upperGap[MAX_ATSC_CATV_GAPS];
+ uint16_t validChBitMask; // Valid channel bitmask
+ uint16_t reserved;
+} MXL_MOCA_BAND_E_TABLE_T; // BandEFTbl_t;
+
+// D2, D4, D6, D8, D10, 1100
+typedef struct
+{
+ uint16_t btscsscvalue[MAX_BTS_CSS_VALUES]; // Channel measurement C1-C5
+ uint16_t btscssnvalue[MAX_BTS_CSS_VALUES]; // Narrow gap measurements N1-N5
+} MXL_MOCA_BAND_D_TABLE_T; // BandDTbl_t;
+
+// BTS constants
+typedef struct
+{
+ uint16_t btsRxLvlMin; // RX_LVL_MIN
+ uint16_t btsRxLvlScale; // RX_LVL_SCALE
+ uint8_t btseChWt[MAX_WEIGHTS]; // BTS even channel weight
+ uint8_t btsoChWt[MAX_WEIGHTS]; // BTS odd channel weight
+ uint8_t btseWtHt; // BTS even WT_HIT
+ uint8_t btsoWtHt; // BTS odd WT_HIT
+ uint8_t btseWtMiss; // BTS even WT_MISS
+ uint8_t btsoWtMiss; // BTS odd WT_MISS
+ uint8_t btseMinCnt; // BTS even MIN_CNT
+ uint8_t btsoMinCnt; // BTS odd MIN_CNT
+ uint8_t btseMaxCnt; // BTS even MAX_CNT
+ uint8_t btsoMaxCnt; // BTS odd MAX_CNT
+ uint8_t btseLoPenalty; // BTS even LO_PENALTY
+ uint8_t btsoLoPenalty; // BTS odd LO_PENALTY
+ uint8_t btseHiPenalty; // BTS even HI_PENALTY
+ uint8_t btsoHiPenalty; // BTS odd HI_PENALTY
+ uint8_t btse1ValidChnList; // Valid BTSe1 channel list
+ uint8_t btse2ValidChnList; // Valid BTSe2 channel list
+ uint8_t btso1ValidChnList; // Valid BTSo1 channel list
+ uint8_t btso2ValidChnList; // Valid BTSo2 channel list
+ uint32_t btsThreshold;
+} MXL_MOCA_BTS_T; // Bts_t;
+
+// CSS constants
+typedef struct
+{
+ uint16_t cssRxLvlMin; // RX_LVL_MIN
+ uint16_t cssRxLvlScale; // RX_LVL_SCALE
+ uint8_t acssChWt[MAX_WEIGHTS]; // aCss channel weight
+ uint8_t dcssChWt[MAX_WEIGHTS]; // dCss channel weight
+ uint8_t acssWtHt; // Analog CSS WT_HIT
+ uint8_t dcssWtHt; // Digital CSS WT_HIT
+ uint8_t acssWtMiss; // Analog CSS WT_MISS
+ uint8_t dcssWtMiss; // Digital CSS WT_MISS
+ uint8_t acssMinCnt; // Analog CSS MIN_CNT
+ uint8_t dcssMinCnt; // Digital CSS MIN_CNT
+ uint8_t acssMaxCnt; // Analog CSS MAX_CNT
+ uint8_t dcssMaxCnt; // Digital CSS MAX_CNT
+ uint8_t acssLoPenalty; // Analog CSS LO_PENALTY
+ uint8_t dcssLoPenalty; // Digital CSS LO_PENALTY
+ uint8_t acssHiPenalty; // Analog CSS HI_PENALTY
+ uint8_t dcssHiPenalty; // Digital CSS HI_PENALTY
+ uint8_t acssValidChnList; // Valid analog CSS channel list
+ uint8_t dcss1ValidChnList; // Valid digital CSS1 channel list
+ uint8_t dcss2ValidChnList; // Valid digital CSS2 channel list
+ uint8_t reserved;
+ uint32_t cssThreshold;
+} MXL_MOCA_CSS_T; // Css_t;
+
+// Energy and usability related thresholds
+typedef struct
+{
+ uint32_t bandEUsabilityThreshold;
+ uint32_t bandFUsabilityThreshold;
+ uint32_t bandDUsabilityThreshold;
+ uint32_t bandEEnergyThreshold;
+ uint32_t bandFEnergyThreshold;
+ uint32_t bandDEnergyThreshold;
+} MXL_MOCA_BAND_DEF_THRESHOLDS_T; //.BandDEFThresholds_t;
+
+// Energy detection configuration parameters
+typedef struct
+{
+ MXL_MOCA_BAND_E_TABLE_T atscTbl[MAX_ATSC_CATV_FREQS]; // ATSC table
+ MXL_MOCA_BAND_E_TABLE_T catvTbl[MAX_ATSC_CATV_FREQS]; // CATV table
+ MXL_MOCA_ATSC_CATV_WEIGHT_T atscWeight; // ATSC weight constants
+ MXL_MOCA_ATSC_CATV_WEIGHT_T catvWeight; // CATV weight constants
+ MXL_MOCA_BAND_D_TABLE_T btsCssTbl[MAX_BTS_CSS_FREQS]; // BTS/CSS table
+ MXL_MOCA_BTS_T bts; // BTS tuning constants
+ MXL_MOCA_CSS_T css; // CSS tuning constants
+ MXL_MOCA_BAND_DEF_THRESHOLDS_T bandDEFThresholds; // Energy and usability related thresholds
+} MXL_MOCA_ENERGY_DETECT_CFG_T;
+
+//! RLAPM configuration
+typedef struct
+{
+ //! RLAPM mode
+ // Bit 0-Enabled(1) or disabled(0) for Extended Band D
+ // Bit 1-Enabled(1) or disabled(0) for Sub-Band D-Low
+ // Bit 2-Enabled(1) or disabled(0) for Sub-Band D-High
+ // Bit 3-Enabled(1) or disabled(0) for Band E
+ // Bit 4-Enabled(1) or disabled(0) for Band F Satellite
+ // Bit 5-Enabled(1) or disabled(0) for Band F Cable
+ // Bit 6-Enabled(1) or disabled(0) for Band H
+ // Bit 7-Enabled(1) or disabled(0) for Custom Band
+ uint32_t rlapmmode;
+
+ //! RLAPM tables
+ MXL_MOCA_RLAPM_TABLE_V2_T tbl[MAX_RLAPM_FREQS];
+} MXL_MOCA_RLAPM_CFG_V2_T;
+
+typedef struct
+{
+ uint8_t modNum[40];
+ uint32_t diplexerCal;
+ uint32_t rgmiiClkCfg;
+ uint32_t hwCfg;
+} MXL_MOCA_PLATFORM_CFG_T;
+
+typedef struct
+{
+ //! The frequency for the PHY margin table
+ uint32_t freq;
+ //! The threshold
+ uint32_t threshold;
+ //! The starting subcarrier index
+ int32_t scstart;
+ //! Added PHY margin table
+ uint8_t phymargin[MAX_MINI_SAPM_MARGIN_LEN];
+} MXL_MOCA_SAPM_TABLE_V2_T;
+
+//! SAPM configuration
+typedef struct
+{
+ //! SAPM mode
+ // Bit 0-Enabled(1) or disabled(0) for Extended Band D
+ // Bit 1-Enabled(1) or disabled(0) for Sub-Band D-Low
+ // Bit 2-Enabled(1) or disabled(0) for Sub-Band D-High
+ // Bit 3-Enabled(1) or disabled(0) for Band E
+ // Bit 4-Enabled(1) or disabled(0) for Band F Satellite
+ // Bit 5-Enabled(1) or disabled(0) for Band F Cable
+ // Bit 6-Enabled(1) or disabled(0) for Band H
+ // Bit 7-Enabled(1) or disabled(0) for Custom Band
+ uint32_t sapmmode;
+ //! SAPM tables
+ MXL_MOCA_SAPM_TABLE_V2_T tbl[MAX_SAPM_FREQS];
+} MXL_MOCA_SAPM_CFG_V2_T;
+
+typedef struct
+{
+ uint8_t freqCompTbl[MAX_FREQ_COMP_TBL_LEN];
+ uint8_t startFreqIndex;
+ uint8_t channelSpacing;
+ int8_t logGainOffset; // signed
+} MXL_MOCA_RSSI_CFG_V2_T;
+
+// MoCA Configuration Parameters
+typedef struct
+{
+ /** The conf version is the Serial number to indicate the changes history of data strucutre.
+ The default value for version is 1.
+ */
+ uint8_t confVersion;
+ /** The test mode for the MoCA device. The values for test mode are as follows:
+ normal operation (0),
+ continuous transmit mode (1),
+ continuous wave mode (2),
+ no SoC download mode (3),
+ no health monitoring mode (4)
+ or test harness mode (5).
+ */
+ uint8_t testMode;
+ /** The turbo mode for the MoCA device.
+ The values for turbo mode are as follows: disabled (0) or enabled (1).
+ */
+ uint8_t turboMode;
+ /** The CLINK LED mode for the MoCA device:
+ bit 0:
+ CLINK LED constant glow with data traffic (0)
+ CLINK LED blinks with data traffic (1)
+ bit 7:
+ Turn off all Leds control bit, when set, it will drive GPIO in gpioAllLedsOffMask */
+ uint8_t clnkLedMode;
+ /** The test parameter 1 for the MoCA device. This parameter is used for internal purposes only. */
+ uint32_t testParam1;
+ /** The test parameter 2 for the MoCA device. This parameter is used for internal purposes only. */
+ uint32_t testParam2;
+ /** The test parameter 3 for the MoCA device. This parameter is used for internal purposes only. */
+ uint32_t testParam3;
+ /** The test parameter 4 for the MoCA device. This parameter is used for internal purposes only. */
+ uint32_t testParam4;
+
+ /** The MII pause priority level specifies the MoCA priority level
+ where MII pause packets are generated for transmit packets of that priority or above.
+ This field is valid only when using xMII mode for the data path.
+ The values for MII pause priority level are:
+ dynamic (-1) or MoCA priority (0-4).
+ */
+ int16_t miiPausePriorityLevel;
+ /** The MII speed for the MoCA device. The values for MII speed are as follows:
+ MII (1),
+ TMII (2),
+ GMII (3)
+ RGMII two ports (4).
+ RGMII one port (5).
+ Strap option (0x80).
+ */
+ uint8_t policingMode;
+ /** The PQoS classification mode specifies the classification mode to
+ use for PQoS flows on the transmit side. The values for PQoS classification mode are:
+ MoCA 1.1 classification (0) or
+ Pre-UpnP PQoS classification (1).
+ */
+ uint8_t pqosClassificationMode;
+ /** The priorities to enable retransmission on the transmit side.
+ The bits for retransmission priorities are defined as follows:
+ Bit 3: High priority enable
+ Bit 2: Medium priority enable
+ Bit 1: Low priority enable
+ Bit 0: Background priority enable
+ */
+ uint32_t miiSpeed;
+ /** The policing mode for the MoCA device. This field is used only when the node is NC.
+ The values for policing mode are as follows:
+ disabled (0) or
+ enabled (1).
+ */
+ uint32_t retransmissionPriority;
+ /** The PER profile to use for each priority on the transmit side.
+ The bits for PER priority are defined as follows:
+ Bit 3 -- High priority (NPER (0) or VLPER (1))
+ Bit 2 -- Medium priority (NPER (0) or VLPER (1))
+ Bit 1 -- Low priority (NPER (0) or VLPER (1))
+ Bit 0 -- Background priority (NPER (0) or VLPER (1))
+ */
+ uint32_t transmissionPriorityPer; //!< The PER profile to use for each priority on the transmit side.
+
+ uint8_t reserverd: 2,
+ /** The LOF update mode for the MoCA device. The values for LOF update mode are as follows:
+ disabled (0) or
+ enabled (1).
+ */
+ lofUpdateMode: 1,
+ /** The network search mode for the MoCA device.
+ The values for network search mode are as follows:
+ disabled (0) or
+ enabled (1).
+ */
+ networkSearchMode : 2,
+ /** The preferred NC mode for the MoCA device.
+ The values for preferred NC mode are as follows:
+ disabled (0),
+ enabled (1) or
+ reserved (2).
+ */
+ preferredNcMode: 1,
+ /**The handoff mode for the MoCA device. This field is used only when the node is NC.
+ The values for handoff mode are as follows:
+ disabled (0) or enabled (1).
+ */
+ handoffMode: 1,
+ /** The failover mode for the MoCA device.
+ This field is used only when the node is NC.
+ The values for failover mode are as follows:
+ disabled (0) or enabled (1)
+ */
+ failoverMode: 1;
+ /** The role is the initial role used to form or join the MoCA network for the MoCA device.
+ The values for role are as follows:
+ normal (0),
+ NC only (1) or
+ client only (2).
+ */
+ uint8_t initialRole;
+ /** The LMO mode for the MoCA device. This field is used only when the node is NC.
+ The values for LMO mode are as follows:
+ disabled (0) or
+ enabled (1).
+ */
+ uint8_t lmoMode;
+ /** The security mode for the MoCA device. The values for security mode are as follows:
+ disabled (0) or
+ enabled (1).
+ */
+ uint8_t securityMode;
+ /** The MoCA password is a user definable password for the MoCA network from 12 to 17 bytes. */
+ uint8_t mocaPassword[MAX_BANDS][18];
+ /** The MoCA reset sequence number. */
+ uint16_t mocaResetSeqNum16[MAX_BANDS];
+ /** The last operating frequency (LOF) in MHz. */
+ uint16_t lof16;
+
+ /* If customBandProfcGapMode set to 0 means, then there is no 25MHz gap between
+ Prof C Bonded channels. Default must be 1. */
+ uint8_t customBandProfcGapMode;
+ /** The frequency band mask defines the frequency bands that the user has selected to scan.
+ The bits for frequency band mask are defined as follows:
+ Bit 0 - Extended Band D
+ Bit 1 - Sub-Band D-Low
+ Bit 2 - Sub-Band D-High
+ Bit 3 - Band E
+ Bit 4 - Band F Satellite
+ Bit 5 - Band F Cable
+ Bit 6 - Band H
+ Bit 7 - Custom Band
+ */
+ uint8_t freqBandMask8;
+ /** The scan mask defines the channels that the user has selected to scan.
+ The channel represents the center frequency of the beacon. The bits for scan mask are defined as follows:
+ Bit 63 - Beacon freq scan offset x 25 MHz
+ Bit 62 - Beacon freq (scan offset+1) x 25 MHz
+ --
+ Bit 0 - Beacon freq (scan offset+63) x 25MHz
+ */
+ uint64_t scanMask64[MAX_BANDS];
+ /** The scan offset is the offset in 25MHz steps starting from 0 MHz for the scan mask.
+ The starting frequency for the scan can be calculated as follows: scan offset x 25 MHz.
+ */
+ uint8_t scanOffset8[MAX_BANDS];
+ /** The primary channel offset is a mask to indicate whether the center frequency of
+ the primary channel is 25 MHz above the beacon channel. This field is used only when
+ the node is NC. The bits for primary channel offset are defined as follows:
+ Bit 63 - Same (0), above (1) for beacon freq scan offset x 25 MHz
+ Bit 62 - Same (0), above (1) for beacon freq (scan offset+1) x 25 MHz
+ --
+ Bit 0 - Same (0), above (1) for beacon freq (scan offset+63) x 25MHz
+ */
+ uint64_t primChnMaskAbove64[MAX_BANDS];
+ /** The primary channel offset is a mask to indicate whether the center frequency of
+ the primary channel is 25 MHz below the beacon channel. This field is used only when
+ the node is NC. The bits for primary channel offset are defined as follows:
+ Bit 63 - Same (0), below (1) for beacon freq scan offset x 25 MHz
+ Bit 62 - Same (0), below (1) for beacon freq (scan offset+1) x 25 MHz
+ --
+ Bit 0 - Same (0), below (1) for beacon freq (scan offset+63) x 25MHz
+ */
+ uint64_t primChnMaskBelow64[MAX_BANDS];
+ /** The secondary channel offset is a mask to indicate whether the center frequency of the
+ secondary channel is 125 MHz above the primary channel. This field is used only when the node is NC.
+ The bits for secondary channel offset are defined as follows:
+ Bit 63 - None (0), above (1) for primary freq scan offset x 25 MHz
+ Bit 62 - None (0), above (1) for primary freq (scan offset+1) x 25 MHz
+ --
+ Bit 0 - None (0), above (1) for primary freq (scan offset+63) x 25MHz
+ */
+ uint64_t secChnMaskAbove64[MAX_BANDS];
+ /** The secondary channel offset is a mask to indicate whether the center frequency of
+ the secondary channel is 125 MHz below the primary channel.
+ This field is used only when the node is NC.
+ The bits for secondary channel offset are defined as follows:
+ Bit 63 - None (0), below (1) for primary freq scan offset x 25 MHz
+ Bit 62 - None (0), below (1) for primary freq (scan offset+1) x 25 MHz
+ --
+ Bit 0 - None (0), below (1) for primary freq (scan offset+63) x 25MHz
+ */
+ uint64_t secChnMaskBelow64[MAX_BANDS];
+ /** The taboo offset is the offset from the beacon frequency for the taboo information. */
+ uint32_t tabooOffset:8,
+ /** The taboo information defines the off-limits channels above and below the active channel
+ which the NC will advertise to all nodes scanning to join a network. The taboo mask is a mask of
+ the channels for the taboo information.
+ The bits for taboo mask are defined as follows:
+ Bit 31: Beacon frequency - taboo offset x 25MHz
+ Bit 30: Beacon frequency - (taboo offset + 1) x 25MHz
+ --
+ Bit 8: Beacon frequency - (taboo offset +23) x 25MHz
+ */
+ tabooMask : 24;
+ /** The minimum time (in seconds) a node stays in listening phase of network search. */
+ uint8_t tlpMin8[MAX_BANDS];
+ /** The maximum time (in seconds) a node stays in listening phase of network search. */
+ uint8_t tlpMax8[MAX_BANDS];
+ /** Power level to use when transmiting beacons*/
+ uint8_t beaconTxPwr;
+ /** Max Tx power for all packets except beacons*/
+ uint8_t maxTxPwr;
+ /** Encoding word length (kLDPCmax) for NPER profiles*/
+ uint32_t encWdLenNper;
+ /** Encoding word length (kLDPCmax) for VLPER profiles*/
+ uint32_t encWdLenVlper;
+ /** dynamic PCL feature enable flags*/
+ uint32_t featureEnFlags;
+ /** PHY Bitloading margin adj for 50 MHz in 0.5dB steps*/
+ uint8_t phyMargin50[MAX_BANDS];
+ /** PHY Bitloading margin adj for 100 MHz NPER in 0.5dB steps*/
+ uint8_t phyMarginNper[MAX_BANDS];
+ /** PHY Bitloading margin adj for 100 MHz VLPER in 0.5dB steps*/
+ uint8_t phyMarginVlper[MAX_BANDS];
+ /** The TPC mode enables/disables TPC from all other nodes to this node.
+ The values for TPC mode are as follows:
+ disabled (0),
+ enabled (1) or
+ reserved (2).
+ */
+ uint16_t tpcMode;
+ /** The TPC target PHY rate for transmissions on the 50MHz channel from all other nodes to this node
+ when TPC mode is enabled. The value for TPC target PHY rate is in Mbps.
+ When operating in MoCA 2.0 mode, the default value is 600 Mbps.
+ When operating in MoCA 1.1 mode, the default value is 235 Mbps.
+ */
+ uint16_t tgtP2p50Rate;
+
+ /** The TPC target PHY rate for transmissions on the 100MHz NPER channel from all other nodes to this node
+ when TPC mode is enabled. The value for TPC target PHY rate is in Mbps.
+ When operating in MoCA 2.0 mode, the default value is 600 Mbps.
+ When operating in MoCA 1.1 mode, the default value is 235 Mbps.
+ */
+ uint16_t tgtP2pNperRate;
+ /** The TPC target PHY rate for transmissions on the 100MHz VLPER channel from all other nodes to this node
+ when TPC mode is enabled. The value for TPC target PHY rate is in Mbps.
+ When operating in MoCA 2.0 mode, the default value is 600 Mbps.
+ When operating in MoCA 1.1 mode, the default value is 235 Mbps.
+ */
+ uint16_t tgtP2pVlperRate;
+ /** The vlan tag to be removed. Bit 31 is used to enable the strip of vlan tag. The LS 12 bits indicate the vlan id to be stripped.
+ If bit 31 is 1, packets with vlan ID equals to the LS 12 bits of this parameter will have the vlan tag be stripped.
+ */
+ uint32_t stripVlanTag;
+ /** Upper 4 bytes of MPA destination MAC Address */
+ uint32_t mpaMacAddrHi;
+ /** 2 bytes of MPA destination MAC Address */
+ uint16_t mpaMacAddrLo;
+ /** 2 bytes for MPA MoCA packet filter */
+ uint16_t mpaPktFilter;
+ /** The offset of first channel's center frequency below the center frequency of the Primary Channel, the valid values range is 0-4.
+ The first channel's center frequency can be calculated as follows:
+ primary channel frequency - frist channel offset * 100 MHz;
+ */
+ uint8_t firstChannelOffset[MAX_BANDS];
+ /** The maximum number of 100MHz channels, the valid values range is 3-5. */
+ uint8_t numberOfChannels[MAX_BANDS];
+ /** The load capacitors configraion for the xtal. */
+ uint32_t loadingCaps;
+ /** E-MAC Address Aging time out. If there is no activity in ETH traffic for this period, FW will remove this entry from DIC-TC CAM. */
+ uint32_t macAddrAgingTimeInSecs;
+ /** Enable or disable beacon power mode. */
+ uint8_t bcnPwrConfigEn;
+ /** Absolute Beacon Power for Distribution -10dbm to +7dbm. */
+ int8_t bcnPwrDist;
+ /** Absolute Beacon Power for Local -10dbm to +7dbm. */
+ int8_t bcnPwrLocal;
+ /** Enable/disable handoff to lower MoCA version. */
+ uint8_t handoffToLowerMoCAVer;
+ /** Privacy support mode for moca version**/
+ int8_t privacySupported;
+ /** Enhanced password for 12 to 64 ASCII printable characters **/
+ uint8_t mocaEPPassword[MAX_MOCA25_ENHANCED_PASSWORD_LEN];
+ /** MPS privacy downgrade, enable or diable **/
+ uint16_t mpsPrivacyDown;
+ /** MPS privacy receive, enable or diable **/
+ uint16_t mpsPrivacyReceive;
+ /** MPS unpaired time, range is 120 ~ 7200 **/
+ uint32_t mpsUnPairedTime;
+ /** MPS unpaired time, range is 12 ~ 1200 **/
+ uint32_t mpsWalkTime;
+ /* Bridge Detection */
+ uint8_t networkName[MAX_NW_NAME_LEN]; //!< Network name updated from Host
+ uint32_t networkNameAdmitCfg; //!< Network Name Admit cfg
+ // meNetworkIePayloadTx: The payload of the Management Entity Request Network IE (when the Node is trying to join the network),
+ // or of the Management Entity Response Network IE (when the Node is the NC).
+ uint8_t meNetworkIePayloadTx[MAX_ME_NW_IE_PAYLOAD_LEN];
+ // meNetworkIeRespTimeout: Indicates the number of Discovery Request transmission opportunities that a NN has to wait for a response.
+ uint32_t meNetworkIeRespTimeout; //!< default of 10 seconds = 1000. Specified in 10msec step
+ uint32_t meNetworkJoinEn; //!< Configures as enable/disable whether managed parameter NETWORKJOIN is yes or no in OSP mode if the Information Fields match.
+ /* MAC Link Authentication params */
+ struct
+ {
+ uint16_t reserved;
+ uint16_t etherType; //!< Ethernet Type
+ uint16_t bitmask[MAX_NUM_NODES]; //!< unicast traffics permission bitmasks
+ } defaultAuthLink;
+ /** Trace type enable/disable. */
+ uint8_t traceEnable;
+ /** Minimum trace level. */
+ uint8_t traceLevel;
+ /** Trace module enable/disable. */
+ uint8_t traceModule;
+ /** Trace destination enable/disable. */
+ uint8_t traceDest;
+ /** Trace host control (common/common2 queue display in host driver enable/disable etc)
+ * Bit0: common queue on/off, Bit1: common2 queue on/off.
+ * Bit8: background clnktrace app on/off flag (only for MXL ECA usage)
+ * Bit16: check and print soc config parameters on/off flag
+ */
+ uint32_t traceHostCtl;
+} MXL_MOCA_CFG_V2_T;
+
+// New MoCA2.5 paramters
+// Beacon Power
+typedef enum
+{
+ MXL_BCN_PWR_TYPE_LOCAL = 0,
+ MXL_BCN_PWR_TYPE_DIST=1
+} MXL_BCN_PWR_TYPE_T;
+
+typedef struct
+{
+ int32_t bcnPwr; // Absolute Beacon Power, Range:-10 to +7 (dbm)
+ MXL_BCN_PWR_TYPE_T bcnPwrType; // BCN_PWR_TYPE_LOCAL(=0) or BCN_PWR_TYPE_DIST(=1)
+} MXL_MOCA_SOC_SET_BCN_POWER_CMD_T;
+
+typedef struct
+{
+ uint32_t result; // 0 - SUCCESS 1 - FAILURE
+} MXL_MOCA_SOC_SET_BCN_POWER_RSP_T;
+
+typedef struct
+{
+ int32_t bcnPwrDist; // Distribute Beacon Power, Range:-10 to +7 (dbm)
+ int32_t bcnPwrLocal; // Local Beacon Power, Range:-10 to +7 (dbm)
+} MXL_MOCA_SOC_GET_BCN_POWER_RSP_T;
+
+typedef struct
+{
+ int32_t bcnPwrPieTxPwr; // Absolute Bcn tx Power(-10 to +7)
+ uint32_t bcnPwrPieTxPwrType; // BCN_PWR_PIE_TYPE_INDIVIDUAL(=0) or BCN_PWR_TYPE_NETWORKWIDE(=1)
+ uint32_t bcnPwrPieNodeMask; // Nodemask of the nodes to which Host wants to send the Bcn Power PIE (0x0000 0xFFFF)
+} MXL_MOCA_SOC_REQUEST_BCNPWR_PIE_CMD_T;
+
+typedef struct
+{
+ uint32_t result; // 0 - SUCCESS 1 - FAILURE
+} MXL_MOCA_SOC_REQUEST_BCNPWR_PIE_RSP_T;
+
+// MPS
+typedef struct
+{
+ /* SUCCESS = 0, FAILURE = 1 */
+ uint32_t mpsTriggerResult;
+} MXL_MOCA_SOC_SET_MPS_TRIGGER_RSP_T;
+
+typedef enum
+{
+ MPS_REPORT_TYPE_SCAN_PAYLOAD = 0,
+ MPS_REPORT_TYPE_NETWORK_NAME_PAYLOAD = 1,
+ MPS_REPORT_TYPE_MPS_PAIR_STATUS = 2,
+ MPS_REPORT_TYPE_MPS_PRIVACY_CHANGE = 3,
+ MPS_REPORT_TYPE_MPS_IN_PROGRESS = 4,
+ MPS_REPORT_TYPE_MPS_SESSION_TIMEOUT = 5,
+ MPS_REPORT_TYPE_MPS_SSN_DONE_CONTINUE_NORMAL_ADM = 6,
+ MPS_REPORT_TYPE_MPS_TRIGGER_FWD_NC = 7,
+ MPS_REPORT_TYPE_MPS_FAILED = 8,
+ MPS_REPORT_TYPE_MAX
+} MPS_REPORT_TYPE_T;
+
+
+typedef struct
+{
+ /* CODE = 0 means no MPS session triggered */
+ uint8_t nc_moca_version;
+ /* Channel Num on which the MPS network found */
+ uint8_t chn_num;
+ /* CODE = 0 means no MPS session triggered */
+ uint8_t code;
+ /* MPS Response from NC - As per spec Section 6.3.2.2.7. Meaning of LSB bits
+ Bit3: Reserved,
+ Bit2: NC Privacy Enabled/Disabled,
+ Bit1: NC Recive Privacy
+ Bit0: NC downgrade Privacy
+ */
+ uint8_t mps_params;
+} MPS_INIT_SCAN_PAYLOAD_T;
+
+typedef struct
+{
+ /* My Node Privacy Support.0x03 (M20P, M1P), 0x04 (EP), 0x6 (EP, M20P), 0x07(EP, M20P, M1P) */
+ uint8_t privacySupport;
+ /* 1 means Privacy is Enabled, 0 means Disabled */
+ uint8_t privacyEn;
+ uint16_t pad;
+ /* 20 Random Decimal Digits */
+ uint8_t Pswd[MAX_PASSWORD_LENGTH_PADDED];
+ /* 64Random ASCII characters */
+ uint8_t Epswd[MAX_MOCA_EP_PASSWORD_LEN_PADDED];
+} MPS_PRIVACY_PARAMS_T;
+
+typedef struct
+{
+ uint32_t mpsState;
+}MXL_MOCA_SOC_GET_MPS_STATE_RSP_T;
+
+typedef struct
+{
+ /* MPS report types are valid in this report.
+ Refer MPS_REPORT_TYPE_T for bit positions of the Report. */
+ uint32_t mpsReportTypeBitMask;
+ /* 0 means the MPS report is Invalid. 1 Means Mps Report is Valid */
+ uint8_t isMpsReportValid;
+ /* 0 - MPS_PAIR_FAIL, 1-MPS_PAIR_SUCCESS */
+ uint8_t mpsPairStatus;
+ /* mpsPrivacyChanged=1 if privacy changed else mpsPrivacyChanged=0 */
+ uint8_t mpsPrivacyChanged;
+
+ uint8_t mpsInPrgPbNodeId;
+
+ /* Network Name */
+ uint8_t networkName[32];
+ /* MPS Init scan params. */
+ MPS_INIT_SCAN_PAYLOAD_T mpsInitScanPayLoad;
+ MPS_PRIVACY_PARAMS_T mpsPrivacyParams;
+} MXL_MOCA_SOC_GET_MPS_REPORT_RSP_T;
+
+// Enhanced Privacy
+typedef struct
+{
+ uint32_t result;
+ uint32_t password[16];
+} MXL_MOCA_SOC_GET_SEC_EP_PASSWORD_RSP_T; /* Hi_TxnGetSecPasswordRsp_t */
+
+typedef struct
+{
+ /* Enhanced Security Keys */
+ uint32_t eammk[4];
+ uint32_t eapmkInit[4];
+ uint32_t eapmk[2][4];
+ uint32_t activeEApmk;
+ uint32_t eatek[2][4];
+ uint32_t activeEAtek;
+} MXL_MOCA_SOC_GET_EP_SEC_INFO_RSP_T; /* Hi_TxnGetEPSecInfoRsp_t */
+
+// Traffic Permission
+
+// MXL_MOCA_SOC_SET_TRAFFIC_PERMIT_CFG / HI_TXNTYPE_SET_TRAFFIC_PERMIT_CFG
+
+typedef struct
+{
+ uint32_t ethernetType; //!< Ethernet Type for Traffic permission , 0~0xffff
+ uint16_t trafficNodeBitMask[16]; //!< Bit Mask for each node >
+} MXL_MOCA_SOC_SET_TRAFFIC_PERMIT_CFG_CMD_T; /* Hi_TxnSetTrafficPermissionCfgCmd_t */
+
+// MXL_MOCA_SOC_GET_TRAFFIC_PERMIT_STS / HI_TXNTYPE_GET_TRAFFIC_PERMIT_STS
+
+typedef struct
+{
+ uint32_t trafficPermissionStatus; //!< Traffice permission Response for the command already sent , 1-successful, 2-failed
+} MXL_MOCA_SOC_GET_TRAFFIC_PERMIT_STS_RSP_T; /* Hi_TxnGetTrafficPermissionStsRsp_t */
+
+// MXL_MOCA_SOC_GET_ETHER_TYPE_INFO / HI_TXNTYPE_GET_ETHER_TYPE_INFO
+
+typedef struct
+{
+ uint32_t ethernetType; //!< Ethernet Type for Traffic permission , 0~0xffff
+} MXL_MOCA_SOC_GET_ETHER_TYPE_INFO_RSP_T; /* Hi_TxnGetEtherTypeInfoRsp_t */
+
+/*
+ * MxL MoCA Driver command data structure
+ */
+
+// MXL_MOCA_DRV_GET_CFG_AND_FW_DIR
+
+typedef struct
+{
+ char confDir[CONFDIR_NAME_MAX];
+ char fwDir[FWDIR_NAME_MAX];
+} MXL_MOCA_DRV_GET_CFG_AND_FW_DIR_RSP_T;
+
+// MXL_MOCA_DRV_GET_DAEMON_INFO
+
+typedef struct
+{
+ uint32_t clear;
+} MXL_MOCA_DRV_GET_DAEMON_INFO_CMD_T;
+
+typedef struct
+{
+ uint32_t cdUpTimeInSecs;
+ uint32_t linkUpTimeInSecs;
+ uint32_t resetCount;
+ uint32_t resetHistory;
+ uint32_t resetLine;
+ uint32_t resetEpc;
+ uint32_t linkLostCount; // link lost count record
+ uint32_t drvVersionStr[MAX_HOST_VERSION_STR_SIZE / 4];
+ uint32_t pkgVersionStr[MAX_HOST_VERSION_STR_SIZE / 4];
+} MXL_MOCA_DRV_GET_DAEMON_INFO_RSP_T;
+
+// MXL_MOCA_DRV_SET_SOC_BOOTED
+
+typedef struct
+{
+ uint32_t dlOnly;
+} MXL_MOCA_DRV_SET_SOC_BOOTED_CMD_T;
+
+// MXL_MOCA_DRV_SET_CD_FIRMWARE_CMD_T / MXL_MOCA_DRV_SET_CD_FIRMWARE
+
+typedef struct
+{
+ uint32_t size;
+ uint8_t *pData;
+ void **ppPages;
+} MXL_MOCA_FIRMWARE_ENTRY_T;
+
+typedef struct
+{
+ MXL_MOCA_FIRMWARE_ENTRY_T *fw_entry[MXL_MOCA_MAX_FW_IDX];
+ uint32_t ret;
+} MXL_MOCA_DRV_SET_CD_FIRMWARE_CMD_T;
+
+typedef MXL_MOCA_DRV_SET_CD_FIRMWARE_CMD_T MXL_MOCA_FIRMWARE_T;
+
+// MXL_MOCA_DRV_GET_CHIP_TYPE
+
+typedef struct
+{
+ uint32_t type; // 0: Jaws, 1: Malaga, 2: Cardiff, 3: Leucadia
+} MXL_MOCA_DRV_GET_CHIP_TYPE_RSP_T;
+
+// MXL_MOCA_DBG_SET_MEM
+
+typedef struct
+{
+ uint32_t socMemAddr[CLNK_CTL_MAX_IN_LEN/4]; // The first word is the address, following words are data
+} MXL_MOCA_DRV_SET_DBG_MEM_CMD_T;
+
+// MXL_MOCA_DBG_GET_MEM
+
+typedef struct
+{
+ uint32_t socMemAddr;
+} MXL_MOCA_DRV_GET_DBG_MEM_CMD_T;
+
+typedef struct
+{
+ uint32_t usrData[CLNK_CTL_MAX_OUT_LEN/4];
+} MXL_MOCA_DRV_GET_DBG_MEM_RSP_T;
+
+// MXL_MOCA_DRV_START_DAEMON
+
+typedef struct
+{
+ uint8_t confDir[CONFDIR_NAME_MAX];
+ uint8_t fwDir[FWDIR_NAME_MAX];
+ uint32_t macHi;
+ uint32_t macLo;
+ uint32_t dlOnly;
+ uint32_t dlVerify;
+} MXL_MOCA_DRV_START_DAEMON_CMD_T;
+
+// SIOC_MXL_MOCA_START_DAEMON
+
+typedef struct
+{
+ uint16_t phyId;
+ uint16_t regNum;
+ uint16_t valIn;
+ uint16_t valOut;
+ uint16_t devAddr; //Used for Clause 45 MDIO
+} MXL_MOCA_MMI_IOCTL_DATA_T; ///< mmi_ioctl_data
+
+typedef struct
+{
+ uint8_t name[16];
+ union
+ {
+ uint32_t *ptr;
+ MXL_MOCA_MMI_IOCTL_DATA_T mmi;
+ uint8_t mac[8];
+ uint32_t otpDword;
+ } dat;
+} MXL_MOCA_DRV_RW_MII_REG_CMD_T; ///< ioctl_stuff
+
+// MXL_MOCA_DRV_SET_APPLICATION_TRACE
+
+typedef struct
+{
+ uint32_t flag;
+} MXL_MOCA_DRV_SET_APPLICATION_TRACE_CMD_T;
+
+typedef struct
+{
+ uint16_t valOut;
+} MXL_MOCA_DRV_RD_MII_REG_RSP_T;
+
+// MoCA Control Commands
+typedef struct
+{
+ // moca command
+ uint32_t mocaCmdId; // MoCA command: MXL_MOCA_SOC_GET_SOC_STATUS, MXL_MOCA_DRV_GET_ETH_STATS
+
+ // in_len
+ uint32_t mocaCmdLenInBytes; // 0 or actual size in uCmd (0 means Cmd is not input argument in uCmd
+
+ // union structure for request of all Moca Cmd
+ union
+ {
+ MXL_MOCA_SOC_SET_INIT_PARAM_CMD_T socSetInitParamCmd;
+ MXL_MOCA_SOC_SET_INIT_RLAPM_CMD_T socSetInitRlapmCmd;
+ MXL_MOCA_SOC_SET_INIT_SAPM_CMD_T socSetInitSapmCmd;
+ MXL_MOCA_SOC_SET_INIT_PARAM_V25_CMD_T socSetInitParamV25Cmd;
+ MXL_MOCA_SOC_GET_AGGR_STATS_CMD_T socGetAggrStatsCmd;
+ MXL_MOCA_SOC_GET_BRIDGE_STATS_CMD_T socGetBridgeStatsCmd;
+ MXL_MOCA_SOC_GET_BRIDGE_TABLE_CMD_T socGetBridgeTableCmd;
+ MXL_MOCA_SOC_GET_EPHY_STATS_CMD_T socGetEphyStatsCmd;
+ MXL_MOCA_SOC_GET_FRAME_STATS_CMD_T socGetFrameStatsCmd;
+ MXL_MOCA_SOC_GET_NET_INFO_CMD_T socGetNetInfoCmd;
+ MXL_MOCA_SOC_SET_MULTICAST_FILTER_CMD_T socSetMultiCastFilterCmd;
+ MXL_MOCA_SOC_GET_RETRANS_STATS_CMD_T socGetRetransStatsCmd;
+ MXL_MOCA_SOC_GET_FRAG_STATS_CMD_T socGetFragStatsCmd;
+ MXL_MOCA_SOC_GET_L2ME_STATS_CMD_T socGetL2meStatsCmd;
+ MXL_MOCA_SOC_SET_MCAST_MODE_CMD_T socSetMcastModeCmd;
+ MXL_MOCA_SOC_SET_PHYMODE_BITMASK_CMD_T socSetPhyModBitmaskCmd;
+ MXL_MOCA_SOC_REQ_HANDOFF_CMD_T socReqHandOffCmd;
+ MXL_MOCA_SOC_REQ_LMO_CMD_T socReqLMOCmd;
+ MXL_MOCA_SOC_GET_FMR_INFO_CMD_T socGetFmrInfoCmd;
+ MXL_MOCA_SOC_GET_DD_INFO_CMD_T socGetDdInfoCmd;
+ MXL_MOCA_SOC_MOCA_RESET_CMD_T socMocaResetCmd;
+ MXL_MOCA_SOC_REQ_NMS_CMD_T socReqNmsCmd;
+ MXL_MOCA_SOC_GET_PHY_TX_PROFILE_CMD_T socGetPhyTxProfileCmd;
+ MXL_MOCA_SOC_GET_PHY_RX_PROFILE_CMD_T socGetPhyRxProfileCmd;
+ MXL_MOCA_SOC_GET_PHY_NODE_CMD_T socGetPhyNodeCmd;
+ MXL_MOCA_SOC_GET_PHY_EVM_CMD_T socGetPhyEvmCmd;
+ MXL_MOCA_SOC_GET_OFDMA_TX_PROFILE_CMD_T socGetOfdmaTxProfileCmd;
+ MXL_MOCA_SOC_GET_OFDMA_RX_PROFILE_CMD_T socGetOfdmaRxProfileCmd;
+ MXL_MOCA_SOC_POWER_SLEEP_CMD_T socPowerSleepCmd;
+ MXL_MOCA_SOC_POWER_WAKE_CMD_T socPowerWakeCmd;
+ MXL_MOCA_SOC_QUERY_PM_STATE_CMD_T socQueryPmStateCmd;
+ MXL_MOCA_SOC_GET_PM_EVENT_CMD_T socGetPmEventCmd;
+ MXL_MOCA_SOC_PFP_CMD_T socCreateFlowCmd;
+ MXL_MOCA_SOC_PFP_CMD_T socUpdateFlowCmd;
+ MXL_MOCA_MAC_ADDR_T socDeleteFlowCmd;
+ MXL_MOCA_SOC_FLOW_LIST_CMD_T socFlowListCmd;
+ MXL_MOCA_MAC_ADDR_T socQueryFlowCmd;
+ MXL_MOCA_SOC_GET_FLOW_STATS_CMD_T socGetFlowStatsCmd;
+ MXL_MOCA_SOC_GET_SEC_STATS_CMD_T socGetSecStatsCmd;
+ MXL_MOCA_SOC_SET_MULTICAST_CFG_CMD_T socSetMultiCastCfgCmd;
+ MXL_MOCA_SOC_SET_GET_TXPWR_VAR_CMD_T socSetGetTxPwrVarCmd;
+ MXL_MOCA_SOC_TEST_CMD_T socTestCmd;
+ MXL_MOCA_SOC_GET_SWITCH_STATS_CMD_T socGetSwitchStatsCmd;
+ MXL_MOCA_SOC_GET_SWITCH_CONFIG_CMD_T socGetSwitchConfigCmd;
+
+ MXL_MOCA_SOC_GET_NETWORK_NAME_REC_CMD_T socGetNetworkNameRecCmd;
+ MXL_MOCA_SOC_GET_NETWORK_NAME_PAYLOAD_CMD_T socGetNetworkNamePayloadCmd;
+ MXL_MOCA_SOC_ME_NETWORK_IE_PAYLOAD_TX_CMD_T socMeNetworkIePayloadTxCmd;
+ MXL_MOCA_SOC_ME_NETWORK_IE_PAYLOAD_RX_CMD_T socMeNetworkIePayloadRxCmd;
+ MXL_MOCA_SOC_ME_NETWORK_JOIN_CMD_T socMeNetworkJoinCmd;
+
+ MXL_MOCA_SOC_RESET_SWITCH_CONFIG_CMD_T socResetSwitchConfigCmd;
+ MXL_MOCA_SOC_SET_SWITCH_TMO_CMD_T socSetSwitchTmoCmd;
+ MXL_MOCA_SOC_ENA_SWITCH_VLAN_CHECK_CMD_T socEnaSwitchVlanCheckCmd;
+ MXL_MOCA_SOC_DIS_SWITCH_VLAN_CHECK_CMD_T socDisSwitchVlanCheckCmd;
+ MXL_MOCA_SOC_ENA_SWITCH_VLAN_STRIP_CMD_T socEnaSwitchVlanStripCmd;
+ MXL_MOCA_SOC_DIS_SWITCH_VLAN_STRIP_CMD_T socDisSwitchVlanStripCmd;
+ MXL_MOCA_SOC_SET_SWITCH_VLAN_PVID_CMD_T socSetSwitchVlanPvidCmd;
+ MXL_MOCA_SOC_ADD_SWITCH_VLANID_CMD_T socAddSwitchVlanIdCmd;
+ MXL_MOCA_SOC_DEL_SWITCH_VLANID_CMD_T socDelSwitchVlanIdCmd;
+ MXL_MOCA_SOC_SET_SWITCH_MGMT_MAC_CMD_T socSetSwitchMgmtMacCmd;
+ MXL_MOCA_SOC_GET_MACDATA_STATS_CMD_T socGetMacDataStatsCmd;
+ MXL_MOCA_SOC_SET_SWITCH_PORT_CONFIG_CMD_T socSetSwitchPortConfigCmd;
+ MXL_MOCA_SOC_GET_ACTIVE_RLAPM_CMD_T socGetActiveRlapmCmd;
+ MXL_MOCA_SOC_GET_ACTIVE_SAPM_CMD_T socGetActiveSapmCmd;
+ MXL_MOCA_SOC_NET_PROXY_PKT_SEND_REQ_CMD_T socSendNetProxyPktCmd;
+ MXL_MOCA_SOC_NET_PROXY_TEST_MODE_CTRL_CMD_T socSendNetProxyTestModeCtrlCmd;
+ MXL_MOCA_SOC_SET_BCN_POWER_CMD_T socSetBcnPowerCmd;
+ MXL_MOCA_SOC_REQUEST_BCNPWR_PIE_CMD_T socReqBcnPowerPiecmd;
+ MXL_MOCA_SOC_SET_TRAFFIC_PERMIT_CFG_CMD_T socSetTrafficPermitCfgCmd;
+ MXL_MOCA_SOC_GET_ECB_STATS_CMD_T socGetEcbStatsCmd;
+
+ MXL_MOCA_DRV_SET_OTP_CONFIG_CMD_T drvSetOtpConfigCmd;
+ MXL_MOCA_DRV_GET_DAEMON_INFO_CMD_T drvGetDaemonInfoCmd;
+ MXL_MOCA_DRV_SET_SOC_BOOTED_CMD_T drvSetSocBootedCmd;
+ MXL_MOCA_DRV_SET_DBG_MEM_CMD_T drvSetDbgMemCmd;
+ MXL_MOCA_DRV_GET_DBG_MEM_CMD_T drvGetDbgMemCmd;
+ MXL_MOCA_DRV_SET_CD_FIRMWARE_CMD_T drvSetDaemonFirmwareCmd;
+ MXL_MOCA_DRV_START_DAEMON_CMD_T drvStartDaemonCmd;
+ MXL_MOCA_MAC_ADDR_T drvSetMacAddrCmd;
+ MXL_MOCA_DRV_RW_MII_REG_CMD_T drvRwMiiRegCmd;
+ MXL_MOCA_DRV_SET_APPLICATION_TRACE_CMD_T drvSetAppTraceCmd;
+
+ } uCmd;
+
+} MXL_MOCA_OP_CMD_T;
+
+typedef struct
+{
+ // moca command
+ uint32_t mocaCmdId; // Callee should return the same command Id that it got from Op Command, if it's NULL, Response had been failed.
+
+ // out_len
+ uint32_t mocaRspLenInBytes; // 0 or actual size in uRsp (0 means Cmd is not output argument in uRsp)
+
+ // union structure for response of all Moca Cmd
+ union
+ {
+ MXL_MOCA_SOC_GET_SOC_STATUS_RSP_T socGetStatusRsp;
+ MXL_MOCA_SOC_GET_IMAGE_INFO_RSP_T socGetImageInfoRsp;
+ MXL_MOCA_SOC_INIT_SYSTEM_START_RSP_T socSetInitSystemStartRsp;
+ MXL_MOCA_SOC_GET_AGGR_STATS_RSP_T socGetAggrStatsRsp;
+ MXL_MOCA_SOC_GET_BRIDGE_STATS_RSP_T socGetBridgeStatsRsp;
+ MXL_MOCA_SOC_GET_BRIDGE_TABLE_RSP_T socGetBridgeTableRsp;
+ MXL_MOCA_SOC_GET_EPHY_STATS_RSP_T socGetEphyStatsRsp;
+ MXL_MOCA_SOC_GET_FRAME_STATS_RSP_T socGetFrameStatsRsp;
+ MXL_MOCA_SOC_GET_DATA_STATS_RSP_T socGetDataStatsRsp;
+ MXL_MOCA_SOC_GET_LOCAL_INFO_RSP_T socGetLocalInfoRsp;
+ MXL_MOCA_SOC_GET_NET_INFO_RSP_T socGetNetInfoRsp;
+ MXL_MOCA_SOC_SET_MULTICAST_FILTER_RSP_T socSetMultiCastFilterRsp;
+ MXL_MOCA_SOC_GET_RETRANS_STATS_RSP_T socRetransStatsRsp;
+ MXL_MOCA_SOC_GET_FRAG_STATS_RSP_T socGetFragStatsRsp;
+ MXL_MOCA_SOC_GET_L2ME_STATS_RSP_T socGetL2meStatsRsp;
+ MXL_MOCA_SOC_GET_MCAST_MODE_RSP_T socGetMcastModeRsp;
+ MXL_MOCA_SOC_SET_MCAST_MODE_RSP_T socSetMcastModeRsp;
+ MXL_MOCA_SOC_SET_PHYMODE_BITMASK_RSP_T socSetPhyModBitmaskRsp;
+ MXL_MOCA_SOC_REQ_HANDOFF_RSP_T socReqHandoffRsp;
+ MXL_MOCA_SOC_REQ_LMO_RSP_T socReqLMORsp;
+ MXL_MOCA_SOC_GET_FMR_INFO_RSP_T socGetFmrInfoRsp;
+ MXL_MOCA_SOC_GET_DD_INFO_RSP_T socGetDdInfoRsp;
+ MXL_MOCA_SOC_MOCA_RESET_RSP_T socMocaResetRsp;
+ MXL_MOCA_SOC_REQ_NMS_RSP_T socReqNmsRsp;
+ MXL_MOCA_SOC_GET_PHY_TX_PROFILE_RSP_T socGetPhyTxProfileRsp;
+ MXL_MOCA_SOC_GET_PHY_RX_PROFILE_RSP_T socGetPhyRxProfileRsp;
+ MXL_MOCA_SOC_GET_PHY_NODE_RSP_T socGetPhyNodeRsp;
+ MXL_MOCA_SOC_GET_PHY_EVM_RSP_T socGetPhyEvmRsp;
+ MXL_MOCA_SOC_GET_PHY_MISC_RSP_T socGetPhyMiscRsp;
+ MXL_MOCA_SOC_GET_PHY_OFDMA_DEF_RSP_T socGetPhyOfdmaDefRsp;
+ MXL_MOCA_SOC_GET_PHY_OFDMA_ASSIGN_RSP_T socGetPhyOfdmaAssignRsp;
+ MXL_MOCA_SOC_GET_OFDMA_PARAMS_RSP_T socGetOfdmaParamsRsp;
+ MXL_MOCA_SOC_GET_OFDMA_TX_PROFILE_RSP_T socGetOfdmaTxProfileRsp;
+ MXL_MOCA_SOC_GET_OFDMA_RX_PROFILE_RSP_T socGetOfdmaRxProfileRsp;
+ MXL_MOCA_SOC_POWER_SLEEP_RSP_T socPowerSleepRsp;
+ MXL_MOCA_SOC_POWER_WAKE_RSP_T socPowerWakeRsp;
+ MXL_MOCA_SOC_GET_PM_CAPS_RSP_T socGetPmCapsRsp;
+ MXL_MOCA_SOC_QUERY_PM_STATE_RSP_T socQueryPmStateRsp;
+ MXL_MOCA_SOC_GET_PM_EVENT_RSP_T socGetPmEventRsp;
+ MXL_MOCA_SOC_HOST_IF_READY_RSP_T socHostIfReadyRsp;
+ MXL_MOCA_SOC_FLOW_CREATE_OR_UPDATE_RSP_T socFlowCreateRsp;
+ MXL_MOCA_SOC_FLOW_CREATE_OR_UPDATE_RSP_T socFlowUpdateRsp;
+ MXL_MOCA_SOC_FLOW_DELETE_RSP_T socFlowDeleteRsp;
+ MXL_MOCA_SOC_FLOW_LIST_RSP_T socFlowListRsp;
+ MXL_MOCA_SOC_FLOW_QUERY_RSP_T socFlowQueryRsp;
+ MXL_MOCA_SOC_FLOW_STATS_RSP_T socFlowStatsRsp;
+ MXL_MOCA_SEC_PASSWORD_T socSecPassword;
+ MXL_MOCA_SOC_GET_SEC_PASSWD_RSP_T socGetSecPasswdRsp;
+ MXL_MOCA_SOC_GET_SEC_INFO_RSP_T socGetSecInfoRsp;
+ MXL_MOCA_SOC_GET_SEC_STATS_RSP_T socGetSecStatsRsp;
+ MXL_MOCA_SOC_SET_MULTICAST_CFG_RSP_T socSetMultiCastCfgRsp;
+ MXL_MOCA_SOC_SET_GET_TXPWR_VAR_RSP_T socSetGetTxPwrVarRsp;
+ MXL_MOCA_SOC_GET_ACTIVE_RLAPM_RSP_T socGetActiveRlapmRsp;
+ MXL_MOCA_SOC_GET_ACTIVE_SAPM_RSP_T socGetActiveSapmRsp;
+ MXL_MOCA_SOC_ENDET_STATUS_RSP_T socEndetStatusRsp;
+ MXL_MOCA_SOC_TEST_RSP_T socTestRsp;
+ MXL_MOCA_SOC_GET_SWITCH_STATS_RSP_T socGetSwitchStatsRsp;
+ MXL_MOCA_SOC_GET_SWITCH_CONFIG_RSP_T socGetSwitchConfigRsp;
+
+ MXL_MOCA_SOC_GET_NETWORK_NAME_REC_RSP_T socGetNetworkNameRecRsp;
+ MXL_MOCA_SOC_GET_NETWORK_NAME_PAYLOAD_RSP_T socGetNetworkNamePayloadRsp;
+ MXL_MOCA_SOC_ME_NETWORK_IE_PAYLOAD_TX_RSP_T socMeNetworkIePayloadTxRsp;
+ MXL_MOCA_SOC_ME_NETWORK_IE_PAYLOAD_RX_RSP_T socMeNetworkIePayloadRxRsp;
+ MXL_MOCA_SOC_ME_NETWORK_JOIN_RSP_T socMeNetworkJoinRsp;
+ MXL_MOCA_SOC_GET_TRAFFIC_PERMIT_STS_RSP_T socGetTrafficPermitStsRsp;
+ MXL_MOCA_SOC_GET_ETHER_TYPE_INFO_RSP_T socGetEtherTypeInfoRsp;
+
+ MXL_MOCA_SOC_NET_PROXY_TEST_MODE_CTRL_RSP_T socSendNetProxyTestModeCtrlRsp;
+
+ MXL_MOCA_SOC_RESET_SWITCH_CONFIG_RSP_T socResetSwitchConfigRsp;
+ MXL_MOCA_SOC_SET_SWITCH_TMO_RSP_T socSetSwitchTmoRsp;
+ MXL_MOCA_SOC_ENA_SWITCH_VLAN_CHECK_RSP_T socEnaSwitchVlanCheckRsp;
+ MXL_MOCA_SOC_DIS_SWITCH_VLAN_CHECK_RSP_T socDisSwitchVlanCheckRsp;
+ MXL_MOCA_SOC_ENA_SWITCH_VLAN_STRIP_RSP_T socEnaSwitchVlanStripRsp;
+ MXL_MOCA_SOC_DIS_SWITCH_VLAN_STRIP_RSP_T socDisSwitchVlanStripRsp;
+ MXL_MOCA_SOC_SET_SWITCH_VLAN_PVID_RSP_T socSetSwitchVlanPvidRsp;
+ MXL_MOCA_SOC_ADD_SWITCH_VLANID_RSP_T socAddSwitchVlanIdRsp;
+ MXL_MOCA_SOC_DEL_SWITCH_VLANID_RSP_T socDelSwitchVlanIdRsp;
+ MXL_MOCA_SOC_SET_SWITCH_MGMT_MAC_RSP_T socSetSwitchMgmtMacRsp;
+ MXL_MOCA_SOC_GET_MACDATA_STATS_RSP_T socGetMacDataStatsRsp;
+ MXL_MOCA_SOC_SET_SWITCH_PORT_CONFIG_RSP_T socSetSwitchConfigRsp;
+ MXL_MOCA_SOC_SET_BCN_POWER_RSP_T socSetBcnPowerRsp;
+ MXL_MOCA_SOC_GET_BCN_POWER_RSP_T socGetBcnPowerRsp;
+ MXL_MOCA_SOC_REQUEST_BCNPWR_PIE_RSP_T socReqBcnPowerPieRsp;
+ MXL_MOCA_SOC_SET_MPS_TRIGGER_RSP_T socSetMpsTriggerRsp;
+ MXL_MOCA_SOC_GET_MPS_REPORT_RSP_T socGetMpsReportRsp;
+ MXL_MOCA_SOC_GET_MPS_STATE_RSP_T socGetMpsStateRsp;
+ MXL_MOCA_SOC_GET_SEC_EP_PASSWORD_RSP_T socGetSecEpPasswordRsp;
+ MXL_MOCA_SOC_GET_EP_SEC_INFO_RSP_T socGetEpSecInfoRsp;
+ MXL_MOCA_SOC_NET_PROXY_PKT_RCV_RSP_T socSendNetProxyPktRsp;
+ MXL_MOCA_DRV_GET_CFG_AND_FW_DIR_RSP_T drvGetCfgAndFwDirRsp;
+ MXL_MOCA_DRV_GET_DAEMON_INFO_RSP_T drvGetDaemonInfoRsp;
+ MXL_MOCA_DRV_GET_CHIP_TYPE_RSP_T drvGetChipTypeRsp;
+ MXL_MOCA_DRV_GET_DBG_MEM_RSP_T drvGetDbgMemRsp;
+ MXL_MOCA_DRV_RD_MII_REG_RSP_T drvRwMiiRegRsp;
+ MXL_MOCA_SOC_GET_EPHY_STATS_RSP_T socGetEcbStatsRsp;
+
+ } uRsp;
+
+} MXL_MOCA_OP_RSP_T;
+
+typedef struct
+{
+ void* pParam1;
+ void* pParam2;
+ void* pParam3;
+} MXL_MOCA_CMD_PARAMS;
+
+/*****************************************************************************************
+ Global Variable Declarations
+ ****************************************************************************************/
+
+/*****************************************************************************************
+ Function Prototypes
+ ****************************************************************************************/
+
+#endif // __MXL_MOCA_SOC_CMD_H__
--
2.34.1
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