airco_comp.vhd

-- Extended Full Added
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY Ex_fadder IS
    PORT (
        a, b, sel, ci : IN STD_LOGIC;
        sum, co : OUT STD_LOGIC);
END Ex_fadder;

ARCHITECTURE structural OF Ex_fadder IS

    COMPONENT inver
        PORT (
            a : IN STD_LOGIC;
            y : OUT STD_LOGIC);
    END COMPONENT;

    COMPONENT mux21
        PORT (
            a, b, sel : IN STD_LOGIC;
            y : OUT STD_LOGIC);
    END COMPONENT;

    COMPONENT fadder
        PORT (
            a, b, ci : IN STD_LOGIC;
            sum, co : OUT STD_LOGIC);
    END COMPONENT;

    SIGNAL nb, s1 : STD_LOGIC;
BEGIN
    lbl1 : inver PORT MAP(a => b, y => nb);
    lbl2 : mux21 PORT MAP(a => b, b => nb, sel => sel, y => s1);
    lbl3 : fadder PORT MAP(a => a, b => s1, ci => ci, sum => sum, co => co);
END structural;



-- 2's complement 8-bit adder/substractor
-- A, B input operands
-- f = 0 compute C = A+B
-- f = 1 compute C = A-B
-- o overflow flag
-- z zero flag
-- the sign flag is C(7)! 
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY eight_bitadder IS
    PORT (
        A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        f : IN STD_LOGIC;
        C : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        o, z : OUT STD_LOGIC
    );
END eight_bitadder;

ARCHITECTURE structural OF eight_bitadder IS
    SIGNAL c_temp : STD_LOGIC;
    COMPONENT inver
        PORT (
            a : IN STD_LOGIC;
            y : OUT STD_LOGIC);
    END COMPONENT;
    COMPONENT mux21
        PORT (
            a, b, sel : IN STD_LOGIC;
            y : OUT STD_LOGIC);
    END COMPONENT;
    COMPONENT fadder
        PORT (
            a, b, ci : IN STD_LOGIC;
            sum, co : OUT STD_LOGIC);
    END COMPONENT;
BEGIN
    l_i0 : inver PORT MAP(a => B(0), y => C(0));
    l_i1 : inver PORT MAP(a => B(1), y => C(1));
    l_i2 : inver PORT MAP(a => B(2), y => C(2));
    l_i3 : inver PORT MAP(a => B(3), y => C(3));
    l_i4 : inver PORT MAP(a => B(4), y => C(4));
    l_i5 : inver PORT MAP(a => B(5), y => C(5));
    l_i6 : inver PORT MAP(a => B(6), y => C(6));
    l_i7 : inver PORT MAP(a => B(7), y => C(7));

    l_m0 : mux21 PORT MAP(a => C(0), b => B(0), sel => f, y => C(0));
    l_m1 : mux21 PORT MAP(a => C(1), b => B(1), sel => f, y => C(1));
    l_m2 : mux21 PORT MAP(a => C(2), b => B(2), sel => f, y => C(2));
    l_m3 : mux21 PORT MAP(a => C(3), b => B(3), sel => f, y => C(3));
    l_m4 : mux21 PORT MAP(a => C(4), b => B(4), sel => f, y => C(4));
    l_m5 : mux21 PORT MAP(a => C(5), b => B(5), sel => f, y => C(5));
    l_m6 : mux21 PORT MAP(a => C(6), b => B(6), sel => f, y => C(6));
    l_m7 : mux21 PORT MAP(a => C(7), b => B(7), sel => f, y => C(7));

    l_a7 : fadder PORT MAP(a => A(7), b => C(7), ci => f, sum => C(7), co => c_temp);
    l_a6 : fadder PORT MAP(a => A(6), b => C(6), ci => c_temp, sum => C(6), co => c_temp);
    l_a5 : fadder PORT MAP(a => A(5), b => C(5), ci => c_temp, sum => C(5), co => c_temp);
    l_a4 : fadder PORT MAP(a => A(4), b => C(4), ci => c_temp, sum => C(4), co => c_temp);
    l_a3 : fadder PORT MAP(a => A(3), b => C(3), ci => c_temp, sum => C(3), co => c_temp);
    l_a2 : fadder PORT MAP(a => A(2), b => C(2), ci => c_temp, sum => C(2), co => c_temp);
    l_a1 : fadder PORT MAP(a => A(1), b => C(1), ci => c_temp, sum => C(1), co => c_temp);
    l_a0 : fadder PORT MAP(a => A(0), b => C(0), ci => c_temp, sum => C(0), co => c_temp);
END structural;



-- A, B, C input operands (8-bit 2's complement!)
-- compute D = A - (B + C)
-- gz = 1 if D > 0
-- o overflow flag
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY add_comp IS
    PORT (
        A, B, C : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        gz, o : OUT STD_LOGIC
    );
END add_comp;

ARCHITECTURE structural OF add_comp IS

BEGIN

    -- ??
    -- ??
    -- ??

END structural;

-- airco_comp at structural level
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY airco_comp IS
    PORT (
        Tin : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        Tref : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        Td : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        c0 : OUT STD_LOGIC;
        c1 : OUT STD_LOGIC
    );
END airco_comp;

ARCHITECTURE structural OF airco_comp IS
    SIGNAL both_unsigned : STD_LOGIC;

    COMPONENT inver
        PORT (
            a : IN STD_LOGIC;
            y : OUT STD_LOGIC);
    END COMPONENT;

    COMPONENT mux21
        PORT (
            a, b, sel : IN STD_LOGIC;
            y : OUT STD_LOGIC);
    END COMPONENT;

    COMPONENT nor_2
        PORT (
            a, b : IN STD_LOGIC;
            y : OUT STD_LOGIC);
    END COMPONENT;
BEGIN

END structural;

airco_fsm.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity airco_fsm is
    port (clk:     in  std_logic;
          reset:   in  std_logic;
          Z:       in  std_logic;
          E:       in  std_logic;
          W:       in  std_logic;
          G:       in  std_logic;
          c0:      in  std_logic;
          c1:      in  std_logic;
          heat:    out std_logic;
          cool:    out std_logic;
          off:     out std_logic;
          service: out std_logic);
end airco_fsm;

architecture behaviour of airco_fsm is
    type airco_fsm_state is (AIRCO_OFF, COOLING, HEATING, BROKEN);
    signal state, new_state: airco_fsm_state;
begin
    l1: process (clk)
    begin
        if (clk'event and clk = '1') then
            state <= new_state;
        end if;
    end process;

    l2: process (state, c0, c1, Z, E, W, G)
    begin
        if (Z='0' OR E='0' OR W='0' OR G='0') then
            new_state <= BROKEN;
        elsif (c0='0') then
            new_state <= AIRCO_OFF;
        elsif (c1='1') then
            new_state <= COOLING;
        else
            new_state <= HEATING;
        end if;

        case state is
        when AIRCO_OFF =>
            heat    <= '0';
            cool    <= '0';
            off     <= '1';
            service <= '0';
        when COOLING =>
            heat    <= '0';
            cool    <= '1';
            off     <= '0';
            service <= '0';
        when HEATING =>
            heat    <= '1';
            cool    <= '0';
            off     <= '0';
            service <= '0';
        when BROKEN =>
            heat    <= '0';
            cool    <= '0';
            off     <= '0';
            service <= '1';
        end case;
    end process;
end behaviour;