Graphics AGX L2C Error Status (0x206140008 in Operation Triangulation)

l2c_sts.txt

The `chkdatecc` field was set during Operation Triangulation.

0x206140008:
b[63]:	rsvd_63			Reserved
b[62]:	cfgerren		Enable error register locking and asynchronous reporting when CfgErrESV is set.

b[61]:	chksnphit 		Deprecated
				(If set, check that snoops hit in L2C tag, and if they miss, log an error.
				If clear, trust the way info from AF and do not read the tags for snoops.)

b[60]:	chkdatecc   		If set, check data ECC, enable single bit error correction, and log status.
				If clear, do not check data ECC, don't correct errors, and don't log status.

b[59:57]: injdatratedbe		Rate at which double random ECC errors are injected.
				The rate is approximately (2^(2*InjDatRateDbe)) accesses.

b[56]: esvw1c			If set then the ESV and OvFlow bits are write-one-to-clear,
				a write of 1'b0 to an ESV bit will leave the state of the bit unchanged,
				a write of 1'b1 will leave the the value of the ESV bit 1'b0.
				If clear the ESV bits have normal write functionality.

b[55:53]: injdatratesbe		Rate at which single random ECC errors are injected.
				The rate is approximately(2^(2*InjDatRateSbe)) accesses.

b[52]: injdatrandomdbe		Enables random data double bit ECC error injection.

b[51]: injdupmultoneshot 	Deprecated
				(Enables duplicate tag multiple hit error injection.
				Cleared by hardware after injection occurs.
				HID8.DisAfEarlyFill should be set to 1 to make sure the injection occurs.)
				
b[50]: injtagmultoneshot 	Deprecated
				(Enables tag multiple hit error injection.
				Cleared by hardware after injection occurs.
				HID8.DisAfEarlyFill should be set to 1 to make sure the injection occurs.)

b[49]: injdatoneshot     	Enables one shot data ECC error injection.
				Cleared by hardware after injection occurs.
				HID8.DisAfEarlyFill should be set to 1 to make sure the injection occurs.

b[48]: injdatrandomsbe		Enables random data single bit ECC error injection.
b[47]: noaccessl2gnterren    	L2 should not send a core Gnt when soc_asc_noaccess is asserted.
b[46]: snpdatfillfwderren	Enable Parity detected in Core-to-Core snoop data fill fowarding.
b[45]: unexprsperren		Enable unexpected response error from AXI bus.
b[44]: dpcerren			Enable error register locking and asynchronous reporting when DpcErrESV is set.
b[43]: ramadrooren		Enable error register locking and asynchronous reporting when RamAdrOorESV is set.

b[42]: datpoisonlogen		Log Poisoned lines as DBEs.
				Default is off so that L1D parity errors which poison the L2 are not logged as DBEs.

b[41]: pioerren			Enable error register locking and asynchronous reporting when PioErrESV is set.
b[40]: snperren			Enable error register locking and asynchronous reporting when SnpErrESV is set.
b[39]: buserren			Enable error register locking and asynchronous reporting when BusErrESV is set.
b[38]: dupmulhiten		Enable error register locking and asynchronous reporting when DupMulHitESV is set.
b[37]: tagmulhiten		Enable error register locking and asynchronous reporting when TagMulHitESV is set.
b[36]: datdbeen			Enable error register locking and asynchronous reporting when DatDbeESV is set.
b[35]: datsbeovfen		Enable error register locking and asynchronous reporting when DatSbeOvfESV is set.
b[34]: datsbeen			Enable error register locking and asynchronous reporting when DatSbeESV is set.
b[33:32]: rsvd_33_32      	Reserved
b[31:16]: sbecnt		Count of single bit data ECC errors detected.
b[15]: noaccessl2gnterresv	L2 should not send a core Gnt when soc_asc_noaccess is asserted.
b[14]: snpdatfillfwderresv	Parity detected in Core-to-Core snoop data fill fowarding.
b[13]: unexprsperresv		XPM detects an unexpected response error from AXI bus.
b[12]: dpcerresv		DPC detected an error.  In Cayman this is only used for ADCLK calibration errors.
b[11]: ramadrooresv		A request to L2C as RAM address region was out of range of the enabled RAM size.

b[10]: cfgerresv		Configuration error.
				This bit can be set based on an illegal combination of
				HID5.CrdPrbMaxM1, HID5.CrdPrbCpuRsvd, and CrdPrbAxiSlaveExtraRsvd,
				or setting HID5.CrdPrbMaxM1 or HID5.AwtMax to a value less than it's reset value.
				When this bit is set, the L2C_ERR_ADR and L2C_ERR_INF registers are not updated.

b[9]: pioerresv			A PIO request from AF either hit a hole in the address map,
				or used an unsupported (wrapping) command,
				or specified an illegal size,
				or had any byte enables not set in a write's range.
				The type of error is specified in L2CERRINF[17:16].

b[8]: snperresv			A snoop from AF missed in L2C tags.
b[7]: buserresv			A response from AF indicated an error.
b[6]: dupmulhitesv		A hit was detected in multiple ways in the L1D duplicate tags.
b[5]: tagmulhitesv		A hit was detected in multiple ways in the L2C tags.
b[4]: datdbeesv			A double bit data ECC error was detected.
b[3]: datsbeovfesv		The SbeCnt has overflowed.
b[2]: datsbeesv			A single bit data ECC error was detected.

b[1]: ovflowunc			Uncorrectable error overflow: will be set if an uncorrectable error is detected
				while any uncorrectable error is locked.

b[0]: ovflowcor			Correctable error overflow: will be set if a correctable error is detected
				while any error is locked or when a locked correctable error gets
				overwritten by an uncorrectable error.
				An error is considered locked if both its ESV and EN bits are set.
				Data single bit errors are correctable, all other errors are uncorrectable.