Graphics AGX L2C Error Status (0x206140008 in Operation Triangulation)

l2c_sts.txt

0x206140008:
rsvd_63
cfgerren		Enable error register locking and asynch reporting when CfgErrESV is set
chksnphit 		Deprecated

chkdatecc   		If set check data ECC, enable single bit error correction, log status.  If clear
			do not check data ECC, don't correct errors, don't log status.

injdatratedbe		Rate at which double random ECC errors are injected. The rate is approximately
			(2^(2*InjDatRateDbe)) accesses  

esvw1c			If set then the ESV and OvFlow bits are write-one-to-clear, a write of 
			1'b0 to an ESV bit will leave the state of the bit unchanged, a write of 1'b1 will leave
			the the value of the ESV bit 1'b0.  If clear the ESV bits have normal write functionality.

injdatratesbe		Rate at which single random ECC errors are injected. The rate is approximately
			(2^(2*InjDatRateSbe)) accesses  
injdatrandomdbe		Enables random data double bit ECC error injection
injdupmultoneshot 	Deprecated
injtagmultoneshot 	Deprecated

injdatoneshot     	Enables one shot data ECC error injection.  Cleared by hardware after injection
			occurs.  HID8.DisAfEarlyFill should be set to 1 to
			make sure the injection occurs.

injdatrandomsbe		Enables random data single bit ECC error injection.
noaccessl2gnterren    
snpdatfillfwderren	Enable Parity detected in Core-to-Core snoop data fill fowarding
unexprsperren		Enable unexpected response error from AXI bus
dpcerren		Enable error register locking and asynch reporting when DpcErrESV is set 
ramadrooren		Enable error register locking and asynch reporting when RamAdrOorESV is set 
datpoisonlogen		Log Poisoned lines as DBEs. Default is off so that L1D parity errors which poison the L2 are not logged as DBEs
pioerren		Enable error register locking and asynch reporting when PioErrESV is set
snperren		Enable error register locking and asynch reporting when SnpErrESV is set
buserren		Enable error register locking and asynch reporting when BusErrESV is set
dupmulhiten		Enable error register locking and asynch reporting when DupMulHitESV is set
tagmulhiten		Enable error register locking and asynch reporting when TagMulHitESV is set
datdbeen		Enable error register locking and asynch reporting when DatDbeESV is set
datsbeovfen		Enable error register locking and asynch reporting when DatSbeOvfESV is set
datsbeen		Enable error register locking and asynch reporting when DatSbeESV is set
rsvd_33_32      
sbecnt			Count of single bit data ECC errors detected
noaccessl2gnterresv	L2 should not send a core Gnt when soc_asc_noaccess is asserted.
snpdatfillfwderresv	Parity detected in Core-to-Core snoop data fill fowarding
unexprsperresv		XPM detects an unexpected response error from AXI bus
dpcerresv		DPC detected an error.  In Cayman this is only used for ADCLK calibration errors.
ramadrooresv		A reqeust to L2C as RAM address region was out of range of the enabled RAM size

cfgerresv		Configuration error.  This bit can be set based on an illegal combination of HID5.CrdPrbMaxM1, 
			HID5.CrdPrbCpuRsvd, and CrdPrbAxiSlaveExtraRsvd, or setting HID5.CrdPrbMaxM1 or HID5.AwtMax to 
			a value less than it's reset value.  When this bit is set, the L2C_ERR_ADR and 
			L2C_ERR_INF registers are not updated.

pioerresv		A PIO request from AF either hit a hole in the address map, or used an unsupported (wrapping)
			command, or specified an illegal size, or had any byte enables not
			set in a write's range.  The type of error is specified in L2CERRINF[17:16]

snperresv		A snoop from AF missed in L2C tags
buserresv		A response from AF indicated error
dupmulhitesv		A hit was detected in multiple ways in the L1D duplicate tags
tagmulhitesv		A hit was detected in mulitple ways in the L2C tags
datdbeesv		A double bit data ECC error was detected
datsbeovfesv		The SbeCnt has overflowed
datsbeesv		A single bit data ECC error was detected

ovflowunc		Uncorrectable error overflow: will be set if an uncorrectable error is detected
			while any uncorrectable error is locked.

ovflowcor		Correctable error overflow: will be set if a correctable error is detected while any error is\
			locked or when a locked correctable error gets overwritten by an
			uncorrectable error.  An error is considered locked if both its ESV and EN bits
			are set.  Data single bit errors are correctable, all other erros are uncorrectable.