pure verilog litex wishbone slave?

target.py

    # wishbone slave
    myslave =  Instance("myslave", i_clk_i = ClockSignal(), i_rst_i = ResetSignal(), 
      i_cyc = wb_cyc_i,
      i_stb = wb_stb_i,
      i_we = wb_we_i,
      i_adr = wb_addr_i,
      i_dat_w = wb_data_i,
      i_sel = wb_sel_i,
      wb_stall_o,
      o_ack = wb_ack_o,
      o_dat_r = wb_data_o)
    soc.specials += myslave
    soc.platform.add_source("slave.v")
    soc.bus.add_slave(name="myslave", slave=myslave, region=SoCRegion(
           origin = 0x2000_0000,
           size   = 32*4,
     ))