MIPS Assembler OP/FUNC codes and register encodings

codes.py

rtypes = [
  # List of all R-type instructions.
  "sll", "srl", "sra", "sllv", "srlv", "srav",  # shifts
  "jr", "jalr",                                 # jumps
  "syscall", "break",                           # system
  "mfhi", "mthi", "mflo", "mtlo",               # move to
  "mult", "multu", "div", "divu",               # mult/div
  "add", "addu", "sub", "subu",                 # add/sub
  "and", "or", "xor", "nor",                    # bitwise
  "slt", "sltu"                                 # set less than
]

shifts = [
  "sll", "srl", "sra", "sllv", "srlv", "srav"
]

jumps = [
  "j", "jal", "jr", "jalr", "beq", "bne"
]

op_codes = {
  # Fill in mapping from instruction to its opcode.
  "r-type"    : dec_to_bin(0,  6),
  "bltz"      : dec_to_bin(1,  6),
  "bgez"      : dec_to_bin(1,  6),
  "j"         : dec_to_bin(2,  6),
  "jal"       : dec_to_bin(3,  6),
  "beq"       : dec_to_bin(4,  6),
  "bne"       : dec_to_bin(5,  6),
  "blez"      : dec_to_bin(6,  6),
  "bgtz"      : dec_to_bin(7,  6),
  "addi"      : dec_to_bin(8,  6),
  "addiu"     : dec_to_bin(9,  6),
  "slti"      : dec_to_bin(10, 6),
  "stliu"     : dec_to_bin(11, 6),
  "andi"      : dec_to_bin(12, 6),
  "ori"       : dec_to_bin(13, 6),
  "xori"      : dec_to_bin(14, 6),
  "lui"       : dec_to_bin(15, 6),
  "mfc0"      : dec_to_bin(16, 6),
  "mtc0"      : dec_to_bin(16, 6),
  "f-type"    : dec_to_bin(17, 6),
  "bclf"      : dec_to_bin(17, 6),
  "bclt"      : dec_to_bin(17, 6),
  "mul"       : dec_to_bin(28, 6),
  "lb"        : dec_to_bin(32, 6),
  "lh"        : dec_to_bin(33, 6),
  "lw"        : dec_to_bin(35, 6),
  "lbu"       : dec_to_bin(36, 6),
  "lhu"       : dec_to_bin(37, 6),
  "sb"        : dec_to_bin(40, 6),
  "sh"        : dec_to_bin(41, 6),
  "sw"        : dec_to_bin(43, 6),
  "lwcl"      : dec_to_bin(49, 6),
  "swcl"      : dec_to_bin(56, 6)
}

function_codes = {
  # Fill in function codes.
  "sll"       : dec_to_bin(0,  6),
  "srl"       : dec_to_bin(2,  6),
  "sra"       : dec_to_bin(3,  6),
  "sllv"      : dec_to_bin(4,  6),
  "srlv"      : dec_to_bin(6,  6),
  "srav"      : dec_to_bin(7,  6),
  "jr"        : dec_to_bin(8,  6),
  "jalr"      : dec_to_bin(9,  6),
  "syscall"   : dec_to_bin(12, 6),
  "break"     : dec_to_bin(13, 6),
  "mfhi"      : dec_to_bin(16, 6),
  "mthi"      : dec_to_bin(17, 6),
  "mflo"      : dec_to_bin(18, 6),
  "mtlo"      : dec_to_bin(19, 6),
  "mult"      : dec_to_bin(24, 6),
  "multu"     : dec_to_bin(25, 6),
  "div"       : dec_to_bin(26, 6),
  "divu"      : dec_to_bin(27, 6),
  "add"       : dec_to_bin(32, 6),
  "addu"      : dec_to_bin(33, 6),
  "sub"       : dec_to_bin(34, 6),
  "subu"      : dec_to_bin(35, 6),
  "and"       : dec_to_bin(36, 6),
  "or"        : dec_to_bin(37, 6),
  "xor"       : dec_to_bin(38, 6),
  "nor"       : dec_to_bin(39, 6),
  "slt"       : dec_to_bin(42, 6),
  "sltu"      : dec_to_bin(43, 6)
}

registers = {
  '$zero' : dec_to_bin(0, 5),
  '$at' : dec_to_bin(1, 5),
  '$v0' : dec_to_bin(2, 5),
  '$v1' : dec_to_bin(3, 5),

  '$a0' : dec_to_bin(4, 5),
  '$a1' : dec_to_bin(5, 5),
  '$a2' : dec_to_bin(6, 5),
  '$a3' : dec_to_bin(7, 5),

  '$t0' : dec_to_bin(8, 5),
  '$t1' : dec_to_bin(9, 5),
  '$t2' : dec_to_bin(10, 5),
  '$t3' : dec_to_bin(11, 5),
  '$t4' : dec_to_bin(12, 5),
  '$t5' : dec_to_bin(13, 5),
  '$t6' : dec_to_bin(14, 5),
  '$t7' : dec_to_bin(15, 5),
  '$s0' : dec_to_bin(16, 5),
  '$s1' : dec_to_bin(17, 5),
  '$s2' : dec_to_bin(18, 5),
  '$s3' : dec_to_bin(19, 5),
  '$s4' : dec_to_bin(20, 5),
  '$s5' : dec_to_bin(21, 5),
  '$s6' : dec_to_bin(22, 5),
  '$s7' : dec_to_bin(23, 5),
  '$t8' : dec_to_bin(24, 5),
  '$t9' : dec_to_bin(25, 5),
  '$k0' : dec_to_bin(26, 5),
  '$k1' : dec_to_bin(27, 5),
  '$gp' : dec_to_bin(28, 5),
  '$sp' : dec_to_bin(29, 5),
  '$fp' : dec_to_bin(30, 5),
  '$ra' : dec_to_bin(31, 5),
  '$r0' : dec_to_bin(0, 5),
  '$r1' : dec_to_bin(1, 5),
  '$r2' : dec_to_bin(2, 5),
  '$r3' : dec_to_bin(3, 5),
  '$r4' : dec_to_bin(4, 5),
  '$r5' : dec_to_bin(5, 5),
  '$r6' : dec_to_bin(6, 5),
  '$r7' : dec_to_bin(7, 5),
  '$r8' : dec_to_bin(8, 5),
  '$r9' : dec_to_bin(9, 5),
  '$r10' : dec_to_bin(10, 5),
  '$r11' : dec_to_bin(11, 5),
  '$r12' : dec_to_bin(12, 5),
  '$r13' : dec_to_bin(13, 5),
  '$r14' : dec_to_bin(14, 5),
  '$r15' : dec_to_bin(15, 5),
  '$r16' : dec_to_bin(16, 5),
  '$r17' : dec_to_bin(17, 5),
  '$r18' : dec_to_bin(18, 5),
  '$r19' : dec_to_bin(19, 5),
  '$r20' : dec_to_bin(20, 5),
  '$r21' : dec_to_bin(21, 5),
  '$r22' : dec_to_bin(22, 5),
  '$r23' : dec_to_bin(23, 5),
  '$r24' : dec_to_bin(24, 5),
  '$r25' : dec_to_bin(25, 5),
  '$r26' : dec_to_bin(26, 5),
  '$r27' : dec_to_bin(27, 5),
  '$r28' : dec_to_bin(28, 5),
  '$r29' : dec_to_bin(29, 5),
  '$r30' : dec_to_bin(30, 5),
  '$r31' : dec_to_bin(31, 5)
}