Created
February 12, 2022 18:05
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static int bcm54210pe_adjfine(struct ptp_clock_info *info, long scaled_ppm)
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#define NSE_DPPL_NCO_6_REG 0x087F | |
#define NSE_DPPL_NCO_1_LSB_REG 0x0873 | |
#define NSE_DPPL_NCO_1_MSB_REG 0x0874 | |
#define SHADOW_REG_CONTROL 0x085C | |
#define SHADOW_REG_LOAD 0x085D | |
u64 adj; | |
u16 lo, hi; | |
struct bcm54210pe_ptp *ptp = container_of(info, struct bcm54210pe_ptp, caps); | |
struct phy_device *phydev = ptp->chosen->phydev; | |
hi = (adj >> 16); | |
lo = adj & 0xffff; | |
mutex_lock(&ptp->timeset_lock); | |
phy_lock_mdio_bus(phydev); | |
__bcm_phy_write_exp(phydev, NSE_DPPL_NCO_6_REG, 0xE000); | |
__bcm_phy_write_exp(phydev, NSE_DPPL_NCO_1_LSB_REG, lo); | |
__bcm_phy_write_exp(phydev, NSE_DPPL_NCO_1_MSB_REG, hi); | |
//Enable shadow register | |
__bcm_phy_write_exp(phydev, SHADOW_REG_CONTROL, 0x0000); | |
__bcm_phy_write_exp(phydev, SHADOW_REG_LOAD, 0x0340); | |
//Force sync | |
__bcm_phy_write_exp(phydev, NSE_DPPL_NCO_6_REG, 0xE020); | |
phy_unlock_mdio_bus(phydev); | |
mutex_unlock(&ptp->timeset_lock); | |
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