Boilterplate for VHDL IP

VHDL_boilter_plate.vhd

-------------------------------------------------------------------------------
-- Title      : Arithmetic Logic Unit
-- Project    : PROCESSEUR MONO-CYCLE: SIMULATION VHDL
-------------------------------------------------------------------------------
-- File       : arithmetic_logic_unit.vhd
-- Author     : Lucas GRELAUD <[email protected]>
-- Company    : ESIEA (Student)
-- Created    : 2022-03-29
-- Standard   : VHDL'93
-------------------------------------------------------------------------------
-- Description: Simple ALU design for a 32 bit processor.
-------------------------------------------------------------------------------
LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;

Entity Name is
  Generic (  
    -- generic params,
    -- generic params
  ); 
  Port    (     
    -- port,
    -- port
  );
end Name;

Architecture RTL of Name is
  -- constant;
  -- signal;
  -- signal-
  begin
  
  -- RTL instructions

  ProcessName: process(Input1, Input2) -- The sensibility list should have all input
    -- variables
    begin
      --process instructions
  end ProcessName;
end RTL;