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[79]HELLO! BOOT0 is starting!
[82]BOOT0 commit : 749c1f9a-dirty
[85]set pll start
[87]periph0 has been enabled
[90]set pll end
[92][pmu]: bus read error
[95][pmu]: bus read error
[97]PMU: AXP2202
[105]vaild para:8 select dram para0
[109]board init ok
@macromorgan
macromorgan / bootlog
Created December 16, 2024 22:02
RG40XXV
[121]HELLO! BOOT0 is starting!
[124]BOOT0 commit : 749c1f9a-dirty
[128]set pll start
[130]periph0 has been enabled
[134]set pll end
[135][pmu]: bus read error
[138][pmu]: bus read error
[141]PMU: AXP2202
[144]dram return write ok
[146]board init ok
@macromorgan
macromorgan / Bootlog
Created December 16, 2024 16:49
RG34XX
[105]HELLO! BOOT0 is starting!
[108]BOOT0 commit : 749c1f9a-dirty
[111]set pll start
[114]periph0 has been enabled
[117]set pll end
[119][pmu]: bus read error
[122][pmu]: bus read error
[124]PMU: AXP2202
[133]vaild para:8 select dram para0
[136]board init ok
@macromorgan
macromorgan / 0000-cover-letter.patch
Last active November 5, 2024 19:35
RGxx3 Misc Fixes
From b6b53dc73e3eee903cf1de745266138d7a3327d8 Mon Sep 17 00:00:00 2001
From: Chris Morgan <[email protected]>
Date: Thu, 31 Oct 2024 09:00:12 -0500
Subject: [PATCH 00/10] Misc Fixes for RGxx3
This is a series of misc fixes for the RGxx3, mostly aimed at reducing
power consumption.
Chris Morgan (10):
arm64: dts: rockchip: Add idle-states for rk356x
@macromorgan
macromorgan / 0000-cover-letter.patch
Created September 6, 2024 20:17
RGxx3 U-Boot Updates for 2024-09-06
From 21af290030161a3f8c8d6576dba1c5c3da3aca02 Mon Sep 17 00:00:00 2001
From: Chris Morgan <[email protected]>
Date: Fri, 6 Sep 2024 15:11:57 -0500
Subject: [PATCH 0/3] Anbernic RGxx3 Bootloader Fixes
Update the Anbernic RGxx3 "device" to use upstream device-trees,
add logic to detect a different vdd_cpu regulator, and implement a
fix to allow the panel auto-detection to run when using mainline
A-TF.
/dts-v1/;
/memreserve/ 0x0000000048000000 0x0000000001000000;
/ {
interrupt-parent = <0x01>;
#address-cells = <0x02>;
#size-cells = <0x02>;
model = "sun50iw9";
compatible = "allwinner,h616\0arm,sun50iw9p1";
@macromorgan
macromorgan / bootlog
Created May 20, 2024 15:56
Anbernic RG35XXSP Data
[37]HELLO! BOOT0 is starting!
[40]BOOT0 commit : 749c1f9a-dirty
[43]set pll start
[45]periph0 has been enabled
[48]set pll end
[50][pmu]: bus read error
[53][pmu]: bus read error
[55]PMU: AXP2202
[63]vaild para:8 select dram para0
[67]board init ok
From 1340ad97d35cf4ea7b82be650530ac48bdd0ac1b Mon Sep 17 00:00:00 2001
From: Chris Morgan <[email protected]>
Date: Fri, 10 May 2024 10:43:01 -0500
Subject: [PATCH 1/4] dt-bindings: pwm: Add binding for Allwinner
D1/T113-S3/R329/H616 PWM
Allwinner's D1, T113-S3, R329, and H616 SoCs have a new pwm
controller witch is different from the previous pwm-sun4i.
The D1 and T113 are identical in terms of peripherals,
@macromorgan
macromorgan / clk_summary
Created May 9, 2024 15:52
RG28XX Boot Information
clock enable_cnt prepare_cnt rate accuracy phase
----------------------------------------------------------------------------------------
pcf8563-clkout 0 0 32768 0 0
pll_periph0div25m 0 0 25000000 0 0
ephy_25m 0 0 25000000 0 0
hoscdiv32k 0 0 32768 0 0
hosc32k 0 0 32768 0 0
losc_out 0 0 32768 0 0
osc48m 0 0 48000000 0 0
osc48md4 0 0 12000000 0 0
@macromorgan
macromorgan / sun50i-h700-anbernic-rg28xx.dts
Created May 7, 2024 15:41
Dumps from Anbernic RG28XX
/dts-v1/;
/memreserve/ 0x0000000048000000 0x0000000001000000;
/ {
interrupt-parent = <0x01>;
#address-cells = <0x02>;
#size-cells = <0x02>;
model = "sun50iw9";
compatible = "allwinner,h616\0arm,sun50iw9p1";