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@denniskupec
denniskupec / rules.txt
Created June 5, 2021 23:17
KiCad DRC rules for JLCPCB, 4-layer PCB
(version 1)
# 4-layer, 1oz copper
(rule "Minimum Trace Width and Spacing (inner layer)"
(constraint track_width (min 5mil))
(constraint clearance (min 5mil))
(layer inner)
(condition "A.Type == 'track'"))
(rule "Minimum Trace Width and Spacing (outer layer)"
RUBY_GC_HEAP_FREE_SLOTS=600000
RUBY_GC_HEAP_GROWTH_FACTOR=1.25
RUBY_GC_HEAP_GROWTH_MAX_SLOTS=300000
RUBY_GC_HEAP_INIT_SLOTS=600000
RUBY_GC_HEAP_OLDOBJECT_LIMIT_FACTOR=1.3
RUBY_GC_MALLOC_LIMIT=64000000
RUBY_GC_OLDMALLOC_LIMIT=64000000
RUBY_HEAP_FREE_MIN=12500
RUBY_HEAP_SLOTS_GROWTH_FACTOR=1
RUBY_HEAP_SLOTS_INCREMENT=100000
@xuwei-k
xuwei-k / Main.scala
Last active December 29, 2015 21:59
Scala2.11 awesome!
import scala.sys._
object Main{
val a = b + "foo"
val b = "b"
private val c = 0
private var d = 1
println(d)
@ryandotsmith
ryandotsmith / hack-reactor.md
Last active November 24, 2022 07:01
Hack Reactor Talk

Tales From a Heroku User

Here are some things I have learned along the way.

Last Updated: 2013-02-08

Original Audience: Hack Reactor

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