fusesoc2sc.py

#!/usr/bin/env python3

import argparse
import siliconcompiler as sc
import os

def fusesoc2edam():

    from fusesoc.config import Config
    from fusesoc.coremanager import CoreManager
    from fusesoc.edalizer import Edalizer
    from fusesoc.librarymanager import Library
    from fusesoc.vlnv import Vlnv

    cm = CoreManager(Config())

    cm.add_library(Library("zerosoc", '.'))
    #Add hw last because we override some cores from opentitan there
    cm.add_library(Library("hw", 'hw'))

    core = cm.get_core(Vlnv("zeroasic::zerosoc"))

    edam = Edalizer(
        toplevel=core.name,
        flags={"tool": "icestorm", "target" : "icebreaker"},
        core_manager=cm,
        work_root=".",
    ).run()

    return edam

def edam2sc(edam):
    chip = sc.Chip()

    # Prevent us from erroring out on lint warnings during import
    chip.set('relax', 'true')
    chip.set('quiet', 'true')

    #FIXME: Add proper support for defines
    cur_dir = os.path.dirname(os.path.realpath(__file__))
    chip.add('define', f'MEM_ROOT={cur_dir}')

    #Flowarg and tech arg needs to be set first
    chip.set('flowarg', 'sv', ['true'])
    chip.target('fpgaflow_ice40up5k-sg48')

    #Automatically set sv flowarg when systemVerilogSource files are found?
    for f in edam.get('files'):
        if f.get('is_include_file'):
            chip.add('idir', os.path.dirname(f['name']))
        elif not 'file_type' in f:
            print(f['name'] + " has no file type")
        elif f['file_type'] in ['PCF']:
            chip.add('constraint', f['name'])
        else: #FIXME: More sanity checks here
            chip.add('source', f['name'])

    for name,p in edam.get('parameters').items():
        if p['paramtype'] == 'vlogdefine':
            #This is a bit of a hack. Probably copy some code from Edalize here
            val = p.get('default', '')
            if p['datatype'] == 'str':
                val = f'="{val}"'
            elif p['datatype'] == 'bool':
                val = ''
            else:
                print("FIXME")
                exit(1)
            chip.add('define', name+val)

    chip.set('design', edam['toplevel'])

    return chip

if __name__ == '__main__':
    edam = fusesoc2edam()
    chip = edam2sc(edam)
    chip.run()
    chip.summary()