This gist discusses implementation of a Debug Module (DM) primarily per RISC-V Debug Specification v0.11. The core ideas, though, apply to Debug Specification v0.13. Information presented here come from various sources, but mostly from Debug Specs, riscv-isa-sim and from reverse engineering e200_opensource. Relevant source of information is also riscv-openocd.
RISC-V Foundation established a debug task group to propose and standardize mechanisms for external debugging of RISC-V (RV) cores. This effort resulted in drafting a RISC-V External Debug Supprt specification, early [v0.1