valid_store.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

library unisim;
use unisim.vcomponents.all;

entity valid_store is
   port (
      clock    : in  std_logic;
      rst      : in  std_logic;

      wen      : in  std_logic;
      addr     : in  std_logic_vector(11 downto 0);
      dout     : out std_logic
   );
end entity;

architecture arch of valid_store is
   signal rst_s, din_s, dout_s, wen_s : std_logic_vector(63 downto 0) := (others => '0');
   
   function slv_to_int(X : std_logic_vector) return integer is
   begin
      return to_integer(unsigned(X));
   end slv_to_int;
begin
   dram_gen : for i in 63 downto 0 generate
      RAM64X1D_i : RAM64X1D
      generic map (
         INIT => X"0000000000000000") -- Initial contents of RAM
      port map (
         DPO => open,     -- Read-only 1-bit data output
         SPO => dout_s(i),     -- R/W 1-bit data output
         A0 => addr(6),       -- R/W address[0] input bit
         A1 => addr(7),       -- R/W address[1] input bit
         A2 => addr(8),       -- R/W address[2] input bit
         A3 => addr(9),       -- R/W address[3] input bit
         A4 => addr(10),       -- R/W address[4] input bit
         A5 => addr(11),       -- R/W address[5] input bit
         D => din_s(i),         -- Write 1-bit data input
         DPRA0 => '0', -- Read-only address[0] input bit
         DPRA1 => '0', -- Read-only address[1] input bit
         DPRA2 => '0', -- Read-only address[2] input bit
         DPRA3 => '0', -- Read-only address[3] input bit
         DPRA4 => '0', -- Read-only address[4] input bit
         DPRA5 => '0', -- Read-only address[5] input bit
         WCLK => clock,   -- Write clock input
         WE => wen_s(i)        -- Write enable input
      );
   end generate dram_gen;

   process (clock) begin
      if rising_edge(clock) then
         if (rst = '1') then
            rst_s    <= (others => '1');
         else
            rst_s(slv_to_int(addr(11 downto 6))) <= '0';
            wen_s    <= (others => '0');
            dout     <= dout_s(slv_to_int(addr(5 downto 0)));

            if (rst_s(slv_to_int(addr(11 downto 6))) = '1') then
               din_s    <= (others => '0');
               wen_s    <= (others => '1');
               dout     <= '0';
            elsif (wen = '1') then
               wen_s(slv_to_int(addr(5 downto 0))) <= '1';
               din_s(slv_to_int(addr(5 downto 0))) <= '1';
            end if;
         end if;
      end if;
   end process;

end architecture;