ghdl/docker issue #11

Makefile

mkfile_path := $(abspath $(lastword ${MAKEFILE_LIST}))
my_dir := $(dir ${mkfile_path})
base := $(shell basename $$(pwd))
basedir := $(shell dirname $$(pwd))
docker_path :=  -v /${basedir}://work
docker_path_all :=  -v /$(shell pwd)://work
docker_opts  = --rm -it -w //work --user $(shell id -u)
#docker_opts += ghdl/ghdl:buster-gcc-7.4.0-mcode
#docker_opts += ghdl/ghdl:buster-gcc-8.3.0-1
docker_opts += ghdl/vunit:gcc-master-1
test_threads = 4

default: run

run:
	docker run ${docker_path} ${docker_opts} sh -c 'VUNIT_SIMULATOR=ghdl; python3 ${base}/run.py -p ${test_threads} --fail-fast ${T};'

run.py

from os.path import join, dirname
from vunit import VUnit
import subprocess
import os

# Create VUnit instance by parsing command line arguments
ui = VUnit.from_argv()

ui.add_osvvm()
ui.add_verification_components()

ui.add_source_files_from_csv(join(dirname(__file__), "vunit_files.csv"))

ui.set_sim_option("enable_coverage", True)


# Run vunit function
try:
    ui.main()
except SystemExit as exc:
    retval = exc.code


if retval == 0:
    srcs = join(dirname(__file__), "src/rtl/*.vhd").lstrip("/")
    subprocess.call(["gcovr", "-r", os.getcwd(), "-f", srcs])

exit(retval)

serial_io.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity serial_io is
	port(
		-- generic signals
		clk  : in  std_logic;
		rst  : in  std_logic;
		-- input data
		io_i : in  std_logic;
		-- output-data
		io_o : out std_logic
	);
end serial_io;

architecture Behavioral of serial_io is
	signal r : std_logic;
begin

	proc : process(clk, rst) is
	begin
		if rst = '1' then
			r    <= '1';
			io_o <= '1';
		elsif rising_edge(clk) then
			r    <= io_i;
			io_o <= r;
		end if;
	end process proc;

end Behavioral;

tb_serial_io.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;

library osvvm;
use osvvm.RandomPkg.all;

entity tb_serial_io is
	generic(
		runner_cfg : string);
end entity;

architecture tb of tb_serial_io is
	constant clk_period : time := 1 sec / (1000 * 1000);

	signal rst : std_logic := '1';
	signal clk : std_logic := '0';

	shared variable rnd_stimuli, rnd_expected : RandomPType;

	constant uart_slv_bfm : uart_slave_t   := new_uart_slave(initial_baud_rate => 57600,
	                                                         data_length       => 8);
	constant uart_slv     : stream_slave_t := as_stream(uart_slv_bfm);

	constant uart_ma_bfm : uart_master_t   := new_uart_master(initial_baud_rate => 57600);
	constant uart_ma     : stream_master_t := as_stream(uart_ma_bfm);

	signal io_i, io_o : std_logic;

begin

	main : process
		variable rnd8 : std_logic_vector(7 downto 0);

	begin
		test_runner_setup(runner, runner_cfg);

		wait until rising_edge(clk);
		wait until rising_edge(clk);
		wait until rising_edge(clk);
		rst <= '0';
		wait until rising_edge(clk);
		wait until rising_edge(clk);

		-- Initialize to same seed to get same sequence
		rnd_stimuli.InitSeed(rnd_stimuli'instance_name);
		rnd_expected.InitSeed(rnd_stimuli'instance_name);

		while test_suite loop
			if run("test_send_one_byte") then
				rnd8 := rnd_stimuli.RandSlv(8);
				push_stream(net, uart_ma, rnd8);
				check_stream(net, uart_slv, rnd8(7 downto 0));
			end if;
		end loop;

		test_runner_cleanup(runner);
		wait;
	end process;
	test_runner_watchdog(runner, 10 ms);

	clk <= not clk after (clk_period / 2);

	dut : entity work.serial_io
		port map(
			clk  => clk,
			rst  => rst,
			io_i => io_i,
			io_o => io_o
		);

	uart_master_bfm : entity vunit_lib.uart_master
		generic map(
			uart => uart_ma_bfm)
		port map(
			tx => io_i);

	uart_slave_bfm : entity vunit_lib.uart_slave
		generic map(
			uart => uart_slv_bfm)
		port map(
			rx => io_o);

end architecture;

vunit_files.csv