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claude ported pinctrl drivers from linux to barebox
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| From ee00e8132064c3038638c03f74cb24d50895ae83 Mon Sep 17 00:00:00 2001 | |
| From: Sohaib Mohamed <sohaib.amhmd@gmail.com> | |
| Date: Mon, 9 Mar 2026 01:33:31 +0100 | |
| Subject: [PATCH 1/2] pinctrl: original copy from linux | |
| Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> | |
| --- | |
| drivers/pinctrl/Kconfig | 1 + | |
| drivers/pinctrl/Makefile | 1 + | |
| drivers/pinctrl/meson/Kconfig | 93 + | |
| drivers/pinctrl/meson/Makefile | 15 + | |
| drivers/pinctrl/meson/pinctrl-amlogic-a4.c | 1109 ++++++++++++ | |
| drivers/pinctrl/meson/pinctrl-amlogic-c3.c | 1108 ++++++++++++ | |
| drivers/pinctrl/meson/pinctrl-amlogic-t7.c | 1611 +++++++++++++++++ | |
| drivers/pinctrl/meson/pinctrl-meson-a1.c | 940 ++++++++++ | |
| drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | 121 ++ | |
| drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h | 62 + | |
| drivers/pinctrl/meson/pinctrl-meson-axg.c | 1095 +++++++++++ | |
| drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1454 +++++++++++++++ | |
| drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 914 ++++++++++ | |
| drivers/pinctrl/meson/pinctrl-meson-gxl.c | 885 +++++++++ | |
| drivers/pinctrl/meson/pinctrl-meson-s4.c | 1234 +++++++++++++ | |
| drivers/pinctrl/meson/pinctrl-meson.c | 772 ++++++++ | |
| drivers/pinctrl/meson/pinctrl-meson.h | 183 ++ | |
| drivers/pinctrl/meson/pinctrl-meson8-pmx.c | 105 ++ | |
| drivers/pinctrl/meson/pinctrl-meson8-pmx.h | 42 + | |
| drivers/pinctrl/meson/pinctrl-meson8.c | 1136 ++++++++++++ | |
| drivers/pinctrl/meson/pinctrl-meson8b.c | 992 ++++++++++ | |
| include/pinctrl.h | 3 + | |
| 22 files changed, 13876 insertions(+) | |
| create mode 100644 drivers/pinctrl/meson/Kconfig | |
| create mode 100644 drivers/pinctrl/meson/Makefile | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-amlogic-a4.c | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-amlogic-c3.c | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-amlogic-t7.c | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson-a1.c | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.c | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gxl.c | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson-s4.c | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson8-pmx.c | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson8-pmx.h | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson8.c | |
| create mode 100644 drivers/pinctrl/meson/pinctrl-meson8b.c | |
| diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig | |
| index 1d237db106..5f50360a34 100644 | |
| --- a/drivers/pinctrl/Kconfig | |
| +++ b/drivers/pinctrl/Kconfig | |
| @@ -112,6 +112,7 @@ config PINCTRL_STM32 | |
| Pinmux and GPIO controller found on STM32 family | |
| source "drivers/pinctrl/sunxi/Kconfig" | |
| +source "drivers/pinctrl/meson/Kconfig" | |
| endif | |
| endmenu | |
| diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile | |
| index 3bc718d355..daa6133de4 100644 | |
| --- a/drivers/pinctrl/Makefile | |
| +++ b/drivers/pinctrl/Makefile | |
| @@ -17,3 +17,4 @@ obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o | |
| obj-$(CONFIG_ARCH_MVEBU) += mvebu/ | |
| obj-$(CONFIG_ARCH_SUNXI) += sunxi/ | |
| +obj-$(CONFIG_PINCTRL_MESON) += meson/ | |
| diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig | |
| new file mode 100644 | |
| index 0000000000..0315e224bc | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/Kconfig | |
| @@ -0,0 +1,93 @@ | |
| +# SPDX-License-Identifier: GPL-2.0-only | |
| +menuconfig PINCTRL_MESON | |
| + tristate "Amlogic SoC pinctrl drivers" | |
| + depends on ARCH_MESON || COMPILE_TEST | |
| + depends on OF | |
| + default ARCH_MESON | |
| + select PINMUX | |
| + select PINCONF | |
| + select GENERIC_PINCONF | |
| + select GPIOLIB | |
| + select OF_GPIO | |
| + select REGMAP_MMIO | |
| + | |
| +if PINCTRL_MESON | |
| + | |
| +config PINCTRL_MESON8 | |
| + bool "Meson 8 SoC pinctrl driver" | |
| + depends on ARM | |
| + select PINCTRL_MESON8_PMX | |
| + default ARCH_MESON | |
| + | |
| +config PINCTRL_MESON8B | |
| + bool "Meson 8b SoC pinctrl driver" | |
| + depends on ARM | |
| + select PINCTRL_MESON8_PMX | |
| + default ARCH_MESON | |
| + | |
| +config PINCTRL_MESON_GXBB | |
| + tristate "Meson gxbb SoC pinctrl driver" | |
| + depends on ARM64 | |
| + select PINCTRL_MESON8_PMX | |
| + default ARCH_MESON | |
| + | |
| +config PINCTRL_MESON_GXL | |
| + tristate "Meson gxl SoC pinctrl driver" | |
| + depends on ARM64 | |
| + select PINCTRL_MESON8_PMX | |
| + default ARCH_MESON | |
| + | |
| +config PINCTRL_MESON8_PMX | |
| + tristate | |
| + | |
| +config PINCTRL_MESON_AXG | |
| + tristate "Meson axg Soc pinctrl driver" | |
| + depends on ARM64 | |
| + select PINCTRL_MESON_AXG_PMX | |
| + default ARCH_MESON | |
| + | |
| +config PINCTRL_MESON_AXG_PMX | |
| + tristate | |
| + | |
| +config PINCTRL_MESON_G12A | |
| + tristate "Meson g12a Soc pinctrl driver" | |
| + depends on ARM64 | |
| + select PINCTRL_MESON_AXG_PMX | |
| + default ARCH_MESON | |
| + | |
| +config PINCTRL_MESON_A1 | |
| + tristate "Meson a1 Soc pinctrl driver" | |
| + depends on ARM64 | |
| + select PINCTRL_MESON_AXG_PMX | |
| + default ARCH_MESON | |
| + | |
| +config PINCTRL_MESON_S4 | |
| + tristate "Meson s4 Soc pinctrl driver" | |
| + depends on ARM64 | |
| + select PINCTRL_MESON_AXG_PMX | |
| + default ARCH_MESON | |
| + | |
| +config PINCTRL_AMLOGIC_A4 | |
| + bool "AMLOGIC pincontrol" | |
| + depends on ARM64 | |
| + default ARCH_MESON | |
| + help | |
| + This is the driver for the pin controller found on Amlogic SoCs. | |
| + | |
| + This driver is simplify subsequent support for new amlogic SoCs, | |
| + to support new Amlogic SoCs, only need to add the corresponding dts file, | |
| + no additional binding header files or C file are added. | |
| + | |
| +config PINCTRL_AMLOGIC_C3 | |
| + tristate "Amlogic C3 SoC pinctrl driver" | |
| + depends on ARM64 | |
| + select PINCTRL_MESON_AXG_PMX | |
| + default ARCH_MESON | |
| + | |
| +config PINCTRL_AMLOGIC_T7 | |
| + tristate "Amlogic T7 SoC pinctrl driver" | |
| + depends on ARM64 | |
| + select PINCTRL_MESON_AXG_PMX | |
| + default ARCH_MESON | |
| + | |
| +endif | |
| diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile | |
| new file mode 100644 | |
| index 0000000000..c92a65a833 | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/Makefile | |
| @@ -0,0 +1,15 @@ | |
| +# SPDX-License-Identifier: GPL-2.0-only | |
| +obj-$(CONFIG_PINCTRL_MESON) += pinctrl-meson.o | |
| +obj-$(CONFIG_PINCTRL_MESON8_PMX) += pinctrl-meson8-pmx.o | |
| +obj-$(CONFIG_PINCTRL_MESON8) += pinctrl-meson8.o | |
| +obj-$(CONFIG_PINCTRL_MESON8B) += pinctrl-meson8b.o | |
| +obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o | |
| +obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o | |
| +obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o | |
| +obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o | |
| +obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o | |
| +obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o | |
| +obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o | |
| +obj-$(CONFIG_PINCTRL_AMLOGIC_A4) += pinctrl-amlogic-a4.o | |
| +obj-$(CONFIG_PINCTRL_AMLOGIC_C3) += pinctrl-amlogic-c3.o | |
| +obj-$(CONFIG_PINCTRL_AMLOGIC_T7) += pinctrl-amlogic-t7.o | |
| diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c | |
| new file mode 100644 | |
| index 0000000000..d9e3a8d593 | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c | |
| @@ -0,0 +1,1109 @@ | |
| +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) | |
| +/* | |
| + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. | |
| + * Author: Xianwei Zhao <xianwei.zhao@amlogic.com> | |
| + */ | |
| + | |
| +#include <linux/err.h> | |
| +#include <linux/gpio/driver.h> | |
| +#include <linux/init.h> | |
| +#include <linux/io.h> | |
| +#include <linux/module.h> | |
| +#include <linux/of.h> | |
| +#include <linux/of_address.h> | |
| +#include <linux/platform_device.h> | |
| +#include <linux/regmap.h> | |
| +#include <linux/seq_file.h> | |
| +#include <linux/slab.h> | |
| +#include <linux/string_helpers.h> | |
| + | |
| +#include <linux/pinctrl/consumer.h> | |
| +#include <linux/pinctrl/pinconf.h> | |
| +#include <linux/pinctrl/pinctrl.h> | |
| +#include <linux/pinctrl/pinmux.h> | |
| +#include <dt-bindings/pinctrl/amlogic,pinctrl.h> | |
| + | |
| +#include "../core.h" | |
| +#include "../pinconf.h" | |
| + | |
| +#define gpio_chip_to_bank(chip) \ | |
| + container_of(chip, struct aml_gpio_bank, gpio_chip) | |
| + | |
| +#define AML_REG_PULLEN 0 | |
| +#define AML_REG_PULL 1 | |
| +#define AML_REG_DIR 2 | |
| +#define AML_REG_OUT 3 | |
| +#define AML_REG_IN 4 | |
| +#define AML_REG_DS 5 | |
| +#define AML_NUM_REG 6 | |
| + | |
| +enum aml_pinconf_drv { | |
| + PINCONF_DRV_500UA, | |
| + PINCONF_DRV_2500UA, | |
| + PINCONF_DRV_3000UA, | |
| + PINCONF_DRV_4000UA, | |
| +}; | |
| + | |
| +struct aml_pio_control { | |
| + u32 gpio_offset; | |
| + u32 reg_offset[AML_NUM_REG]; | |
| + u32 bit_offset[AML_NUM_REG]; | |
| +}; | |
| + | |
| +/* | |
| + * partial bank(subordinate) pins mux config use other bank(main) mux registgers | |
| + * m_bank_id: the main bank which pin_id from 0, but register bit not from bit 0 | |
| + * m_bit_offs: bit offset the main bank mux register | |
| + * sid: start pin_id of subordinate bank | |
| + * eid: end pin_id of subordinate bank | |
| + */ | |
| +struct multi_mux { | |
| + unsigned int m_bank_id; | |
| + unsigned int m_bit_offs; | |
| + unsigned int sid; | |
| + unsigned int eid; | |
| +}; | |
| + | |
| +struct aml_pctl_data { | |
| + unsigned int number; | |
| + const struct multi_mux *p_mux; | |
| +}; | |
| + | |
| +struct aml_pmx_func { | |
| + const char *name; | |
| + const char **groups; | |
| + unsigned int ngroups; | |
| +}; | |
| + | |
| +struct aml_pctl_group { | |
| + const char *name; | |
| + unsigned int npins; | |
| + unsigned int *pins; | |
| + unsigned int *func; | |
| +}; | |
| + | |
| +struct aml_gpio_bank { | |
| + struct gpio_chip gpio_chip; | |
| + struct aml_pio_control pc; | |
| + u32 bank_id; | |
| + u32 mux_bit_offs; | |
| + unsigned int pin_base; | |
| + struct regmap *reg_mux; | |
| + struct regmap *reg_gpio; | |
| + struct regmap *reg_ds; | |
| + const struct multi_mux *p_mux; | |
| +}; | |
| + | |
| +struct aml_pinctrl { | |
| + struct device *dev; | |
| + struct pinctrl_dev *pctl; | |
| + struct aml_gpio_bank *banks; | |
| + int nbanks; | |
| + struct aml_pmx_func *functions; | |
| + int nfunctions; | |
| + struct aml_pctl_group *groups; | |
| + int ngroups; | |
| + | |
| + const struct aml_pctl_data *data; | |
| +}; | |
| + | |
| +static const unsigned int aml_bit_strides[AML_NUM_REG] = { | |
| + 1, 1, 1, 1, 1, 2 | |
| +}; | |
| + | |
| +static const unsigned int aml_def_regoffs[AML_NUM_REG] = { | |
| + 3, 4, 2, 1, 0, 7 | |
| +}; | |
| + | |
| +static const char *aml_bank_name[31] = { | |
| +"GPIOA", "GPIOB", "GPIOC", "GPIOD", "GPIOE", "GPIOF", "GPIOG", | |
| +"GPIOH", "GPIOI", "GPIOJ", "GPIOK", "GPIOL", "GPIOM", "GPION", | |
| +"GPIOO", "GPIOP", "GPIOQ", "GPIOR", "GPIOS", "GPIOT", "GPIOU", | |
| +"GPIOV", "GPIOW", "GPIOX", "GPIOY", "GPIOZ", "GPIODV", "GPIOAO", | |
| +"GPIOCC", "TEST_N", "ANALOG" | |
| +}; | |
| + | |
| +static const struct multi_mux multi_mux_s7[] = { | |
| + { | |
| + .m_bank_id = AMLOGIC_GPIO_CC, | |
| + .m_bit_offs = 24, | |
| + .sid = (AMLOGIC_GPIO_X << 8) + 16, | |
| + .eid = (AMLOGIC_GPIO_X << 8) + 19, | |
| + }, | |
| +}; | |
| + | |
| +static const struct aml_pctl_data s7_priv_data = { | |
| + .number = ARRAY_SIZE(multi_mux_s7), | |
| + .p_mux = multi_mux_s7, | |
| +}; | |
| + | |
| +static const struct multi_mux multi_mux_s6[] = { | |
| + { | |
| + .m_bank_id = AMLOGIC_GPIO_CC, | |
| + .m_bit_offs = 24, | |
| + .sid = (AMLOGIC_GPIO_X << 8) + 16, | |
| + .eid = (AMLOGIC_GPIO_X << 8) + 19, | |
| + }, { | |
| + .m_bank_id = AMLOGIC_GPIO_F, | |
| + .m_bit_offs = 4, | |
| + .sid = (AMLOGIC_GPIO_D << 8) + 6, | |
| + .eid = (AMLOGIC_GPIO_D << 8) + 6, | |
| + }, | |
| +}; | |
| + | |
| +static const struct aml_pctl_data s6_priv_data = { | |
| + .number = ARRAY_SIZE(multi_mux_s6), | |
| + .p_mux = multi_mux_s6, | |
| +}; | |
| + | |
| +static int aml_pmx_calc_reg_and_offset(struct pinctrl_gpio_range *range, | |
| + unsigned int pin, unsigned int *reg, | |
| + unsigned int *offset) | |
| +{ | |
| + unsigned int shift; | |
| + | |
| + shift = ((pin - range->pin_base) << 2) + *offset; | |
| + *reg = (shift / 32) * 4; | |
| + *offset = shift % 32; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int aml_pctl_set_function(struct aml_pinctrl *info, | |
| + struct pinctrl_gpio_range *range, | |
| + int pin_id, int func) | |
| +{ | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| + unsigned int shift; | |
| + int reg; | |
| + int i; | |
| + unsigned int offset = bank->mux_bit_offs; | |
| + const struct multi_mux *p_mux; | |
| + | |
| + /* peculiar mux reg set */ | |
| + if (bank->p_mux) { | |
| + p_mux = bank->p_mux; | |
| + if (pin_id >= p_mux->sid && pin_id <= p_mux->eid) { | |
| + bank = NULL; | |
| + for (i = 0; i < info->nbanks; i++) { | |
| + if (info->banks[i].bank_id == p_mux->m_bank_id) { | |
| + bank = &info->banks[i]; | |
| + break; | |
| + } | |
| + } | |
| + | |
| + if (!bank || !bank->reg_mux) | |
| + return -EINVAL; | |
| + | |
| + shift = (pin_id - p_mux->sid) << 2; | |
| + reg = (shift / 32) * 4; | |
| + offset = shift % 32; | |
| + return regmap_update_bits(bank->reg_mux, reg, | |
| + 0xf << offset, (func & 0xf) << offset); | |
| + } | |
| + } | |
| + | |
| + /* normal mux reg set */ | |
| + if (!bank->reg_mux) | |
| + return 0; | |
| + | |
| + aml_pmx_calc_reg_and_offset(range, pin_id, ®, &offset); | |
| + return regmap_update_bits(bank->reg_mux, reg, | |
| + 0xf << offset, (func & 0xf) << offset); | |
| +} | |
| + | |
| +static int aml_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
| +{ | |
| + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| + | |
| + return info->nfunctions; | |
| +} | |
| + | |
| +static const char *aml_pmx_get_fname(struct pinctrl_dev *pctldev, | |
| + unsigned int selector) | |
| +{ | |
| + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| + | |
| + return info->functions[selector].name; | |
| +} | |
| + | |
| +static int aml_pmx_get_groups(struct pinctrl_dev *pctldev, | |
| + unsigned int selector, | |
| + const char * const **grps, | |
| + unsigned * const ngrps) | |
| +{ | |
| + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| + | |
| + *grps = info->functions[selector].groups; | |
| + *ngrps = info->functions[selector].ngroups; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int aml_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned int fselector, | |
| + unsigned int group_id) | |
| +{ | |
| + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| + struct aml_pctl_group *group = &info->groups[group_id]; | |
| + struct pinctrl_gpio_range *range; | |
| + int i; | |
| + | |
| + for (i = 0; i < group->npins; i++) { | |
| + range = pinctrl_find_gpio_range_from_pin(pctldev, group->pins[i]); | |
| + aml_pctl_set_function(info, range, group->pins[i], group->func[i]); | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int aml_pmx_request_gpio(struct pinctrl_dev *pctldev, | |
| + struct pinctrl_gpio_range *range, | |
| + unsigned int pin) | |
| +{ | |
| + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| + | |
| + return aml_pctl_set_function(info, range, pin, 0); | |
| +} | |
| + | |
| +static const struct pinmux_ops aml_pmx_ops = { | |
| + .set_mux = aml_pmx_set_mux, | |
| + .get_functions_count = aml_pmx_get_funcs_count, | |
| + .get_function_name = aml_pmx_get_fname, | |
| + .get_function_groups = aml_pmx_get_groups, | |
| + .gpio_request_enable = aml_pmx_request_gpio, | |
| +}; | |
| + | |
| +static int aml_calc_reg_and_bit(struct pinctrl_gpio_range *range, | |
| + unsigned int pin, | |
| + unsigned int reg_type, | |
| + unsigned int *reg, unsigned int *bit) | |
| +{ | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| + | |
| + *bit = (pin - range->pin_base) * aml_bit_strides[reg_type] | |
| + + bank->pc.bit_offset[reg_type]; | |
| + *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; | |
| + *bit &= 0x1f; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int aml_pinconf_get_pull(struct aml_pinctrl *info, unsigned int pin) | |
| +{ | |
| + struct pinctrl_gpio_range *range = | |
| + pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| + unsigned int reg, bit, val; | |
| + int ret, conf; | |
| + | |
| + aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); | |
| + | |
| + ret = regmap_read(bank->reg_gpio, reg, &val); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + if (!(val & BIT(bit))) { | |
| + conf = PIN_CONFIG_BIAS_DISABLE; | |
| + } else { | |
| + aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); | |
| + | |
| + ret = regmap_read(bank->reg_gpio, reg, &val); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + if (val & BIT(bit)) | |
| + conf = PIN_CONFIG_BIAS_PULL_UP; | |
| + else | |
| + conf = PIN_CONFIG_BIAS_PULL_DOWN; | |
| + } | |
| + | |
| + return conf; | |
| +} | |
| + | |
| +static int aml_pinconf_get_drive_strength(struct aml_pinctrl *info, | |
| + unsigned int pin, | |
| + u16 *drive_strength_ua) | |
| +{ | |
| + struct pinctrl_gpio_range *range = | |
| + pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| + unsigned int reg, bit; | |
| + unsigned int val; | |
| + int ret; | |
| + | |
| + if (!bank->reg_ds) | |
| + return -EOPNOTSUPP; | |
| + | |
| + aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); | |
| + ret = regmap_read(bank->reg_ds, reg, &val); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + switch ((val >> bit) & 0x3) { | |
| + case PINCONF_DRV_500UA: | |
| + *drive_strength_ua = 500; | |
| + break; | |
| + case PINCONF_DRV_2500UA: | |
| + *drive_strength_ua = 2500; | |
| + break; | |
| + case PINCONF_DRV_3000UA: | |
| + *drive_strength_ua = 3000; | |
| + break; | |
| + case PINCONF_DRV_4000UA: | |
| + *drive_strength_ua = 4000; | |
| + break; | |
| + default: | |
| + return -EINVAL; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int aml_pinconf_get_gpio_bit(struct aml_pinctrl *info, | |
| + unsigned int pin, | |
| + unsigned int reg_type) | |
| +{ | |
| + struct pinctrl_gpio_range *range = | |
| + pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| + unsigned int reg, bit, val; | |
| + int ret; | |
| + | |
| + aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); | |
| + ret = regmap_read(bank->reg_gpio, reg, &val); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + return BIT(bit) & val ? 1 : 0; | |
| +} | |
| + | |
| +static int aml_pinconf_get_output(struct aml_pinctrl *info, | |
| + unsigned int pin) | |
| +{ | |
| + int ret = aml_pinconf_get_gpio_bit(info, pin, AML_REG_DIR); | |
| + | |
| + if (ret < 0) | |
| + return ret; | |
| + | |
| + return !ret; | |
| +} | |
| + | |
| +static int aml_pinconf_get_drive(struct aml_pinctrl *info, | |
| + unsigned int pin) | |
| +{ | |
| + return aml_pinconf_get_gpio_bit(info, pin, AML_REG_OUT); | |
| +} | |
| + | |
| +static int aml_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, | |
| + unsigned long *config) | |
| +{ | |
| + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); | |
| + enum pin_config_param param = pinconf_to_config_param(*config); | |
| + u16 arg; | |
| + int ret; | |
| + | |
| + switch (param) { | |
| + case PIN_CONFIG_BIAS_DISABLE: | |
| + case PIN_CONFIG_BIAS_PULL_DOWN: | |
| + case PIN_CONFIG_BIAS_PULL_UP: | |
| + if (aml_pinconf_get_pull(info, pin) == param) | |
| + arg = 1; | |
| + else | |
| + return -EINVAL; | |
| + break; | |
| + case PIN_CONFIG_DRIVE_STRENGTH_UA: | |
| + ret = aml_pinconf_get_drive_strength(info, pin, &arg); | |
| + if (ret) | |
| + return ret; | |
| + break; | |
| + case PIN_CONFIG_OUTPUT_ENABLE: | |
| + ret = aml_pinconf_get_output(info, pin); | |
| + if (ret <= 0) | |
| + return -EINVAL; | |
| + arg = 1; | |
| + break; | |
| + case PIN_CONFIG_LEVEL: | |
| + ret = aml_pinconf_get_output(info, pin); | |
| + if (ret <= 0) | |
| + return -EINVAL; | |
| + | |
| + ret = aml_pinconf_get_drive(info, pin); | |
| + if (ret < 0) | |
| + return -EINVAL; | |
| + | |
| + arg = ret; | |
| + break; | |
| + | |
| + default: | |
| + return -ENOTSUPP; | |
| + } | |
| + | |
| + *config = pinconf_to_config_packed(param, arg); | |
| + dev_dbg(info->dev, "pinconf for pin %u is %lu\n", pin, *config); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int aml_pinconf_disable_bias(struct aml_pinctrl *info, | |
| + unsigned int pin) | |
| +{ | |
| + struct pinctrl_gpio_range *range = | |
| + pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| + unsigned int reg, bit = 0; | |
| + | |
| + aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); | |
| + | |
| + return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); | |
| +} | |
| + | |
| +static int aml_pinconf_enable_bias(struct aml_pinctrl *info, unsigned int pin, | |
| + bool pull_up) | |
| +{ | |
| + struct pinctrl_gpio_range *range = | |
| + pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| + unsigned int reg, bit, val = 0; | |
| + int ret; | |
| + | |
| + aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); | |
| + if (pull_up) | |
| + val = BIT(bit); | |
| + | |
| + ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), val); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); | |
| + return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); | |
| +} | |
| + | |
| +static int aml_pinconf_set_drive_strength(struct aml_pinctrl *info, | |
| + unsigned int pin, | |
| + u16 drive_strength_ua) | |
| +{ | |
| + struct pinctrl_gpio_range *range = | |
| + pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| + unsigned int reg, bit, ds_val; | |
| + | |
| + if (!bank->reg_ds) { | |
| + dev_err(info->dev, "drive-strength not supported\n"); | |
| + return -EOPNOTSUPP; | |
| + } | |
| + | |
| + aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); | |
| + | |
| + if (drive_strength_ua <= 500) { | |
| + ds_val = PINCONF_DRV_500UA; | |
| + } else if (drive_strength_ua <= 2500) { | |
| + ds_val = PINCONF_DRV_2500UA; | |
| + } else if (drive_strength_ua <= 3000) { | |
| + ds_val = PINCONF_DRV_3000UA; | |
| + } else if (drive_strength_ua <= 4000) { | |
| + ds_val = PINCONF_DRV_4000UA; | |
| + } else { | |
| + dev_warn_once(info->dev, | |
| + "pin %u: invalid drive-strength : %d , default to 4mA\n", | |
| + pin, drive_strength_ua); | |
| + ds_val = PINCONF_DRV_4000UA; | |
| + } | |
| + | |
| + return regmap_update_bits(bank->reg_ds, reg, 0x3 << bit, ds_val << bit); | |
| +} | |
| + | |
| +static int aml_pinconf_set_gpio_bit(struct aml_pinctrl *info, | |
| + unsigned int pin, | |
| + unsigned int reg_type, | |
| + bool arg) | |
| +{ | |
| + struct pinctrl_gpio_range *range = | |
| + pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| + unsigned int reg, bit; | |
| + | |
| + aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); | |
| + return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), | |
| + arg ? BIT(bit) : 0); | |
| +} | |
| + | |
| +static int aml_pinconf_set_output(struct aml_pinctrl *info, | |
| + unsigned int pin, | |
| + bool out) | |
| +{ | |
| + return aml_pinconf_set_gpio_bit(info, pin, AML_REG_DIR, !out); | |
| +} | |
| + | |
| +static int aml_pinconf_set_drive(struct aml_pinctrl *info, | |
| + unsigned int pin, | |
| + bool high) | |
| +{ | |
| + return aml_pinconf_set_gpio_bit(info, pin, AML_REG_OUT, high); | |
| +} | |
| + | |
| +static int aml_pinconf_set_output_drive(struct aml_pinctrl *info, | |
| + unsigned int pin, | |
| + bool high) | |
| +{ | |
| + int ret; | |
| + | |
| + ret = aml_pinconf_set_output(info, pin, true); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + return aml_pinconf_set_drive(info, pin, high); | |
| +} | |
| + | |
| +static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, | |
| + unsigned long *configs, unsigned int num_configs) | |
| +{ | |
| + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); | |
| + enum pin_config_param param; | |
| + unsigned int arg = 0; | |
| + int i, ret; | |
| + | |
| + for (i = 0; i < num_configs; i++) { | |
| + param = pinconf_to_config_param(configs[i]); | |
| + | |
| + switch (param) { | |
| + case PIN_CONFIG_DRIVE_STRENGTH_UA: | |
| + case PIN_CONFIG_OUTPUT_ENABLE: | |
| + case PIN_CONFIG_LEVEL: | |
| + arg = pinconf_to_config_argument(configs[i]); | |
| + break; | |
| + | |
| + default: | |
| + break; | |
| + } | |
| + | |
| + switch (param) { | |
| + case PIN_CONFIG_BIAS_DISABLE: | |
| + ret = aml_pinconf_disable_bias(info, pin); | |
| + break; | |
| + case PIN_CONFIG_BIAS_PULL_UP: | |
| + ret = aml_pinconf_enable_bias(info, pin, true); | |
| + break; | |
| + case PIN_CONFIG_BIAS_PULL_DOWN: | |
| + ret = aml_pinconf_enable_bias(info, pin, false); | |
| + break; | |
| + case PIN_CONFIG_DRIVE_STRENGTH_UA: | |
| + ret = aml_pinconf_set_drive_strength(info, pin, arg); | |
| + break; | |
| + case PIN_CONFIG_OUTPUT_ENABLE: | |
| + ret = aml_pinconf_set_output(info, pin, arg); | |
| + break; | |
| + case PIN_CONFIG_LEVEL: | |
| + ret = aml_pinconf_set_output_drive(info, pin, arg); | |
| + break; | |
| + default: | |
| + ret = -ENOTSUPP; | |
| + } | |
| + | |
| + if (ret) | |
| + return ret; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int aml_pinconf_group_set(struct pinctrl_dev *pcdev, | |
| + unsigned int num_group, | |
| + unsigned long *configs, | |
| + unsigned int num_configs) | |
| +{ | |
| + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); | |
| + int i; | |
| + | |
| + for (i = 0; i < info->groups[num_group].npins; i++) { | |
| + aml_pinconf_set(pcdev, info->groups[num_group].pins[i], configs, | |
| + num_configs); | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int aml_pinconf_group_get(struct pinctrl_dev *pcdev, | |
| + unsigned int group, unsigned long *config) | |
| +{ | |
| + return -EOPNOTSUPP; | |
| +} | |
| + | |
| +static const struct pinconf_ops aml_pinconf_ops = { | |
| + .pin_config_get = aml_pinconf_get, | |
| + .pin_config_set = aml_pinconf_set, | |
| + .pin_config_group_get = aml_pinconf_group_get, | |
| + .pin_config_group_set = aml_pinconf_group_set, | |
| + .is_generic = true, | |
| +}; | |
| + | |
| +static int aml_get_groups_count(struct pinctrl_dev *pctldev) | |
| +{ | |
| + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| + | |
| + return info->ngroups; | |
| +} | |
| + | |
| +static const char *aml_get_group_name(struct pinctrl_dev *pctldev, | |
| + unsigned int selector) | |
| +{ | |
| + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| + | |
| + return info->groups[selector].name; | |
| +} | |
| + | |
| +static int aml_get_group_pins(struct pinctrl_dev *pctldev, | |
| + unsigned int selector, const unsigned int **pins, | |
| + unsigned int *npins) | |
| +{ | |
| + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| + | |
| + if (selector >= info->ngroups) | |
| + return -EINVAL; | |
| + | |
| + *pins = info->groups[selector].pins; | |
| + *npins = info->groups[selector].npins; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static void aml_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, | |
| + unsigned int offset) | |
| +{ | |
| + seq_printf(s, " %s", dev_name(pcdev->dev)); | |
| +} | |
| + | |
| +static const struct pinctrl_ops aml_pctrl_ops = { | |
| + .get_groups_count = aml_get_groups_count, | |
| + .get_group_name = aml_get_group_name, | |
| + .get_group_pins = aml_get_group_pins, | |
| + .dt_node_to_map = pinconf_generic_dt_node_to_map_pinmux, | |
| + .dt_free_map = pinconf_generic_dt_free_map, | |
| + .pin_dbg_show = aml_pin_dbg_show, | |
| +}; | |
| + | |
| +static int aml_pctl_parse_functions(struct device_node *np, | |
| + struct aml_pinctrl *info, u32 index, | |
| + int *grp_index) | |
| +{ | |
| + struct device *dev = info->dev; | |
| + struct aml_pmx_func *func; | |
| + struct aml_pctl_group *grp; | |
| + int ret, i; | |
| + | |
| + func = &info->functions[index]; | |
| + func->name = np->name; | |
| + func->ngroups = of_get_child_count(np); | |
| + if (func->ngroups == 0) | |
| + return dev_err_probe(dev, -EINVAL, "No groups defined\n"); | |
| + | |
| + func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); | |
| + if (!func->groups) | |
| + return -ENOMEM; | |
| + | |
| + i = 0; | |
| + for_each_child_of_node_scoped(np, child) { | |
| + func->groups[i++] = child->name; | |
| + grp = &info->groups[*grp_index]; | |
| + grp->name = child->name; | |
| + *grp_index += 1; | |
| + ret = pinconf_generic_parse_dt_pinmux(child, dev, &grp->pins, | |
| + &grp->func, &grp->npins); | |
| + if (ret) { | |
| + dev_err(dev, "function :%s, groups:%s fail\n", func->name, child->name); | |
| + return ret; | |
| + } | |
| + } | |
| + dev_dbg(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static u32 aml_bank_pins(struct device_node *np) | |
| +{ | |
| + struct of_phandle_args of_args; | |
| + | |
| + if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, | |
| + 0, &of_args)) | |
| + return 0; | |
| + else | |
| + return of_args.args[2]; | |
| +} | |
| + | |
| +static int aml_bank_number(struct device_node *np) | |
| +{ | |
| + struct of_phandle_args of_args; | |
| + | |
| + if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, | |
| + 0, &of_args)) | |
| + return -EINVAL; | |
| + else | |
| + return of_args.args[1] >> 8; | |
| +} | |
| + | |
| +static unsigned int aml_count_pins(struct device_node *np) | |
| +{ | |
| + struct device_node *child; | |
| + unsigned int pins = 0; | |
| + | |
| + for_each_child_of_node(np, child) { | |
| + if (of_property_read_bool(child, "gpio-controller")) | |
| + pins += aml_bank_pins(child); | |
| + } | |
| + | |
| + return pins; | |
| +} | |
| + | |
| +/* | |
| + * A pinctrl device contains two types of nodes. The one named GPIO | |
| + * bank which includes gpio-controller property. The other one named | |
| + * function which includes one or more pin groups. The pin group | |
| + * include pinmux property(global index in pinctrl dev, and mux vlaue | |
| + * in mux reg) and pin configuration properties. | |
| + */ | |
| +static void aml_pctl_dt_child_count(struct aml_pinctrl *info, | |
| + struct device_node *np) | |
| +{ | |
| + struct device_node *child; | |
| + | |
| + for_each_child_of_node(np, child) { | |
| + if (of_property_read_bool(child, "gpio-controller")) { | |
| + info->nbanks++; | |
| + } else { | |
| + info->nfunctions++; | |
| + info->ngroups += of_get_child_count(child); | |
| + } | |
| + } | |
| +} | |
| + | |
| +static struct regmap *aml_map_resource(struct device *dev, unsigned int id, | |
| + struct device_node *node, char *name) | |
| +{ | |
| + struct resource res; | |
| + void __iomem *base; | |
| + int i; | |
| + | |
| + struct regmap_config aml_regmap_config = { | |
| + .reg_bits = 32, | |
| + .val_bits = 32, | |
| + .reg_stride = 4, | |
| + }; | |
| + | |
| + i = of_property_match_string(node, "reg-names", name); | |
| + if (i < 0) | |
| + return NULL; | |
| + if (of_address_to_resource(node, i, &res)) | |
| + return NULL; | |
| + base = devm_ioremap_resource(dev, &res); | |
| + if (IS_ERR(base)) | |
| + return ERR_CAST(base); | |
| + | |
| + aml_regmap_config.max_register = resource_size(&res) - 4; | |
| + aml_regmap_config.name = devm_kasprintf(dev, GFP_KERNEL, | |
| + "%s-%s", aml_bank_name[id], name); | |
| + if (!aml_regmap_config.name) | |
| + return ERR_PTR(-ENOMEM); | |
| + | |
| + return devm_regmap_init_mmio(dev, base, &aml_regmap_config); | |
| +} | |
| + | |
| +static inline int aml_gpio_calc_reg_and_bit(struct aml_gpio_bank *bank, | |
| + unsigned int reg_type, | |
| + unsigned int gpio, | |
| + unsigned int *reg, | |
| + unsigned int *bit) | |
| +{ | |
| + *bit = gpio * aml_bit_strides[reg_type] + bank->pc.bit_offset[reg_type]; | |
| + *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; | |
| + *bit &= 0x1f; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int aml_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) | |
| +{ | |
| + struct aml_gpio_bank *bank = gpiochip_get_data(chip); | |
| + unsigned int bit, reg, val; | |
| + int ret; | |
| + | |
| + aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); | |
| + | |
| + ret = regmap_read(bank->reg_gpio, reg, &val); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + return BIT(bit) & val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; | |
| +} | |
| + | |
| +static int aml_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) | |
| +{ | |
| + struct aml_gpio_bank *bank = gpiochip_get_data(chip); | |
| + unsigned int bit, reg; | |
| + | |
| + aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); | |
| + | |
| + return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); | |
| +} | |
| + | |
| +static int aml_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, | |
| + int value) | |
| +{ | |
| + struct aml_gpio_bank *bank = gpiochip_get_data(chip); | |
| + unsigned int bit, reg; | |
| + int ret; | |
| + | |
| + aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); | |
| + ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); | |
| + if (ret < 0) | |
| + return ret; | |
| + | |
| + aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); | |
| + | |
| + return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), | |
| + value ? BIT(bit) : 0); | |
| +} | |
| + | |
| +static int aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) | |
| +{ | |
| + struct aml_gpio_bank *bank = gpiochip_get_data(chip); | |
| + unsigned int bit, reg; | |
| + | |
| + aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); | |
| + | |
| + return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), | |
| + value ? BIT(bit) : 0); | |
| +} | |
| + | |
| +static int aml_gpio_get(struct gpio_chip *chip, unsigned int gpio) | |
| +{ | |
| + struct aml_gpio_bank *bank = gpiochip_get_data(chip); | |
| + unsigned int reg, bit, val; | |
| + | |
| + aml_gpio_calc_reg_and_bit(bank, AML_REG_IN, gpio, ®, &bit); | |
| + regmap_read(bank->reg_gpio, reg, &val); | |
| + | |
| + return !!(val & BIT(bit)); | |
| +} | |
| + | |
| +static const struct gpio_chip aml_gpio_template = { | |
| + .request = gpiochip_generic_request, | |
| + .free = gpiochip_generic_free, | |
| + .set_config = gpiochip_generic_config, | |
| + .set = aml_gpio_set, | |
| + .get = aml_gpio_get, | |
| + .direction_input = aml_gpio_direction_input, | |
| + .direction_output = aml_gpio_direction_output, | |
| + .get_direction = aml_gpio_get_direction, | |
| + .can_sleep = false, | |
| +}; | |
| + | |
| +static void init_bank_register_bit(struct aml_pinctrl *info, | |
| + struct aml_gpio_bank *bank) | |
| +{ | |
| + const struct aml_pctl_data *data = info->data; | |
| + const struct multi_mux *p_mux; | |
| + int i; | |
| + | |
| + for (i = 0; i < AML_NUM_REG; i++) { | |
| + bank->pc.reg_offset[i] = aml_def_regoffs[i]; | |
| + bank->pc.bit_offset[i] = 0; | |
| + } | |
| + | |
| + bank->mux_bit_offs = 0; | |
| + | |
| + if (data) { | |
| + for (i = 0; i < data->number; i++) { | |
| + p_mux = &data->p_mux[i]; | |
| + if (bank->bank_id == p_mux->m_bank_id) { | |
| + bank->mux_bit_offs = p_mux->m_bit_offs; | |
| + break; | |
| + } | |
| + if (p_mux->sid >> 8 == bank->bank_id) { | |
| + bank->p_mux = p_mux; | |
| + break; | |
| + } | |
| + } | |
| + } | |
| +} | |
| + | |
| +static int aml_gpiolib_register_bank(struct aml_pinctrl *info, | |
| + int bank_nr, struct device_node *np) | |
| +{ | |
| + struct aml_gpio_bank *bank = &info->banks[bank_nr]; | |
| + struct device *dev = info->dev; | |
| + int ret = 0; | |
| + | |
| + ret = aml_bank_number(np); | |
| + if (ret < 0) { | |
| + dev_err(dev, "get num=%d bank identity fail\n", bank_nr); | |
| + return -EINVAL; | |
| + } | |
| + bank->bank_id = ret; | |
| + | |
| + bank->reg_mux = aml_map_resource(dev, bank->bank_id, np, "mux"); | |
| + if (IS_ERR_OR_NULL(bank->reg_mux)) { | |
| + if (bank->bank_id == AMLOGIC_GPIO_TEST_N || | |
| + bank->bank_id == AMLOGIC_GPIO_ANALOG) | |
| + bank->reg_mux = NULL; | |
| + else | |
| + return dev_err_probe(dev, bank->reg_mux ? PTR_ERR(bank->reg_mux) : -ENOENT, | |
| + "mux registers not found\n"); | |
| + } | |
| + | |
| + bank->reg_gpio = aml_map_resource(dev, bank->bank_id, np, "gpio"); | |
| + if (IS_ERR_OR_NULL(bank->reg_gpio)) | |
| + return dev_err_probe(dev, bank->reg_gpio ? PTR_ERR(bank->reg_gpio) : -ENOENT, | |
| + "gpio registers not found\n"); | |
| + | |
| + bank->reg_ds = aml_map_resource(dev, bank->bank_id, np, "ds"); | |
| + if (IS_ERR_OR_NULL(bank->reg_ds)) { | |
| + dev_dbg(info->dev, "ds registers not found - skipping\n"); | |
| + bank->reg_ds = bank->reg_gpio; | |
| + } | |
| + | |
| + bank->gpio_chip = aml_gpio_template; | |
| + bank->gpio_chip.base = -1; | |
| + bank->gpio_chip.ngpio = aml_bank_pins(np); | |
| + bank->gpio_chip.fwnode = of_fwnode_handle(np); | |
| + bank->gpio_chip.parent = dev; | |
| + | |
| + init_bank_register_bit(info, bank); | |
| + bank->gpio_chip.label = aml_bank_name[bank->bank_id]; | |
| + | |
| + bank->pin_base = bank->bank_id << 8; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int aml_pctl_probe_dt(struct platform_device *pdev, | |
| + struct pinctrl_desc *pctl_desc, | |
| + struct aml_pinctrl *info) | |
| +{ | |
| + struct device *dev = &pdev->dev; | |
| + struct pinctrl_pin_desc *pdesc; | |
| + struct device_node *np = dev->of_node; | |
| + int grp_index = 0; | |
| + int i = 0, j = 0, k = 0, bank; | |
| + int ret = 0; | |
| + | |
| + aml_pctl_dt_child_count(info, np); | |
| + if (!info->nbanks) | |
| + return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); | |
| + | |
| + dev_dbg(dev, "nbanks = %d\n", info->nbanks); | |
| + dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); | |
| + dev_dbg(dev, "ngroups = %d\n", info->ngroups); | |
| + | |
| + info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); | |
| + | |
| + info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); | |
| + | |
| + info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); | |
| + | |
| + if (!info->functions || !info->groups || !info->banks) | |
| + return -ENOMEM; | |
| + | |
| + info->data = (struct aml_pctl_data *)of_device_get_match_data(dev); | |
| + | |
| + pctl_desc->npins = aml_count_pins(np); | |
| + | |
| + pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); | |
| + if (!pdesc) | |
| + return -ENOMEM; | |
| + | |
| + pctl_desc->pins = pdesc; | |
| + | |
| + bank = 0; | |
| + for_each_child_of_node_scoped(np, child) { | |
| + if (of_property_read_bool(child, "gpio-controller")) { | |
| + const char *bank_name = NULL; | |
| + char **pin_names; | |
| + | |
| + ret = aml_gpiolib_register_bank(info, bank, child); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + k = info->banks[bank].pin_base; | |
| + bank_name = info->banks[bank].gpio_chip.label; | |
| + | |
| + pin_names = devm_kasprintf_strarray(dev, bank_name, | |
| + info->banks[bank].gpio_chip.ngpio); | |
| + if (IS_ERR(pin_names)) | |
| + return PTR_ERR(pin_names); | |
| + | |
| + for (j = 0; j < info->banks[bank].gpio_chip.ngpio; j++, k++) { | |
| + pdesc->number = k; | |
| + pdesc->name = pin_names[j]; | |
| + pdesc++; | |
| + } | |
| + bank++; | |
| + } else { | |
| + ret = aml_pctl_parse_functions(child, info, | |
| + i++, &grp_index); | |
| + if (ret) | |
| + return ret; | |
| + } | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int aml_pctl_probe(struct platform_device *pdev) | |
| +{ | |
| + struct device *dev = &pdev->dev; | |
| + struct aml_pinctrl *info; | |
| + struct pinctrl_desc *pctl_desc; | |
| + int ret, i; | |
| + | |
| + pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); | |
| + if (!pctl_desc) | |
| + return -ENOMEM; | |
| + | |
| + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); | |
| + if (!info) | |
| + return -ENOMEM; | |
| + | |
| + info->dev = dev; | |
| + platform_set_drvdata(pdev, info); | |
| + ret = aml_pctl_probe_dt(pdev, pctl_desc, info); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + pctl_desc->owner = THIS_MODULE; | |
| + pctl_desc->pctlops = &aml_pctrl_ops; | |
| + pctl_desc->pmxops = &aml_pmx_ops; | |
| + pctl_desc->confops = &aml_pinconf_ops; | |
| + pctl_desc->name = dev_name(dev); | |
| + | |
| + info->pctl = devm_pinctrl_register(dev, pctl_desc, info); | |
| + if (IS_ERR(info->pctl)) | |
| + return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); | |
| + | |
| + for (i = 0; i < info->nbanks; i++) { | |
| + ret = gpiochip_add_data(&info->banks[i].gpio_chip, &info->banks[i]); | |
| + if (ret) | |
| + return dev_err_probe(dev, ret, "Failed to add gpiochip(%d)!\n", i); | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static const struct of_device_id aml_pctl_of_match[] = { | |
| + { .compatible = "amlogic,pinctrl-a4", }, | |
| + { .compatible = "amlogic,pinctrl-s7", .data = &s7_priv_data, }, | |
| + { .compatible = "amlogic,pinctrl-s6", .data = &s6_priv_data, }, | |
| + { /* sentinel */ } | |
| +}; | |
| +MODULE_DEVICE_TABLE(of, aml_pctl_of_match); | |
| + | |
| +static struct platform_driver aml_pctl_driver = { | |
| + .driver = { | |
| + .name = "amlogic-pinctrl", | |
| + .of_match_table = aml_pctl_of_match, | |
| + }, | |
| + .probe = aml_pctl_probe, | |
| +}; | |
| +module_platform_driver(aml_pctl_driver); | |
| + | |
| +MODULE_AUTHOR("Xianwei Zhao <xianwei.zhao@amlogic.com>"); | |
| +MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic SoC"); | |
| +MODULE_LICENSE("Dual BSD/GPL"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-c3.c b/drivers/pinctrl/meson/pinctrl-amlogic-c3.c | |
| new file mode 100644 | |
| index 0000000000..776d32465a | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-amlogic-c3.c | |
| @@ -0,0 +1,1108 @@ | |
| +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) | |
| +/* | |
| + * Pin controller and GPIO driver for Amlogic C3 SoC. | |
| + * | |
| + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. | |
| + * Author: Huqiang Qin <huqiang.qin@amlogic.com> | |
| + */ | |
| + | |
| +#include <dt-bindings/gpio/amlogic-c3-gpio.h> | |
| +#include "pinctrl-meson.h" | |
| +#include "pinctrl-meson-axg-pmx.h" | |
| + | |
| +static const struct pinctrl_pin_desc c3_periphs_pins[] = { | |
| + MESON_PIN(GPIOE_0), | |
| + MESON_PIN(GPIOE_1), | |
| + MESON_PIN(GPIOE_2), | |
| + MESON_PIN(GPIOE_3), | |
| + MESON_PIN(GPIOE_4), | |
| + MESON_PIN(GPIOB_0), | |
| + MESON_PIN(GPIOB_1), | |
| + MESON_PIN(GPIOB_2), | |
| + MESON_PIN(GPIOB_3), | |
| + MESON_PIN(GPIOB_4), | |
| + MESON_PIN(GPIOB_5), | |
| + MESON_PIN(GPIOB_6), | |
| + MESON_PIN(GPIOB_7), | |
| + MESON_PIN(GPIOB_8), | |
| + MESON_PIN(GPIOB_9), | |
| + MESON_PIN(GPIOB_10), | |
| + MESON_PIN(GPIOB_11), | |
| + MESON_PIN(GPIOB_12), | |
| + MESON_PIN(GPIOB_13), | |
| + MESON_PIN(GPIOB_14), | |
| + MESON_PIN(GPIOC_0), | |
| + MESON_PIN(GPIOC_1), | |
| + MESON_PIN(GPIOC_2), | |
| + MESON_PIN(GPIOC_3), | |
| + MESON_PIN(GPIOC_4), | |
| + MESON_PIN(GPIOC_5), | |
| + MESON_PIN(GPIOC_6), | |
| + MESON_PIN(GPIOX_0), | |
| + MESON_PIN(GPIOX_1), | |
| + MESON_PIN(GPIOX_2), | |
| + MESON_PIN(GPIOX_3), | |
| + MESON_PIN(GPIOX_4), | |
| + MESON_PIN(GPIOX_5), | |
| + MESON_PIN(GPIOX_6), | |
| + MESON_PIN(GPIOX_7), | |
| + MESON_PIN(GPIOX_8), | |
| + MESON_PIN(GPIOX_9), | |
| + MESON_PIN(GPIOX_10), | |
| + MESON_PIN(GPIOX_11), | |
| + MESON_PIN(GPIOX_12), | |
| + MESON_PIN(GPIOX_13), | |
| + MESON_PIN(GPIOD_0), | |
| + MESON_PIN(GPIOD_1), | |
| + MESON_PIN(GPIOD_2), | |
| + MESON_PIN(GPIOD_3), | |
| + MESON_PIN(GPIOD_4), | |
| + MESON_PIN(GPIOD_5), | |
| + MESON_PIN(GPIOD_6), | |
| + MESON_PIN(GPIOA_0), | |
| + MESON_PIN(GPIOA_1), | |
| + MESON_PIN(GPIOA_2), | |
| + MESON_PIN(GPIOA_3), | |
| + MESON_PIN(GPIOA_4), | |
| + MESON_PIN(GPIOA_5), | |
| + MESON_PIN(GPIO_TEST_N), | |
| +}; | |
| + | |
| +/* Bank E func1 */ | |
| +static const unsigned int pwm_a_pins[] = { GPIOE_0 }; | |
| +static const unsigned int pwm_b_pins[] = { GPIOE_1 }; | |
| +static const unsigned int i2c2_sda_pins[] = { GPIOE_2 }; | |
| +static const unsigned int i2c2_scl_pins[] = { GPIOE_3 }; | |
| +static const unsigned int gen_clk_e_pins[] = { GPIOE_4 }; | |
| + | |
| +/* Bank E func2 */ | |
| +static const unsigned int i2c0_sda_e_pins[] = { GPIOE_0 }; | |
| +static const unsigned int i2c0_scl_e_pins[] = { GPIOE_1 }; | |
| +static const unsigned int clk_32k_in_pins[] = { GPIOE_4 }; | |
| + | |
| +/* Bank E func3 */ | |
| +static const unsigned int i2c_slave_scl_pins[] = { GPIOE_0 }; | |
| +static const unsigned int i2c_slave_sda_pins[] = { GPIOE_1 }; | |
| +static const unsigned int clk12_24_e_pins[] = { GPIOE_4 }; | |
| + | |
| +/* Bank B func1 */ | |
| +static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 }; | |
| +static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 }; | |
| +static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 }; | |
| +static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 }; | |
| +static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 }; | |
| +static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 }; | |
| +static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 }; | |
| +static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 }; | |
| +static const unsigned int emmc_clk_pins[] = { GPIOB_8 }; | |
| +static const unsigned int emmc_rst_pins[] = { GPIOB_9 }; | |
| +static const unsigned int emmc_cmd_pins[] = { GPIOB_10 }; | |
| +static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 }; | |
| + | |
| +/* Bank B func2 */ | |
| +static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 }; | |
| +static const unsigned int nand_ale_pins[] = { GPIOB_9 }; | |
| +static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 }; | |
| +static const unsigned int nand_cle_pins[] = { GPIOB_11 }; | |
| +static const unsigned int nand_ce0_pins[] = { GPIOB_12 }; | |
| + | |
| +/* Bank B func3 */ | |
| +static const unsigned int pwm_g_b_pins[] = { GPIOB_0 }; | |
| +static const unsigned int pwm_h_b_pins[] = { GPIOB_1 }; | |
| +static const unsigned int pwm_i_b_pins[] = { GPIOB_2 }; | |
| +static const unsigned int spif_hold_pins[] = { GPIOB_3 }; | |
| +static const unsigned int spif_mo_pins[] = { GPIOB_4 }; | |
| +static const unsigned int spif_mi_pins[] = { GPIOB_5 }; | |
| +static const unsigned int spif_clk_pins[] = { GPIOB_6 }; | |
| +static const unsigned int spif_wp_pins[] = { GPIOB_7 }; | |
| +static const unsigned int pwm_j_b_pins[] = { GPIOB_8 }; | |
| +static const unsigned int pwm_k_b_pins[] = { GPIOB_9 }; | |
| +static const unsigned int pwm_l_b_pins[] = { GPIOB_10 }; | |
| +static const unsigned int pwm_m_b_pins[] = { GPIOB_11 }; | |
| +static const unsigned int pwm_n_b_pins[] = { GPIOB_12 }; | |
| +static const unsigned int spif_cs_pins[] = { GPIOB_13 }; | |
| +static const unsigned int spif_clk_loop_pins[] = { GPIOB_14 }; | |
| + | |
| +/* Bank B func4 */ | |
| +static const unsigned int lcd_d0_pins[] = { GPIOB_0 }; | |
| +static const unsigned int lcd_d1_pins[] = { GPIOB_1 }; | |
| +static const unsigned int lcd_d2_pins[] = { GPIOB_2 }; | |
| +static const unsigned int lcd_d3_pins[] = { GPIOB_8 }; | |
| +static const unsigned int lcd_d4_pins[] = { GPIOB_9 }; | |
| +static const unsigned int lcd_d5_pins[] = { GPIOB_10 }; | |
| +static const unsigned int lcd_d6_pins[] = { GPIOB_11 }; | |
| +static const unsigned int lcd_d7_pins[] = { GPIOB_12 }; | |
| + | |
| +/* Bank B func5 */ | |
| +static const unsigned int spi_a_mosi_b_pins[] = { GPIOB_0 }; | |
| +static const unsigned int spi_a_miso_b_pins[] = { GPIOB_1 }; | |
| +static const unsigned int spi_a_clk_b_pins[] = { GPIOB_2 }; | |
| +static const unsigned int spi_a_ss0_b_pins[] = { GPIOB_8 }; | |
| +static const unsigned int spi_a_ss1_b_pins[] = { GPIOB_9 }; | |
| +static const unsigned int spi_a_ss2_b_pins[] = { GPIOB_10 }; | |
| +static const unsigned int i2c1_sda_b_pins[] = { GPIOB_11 }; | |
| +static const unsigned int i2c1_scl_b_pins[] = { GPIOB_12 }; | |
| + | |
| +/* Bank B func6 */ | |
| +static const unsigned int uart_a_tx_b_pins[] = { GPIOB_0 }; | |
| +static const unsigned int uart_a_rx_b_pins[] = { GPIOB_1 }; | |
| +static const unsigned int uart_a_cts_b_pins[] = { GPIOB_2 }; | |
| +static const unsigned int uart_a_rts_b_pins[] = { GPIOB_8 }; | |
| +static const unsigned int uart_d_tx_b_pins[] = { GPIOB_9 }; | |
| +static const unsigned int uart_d_rx_b_pins[] = { GPIOB_10 }; | |
| +static const unsigned int pdm_dclk_b_pins[] = { GPIOB_11 }; | |
| +static const unsigned int pdm_din0_b_pins[] = { GPIOB_12 }; | |
| + | |
| +/* Bank C func1 */ | |
| +static const unsigned int sdcard_d0_pins[] = { GPIOC_0 }; | |
| +static const unsigned int sdcard_d1_pins[] = { GPIOC_1 }; | |
| +static const unsigned int sdcard_d2_pins[] = { GPIOC_2 }; | |
| +static const unsigned int sdcard_d3_pins[] = { GPIOC_3 }; | |
| +static const unsigned int sdcard_clk_pins[] = { GPIOC_4 }; | |
| +static const unsigned int sdcard_cmd_pins[] = { GPIOC_5 }; | |
| +static const unsigned int sdcard_cd_pins[] = { GPIOC_6 }; | |
| + | |
| +/* Bank C func2 */ | |
| +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 }; | |
| +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 }; | |
| +static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 }; | |
| +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 }; | |
| +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 }; | |
| +static const unsigned int gen_clk_c_pins[] = { GPIOC_6 }; | |
| + | |
| +/* Bank C func3 */ | |
| +static const unsigned int tdm_d3_pins[] = { GPIOC_0 }; | |
| +static const unsigned int tdm_d2_pins[] = { GPIOC_1 }; | |
| +static const unsigned int mclk_1_pins[] = { GPIOC_2 }; | |
| +static const unsigned int tdm_sclk1_pins[] = { GPIOC_3 }; | |
| +static const unsigned int tdm_fs1_pins[] = { GPIOC_4 }; | |
| +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_5 }; | |
| +static const unsigned int pdm_din0_c_pins[] = { GPIOC_6 }; | |
| + | |
| +/* Bank C func4 */ | |
| +static const unsigned int spi_a_mosi_c_pins[] = { GPIOC_0 }; | |
| +static const unsigned int spi_a_miso_c_pins[] = { GPIOC_1 }; | |
| +static const unsigned int spi_a_clk_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int spi_a_ss0_c_pins[] = { GPIOC_3 }; | |
| +static const unsigned int spi_a_ss1_c_pins[] = { GPIOC_4 }; | |
| + | |
| +/* Bank C func5 */ | |
| +static const unsigned int pwm_g_c_pins[] = { GPIOC_0 }; | |
| +static const unsigned int pwm_h_c_pins[] = { GPIOC_1 }; | |
| +static const unsigned int pwm_i_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int pwm_j_c_pins[] = { GPIOC_3 }; | |
| +static const unsigned int pwm_k_c_pins[] = { GPIOC_4 }; | |
| +static const unsigned int pwm_l_c_pins[] = { GPIOC_5 }; | |
| +static const unsigned int pwm_m_c_pins[] = { GPIOC_6 }; | |
| + | |
| +/* Bank C func6 */ | |
| +static const unsigned int uart_a_rx_c_pins[] = { GPIOC_0 }; | |
| +static const unsigned int uart_a_tx_c_pins[] = { GPIOC_1 }; | |
| +static const unsigned int uart_c_rx_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int uart_c_tx_c_pins[] = { GPIOC_3 }; | |
| +static const unsigned int i2c3_sda_c_pins[] = { GPIOC_4 }; | |
| +static const unsigned int i2c3_scl_c_pins[] = { GPIOC_5 }; | |
| +static const unsigned int clk12_24_c_pins[] = { GPIOC_6 }; | |
| + | |
| +/* Bank X func1 */ | |
| +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; | |
| +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; | |
| +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; | |
| +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; | |
| +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; | |
| +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; | |
| +static const unsigned int clk12_24_x_pins[] = { GPIOX_6 }; | |
| +static const unsigned int uart_e_tx_x_pins[] = { GPIOX_7 }; | |
| +static const unsigned int uart_e_rx_x_pins[] = { GPIOX_8 }; | |
| +static const unsigned int uart_e_cts_pins[] = { GPIOX_9 }; | |
| +static const unsigned int uart_e_rts_pins[] = { GPIOX_10 }; | |
| +static const unsigned int pwm_e_pins[] = { GPIOX_11 }; | |
| +static const unsigned int pwm_j_x12_pins[] = { GPIOX_12 }; | |
| +static const unsigned int pwm_k_x13_pins[] = { GPIOX_13 }; | |
| + | |
| +/* Bank X func2 */ | |
| +static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_0 }; | |
| +static const unsigned int spi_a_miso_x_pins[] = { GPIOX_1 }; | |
| +static const unsigned int spi_a_clk_x_pins[] = { GPIOX_2 }; | |
| +static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_3 }; | |
| +static const unsigned int spi_a_ss1_x_pins[] = { GPIOX_4 }; | |
| +static const unsigned int spi_a_ss2_x_pins[] = { GPIOX_5 }; | |
| +static const unsigned int spi_b_ss2_x6_pins[] = { GPIOX_6 }; | |
| +static const unsigned int spi_b_miso_x_pins[] = { GPIOX_7 }; | |
| +static const unsigned int spi_b_clk_x_pins[] = { GPIOX_8 }; | |
| +static const unsigned int spi_b_mosi_x_pins[] = { GPIOX_9 }; | |
| +static const unsigned int spi_b_ss0_x_pins[] = { GPIOX_10 }; | |
| +static const unsigned int spi_b_ss1_x_pins[] = { GPIOX_11 }; | |
| +static const unsigned int spi_b_ss2_x12_pins[] = { GPIOX_12 }; | |
| +static const unsigned int gen_clk_x_pins[] = { GPIOX_13 }; | |
| + | |
| +/* Bank X func3 */ | |
| +static const unsigned int tdm_d1_x_pins[] = { GPIOX_0 }; | |
| +static const unsigned int tdm_d0_x_pins[] = { GPIOX_1 }; | |
| +static const unsigned int mclk_0_x_pins[] = { GPIOX_2 }; | |
| +static const unsigned int tdm_sclk0_x_pins[] = { GPIOX_3 }; | |
| +static const unsigned int tdm_fs0_x_pins[] = { GPIOX_4 }; | |
| +static const unsigned int pdm_dclk_x5_pins[] = { GPIOX_5 }; | |
| +static const unsigned int pdm_din0_x6_pins[] = { GPIOX_6 }; | |
| +static const unsigned int pdm_din0_x9_pins[] = { GPIOX_9 }; | |
| +static const unsigned int pdm_dclk_x10_pins[] = { GPIOX_10 }; | |
| +static const unsigned int clk12_24_x13_pins[] = { GPIOX_13 }; | |
| + | |
| +/* Bank X func4 */ | |
| +static const unsigned int lcd_d8_pins[] = { GPIOX_0 }; | |
| +static const unsigned int lcd_d9_pins[] = { GPIOX_1 }; | |
| +static const unsigned int lcd_d10_pins[] = { GPIOX_2 }; | |
| +static const unsigned int lcd_d11_pins[] = { GPIOX_3 }; | |
| +static const unsigned int lcd_d12_pins[] = { GPIOX_4 }; | |
| +static const unsigned int lcd_d13_pins[] = { GPIOX_5 }; | |
| +static const unsigned int lcd_d14_pins[] = { GPIOX_6 }; | |
| +static const unsigned int lcd_d15_pins[] = { GPIOX_7 }; | |
| +static const unsigned int lcd_vs_pins[] = { GPIOX_8 }; | |
| +static const unsigned int lcd_hs_pins[] = { GPIOX_9 }; | |
| +static const unsigned int lcd_den_pins[] = { GPIOX_10 }; | |
| +static const unsigned int lcd_d16_pins[] = { GPIOX_11 }; | |
| +static const unsigned int lcd_clk_x_pins[] = { GPIOX_12 }; | |
| +static const unsigned int lcd_d17_pins[] = { GPIOX_13 }; | |
| + | |
| +/* Bank X func5 */ | |
| +static const unsigned int pwm_g_x0_pins[] = { GPIOX_0 }; | |
| +static const unsigned int pwm_h_x1_pins[] = { GPIOX_1 }; | |
| +static const unsigned int pwm_i_x2_pins[] = { GPIOX_2 }; | |
| +static const unsigned int pwm_j_x3_pins[] = { GPIOX_3 }; | |
| +static const unsigned int pwm_k_x4_pins[] = { GPIOX_4 }; | |
| +static const unsigned int pwm_l_x_pins[] = { GPIOX_5 }; | |
| +static const unsigned int pwm_m_x_pins[] = { GPIOX_6 }; | |
| +static const unsigned int pwm_n_x_pins[] = { GPIOX_7 }; | |
| +static const unsigned int pwm_g_x8_pins[] = { GPIOX_8 }; | |
| +static const unsigned int pwm_h_x9_pins[] = { GPIOX_9 }; | |
| +static const unsigned int pwm_i_x10_pins[] = { GPIOX_10 }; | |
| +static const unsigned int clk12_24_x11_pins[] = { GPIOX_11 }; | |
| + | |
| +/* Bank X func6 */ | |
| +static const unsigned int uart_a_rx_x_pins[] = { GPIOX_0 }; | |
| +static const unsigned int uart_a_tx_x_pins[] = { GPIOX_1 }; | |
| +static const unsigned int uart_c_rx_x_pins[] = { GPIOX_2 }; | |
| +static const unsigned int uart_c_tx_x_pins[] = { GPIOX_3 }; | |
| +static const unsigned int i2c3_sda_x_pins[] = { GPIOX_4 }; | |
| +static const unsigned int i2c3_scl_x_pins[] = { GPIOX_5 }; | |
| +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_7 }; | |
| +static const unsigned int i2c1_scl_x_pins[] = { GPIOX_8 }; | |
| +static const unsigned int uart_d_tx_x_pins[] = { GPIOX_9 }; | |
| +static const unsigned int uart_d_rx_x_pins[] = { GPIOX_10 }; | |
| + | |
| +/* Bank D func1 */ | |
| +static const unsigned int pwm_g_d_pins[] = { GPIOD_0 }; | |
| +static const unsigned int pwm_h_d_pins[] = { GPIOD_1 }; | |
| +static const unsigned int eth_led_act_pins[] = { GPIOD_2 }; | |
| +static const unsigned int eth_led_link_pins[] = { GPIOD_3 }; | |
| +static const unsigned int pwm_d_pins[] = { GPIOD_4 }; | |
| +static const unsigned int pwm_f_pins[] = { GPIOD_5 }; | |
| +static const unsigned int pwm_k_d_pins[] = { GPIOD_6 }; | |
| + | |
| +/* Bank D func2 */ | |
| +static const unsigned int uart_a_tx_d_pins[] = { GPIOD_0 }; | |
| +static const unsigned int uart_a_rx_d_pins[] = { GPIOD_1 }; | |
| +static const unsigned int spi_b_miso_d_pins[] = { GPIOD_2 }; | |
| +static const unsigned int spi_b_clk_d_pins[] = { GPIOD_3 }; | |
| +static const unsigned int spi_b_mosi_d_pins[] = { GPIOD_4 }; | |
| +static const unsigned int spi_b_ss0_d_pins[] = { GPIOD_5 }; | |
| +static const unsigned int spi_b_ss1_d_pins[] = { GPIOD_6 }; | |
| + | |
| +/* Bank D func3 */ | |
| +static const unsigned int i2c0_sda_d_pins[] = { GPIOD_0 }; | |
| +static const unsigned int i2c0_scl_d_pins[] = { GPIOD_1 }; | |
| +static const unsigned int i2c1_sda_d_pins[] = { GPIOD_2 }; | |
| +static const unsigned int i2c1_scl_d_pins[] = { GPIOD_3 }; | |
| +static const unsigned int pdm_dclk_d_pins[] = { GPIOD_4 }; | |
| +static const unsigned int pdm_din0_d_pins[] = { GPIOD_5 }; | |
| +static const unsigned int ir_in_d6_pins[] = { GPIOD_6 }; | |
| + | |
| +/* Bank D func4 */ | |
| +static const unsigned int ir_in_d0_pins[] = { GPIOD_0 }; | |
| +static const unsigned int ir_out_pins[] = { GPIOD_1 }; | |
| +static const unsigned int pwm_i_d_pins[] = { GPIOD_2 }; | |
| +static const unsigned int pwm_j_d_pins[] = { GPIOD_3 }; | |
| +static const unsigned int i2c3_sda_d_pins[] = { GPIOD_4 }; | |
| +static const unsigned int i2c3_scl_d_pins[] = { GPIOD_5 }; | |
| + | |
| +/* Bank D func5 */ | |
| +static const unsigned int tdm_fs0_d_pins[] = { GPIOD_2 }; | |
| +static const unsigned int tdm_sclk0_d_pins[] = { GPIOD_3 }; | |
| +static const unsigned int mclk_0_d_pins[] = { GPIOD_4 }; | |
| +static const unsigned int tdm_d1_d_pins[] = { GPIOD_5 }; | |
| +static const unsigned int tdm_d0_d_pins[] = { GPIOD_6 }; | |
| + | |
| +/* Bank D func6 */ | |
| +static const unsigned int uart_d_tx_d_pins[] = { GPIOD_0 }; | |
| +static const unsigned int uart_d_rx_d_pins[] = { GPIOD_1 }; | |
| +static const unsigned int uart_c_tx_d_pins[] = { GPIOD_2 }; | |
| +static const unsigned int uart_c_rx_d_pins[] = { GPIOD_3 }; | |
| + | |
| +/* Bank A func1 */ | |
| +static const unsigned int uart_b_tx_a_pins[] = { GPIOA_0 }; | |
| +static const unsigned int uart_b_rx_a_pins[] = { GPIOA_1 }; | |
| +static const unsigned int pwm_c_pins[] = { GPIOA_2 }; | |
| +static const unsigned int pwm_l_a_pins[] = { GPIOA_3 }; | |
| +static const unsigned int i2c1_sda_a_pins[] = { GPIOA_4 }; | |
| +static const unsigned int i2c1_scl_a_pins[] = { GPIOA_5 }; | |
| + | |
| +/* Bank A func2 */ | |
| +static const unsigned int pwm_c_hiz_pins[] = { GPIOA_2 }; | |
| +static const unsigned int gen_clk_a_pins[] = { GPIOA_3 }; | |
| +static const unsigned int pdm_dclk_z_pins[] = { GPIOA_4 }; | |
| +static const unsigned int pdm_din0_a_pins[] = { GPIOA_5 }; | |
| + | |
| +/* Bank A func3 */ | |
| +static const unsigned int jtag_a_clk_pins[] = { GPIOA_2 }; | |
| +static const unsigned int jtag_a_tms_pins[] = { GPIOA_3 }; | |
| +static const unsigned int jtag_a_tdi_pins[] = { GPIOA_4 }; | |
| +static const unsigned int jtag_a_tdo_pins[] = { GPIOA_5 }; | |
| + | |
| +/* Bank A func4 */ | |
| +static const unsigned int lcd_clk_a_pins[] = { GPIOA_3 }; | |
| +static const unsigned int uart_f_tx_a_pins[] = { GPIOA_4 }; | |
| +static const unsigned int uart_f_rx_a_pins[] = { GPIOA_5 }; | |
| + | |
| +/* Bank A func5 */ | |
| +static const unsigned int uart_e_tx_a_pins[] = { GPIOA_2 }; | |
| +static const unsigned int uart_e_rx_a_pins[] = { GPIOA_3 }; | |
| +static const unsigned int pwm_m_a_pins[] = { GPIOA_4 }; | |
| +static const unsigned int pwm_n_a_pins[] = { GPIOA_5 }; | |
| + | |
| +/* Bank A func6 */ | |
| +static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_3 }; | |
| +static const unsigned int gen_clk_a4_pins[] = { GPIOA_4 }; | |
| +static const unsigned int clk12_24_a_pins[] = { GPIOA_5 }; | |
| + | |
| +static const struct meson_pmx_group c3_periphs_groups[] = { | |
| + GPIO_GROUP(GPIOE_0), | |
| + GPIO_GROUP(GPIOE_1), | |
| + GPIO_GROUP(GPIOE_2), | |
| + GPIO_GROUP(GPIOE_3), | |
| + GPIO_GROUP(GPIOE_4), | |
| + GPIO_GROUP(GPIOB_0), | |
| + GPIO_GROUP(GPIOB_1), | |
| + GPIO_GROUP(GPIOB_2), | |
| + GPIO_GROUP(GPIOB_3), | |
| + GPIO_GROUP(GPIOB_4), | |
| + GPIO_GROUP(GPIOB_5), | |
| + GPIO_GROUP(GPIOB_6), | |
| + GPIO_GROUP(GPIOB_7), | |
| + GPIO_GROUP(GPIOB_8), | |
| + GPIO_GROUP(GPIOB_9), | |
| + GPIO_GROUP(GPIOB_10), | |
| + GPIO_GROUP(GPIOB_11), | |
| + GPIO_GROUP(GPIOB_12), | |
| + GPIO_GROUP(GPIOB_13), | |
| + GPIO_GROUP(GPIOB_14), | |
| + GPIO_GROUP(GPIOC_0), | |
| + GPIO_GROUP(GPIOC_1), | |
| + GPIO_GROUP(GPIOC_2), | |
| + GPIO_GROUP(GPIOC_3), | |
| + GPIO_GROUP(GPIOC_4), | |
| + GPIO_GROUP(GPIOC_5), | |
| + GPIO_GROUP(GPIOC_6), | |
| + GPIO_GROUP(GPIOX_0), | |
| + GPIO_GROUP(GPIOX_1), | |
| + GPIO_GROUP(GPIOX_2), | |
| + GPIO_GROUP(GPIOX_3), | |
| + GPIO_GROUP(GPIOX_4), | |
| + GPIO_GROUP(GPIOX_5), | |
| + GPIO_GROUP(GPIOX_6), | |
| + GPIO_GROUP(GPIOX_7), | |
| + GPIO_GROUP(GPIOX_8), | |
| + GPIO_GROUP(GPIOX_9), | |
| + GPIO_GROUP(GPIOX_10), | |
| + GPIO_GROUP(GPIOX_11), | |
| + GPIO_GROUP(GPIOX_12), | |
| + GPIO_GROUP(GPIOX_13), | |
| + GPIO_GROUP(GPIOD_0), | |
| + GPIO_GROUP(GPIOD_1), | |
| + GPIO_GROUP(GPIOD_2), | |
| + GPIO_GROUP(GPIOD_3), | |
| + GPIO_GROUP(GPIOD_4), | |
| + GPIO_GROUP(GPIOD_5), | |
| + GPIO_GROUP(GPIOD_6), | |
| + GPIO_GROUP(GPIOA_0), | |
| + GPIO_GROUP(GPIOA_1), | |
| + GPIO_GROUP(GPIOA_2), | |
| + GPIO_GROUP(GPIOA_3), | |
| + GPIO_GROUP(GPIOA_4), | |
| + GPIO_GROUP(GPIOA_5), | |
| + GPIO_GROUP(GPIO_TEST_N), | |
| + | |
| + /* Bank E func1 */ | |
| + GROUP(pwm_a, 1), | |
| + GROUP(pwm_b, 1), | |
| + GROUP(i2c2_sda, 1), | |
| + GROUP(i2c2_scl, 1), | |
| + GROUP(gen_clk_e, 1), | |
| + | |
| + /* Bank E func2 */ | |
| + GROUP(i2c0_sda_e, 2), | |
| + GROUP(i2c0_scl_e, 2), | |
| + GROUP(clk_32k_in, 2), | |
| + | |
| + /* Bank E func3 */ | |
| + GROUP(i2c_slave_scl, 3), | |
| + GROUP(i2c_slave_sda, 3), | |
| + GROUP(clk12_24_e, 3), | |
| + | |
| + /* Bank B func1 */ | |
| + GROUP(emmc_nand_d0, 1), | |
| + GROUP(emmc_nand_d1, 1), | |
| + GROUP(emmc_nand_d2, 1), | |
| + GROUP(emmc_nand_d3, 1), | |
| + GROUP(emmc_nand_d4, 1), | |
| + GROUP(emmc_nand_d5, 1), | |
| + GROUP(emmc_nand_d6, 1), | |
| + GROUP(emmc_nand_d7, 1), | |
| + GROUP(emmc_clk, 1), | |
| + GROUP(emmc_rst, 1), | |
| + GROUP(emmc_cmd, 1), | |
| + GROUP(emmc_nand_ds, 1), | |
| + | |
| + /* Bank B func2 */ | |
| + GROUP(nand_wen_clk, 2), | |
| + GROUP(nand_ale, 2), | |
| + GROUP(nand_ren_wr, 2), | |
| + GROUP(nand_cle, 2), | |
| + GROUP(nand_ce0, 2), | |
| + | |
| + /* Bank B func3 */ | |
| + GROUP(pwm_g_b, 3), | |
| + GROUP(pwm_h_b, 3), | |
| + GROUP(pwm_i_b, 3), | |
| + GROUP(spif_hold, 3), | |
| + GROUP(spif_mo, 3), | |
| + GROUP(spif_mi, 3), | |
| + GROUP(spif_clk, 3), | |
| + GROUP(spif_wp, 3), | |
| + GROUP(pwm_j_b, 3), | |
| + GROUP(pwm_k_b, 3), | |
| + GROUP(pwm_l_b, 3), | |
| + GROUP(pwm_m_b, 3), | |
| + GROUP(pwm_n_b, 3), | |
| + GROUP(spif_cs, 3), | |
| + GROUP(spif_clk_loop, 3), | |
| + | |
| + /* Bank B func4 */ | |
| + GROUP(lcd_d0, 4), | |
| + GROUP(lcd_d1, 4), | |
| + GROUP(lcd_d2, 4), | |
| + GROUP(lcd_d3, 4), | |
| + GROUP(lcd_d4, 4), | |
| + GROUP(lcd_d5, 4), | |
| + GROUP(lcd_d6, 4), | |
| + GROUP(lcd_d7, 4), | |
| + | |
| + /* Bank B func5 */ | |
| + GROUP(spi_a_mosi_b, 5), | |
| + GROUP(spi_a_miso_b, 5), | |
| + GROUP(spi_a_clk_b, 5), | |
| + GROUP(spi_a_ss0_b, 5), | |
| + GROUP(spi_a_ss1_b, 5), | |
| + GROUP(spi_a_ss2_b, 5), | |
| + GROUP(i2c1_sda_b, 5), | |
| + GROUP(i2c1_scl_b, 5), | |
| + | |
| + /* Bank B func6 */ | |
| + GROUP(uart_a_tx_b, 6), | |
| + GROUP(uart_a_rx_b, 6), | |
| + GROUP(uart_a_cts_b, 6), | |
| + GROUP(uart_a_rts_b, 6), | |
| + GROUP(uart_d_tx_b, 6), | |
| + GROUP(uart_d_rx_b, 6), | |
| + GROUP(pdm_dclk_b, 6), | |
| + GROUP(pdm_din0_b, 6), | |
| + | |
| + /* Bank C func1 */ | |
| + GROUP(sdcard_d0, 1), | |
| + GROUP(sdcard_d1, 1), | |
| + GROUP(sdcard_d2, 1), | |
| + GROUP(sdcard_d3, 1), | |
| + GROUP(sdcard_clk, 1), | |
| + GROUP(sdcard_cmd, 1), | |
| + GROUP(sdcard_cd, 1), | |
| + | |
| + /* Bank C func2 */ | |
| + GROUP(jtag_b_tdo, 2), | |
| + GROUP(jtag_b_tdi, 2), | |
| + GROUP(uart_b_rx_c, 2), | |
| + GROUP(uart_b_tx_c, 2), | |
| + GROUP(jtag_b_clk, 2), | |
| + GROUP(jtag_b_tms, 2), | |
| + GROUP(gen_clk_c, 2), | |
| + | |
| + /* Bank C func3 */ | |
| + GROUP(tdm_d3, 3), | |
| + GROUP(tdm_d2, 3), | |
| + GROUP(mclk_1, 3), | |
| + GROUP(tdm_sclk1, 3), | |
| + GROUP(tdm_fs1, 3), | |
| + GROUP(pdm_dclk_c, 3), | |
| + GROUP(pdm_din0_c, 3), | |
| + | |
| + /* Bank C func4 */ | |
| + GROUP(spi_a_mosi_c, 4), | |
| + GROUP(spi_a_miso_c, 4), | |
| + GROUP(spi_a_clk_c, 4), | |
| + GROUP(spi_a_ss0_c, 4), | |
| + GROUP(spi_a_ss1_c, 4), | |
| + | |
| + /* Bank C func5 */ | |
| + GROUP(pwm_g_c, 5), | |
| + GROUP(pwm_h_c, 5), | |
| + GROUP(pwm_i_c, 5), | |
| + GROUP(pwm_j_c, 5), | |
| + GROUP(pwm_k_c, 5), | |
| + GROUP(pwm_l_c, 5), | |
| + GROUP(pwm_m_c, 5), | |
| + | |
| + /* Bank C func6 */ | |
| + GROUP(uart_a_rx_c, 6), | |
| + GROUP(uart_a_tx_c, 6), | |
| + GROUP(uart_c_rx_c, 6), | |
| + GROUP(uart_c_tx_c, 6), | |
| + GROUP(i2c3_sda_c, 6), | |
| + GROUP(i2c3_scl_c, 6), | |
| + GROUP(clk12_24_c, 6), | |
| + | |
| + /* Bank X func1 */ | |
| + GROUP(sdio_d0, 1), | |
| + GROUP(sdio_d1, 1), | |
| + GROUP(sdio_d2, 1), | |
| + GROUP(sdio_d3, 1), | |
| + GROUP(sdio_clk, 1), | |
| + GROUP(sdio_cmd, 1), | |
| + GROUP(clk12_24_x, 1), | |
| + GROUP(uart_e_tx_x, 1), | |
| + GROUP(uart_e_rx_x, 1), | |
| + GROUP(uart_e_cts, 1), | |
| + GROUP(uart_e_rts, 1), | |
| + GROUP(pwm_e, 1), | |
| + GROUP(pwm_j_x12, 1), | |
| + GROUP(pwm_k_x13, 1), | |
| + | |
| + /* Bank X func2 */ | |
| + GROUP(spi_a_mosi_x, 2), | |
| + GROUP(spi_a_miso_x, 2), | |
| + GROUP(spi_a_clk_x, 2), | |
| + GROUP(spi_a_ss0_x, 2), | |
| + GROUP(spi_a_ss1_x, 2), | |
| + GROUP(spi_a_ss2_x, 2), | |
| + GROUP(spi_b_ss2_x6, 2), | |
| + GROUP(spi_b_miso_x, 2), | |
| + GROUP(spi_b_clk_x, 2), | |
| + GROUP(spi_b_mosi_x, 2), | |
| + GROUP(spi_b_ss0_x, 2), | |
| + GROUP(spi_b_ss1_x, 2), | |
| + GROUP(spi_b_ss2_x12, 2), | |
| + GROUP(gen_clk_x, 2), | |
| + | |
| + /* Bank X func3 */ | |
| + GROUP(tdm_d1_x, 3), | |
| + GROUP(tdm_d0_x, 3), | |
| + GROUP(mclk_0_x, 3), | |
| + GROUP(tdm_sclk0_x, 3), | |
| + GROUP(tdm_fs0_x, 3), | |
| + GROUP(pdm_dclk_x5, 3), | |
| + GROUP(pdm_din0_x6, 3), | |
| + GROUP(pdm_din0_x9, 3), | |
| + GROUP(pdm_dclk_x10, 3), | |
| + GROUP(clk12_24_x13, 3), | |
| + | |
| + /* Bank X func4 */ | |
| + GROUP(lcd_d8, 4), | |
| + GROUP(lcd_d9, 4), | |
| + GROUP(lcd_d10, 4), | |
| + GROUP(lcd_d11, 4), | |
| + GROUP(lcd_d12, 4), | |
| + GROUP(lcd_d13, 4), | |
| + GROUP(lcd_d14, 4), | |
| + GROUP(lcd_d15, 4), | |
| + GROUP(lcd_vs, 4), | |
| + GROUP(lcd_hs, 4), | |
| + GROUP(lcd_den, 4), | |
| + GROUP(lcd_d16, 4), | |
| + GROUP(lcd_clk_x, 4), | |
| + GROUP(lcd_d17, 4), | |
| + | |
| + /* Bank X func5 */ | |
| + GROUP(pwm_g_x0, 5), | |
| + GROUP(pwm_h_x1, 5), | |
| + GROUP(pwm_i_x2, 5), | |
| + GROUP(pwm_j_x3, 5), | |
| + GROUP(pwm_k_x4, 5), | |
| + GROUP(pwm_l_x, 5), | |
| + GROUP(pwm_m_x, 5), | |
| + GROUP(pwm_n_x, 5), | |
| + GROUP(pwm_g_x8, 5), | |
| + GROUP(pwm_h_x9, 5), | |
| + GROUP(pwm_i_x10, 5), | |
| + GROUP(clk12_24_x11, 5), | |
| + | |
| + /* Bank X func6 */ | |
| + GROUP(uart_a_rx_x, 6), | |
| + GROUP(uart_a_tx_x, 6), | |
| + GROUP(uart_c_rx_x, 6), | |
| + GROUP(uart_c_tx_x, 6), | |
| + GROUP(i2c3_sda_x, 6), | |
| + GROUP(i2c3_scl_x, 6), | |
| + GROUP(i2c1_sda_x, 6), | |
| + GROUP(i2c1_scl_x, 6), | |
| + GROUP(uart_d_tx_x, 6), | |
| + GROUP(uart_d_rx_x, 6), | |
| + | |
| + /* Bank D func1 */ | |
| + GROUP(pwm_g_d, 1), | |
| + GROUP(pwm_h_d, 1), | |
| + GROUP(eth_led_act, 1), | |
| + GROUP(eth_led_link, 1), | |
| + GROUP(pwm_d, 1), | |
| + GROUP(pwm_f, 1), | |
| + GROUP(pwm_k_d, 1), | |
| + | |
| + /* Bank D func2 */ | |
| + GROUP(uart_a_tx_d, 2), | |
| + GROUP(uart_a_rx_d, 2), | |
| + GROUP(spi_b_miso_d, 2), | |
| + GROUP(spi_b_clk_d, 2), | |
| + GROUP(spi_b_mosi_d, 2), | |
| + GROUP(spi_b_ss0_d, 2), | |
| + GROUP(spi_b_ss1_d, 2), | |
| + | |
| + /* Bank D func3 */ | |
| + GROUP(i2c0_sda_d, 3), | |
| + GROUP(i2c0_scl_d, 3), | |
| + GROUP(i2c1_sda_d, 3), | |
| + GROUP(i2c1_scl_d, 3), | |
| + GROUP(pdm_dclk_d, 3), | |
| + GROUP(pdm_din0_d, 3), | |
| + GROUP(ir_in_d6, 3), | |
| + | |
| + /* Bank D func4 */ | |
| + GROUP(ir_in_d0, 4), | |
| + GROUP(ir_out, 4), | |
| + GROUP(pwm_i_d, 4), | |
| + GROUP(pwm_j_d, 4), | |
| + GROUP(i2c3_sda_d, 4), | |
| + GROUP(i2c3_scl_d, 4), | |
| + | |
| + /* Bank D func5 */ | |
| + GROUP(tdm_fs0_d, 5), | |
| + GROUP(tdm_sclk0_d, 5), | |
| + GROUP(mclk_0_d, 5), | |
| + GROUP(tdm_d1_d, 5), | |
| + GROUP(tdm_d0_d, 5), | |
| + | |
| + /* Bank D func6 */ | |
| + GROUP(uart_d_tx_d, 6), | |
| + GROUP(uart_d_rx_d, 6), | |
| + GROUP(uart_c_tx_d, 6), | |
| + GROUP(uart_c_rx_d, 6), | |
| + | |
| + /* Bank A func1 */ | |
| + GROUP(uart_b_tx_a, 1), | |
| + GROUP(uart_b_rx_a, 1), | |
| + GROUP(pwm_c, 1), | |
| + GROUP(pwm_l_a, 1), | |
| + GROUP(i2c1_sda_a, 1), | |
| + GROUP(i2c1_scl_a, 1), | |
| + | |
| + /* Bank A func2 */ | |
| + GROUP(pwm_c_hiz, 2), | |
| + GROUP(gen_clk_a, 2), | |
| + GROUP(pdm_dclk_z, 2), | |
| + GROUP(pdm_din0_a, 2), | |
| + | |
| + /* Bank A func3 */ | |
| + GROUP(jtag_a_clk, 3), | |
| + GROUP(jtag_a_tms, 3), | |
| + GROUP(jtag_a_tdi, 3), | |
| + GROUP(jtag_a_tdo, 3), | |
| + | |
| + /* Bank A func4 */ | |
| + GROUP(lcd_clk_a, 4), | |
| + GROUP(uart_f_tx_a, 4), | |
| + GROUP(uart_f_rx_a, 4), | |
| + | |
| + /* Bank A func5 */ | |
| + GROUP(uart_e_tx_a, 5), | |
| + GROUP(uart_e_rx_a, 5), | |
| + GROUP(pwm_m_a, 5), | |
| + GROUP(pwm_n_a, 5), | |
| + | |
| + /* Bank A func6 */ | |
| + GROUP(spi_a_mosi_a, 6), | |
| + GROUP(gen_clk_a4, 6), | |
| + GROUP(clk12_24_a, 6), | |
| +}; | |
| + | |
| +static const char * const gpio_periphs_groups[] = { | |
| + "GPIO_TEST_N", | |
| + | |
| + "GPIOE_0", "GPIOE_1", "GPIOE_2", "GPIOE_3", "GPIOE_4", | |
| + | |
| + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", | |
| + "GPIOB_5", "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", | |
| + "GPIOB_10", "GPIOB_11", "GPIOB_12", "GPIOB_13", | |
| + "GPIOB_14", | |
| + | |
| + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", | |
| + "GPIOC_5", "GPIOC_6", | |
| + | |
| + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", | |
| + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", | |
| + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", | |
| + | |
| + "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", | |
| + "GPIOD_5", "GPIOD_6", | |
| + | |
| + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", | |
| + "GPIOA_5", | |
| +}; | |
| + | |
| +static const char * const uart_a_groups[] = { | |
| + "uart_a_tx_b", "uart_a_rx_b", "uart_a_cts_b", "uart_a_rts_b", | |
| + "uart_a_rx_c", "uart_a_tx_c", "uart_a_rx_x", "uart_a_tx_x", | |
| + "uart_a_tx_d", "uart_a_rx_d", | |
| +}; | |
| + | |
| +static const char * const uart_b_groups[] = { | |
| + "uart_b_rx_c", "uart_b_tx_c", "uart_b_tx_a", "uart_b_rx_a", | |
| +}; | |
| + | |
| +static const char * const uart_c_groups[] = { | |
| + "uart_c_rx_c", "uart_c_tx_c", | |
| + "uart_c_rx_x", "uart_c_tx_x", | |
| + "uart_c_tx_d", "uart_c_rx_d", | |
| +}; | |
| + | |
| +static const char * const uart_d_groups[] = { | |
| + "uart_d_tx_b", "uart_d_rx_b", "uart_d_tx_d", "uart_d_rx_d", | |
| + "uart_d_rx_x", "uart_d_tx_x", | |
| +}; | |
| + | |
| +static const char * const uart_e_groups[] = { | |
| + "uart_e_cts", "uart_e_tx_x", "uart_e_rx_x", "uart_e_rts", | |
| + "uart_e_tx_a", "uart_e_rx_a", | |
| +}; | |
| + | |
| +static const char * const i2c0_groups[] = { | |
| + "i2c0_sda_e", "i2c0_scl_e", | |
| + "i2c0_sda_d", "i2c0_scl_d", | |
| +}; | |
| + | |
| +static const char * const i2c1_groups[] = { | |
| + "i2c1_sda_x", "i2c1_scl_x", | |
| + "i2c1_sda_d", "i2c1_scl_d", | |
| + "i2c1_sda_a", "i2c1_scl_a", | |
| + "i2c1_sda_b", "i2c1_scl_b", | |
| +}; | |
| + | |
| +static const char * const i2c2_groups[] = { | |
| + "i2c2_sda", "i2c2_scl", | |
| +}; | |
| + | |
| +static const char * const i2c3_groups[] = { | |
| + "i2c3_sda_c", "i2c3_scl_c", | |
| + "i2c3_sda_x", "i2c3_scl_x", | |
| + "i2c3_sda_d", "i2c3_scl_d", | |
| +}; | |
| + | |
| +static const char * const i2c_slave_groups[] = { | |
| + "i2c_slave_scl", "i2c_slave_sda", | |
| +}; | |
| + | |
| +static const char * const pwm_a_groups[] = { | |
| + "pwm_a", | |
| +}; | |
| + | |
| +static const char * const pwm_b_groups[] = { | |
| + "pwm_b", | |
| +}; | |
| + | |
| +static const char * const pwm_c_groups[] = { | |
| + "pwm_c", | |
| +}; | |
| + | |
| +static const char * const pwm_d_groups[] = { | |
| + "pwm_d", | |
| +}; | |
| + | |
| +static const char * const pwm_e_groups[] = { | |
| + "pwm_e", | |
| +}; | |
| + | |
| +static const char * const pwm_f_groups[] = { | |
| + "pwm_f", | |
| +}; | |
| + | |
| +static const char * const pwm_g_groups[] = { | |
| + "pwm_g_b", "pwm_g_c", "pwm_g_d", "pwm_g_x0", "pwm_g_x8", | |
| +}; | |
| + | |
| +static const char * const pwm_h_groups[] = { | |
| + "pwm_h_b", "pwm_h_c", "pwm_h_d", "pwm_h_x1", "pwm_h_x9", | |
| +}; | |
| + | |
| +static const char * const pwm_i_groups[] = { | |
| + "pwm_i_b", "pwm_i_c", "pwm_i_d", "pwm_i_x2", "pwm_i_x10", | |
| +}; | |
| + | |
| +static const char * const pwm_j_groups[] = { | |
| + "pwm_j_c", "pwm_j_d", "pwm_j_b", "pwm_j_x3", "pwm_j_x12", | |
| +}; | |
| + | |
| +static const char * const pwm_k_groups[] = { | |
| + "pwm_k_c", "pwm_k_d", "pwm_k_b", "pwm_k_x4", "pwm_k_x13", | |
| +}; | |
| + | |
| +static const char * const pwm_l_groups[] = { | |
| + "pwm_l_c", "pwm_l_x", "pwm_l_b", "pwm_l_a", | |
| +}; | |
| + | |
| +static const char * const pwm_m_groups[] = { | |
| + "pwm_m_c", "pwm_m_x", "pwm_m_a", "pwm_m_b", | |
| +}; | |
| + | |
| +static const char * const pwm_n_groups[] = { | |
| + "pwm_n_x", "pwm_n_a", "pwm_n_b", | |
| +}; | |
| + | |
| +static const char * const pwm_c_hiz_groups[] = { | |
| + "pwm_c_hiz", | |
| +}; | |
| + | |
| +static const char * const ir_out_groups[] = { | |
| + "ir_out", | |
| +}; | |
| + | |
| +static const char * const ir_in_groups[] = { | |
| + "ir_in_d0", "ir_in_d6", | |
| +}; | |
| + | |
| +static const char * const jtag_a_groups[] = { | |
| + "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo", | |
| +}; | |
| + | |
| +static const char * const jtag_b_groups[] = { | |
| + "jtag_b_tdo", "jtag_b_tdi", "jtag_b_clk", "jtag_b_tms", | |
| +}; | |
| + | |
| +static const char * const gen_clk_groups[] = { | |
| + "gen_clk_e", "gen_clk_c", "gen_clk_a", "gen_clk_x", | |
| + "gen_clk_a4", | |
| +}; | |
| + | |
| +static const char * const clk12_24_groups[] = { | |
| + "clk12_24_e", "clk12_24_c", "clk12_24_x", "clk12_24_a", | |
| + "clk12_24_x13", "clk12_24_x11", | |
| +}; | |
| + | |
| +static const char * const clk_32k_in_groups[] = { | |
| + "clk_32k_in", | |
| +}; | |
| + | |
| +static const char * const emmc_groups[] = { | |
| + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", | |
| + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", | |
| + "emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds", | |
| +}; | |
| + | |
| +static const char * const nand_groups[] = { | |
| + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", | |
| + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", | |
| + "emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds", | |
| + "nand_wen_clk", "nand_ale", "nand_ren_wr", "nand_cle", | |
| + "nand_ce0", | |
| +}; | |
| + | |
| +static const char * const spif_groups[] = { | |
| + "spif_mo", "spif_mi", "spif_wp", "spif_cs", | |
| + "spif_clk", "spif_hold", "spif_clk_loop", | |
| +}; | |
| + | |
| +static const char * const spi_a_groups[] = { | |
| + "spi_a_clk_b", "spi_a_ss0_b", "spi_a_ss1_b", "spi_a_ss2_b", | |
| + "spi_a_mosi_b", "spi_a_miso_b", | |
| + | |
| + "spi_a_clk_c", "spi_a_ss0_c", "spi_a_ss1_c", | |
| + "spi_a_mosi_c", "spi_a_miso_c", | |
| + | |
| + "spi_a_clk_x", "spi_a_ss0_x", "spi_a_ss1_x", "spi_a_ss2_x", | |
| + "spi_a_mosi_x", "spi_a_miso_x", | |
| + "spi_a_mosi_a", | |
| +}; | |
| + | |
| +static const char * const spi_b_groups[] = { | |
| + "spi_b_clk_x", "spi_b_ss0_x", "spi_b_ss1_x", "spi_b_ss2_x6", | |
| + "spi_b_miso_x", "spi_b_mosi_x", "spi_b_ss2_x12", | |
| + | |
| + "spi_b_clk_d", "spi_b_ss0_d", "spi_b_ss1_d", "spi_b_miso_d", | |
| + "spi_b_mosi_d", | |
| +}; | |
| + | |
| +static const char * const sdcard_groups[] = { | |
| + "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", | |
| + "sdcard_cd", "sdcard_clk", "sdcard_cmd", | |
| +}; | |
| + | |
| +static const char * const sdio_groups[] = { | |
| + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", | |
| + "sdio_clk", "sdio_cmd", | |
| +}; | |
| + | |
| +static const char * const pdm_groups[] = { | |
| + "pdm_dclk_c", "pdm_din0_c", "pdm_dclk_d", "pdm_din0_d", | |
| + "pdm_dclk_z", "pdm_din0_a", "pdm_dclk_b", "pdm_din0_b", | |
| + "pdm_dclk_x5", "pdm_din0_x6", "pdm_din0_x9", "pdm_dclk_x10", | |
| +}; | |
| + | |
| +static const char * const eth_groups[] = { | |
| + "eth_led_act", "eth_led_link", | |
| +}; | |
| + | |
| +static const char * const mclk_0_groups[] = { | |
| + "mclk_0_x", "mclk_0_d", | |
| +}; | |
| + | |
| +static const char * const mclk_1_groups[] = { | |
| + "mclk_1", | |
| +}; | |
| + | |
| +static const char * const tdm_groups[] = { | |
| + "tdm_d3", "tdm_d2", "tdm_fs1", "tdm_d1_x", "tdm_d0_x", | |
| + "tdm_d1_d", "tdm_d0_d", "tdm_sclk1", "tdm_fs0_x", "tdm_fs0_d", | |
| + "tdm_sclk0_x", "tdm_sclk0_d", | |
| +}; | |
| + | |
| +static const char * const lcd_groups[] = { | |
| + "lcd_d0", "lcd_d1", "lcd_d2", "lcd_d3", "lcd_d4", | |
| + "lcd_d5", "lcd_d6", "lcd_d7", "lcd_d8", "lcd_d9", | |
| + "lcd_d10", "lcd_d11", "lcd_d12", "lcd_d13", "lcd_d14", | |
| + "lcd_d15", "lcd_d16", "lcd_d17", "lcd_den", | |
| + "lcd_clk_a", "lcd_clk_x", "lcd_hs", "lcd_vs", | |
| +}; | |
| + | |
| +static const struct meson_pmx_func c3_periphs_functions[] = { | |
| + FUNCTION(gpio_periphs), | |
| + FUNCTION(uart_a), | |
| + FUNCTION(uart_b), | |
| + FUNCTION(uart_c), | |
| + FUNCTION(uart_d), | |
| + FUNCTION(uart_e), | |
| + FUNCTION(i2c0), | |
| + FUNCTION(i2c1), | |
| + FUNCTION(i2c2), | |
| + FUNCTION(i2c3), | |
| + FUNCTION(i2c_slave), | |
| + FUNCTION(pwm_a), | |
| + FUNCTION(pwm_b), | |
| + FUNCTION(pwm_c), | |
| + FUNCTION(pwm_d), | |
| + FUNCTION(pwm_e), | |
| + FUNCTION(pwm_f), | |
| + FUNCTION(pwm_g), | |
| + FUNCTION(pwm_h), | |
| + FUNCTION(pwm_i), | |
| + FUNCTION(pwm_j), | |
| + FUNCTION(pwm_k), | |
| + FUNCTION(pwm_l), | |
| + FUNCTION(pwm_m), | |
| + FUNCTION(pwm_n), | |
| + FUNCTION(pwm_c_hiz), | |
| + FUNCTION(ir_out), | |
| + FUNCTION(ir_in), | |
| + FUNCTION(jtag_a), | |
| + FUNCTION(jtag_b), | |
| + FUNCTION(gen_clk), | |
| + FUNCTION(clk12_24), | |
| + FUNCTION(clk_32k_in), | |
| + FUNCTION(emmc), | |
| + FUNCTION(nand), | |
| + FUNCTION(spif), | |
| + FUNCTION(spi_a), | |
| + FUNCTION(spi_b), | |
| + FUNCTION(sdcard), | |
| + FUNCTION(sdio), | |
| + FUNCTION(pdm), | |
| + FUNCTION(eth), | |
| + FUNCTION(mclk_0), | |
| + FUNCTION(mclk_1), | |
| + FUNCTION(tdm), | |
| + FUNCTION(lcd), | |
| +}; | |
| + | |
| +static const struct meson_bank c3_periphs_banks[] = { | |
| + /* name first last irq pullen pull dir out in ds */ | |
| + BANK_DS("X", GPIOX_0, GPIOX_13, 40, 53, | |
| + 0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0), | |
| + BANK_DS("D", GPIOD_0, GPIOD_6, 33, 39, | |
| + 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0), | |
| + BANK_DS("E", GPIOE_0, GPIOE_4, 22, 26, | |
| + 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0), | |
| + BANK_DS("C", GPIOC_0, GPIOC_6, 15, 21, | |
| + 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0), | |
| + BANK_DS("B", GPIOB_0, GPIOB_14, 0, 14, | |
| + 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0), | |
| + BANK_DS("A", GPIOA_0, GPIOA_5, 27, 32, | |
| + 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0), | |
| + BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 54, 54, | |
| + 0x73, 0, 0x74, 0, 0x72, 0, 0x71, 0, 0x70, 0, 0x77, 0), | |
| +}; | |
| + | |
| +static const struct meson_pmx_bank c3_periphs_pmx_banks[] = { | |
| + /* name first last reg offset */ | |
| + BANK_PMX("B", GPIOB_0, GPIOB_14, 0x00, 0), | |
| + BANK_PMX("X", GPIOX_0, GPIOX_13, 0x03, 0), | |
| + BANK_PMX("C", GPIOC_0, GPIOC_6, 0x09, 0), | |
| + BANK_PMX("A", GPIOA_0, GPIOA_5, 0x0b, 0), | |
| + BANK_PMX("D", GPIOD_0, GPIOD_6, 0x10, 0), | |
| + BANK_PMX("E", GPIOE_0, GPIOE_4, 0x12, 0), | |
| + BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0x02, 0), | |
| +}; | |
| + | |
| +static const struct meson_axg_pmx_data c3_periphs_pmx_banks_data = { | |
| + .pmx_banks = c3_periphs_pmx_banks, | |
| + .num_pmx_banks = ARRAY_SIZE(c3_periphs_pmx_banks), | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data c3_periphs_pinctrl_data = { | |
| + .name = "periphs-banks", | |
| + .pins = c3_periphs_pins, | |
| + .groups = c3_periphs_groups, | |
| + .funcs = c3_periphs_functions, | |
| + .banks = c3_periphs_banks, | |
| + .num_pins = ARRAY_SIZE(c3_periphs_pins), | |
| + .num_groups = ARRAY_SIZE(c3_periphs_groups), | |
| + .num_funcs = ARRAY_SIZE(c3_periphs_functions), | |
| + .num_banks = ARRAY_SIZE(c3_periphs_banks), | |
| + .pmx_ops = &meson_axg_pmx_ops, | |
| + .pmx_data = &c3_periphs_pmx_banks_data, | |
| + .parse_dt = &meson_a1_parse_dt_extra, | |
| +}; | |
| + | |
| +static const struct of_device_id c3_pinctrl_dt_match[] = { | |
| + { | |
| + .compatible = "amlogic,c3-periphs-pinctrl", | |
| + .data = &c3_periphs_pinctrl_data, | |
| + }, | |
| + { } | |
| +}; | |
| +MODULE_DEVICE_TABLE(of, c3_pinctrl_dt_match); | |
| + | |
| +static struct platform_driver c3_pinctrl_driver = { | |
| + .probe = meson_pinctrl_probe, | |
| + .driver = { | |
| + .name = "amlogic-c3-pinctrl", | |
| + .of_match_table = c3_pinctrl_dt_match, | |
| + }, | |
| +}; | |
| +module_platform_driver(c3_pinctrl_driver); | |
| + | |
| +MODULE_AUTHOR("Huqiang Qin <huqiang.qin@amlogic.com>"); | |
| +MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic C3 SoC"); | |
| +MODULE_LICENSE("Dual BSD/GPL"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-t7.c b/drivers/pinctrl/meson/pinctrl-amlogic-t7.c | |
| new file mode 100644 | |
| index 0000000000..cfd98b9dcb | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-amlogic-t7.c | |
| @@ -0,0 +1,1611 @@ | |
| +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) | |
| +/* | |
| + * Pin controller and GPIO driver for Amlogic T7 SoC. | |
| + * | |
| + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. | |
| + * Author: Huqiang Qin <huqiang.qin@amlogic.com> | |
| + */ | |
| + | |
| +#include <dt-bindings/gpio/amlogic,t7-periphs-pinctrl.h> | |
| +#include "pinctrl-meson.h" | |
| +#include "pinctrl-meson-axg-pmx.h" | |
| + | |
| +static const struct pinctrl_pin_desc t7_periphs_pins[] = { | |
| + MESON_PIN(GPIOB_0), | |
| + MESON_PIN(GPIOB_1), | |
| + MESON_PIN(GPIOB_2), | |
| + MESON_PIN(GPIOB_3), | |
| + MESON_PIN(GPIOB_4), | |
| + MESON_PIN(GPIOB_5), | |
| + MESON_PIN(GPIOB_6), | |
| + MESON_PIN(GPIOB_7), | |
| + MESON_PIN(GPIOB_8), | |
| + MESON_PIN(GPIOB_9), | |
| + MESON_PIN(GPIOB_10), | |
| + MESON_PIN(GPIOB_11), | |
| + MESON_PIN(GPIOB_12), | |
| + | |
| + MESON_PIN(GPIOC_0), | |
| + MESON_PIN(GPIOC_1), | |
| + MESON_PIN(GPIOC_2), | |
| + MESON_PIN(GPIOC_3), | |
| + MESON_PIN(GPIOC_4), | |
| + MESON_PIN(GPIOC_5), | |
| + MESON_PIN(GPIOC_6), | |
| + | |
| + MESON_PIN(GPIOX_0), | |
| + MESON_PIN(GPIOX_1), | |
| + MESON_PIN(GPIOX_2), | |
| + MESON_PIN(GPIOX_3), | |
| + MESON_PIN(GPIOX_4), | |
| + MESON_PIN(GPIOX_5), | |
| + MESON_PIN(GPIOX_6), | |
| + MESON_PIN(GPIOX_7), | |
| + MESON_PIN(GPIOX_8), | |
| + MESON_PIN(GPIOX_9), | |
| + MESON_PIN(GPIOX_10), | |
| + MESON_PIN(GPIOX_11), | |
| + MESON_PIN(GPIOX_12), | |
| + MESON_PIN(GPIOX_13), | |
| + MESON_PIN(GPIOX_14), | |
| + MESON_PIN(GPIOX_15), | |
| + MESON_PIN(GPIOX_16), | |
| + MESON_PIN(GPIOX_17), | |
| + MESON_PIN(GPIOX_18), | |
| + MESON_PIN(GPIOX_19), | |
| + | |
| + MESON_PIN(GPIOW_0), | |
| + MESON_PIN(GPIOW_1), | |
| + MESON_PIN(GPIOW_2), | |
| + MESON_PIN(GPIOW_3), | |
| + MESON_PIN(GPIOW_4), | |
| + MESON_PIN(GPIOW_5), | |
| + MESON_PIN(GPIOW_6), | |
| + MESON_PIN(GPIOW_7), | |
| + MESON_PIN(GPIOW_8), | |
| + MESON_PIN(GPIOW_9), | |
| + MESON_PIN(GPIOW_10), | |
| + MESON_PIN(GPIOW_11), | |
| + MESON_PIN(GPIOW_12), | |
| + MESON_PIN(GPIOW_13), | |
| + MESON_PIN(GPIOW_14), | |
| + MESON_PIN(GPIOW_15), | |
| + MESON_PIN(GPIOW_16), | |
| + | |
| + MESON_PIN(GPIOD_0), | |
| + MESON_PIN(GPIOD_1), | |
| + MESON_PIN(GPIOD_2), | |
| + MESON_PIN(GPIOD_3), | |
| + MESON_PIN(GPIOD_4), | |
| + MESON_PIN(GPIOD_5), | |
| + MESON_PIN(GPIOD_6), | |
| + MESON_PIN(GPIOD_7), | |
| + MESON_PIN(GPIOD_8), | |
| + MESON_PIN(GPIOD_9), | |
| + MESON_PIN(GPIOD_10), | |
| + MESON_PIN(GPIOD_11), | |
| + MESON_PIN(GPIOD_12), | |
| + | |
| + MESON_PIN(GPIOE_0), | |
| + MESON_PIN(GPIOE_1), | |
| + MESON_PIN(GPIOE_2), | |
| + MESON_PIN(GPIOE_3), | |
| + MESON_PIN(GPIOE_4), | |
| + MESON_PIN(GPIOE_5), | |
| + MESON_PIN(GPIOE_6), | |
| + | |
| + MESON_PIN(GPIOZ_0), | |
| + MESON_PIN(GPIOZ_1), | |
| + MESON_PIN(GPIOZ_2), | |
| + MESON_PIN(GPIOZ_3), | |
| + MESON_PIN(GPIOZ_4), | |
| + MESON_PIN(GPIOZ_5), | |
| + MESON_PIN(GPIOZ_6), | |
| + MESON_PIN(GPIOZ_7), | |
| + MESON_PIN(GPIOZ_8), | |
| + MESON_PIN(GPIOZ_9), | |
| + MESON_PIN(GPIOZ_10), | |
| + MESON_PIN(GPIOZ_11), | |
| + MESON_PIN(GPIOZ_12), | |
| + MESON_PIN(GPIOZ_13), | |
| + | |
| + MESON_PIN(GPIOT_0), | |
| + MESON_PIN(GPIOT_1), | |
| + MESON_PIN(GPIOT_2), | |
| + MESON_PIN(GPIOT_3), | |
| + MESON_PIN(GPIOT_4), | |
| + MESON_PIN(GPIOT_5), | |
| + MESON_PIN(GPIOT_6), | |
| + MESON_PIN(GPIOT_7), | |
| + MESON_PIN(GPIOT_8), | |
| + MESON_PIN(GPIOT_9), | |
| + MESON_PIN(GPIOT_10), | |
| + MESON_PIN(GPIOT_11), | |
| + MESON_PIN(GPIOT_12), | |
| + MESON_PIN(GPIOT_13), | |
| + MESON_PIN(GPIOT_14), | |
| + MESON_PIN(GPIOT_15), | |
| + MESON_PIN(GPIOT_16), | |
| + MESON_PIN(GPIOT_17), | |
| + MESON_PIN(GPIOT_18), | |
| + MESON_PIN(GPIOT_19), | |
| + MESON_PIN(GPIOT_20), | |
| + MESON_PIN(GPIOT_21), | |
| + MESON_PIN(GPIOT_22), | |
| + MESON_PIN(GPIOT_23), | |
| + | |
| + MESON_PIN(GPIOM_0), | |
| + MESON_PIN(GPIOM_1), | |
| + MESON_PIN(GPIOM_2), | |
| + MESON_PIN(GPIOM_3), | |
| + MESON_PIN(GPIOM_4), | |
| + MESON_PIN(GPIOM_5), | |
| + MESON_PIN(GPIOM_6), | |
| + MESON_PIN(GPIOM_7), | |
| + MESON_PIN(GPIOM_8), | |
| + MESON_PIN(GPIOM_9), | |
| + MESON_PIN(GPIOM_10), | |
| + MESON_PIN(GPIOM_11), | |
| + MESON_PIN(GPIOM_12), | |
| + MESON_PIN(GPIOM_13), | |
| + | |
| + MESON_PIN(GPIOY_0), | |
| + MESON_PIN(GPIOY_1), | |
| + MESON_PIN(GPIOY_2), | |
| + MESON_PIN(GPIOY_3), | |
| + MESON_PIN(GPIOY_4), | |
| + MESON_PIN(GPIOY_5), | |
| + MESON_PIN(GPIOY_6), | |
| + MESON_PIN(GPIOY_7), | |
| + MESON_PIN(GPIOY_8), | |
| + MESON_PIN(GPIOY_9), | |
| + MESON_PIN(GPIOY_10), | |
| + MESON_PIN(GPIOY_11), | |
| + MESON_PIN(GPIOY_12), | |
| + MESON_PIN(GPIOY_13), | |
| + MESON_PIN(GPIOY_14), | |
| + MESON_PIN(GPIOY_15), | |
| + MESON_PIN(GPIOY_16), | |
| + MESON_PIN(GPIOY_17), | |
| + MESON_PIN(GPIOY_18), | |
| + | |
| + MESON_PIN(GPIOH_0), | |
| + MESON_PIN(GPIOH_1), | |
| + MESON_PIN(GPIOH_2), | |
| + MESON_PIN(GPIOH_3), | |
| + MESON_PIN(GPIOH_4), | |
| + MESON_PIN(GPIOH_5), | |
| + MESON_PIN(GPIOH_6), | |
| + MESON_PIN(GPIOH_7), | |
| + | |
| + MESON_PIN(GPIO_TEST_N), | |
| +}; | |
| + | |
| +/* Bank B func1 */ | |
| +static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 }; | |
| +static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 }; | |
| +static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 }; | |
| +static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 }; | |
| +static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 }; | |
| +static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 }; | |
| +static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 }; | |
| +static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 }; | |
| +static const unsigned int emmc_clk_pins[] = { GPIOB_8 }; | |
| +static const unsigned int emmc_cmd_pins[] = { GPIOB_10 }; | |
| +static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 }; | |
| + | |
| +/* Bank B func2 */ | |
| +static const unsigned int nor_hold_pins[] = { GPIOB_3 }; | |
| +static const unsigned int nor_d_pins[] = { GPIOB_4 }; | |
| +static const unsigned int nor_q_pins[] = { GPIOB_5 }; | |
| +static const unsigned int nor_c_pins[] = { GPIOB_6 }; | |
| +static const unsigned int nor_wp_pins[] = { GPIOB_7 }; | |
| +static const unsigned int nor_cs_pins[] = { GPIOB_12 }; | |
| + | |
| +/* Bank C func1 */ | |
| +static const unsigned int sdcard_d0_pins[] = { GPIOC_0 }; | |
| +static const unsigned int sdcard_d1_pins[] = { GPIOC_1 }; | |
| +static const unsigned int sdcard_d2_pins[] = { GPIOC_2 }; | |
| +static const unsigned int sdcard_d3_pins[] = { GPIOC_3 }; | |
| +static const unsigned int sdcard_clk_pins[] = { GPIOC_4 }; | |
| +static const unsigned int sdcard_cmd_pins[] = { GPIOC_5 }; | |
| +static const unsigned int gen_clk_out_c_pins[] = { GPIOC_6 }; | |
| + | |
| +/* Bank C func2 */ | |
| +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 }; | |
| +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 }; | |
| +static const unsigned int uart_ao_a_rx_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int uart_ao_a_tx_c_pins[] = { GPIOC_3 }; | |
| +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 }; | |
| +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 }; | |
| + | |
| +/* Bank C func3 */ | |
| +static const unsigned int spi1_mosi_c_pins[] = { GPIOC_0 }; | |
| +static const unsigned int spi1_miso_c_pins[] = { GPIOC_1 }; | |
| +static const unsigned int spi1_sclk_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int spi1_ss0_c_pins[] = { GPIOC_3 }; | |
| + | |
| +/* Bank X func1 */ | |
| +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; | |
| +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; | |
| +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; | |
| +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; | |
| +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; | |
| +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; | |
| +static const unsigned int pwm_b_pins[] = { GPIOX_6 }; | |
| +static const unsigned int pwm_c_pins[] = { GPIOX_7 }; | |
| +static const unsigned int tdm_d0_pins[] = { GPIOX_8 }; | |
| +static const unsigned int tdm_d1_pins[] = { GPIOX_9 }; | |
| +static const unsigned int tdm_fs0_pins[] = { GPIOX_10 }; | |
| +static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 }; | |
| +static const unsigned int uart_c_tx_pins[] = { GPIOX_12 }; | |
| +static const unsigned int uart_c_rx_pins[] = { GPIOX_13 }; | |
| +static const unsigned int uart_c_cts_pins[] = { GPIOX_14 }; | |
| +static const unsigned int uart_c_rts_pins[] = { GPIOX_15 }; | |
| +static const unsigned int pwm_a_pins[] = { GPIOX_16 }; | |
| +static const unsigned int i2c2_sda_x_pins[] = { GPIOX_17 }; | |
| +static const unsigned int i2c2_sck_x_pins[] = { GPIOX_18 }; | |
| +static const unsigned int pwm_d_pins[] = { GPIOX_19 }; | |
| + | |
| +/* Bank X func2 */ | |
| +static const unsigned int clk12_24_x_pins[] = { GPIOX_14 }; | |
| + | |
| +/* Bank W func1 */ | |
| +static const unsigned int hdmirx_a_hpd_pins[] = { GPIOW_0 }; | |
| +static const unsigned int hdmirx_a_det_pins[] = { GPIOW_1 }; | |
| +static const unsigned int hdmirx_a_sda_pins[] = { GPIOW_2 }; | |
| +static const unsigned int hdmirx_a_sck_pins[] = { GPIOW_3 }; | |
| +static const unsigned int hdmirx_c_hpd_pins[] = { GPIOW_4 }; | |
| +static const unsigned int hdmirx_c_det_pins[] = { GPIOW_5 }; | |
| +static const unsigned int hdmirx_c_sda_pins[] = { GPIOW_6 }; | |
| +static const unsigned int hdmirx_c_sck_pins[] = { GPIOW_7 }; | |
| +static const unsigned int hdmirx_b_hpd_pins[] = { GPIOW_8 }; | |
| +static const unsigned int hdmirx_b_det_pins[] = { GPIOW_9 }; | |
| +static const unsigned int hdmirx_b_sda_pins[] = { GPIOW_10 }; | |
| +static const unsigned int hdmirx_b_sck_pins[] = { GPIOW_11 }; | |
| +static const unsigned int cec_a_pins[] = { GPIOW_12 }; | |
| +static const unsigned int hdmitx_sda_w13_pins[] = { GPIOW_13 }; | |
| +static const unsigned int hdmitx_sck_w14_pins[] = { GPIOW_14 }; | |
| +static const unsigned int hdmitx_hpd_in_pins[] = { GPIOW_15 }; | |
| +static const unsigned int cec_b_pins[] = { GPIOW_16 }; | |
| + | |
| +/* Bank W func2 */ | |
| +static const unsigned int uart_ao_a_tx_w2_pins[] = { GPIOW_2 }; | |
| +static const unsigned int uart_ao_a_rx_w3_pins[] = { GPIOW_3 }; | |
| +static const unsigned int uart_ao_a_tx_w6_pins[] = { GPIOW_6 }; | |
| +static const unsigned int uart_ao_a_rx_w7_pins[] = { GPIOW_7 }; | |
| +static const unsigned int uart_ao_a_tx_w10_pins[] = { GPIOW_10 }; | |
| +static const unsigned int uart_ao_a_rx_w11_pins[] = { GPIOW_11 }; | |
| + | |
| +/* Bank W func3 */ | |
| +static const unsigned int hdmitx_sda_w2_pins[] = { GPIOW_2 }; | |
| +static const unsigned int hdmitx_sck_w3_pins[] = { GPIOW_3 }; | |
| + | |
| +/* Bank D func1 */ | |
| +static const unsigned int uart_ao_a_tx_d0_pins[] = { GPIOD_0 }; | |
| +static const unsigned int uart_ao_a_rx_d1_pins[] = { GPIOD_1 }; | |
| +static const unsigned int i2c0_ao_sck_d_pins[] = { GPIOD_2 }; | |
| +static const unsigned int i2c0_ao_sda_d_pins[] = { GPIOD_3 }; | |
| +static const unsigned int remote_out_d4_pins[] = { GPIOD_4 }; | |
| +static const unsigned int remote_in_pins[] = { GPIOD_5 }; | |
| +static const unsigned int jtag_a_clk_pins[] = { GPIOD_6 }; | |
| +static const unsigned int jtag_a_tms_pins[] = { GPIOD_7 }; | |
| +static const unsigned int jtag_a_tdi_pins[] = { GPIOD_8 }; | |
| +static const unsigned int jtag_a_tdo_pins[] = { GPIOD_9 }; | |
| +static const unsigned int gen_clk_out_d_pins[] = { GPIOD_10 }; | |
| +static const unsigned int pwm_ao_g_d11_pins[] = { GPIOD_11 }; | |
| +static const unsigned int wd_rsto_pins[] = { GPIOD_12 }; | |
| + | |
| +/* Bank D func2 */ | |
| +static const unsigned int i2c0_slave_ao_sck_pins[] = { GPIOD_2 }; | |
| +static const unsigned int i2c0_slave_ao_sda_pins[] = { GPIOD_3 }; | |
| +static const unsigned int rtc_clk_in_pins[] = { GPIOD_4 }; | |
| +static const unsigned int pwm_ao_h_d5_pins[] = { GPIOD_5 }; | |
| +static const unsigned int pwm_ao_c_d_pins[] = { GPIOD_6 }; | |
| +static const unsigned int pwm_ao_g_d7_pins[] = { GPIOD_7 }; | |
| +static const unsigned int spdif_out_d_pins[] = { GPIOD_8 }; | |
| +static const unsigned int spdif_in_d_pins[] = { GPIOD_9 }; | |
| +static const unsigned int pwm_ao_h_d10_pins[] = { GPIOD_10 }; | |
| + | |
| +/* Bank D func3 */ | |
| +static const unsigned int uart_ao_b_tx_pins[] = { GPIOD_2 }; | |
| +static const unsigned int uart_ao_b_rx_pins[] = { GPIOD_3 }; | |
| +static const unsigned int uart_ao_b_cts_pins[] = { GPIOD_4 }; | |
| +static const unsigned int pwm_ao_c_hiz_pins[] = { GPIOD_6 }; | |
| +static const unsigned int pwm_ao_g_hiz_pins[] = { GPIOD_7 }; | |
| +static const unsigned int uart_ao_b_rts_pins[] = { GPIOD_10 }; | |
| + | |
| +/* Bank D func4 */ | |
| +static const unsigned int remote_out_d6_pins[] = { GPIOD_6 }; | |
| + | |
| +/* Bank E func1 */ | |
| +static const unsigned int pwm_ao_a_pins[] = { GPIOE_0 }; | |
| +static const unsigned int pwm_ao_b_pins[] = { GPIOE_1 }; | |
| +static const unsigned int pwm_ao_c_e_pins[] = { GPIOE_2 }; | |
| +static const unsigned int pwm_ao_d_pins[] = { GPIOE_3 }; | |
| +static const unsigned int pwm_ao_e_pins[] = { GPIOE_4 }; | |
| +static const unsigned int pwm_ao_f_pins[] = { GPIOE_5 }; | |
| +static const unsigned int pwm_ao_g_e_pins[] = { GPIOE_6 }; | |
| + | |
| +/* Bank E func2 */ | |
| +static const unsigned int i2c0_ao_sck_e_pins[] = { GPIOE_0 }; | |
| +static const unsigned int i2c0_ao_sda_e_pins[] = { GPIOE_1 }; | |
| +static const unsigned int clk25m_pins[] = { GPIOE_2 }; | |
| +static const unsigned int i2c1_ao_sck_pins[] = { GPIOE_3 }; | |
| +static const unsigned int i2c1_ao_sda_pins[] = { GPIOE_4 }; | |
| +static const unsigned int rtc_clk_out_pins[] = { GPIOD_5 }; | |
| + | |
| +/* Bank E func3 */ | |
| +static const unsigned int clk12_24_e_pins[] = { GPIOE_4 }; | |
| + | |
| +/* Bank Z func1 */ | |
| +static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int eth_rgmii_rx_clk_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 }; | |
| +static const unsigned int eth_txen_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int eth_txd0_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int eth_txd1_pins[] = { GPIOZ_11 }; | |
| +static const unsigned int eth_txd2_rgmii_pins[] = { GPIOZ_12 }; | |
| +static const unsigned int eth_txd3_rgmii_pins[] = { GPIOZ_13 }; | |
| + | |
| +/* Bank Z func2 */ | |
| +static const unsigned int iso7816_clk_z_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int iso7816_data_z_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int tsin_b_valid_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int tsin_b_sop_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int tsin_b_din0_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int tsin_b_clk_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int tsin_b_fail_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int tsin_b_din1_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int tsin_b_din2_pins[] = { GPIOZ_8 }; | |
| +static const unsigned int tsin_b_din3_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int tsin_b_din4_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int tsin_b_din5_pins[] = { GPIOZ_11 }; | |
| +static const unsigned int tsin_b_din6_pins[] = { GPIOZ_12 }; | |
| +static const unsigned int tsin_b_din7_pins[] = { GPIOZ_13 }; | |
| + | |
| +/* Bank Z func3 */ | |
| +static const unsigned int tsin_c_z_valid_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int tsin_c_z_sop_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int tsin_c_z_din0_pins[] = { GPIOZ_8 }; | |
| +static const unsigned int tsin_c_z_clk_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int tsin_d_z_valid_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int tsin_d_z_sop_pins[] = { GPIOZ_11 }; | |
| +static const unsigned int tsin_d_z_din0_pins[] = { GPIOZ_12 }; | |
| +static const unsigned int tsin_d_z_clk_pins[] = { GPIOZ_13 }; | |
| + | |
| +/* Bank Z func4 */ | |
| +static const unsigned int spi4_mosi_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int spi4_miso_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int spi4_sclk_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int spi4_ss0_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int spi5_mosi_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int spi5_miso_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int spi5_sclk_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int spi5_ss0_pins[] = { GPIOZ_7 }; | |
| + | |
| +/* Bank T func1 */ | |
| +static const unsigned int mclk1_pins[] = { GPIOT_0 }; | |
| +static const unsigned int tdm_sclk1_pins[] = { GPIOT_1 }; | |
| +static const unsigned int tdm_fs1_pins[] = { GPIOT_2 }; | |
| +static const unsigned int tdm_d2_pins[] = { GPIOT_3 }; | |
| +static const unsigned int tdm_d3_pins[] = { GPIOT_4 }; | |
| +static const unsigned int tdm_d4_pins[] = { GPIOT_5 }; | |
| +static const unsigned int tdm_d5_pins[] = { GPIOT_6 }; | |
| +static const unsigned int tdm_d6_pins[] = { GPIOT_7 }; | |
| +static const unsigned int tdm_d7_pins[] = { GPIOT_8 }; | |
| +static const unsigned int tdm_d8_pins[] = { GPIOT_9 }; | |
| +static const unsigned int tdm_d9_pins[] = { GPIOT_10 }; | |
| +static const unsigned int tdm_d10_pins[] = { GPIOT_11 }; | |
| +static const unsigned int tdm_d11_pins[] = { GPIOT_12 }; | |
| +static const unsigned int mclk2_pins[] = { GPIOT_13 }; | |
| +static const unsigned int tdm_sclk2_pins[] = { GPIOT_14 }; | |
| +static const unsigned int tdm_fs2_pins[] = { GPIOT_15 }; | |
| +static const unsigned int i2c1_sck_pins[] = { GPIOT_16 }; | |
| +static const unsigned int i2c1_sda_pins[] = { GPIOT_17 }; | |
| +static const unsigned int spi0_mosi_pins[] = { GPIOT_18 }; | |
| +static const unsigned int spi0_miso_pins[] = { GPIOT_19 }; | |
| +static const unsigned int spi0_sclk_pins[] = { GPIOT_20 }; | |
| +static const unsigned int spi0_ss0_pins[] = { GPIOT_21 }; | |
| +static const unsigned int spi0_ss1_pins[] = { GPIOT_22 }; | |
| +static const unsigned int spi0_ss2_pins[] = { GPIOT_23 }; | |
| + | |
| +/* Bank T func2 */ | |
| +static const unsigned int spdif_in_t_pins[] = { GPIOT_3 }; | |
| +static const unsigned int spdif_out_t_pins[] = { GPIOT_4 }; | |
| +static const unsigned int iso7816_clk_t_pins[] = { GPIOT_5 }; | |
| +static const unsigned int iso7816_data_t_pins[] = { GPIOT_6 }; | |
| +static const unsigned int tsin_a_sop_t_pins[] = { GPIOT_7 }; | |
| +static const unsigned int tsin_a_din0_t_pins[] = { GPIOT_8 }; | |
| +static const unsigned int tsin_a_clk_t_pins[] = { GPIOT_9 }; | |
| +static const unsigned int tsin_a_valid_t_pins[] = { GPIOT_10 }; | |
| +static const unsigned int i2c0_sck_t_pins[] = { GPIOT_20 }; | |
| +static const unsigned int i2c0_sda_t_pins[] = { GPIOT_21 }; | |
| +static const unsigned int i2c2_sck_t_pins[] = { GPIOT_22 }; | |
| +static const unsigned int i2c2_sda_t_pins[] = { GPIOT_23 }; | |
| + | |
| +/* Bank T func3 */ | |
| +static const unsigned int spi3_mosi_pins[] = { GPIOT_6 }; | |
| +static const unsigned int spi3_miso_pins[] = { GPIOT_7 }; | |
| +static const unsigned int spi3_sclk_pins[] = { GPIOT_8 }; | |
| +static const unsigned int spi3_ss0_pins[] = { GPIOT_9 }; | |
| + | |
| +/* Bank M func1 */ | |
| +static const unsigned int tdm_d12_pins[] = { GPIOM_0 }; | |
| +static const unsigned int tdm_d13_pins[] = { GPIOM_1 }; | |
| +static const unsigned int tdm_d14_pins[] = { GPIOM_2 }; | |
| +static const unsigned int tdm_d15_pins[] = { GPIOM_3 }; | |
| +static const unsigned int tdm_sclk3_pins[] = { GPIOM_4 }; | |
| +static const unsigned int tdm_fs3_pins[] = { GPIOM_5 }; | |
| +static const unsigned int i2c3_sda_m_pins[] = { GPIOM_6 }; | |
| +static const unsigned int i2c3_sck_m_pins[] = { GPIOM_7 }; | |
| +static const unsigned int spi1_mosi_m_pins[] = { GPIOM_8 }; | |
| +static const unsigned int spi1_miso_m_pins[] = { GPIOM_9 }; | |
| +static const unsigned int spi1_sclk_m_pins[] = { GPIOM_10 }; | |
| +static const unsigned int spi1_ss0_m_pins[] = { GPIOM_11 }; | |
| +static const unsigned int spi1_ss1_m_pins[] = { GPIOM_12 }; | |
| +static const unsigned int spi1_ss2_m_pins[] = { GPIOM_13 }; | |
| + | |
| +/* Bank M func2 */ | |
| +static const unsigned int pdm_din1_m0_pins[] = { GPIOM_0 }; | |
| +static const unsigned int pdm_din2_pins[] = { GPIOM_1 }; | |
| +static const unsigned int pdm_din3_pins[] = { GPIOM_2 }; | |
| +static const unsigned int pdm_dclk_pins[] = { GPIOM_3 }; | |
| +static const unsigned int pdm_din0_pins[] = { GPIOM_4 }; | |
| +static const unsigned int pdm_din1_m5_pins[] = { GPIOM_5 }; | |
| +static const unsigned int uart_d_tx_m_pins[] = { GPIOM_8 }; | |
| +static const unsigned int uart_d_rx_m_pins[] = { GPIOM_9 }; | |
| +static const unsigned int uart_d_cts_m_pins[] = { GPIOM_10 }; | |
| +static const unsigned int uart_d_rts_m_pins[] = { GPIOM_11 }; | |
| +static const unsigned int i2c2_sda_m_pins[] = { GPIOM_12 }; | |
| +static const unsigned int i2c2_sck_m_pins[] = { GPIOM_13 }; | |
| + | |
| +/* Bank Y func1 */ | |
| +static const unsigned int spi2_mosi_pins[] = { GPIOY_0 }; | |
| +static const unsigned int spi2_miso_pins[] = { GPIOY_1 }; | |
| +static const unsigned int spi2_sclk_pins[] = { GPIOY_2 }; | |
| +static const unsigned int spi2_ss0_pins[] = { GPIOY_3 }; | |
| +static const unsigned int spi2_ss1_pins[] = { GPIOY_4 }; | |
| +static const unsigned int spi2_ss2_pins[] = { GPIOY_5 }; | |
| +static const unsigned int uart_e_tx_pins[] = { GPIOY_6 }; | |
| +static const unsigned int uart_e_rx_pins[] = { GPIOY_7 }; | |
| +static const unsigned int uart_e_cts_pins[] = { GPIOY_8 }; | |
| +static const unsigned int uart_e_rts_pins[] = { GPIOY_9 }; | |
| +static const unsigned int uart_d_cts_y_pins[] = { GPIOY_10 }; | |
| +static const unsigned int uart_d_rts_y_pins[] = { GPIOY_11 }; | |
| +static const unsigned int uart_d_tx_y_pins[] = { GPIOY_12 }; | |
| +static const unsigned int uart_d_rx_y_pins[] = { GPIOY_13 }; | |
| +static const unsigned int i2c4_sck_y_pins[] = { GPIOY_15 }; | |
| +static const unsigned int i2c4_sda_y_pins[] = { GPIOY_16 }; | |
| +static const unsigned int i2c5_sck_pins[] = { GPIOY_17 }; | |
| +static const unsigned int i2c5_sda_pins[] = { GPIOY_18 }; | |
| + | |
| +/* Bank Y func2 */ | |
| +static const unsigned int tsin_c_y_sop_pins[] = { GPIOY_4 }; | |
| +static const unsigned int tsin_c_y_din0_pins[] = { GPIOY_5 }; | |
| +static const unsigned int tsin_c_y_clk_pins[] = { GPIOY_6 }; | |
| +static const unsigned int tsin_c_y_valid_pins[] = { GPIOY_7 }; | |
| +static const unsigned int tsin_d_y_sop_pins[] = { GPIOY_8 }; | |
| +static const unsigned int tsin_d_y_din0_pins[] = { GPIOY_9 }; | |
| +static const unsigned int tsin_d_y_clk_pins[] = { GPIOY_10 }; | |
| +static const unsigned int tsin_d_y_valid_pins[] = { GPIOY_11 }; | |
| +static const unsigned int pcieck_reqn_y_pins[] = { GPIOY_18 }; | |
| + | |
| +/* Bank Y func3 */ | |
| +static const unsigned int pwm_e_pins[] = { GPIOY_1 }; | |
| +static const unsigned int hsync_pins[] = { GPIOY_4 }; | |
| +static const unsigned int vsync_pins[] = { GPIOY_5 }; | |
| +static const unsigned int pwm_f_pins[] = { GPIOY_8 }; | |
| +static const unsigned int sync_3d_out_pins[] = { GPIOY_9 }; | |
| +static const unsigned int vx1_a_htpdn_pins[] = { GPIOY_10 }; | |
| +static const unsigned int vx1_b_htpdn_pins[] = { GPIOY_11 }; | |
| +static const unsigned int vx1_a_lockn_pins[] = { GPIOY_12 }; | |
| +static const unsigned int vx1_b_lockn_pins[] = { GPIOY_13 }; | |
| +static const unsigned int pwm_vs_y_pins[] = { GPIOY_14 }; | |
| + | |
| +/* Bank Y func4 */ | |
| +static const unsigned int edp_a_hpd_pins[] = { GPIOY_10 }; | |
| +static const unsigned int edp_b_hpd_pins[] = { GPIOY_11 }; | |
| + | |
| +/* Bank H func1 */ | |
| +static const unsigned int mic_mute_key_pins[] = { GPIOH_0 }; | |
| +static const unsigned int mic_mute_led_pins[] = { GPIOH_1 }; | |
| +static const unsigned int i2c3_sck_h_pins[] = { GPIOH_2 }; | |
| +static const unsigned int i2c3_sda_h_pins[] = { GPIOH_3 }; | |
| +static const unsigned int i2c4_sck_h_pins[] = { GPIOH_4 }; | |
| +static const unsigned int i2c4_sda_h_pins[] = { GPIOH_5 }; | |
| +static const unsigned int eth_link_led_pins[] = { GPIOH_6 }; | |
| +static const unsigned int eth_act_led_pins[] = { GPIOH_7 }; | |
| + | |
| +/* Bank H func2 */ | |
| +static const unsigned int pwm_vs_h_pins[] = { GPIOH_1 }; | |
| +static const unsigned int uart_f_tx_pins[] = { GPIOH_2 }; | |
| +static const unsigned int uart_f_rx_pins[] = { GPIOH_3 }; | |
| +static const unsigned int uart_f_cts_pins[] = { GPIOH_4 }; | |
| +static const unsigned int uart_f_rts_pins[] = { GPIOH_5 }; | |
| +static const unsigned int i2c0_sda_h_pins[] = { GPIOH_6 }; | |
| +static const unsigned int i2c0_sck_h_pins[] = { GPIOH_7 }; | |
| + | |
| +/* Bank H func3 */ | |
| +static const unsigned int pcieck_reqn_h_pins[] = { GPIOH_2 }; | |
| + | |
| +static const struct meson_pmx_group t7_periphs_groups[] = { | |
| + GPIO_GROUP(GPIOB_0), | |
| + GPIO_GROUP(GPIOB_1), | |
| + GPIO_GROUP(GPIOB_2), | |
| + GPIO_GROUP(GPIOB_3), | |
| + GPIO_GROUP(GPIOB_4), | |
| + GPIO_GROUP(GPIOB_5), | |
| + GPIO_GROUP(GPIOB_6), | |
| + GPIO_GROUP(GPIOB_7), | |
| + GPIO_GROUP(GPIOB_8), | |
| + GPIO_GROUP(GPIOB_9), | |
| + GPIO_GROUP(GPIOB_10), | |
| + GPIO_GROUP(GPIOB_11), | |
| + GPIO_GROUP(GPIOB_12), | |
| + | |
| + GPIO_GROUP(GPIOC_0), | |
| + GPIO_GROUP(GPIOC_1), | |
| + GPIO_GROUP(GPIOC_2), | |
| + GPIO_GROUP(GPIOC_3), | |
| + GPIO_GROUP(GPIOC_4), | |
| + GPIO_GROUP(GPIOC_5), | |
| + GPIO_GROUP(GPIOC_6), | |
| + | |
| + GPIO_GROUP(GPIOX_0), | |
| + GPIO_GROUP(GPIOX_1), | |
| + GPIO_GROUP(GPIOX_2), | |
| + GPIO_GROUP(GPIOX_3), | |
| + GPIO_GROUP(GPIOX_4), | |
| + GPIO_GROUP(GPIOX_5), | |
| + GPIO_GROUP(GPIOX_6), | |
| + GPIO_GROUP(GPIOX_7), | |
| + GPIO_GROUP(GPIOX_8), | |
| + GPIO_GROUP(GPIOX_9), | |
| + GPIO_GROUP(GPIOX_10), | |
| + GPIO_GROUP(GPIOX_11), | |
| + GPIO_GROUP(GPIOX_12), | |
| + GPIO_GROUP(GPIOX_13), | |
| + GPIO_GROUP(GPIOX_14), | |
| + GPIO_GROUP(GPIOX_15), | |
| + GPIO_GROUP(GPIOX_16), | |
| + GPIO_GROUP(GPIOX_17), | |
| + GPIO_GROUP(GPIOX_18), | |
| + GPIO_GROUP(GPIOX_19), | |
| + | |
| + GPIO_GROUP(GPIOW_0), | |
| + GPIO_GROUP(GPIOW_1), | |
| + GPIO_GROUP(GPIOW_2), | |
| + GPIO_GROUP(GPIOW_3), | |
| + GPIO_GROUP(GPIOW_4), | |
| + GPIO_GROUP(GPIOW_5), | |
| + GPIO_GROUP(GPIOW_6), | |
| + GPIO_GROUP(GPIOW_7), | |
| + GPIO_GROUP(GPIOW_8), | |
| + GPIO_GROUP(GPIOW_9), | |
| + GPIO_GROUP(GPIOW_10), | |
| + GPIO_GROUP(GPIOW_11), | |
| + GPIO_GROUP(GPIOW_12), | |
| + GPIO_GROUP(GPIOW_13), | |
| + GPIO_GROUP(GPIOW_14), | |
| + GPIO_GROUP(GPIOW_15), | |
| + GPIO_GROUP(GPIOW_16), | |
| + | |
| + GPIO_GROUP(GPIOD_0), | |
| + GPIO_GROUP(GPIOD_1), | |
| + GPIO_GROUP(GPIOD_2), | |
| + GPIO_GROUP(GPIOD_3), | |
| + GPIO_GROUP(GPIOD_4), | |
| + GPIO_GROUP(GPIOD_5), | |
| + GPIO_GROUP(GPIOD_6), | |
| + GPIO_GROUP(GPIOD_7), | |
| + GPIO_GROUP(GPIOD_8), | |
| + GPIO_GROUP(GPIOD_9), | |
| + GPIO_GROUP(GPIOD_10), | |
| + GPIO_GROUP(GPIOD_11), | |
| + GPIO_GROUP(GPIOD_12), | |
| + | |
| + GPIO_GROUP(GPIOE_0), | |
| + GPIO_GROUP(GPIOE_1), | |
| + GPIO_GROUP(GPIOE_2), | |
| + GPIO_GROUP(GPIOE_3), | |
| + GPIO_GROUP(GPIOE_4), | |
| + GPIO_GROUP(GPIOE_5), | |
| + GPIO_GROUP(GPIOE_6), | |
| + | |
| + GPIO_GROUP(GPIOZ_0), | |
| + GPIO_GROUP(GPIOZ_1), | |
| + GPIO_GROUP(GPIOZ_2), | |
| + GPIO_GROUP(GPIOZ_3), | |
| + GPIO_GROUP(GPIOZ_4), | |
| + GPIO_GROUP(GPIOZ_5), | |
| + GPIO_GROUP(GPIOZ_6), | |
| + GPIO_GROUP(GPIOZ_7), | |
| + GPIO_GROUP(GPIOZ_8), | |
| + GPIO_GROUP(GPIOZ_9), | |
| + GPIO_GROUP(GPIOZ_10), | |
| + GPIO_GROUP(GPIOZ_11), | |
| + GPIO_GROUP(GPIOZ_12), | |
| + GPIO_GROUP(GPIOZ_13), | |
| + | |
| + GPIO_GROUP(GPIOT_0), | |
| + GPIO_GROUP(GPIOT_1), | |
| + GPIO_GROUP(GPIOT_2), | |
| + GPIO_GROUP(GPIOT_3), | |
| + GPIO_GROUP(GPIOT_4), | |
| + GPIO_GROUP(GPIOT_5), | |
| + GPIO_GROUP(GPIOT_6), | |
| + GPIO_GROUP(GPIOT_7), | |
| + GPIO_GROUP(GPIOT_8), | |
| + GPIO_GROUP(GPIOT_9), | |
| + GPIO_GROUP(GPIOT_10), | |
| + GPIO_GROUP(GPIOT_11), | |
| + GPIO_GROUP(GPIOT_12), | |
| + GPIO_GROUP(GPIOT_13), | |
| + GPIO_GROUP(GPIOT_14), | |
| + GPIO_GROUP(GPIOT_15), | |
| + GPIO_GROUP(GPIOT_16), | |
| + GPIO_GROUP(GPIOT_17), | |
| + GPIO_GROUP(GPIOT_18), | |
| + GPIO_GROUP(GPIOT_19), | |
| + GPIO_GROUP(GPIOT_20), | |
| + GPIO_GROUP(GPIOT_21), | |
| + GPIO_GROUP(GPIOT_22), | |
| + GPIO_GROUP(GPIOT_23), | |
| + | |
| + GPIO_GROUP(GPIOM_0), | |
| + GPIO_GROUP(GPIOM_1), | |
| + GPIO_GROUP(GPIOM_2), | |
| + GPIO_GROUP(GPIOM_3), | |
| + GPIO_GROUP(GPIOM_4), | |
| + GPIO_GROUP(GPIOM_5), | |
| + GPIO_GROUP(GPIOM_6), | |
| + GPIO_GROUP(GPIOM_7), | |
| + GPIO_GROUP(GPIOM_8), | |
| + GPIO_GROUP(GPIOM_9), | |
| + GPIO_GROUP(GPIOM_10), | |
| + GPIO_GROUP(GPIOM_11), | |
| + GPIO_GROUP(GPIOM_12), | |
| + GPIO_GROUP(GPIOM_13), | |
| + | |
| + GPIO_GROUP(GPIOY_0), | |
| + GPIO_GROUP(GPIOY_1), | |
| + GPIO_GROUP(GPIOY_2), | |
| + GPIO_GROUP(GPIOY_3), | |
| + GPIO_GROUP(GPIOY_4), | |
| + GPIO_GROUP(GPIOY_5), | |
| + GPIO_GROUP(GPIOY_6), | |
| + GPIO_GROUP(GPIOY_7), | |
| + GPIO_GROUP(GPIOY_8), | |
| + GPIO_GROUP(GPIOY_9), | |
| + GPIO_GROUP(GPIOY_10), | |
| + GPIO_GROUP(GPIOY_11), | |
| + GPIO_GROUP(GPIOY_12), | |
| + GPIO_GROUP(GPIOY_13), | |
| + GPIO_GROUP(GPIOY_14), | |
| + GPIO_GROUP(GPIOY_15), | |
| + GPIO_GROUP(GPIOY_16), | |
| + GPIO_GROUP(GPIOY_17), | |
| + GPIO_GROUP(GPIOY_18), | |
| + | |
| + GPIO_GROUP(GPIOH_0), | |
| + GPIO_GROUP(GPIOH_1), | |
| + GPIO_GROUP(GPIOH_2), | |
| + GPIO_GROUP(GPIOH_3), | |
| + GPIO_GROUP(GPIOH_4), | |
| + GPIO_GROUP(GPIOH_5), | |
| + GPIO_GROUP(GPIOH_6), | |
| + GPIO_GROUP(GPIOH_7), | |
| + GPIO_GROUP(GPIO_TEST_N), | |
| + | |
| + /* Bank B func1 */ | |
| + GROUP(emmc_nand_d0, 1), | |
| + GROUP(emmc_nand_d1, 1), | |
| + GROUP(emmc_nand_d2, 1), | |
| + GROUP(emmc_nand_d3, 1), | |
| + GROUP(emmc_nand_d4, 1), | |
| + GROUP(emmc_nand_d5, 1), | |
| + GROUP(emmc_nand_d6, 1), | |
| + GROUP(emmc_nand_d7, 1), | |
| + GROUP(emmc_clk, 1), | |
| + GROUP(emmc_cmd, 1), | |
| + GROUP(emmc_nand_ds, 1), | |
| + | |
| + /* Bank B func1 */ | |
| + GROUP(nor_hold, 2), | |
| + GROUP(nor_d, 2), | |
| + GROUP(nor_q, 2), | |
| + GROUP(nor_c, 2), | |
| + GROUP(nor_wp, 2), | |
| + GROUP(nor_cs, 2), | |
| + | |
| + /* Bank C func1 */ | |
| + GROUP(sdcard_d0, 1), | |
| + GROUP(sdcard_d1, 1), | |
| + GROUP(sdcard_d2, 1), | |
| + GROUP(sdcard_d3, 1), | |
| + GROUP(sdcard_clk, 1), | |
| + GROUP(sdcard_cmd, 1), | |
| + GROUP(gen_clk_out_c, 1), | |
| + | |
| + /* Bank C func2 */ | |
| + GROUP(jtag_b_tdo, 2), | |
| + GROUP(jtag_b_tdi, 2), | |
| + GROUP(uart_ao_a_rx_c, 2), | |
| + GROUP(uart_ao_a_tx_c, 2), | |
| + GROUP(jtag_b_clk, 2), | |
| + GROUP(jtag_b_tms, 2), | |
| + | |
| + /* Bank C func3 */ | |
| + GROUP(spi1_mosi_c, 3), | |
| + GROUP(spi1_miso_c, 3), | |
| + GROUP(spi1_sclk_c, 3), | |
| + GROUP(spi1_ss0_c, 3), | |
| + | |
| + /* Bank X func1 */ | |
| + GROUP(sdio_d0, 1), | |
| + GROUP(sdio_d1, 1), | |
| + GROUP(sdio_d2, 1), | |
| + GROUP(sdio_d3, 1), | |
| + GROUP(sdio_clk, 1), | |
| + GROUP(sdio_cmd, 1), | |
| + GROUP(pwm_b, 1), | |
| + GROUP(pwm_c, 1), | |
| + GROUP(tdm_d0, 1), | |
| + GROUP(tdm_d1, 1), | |
| + GROUP(tdm_fs0, 1), | |
| + GROUP(tdm_sclk0, 1), | |
| + GROUP(uart_c_tx, 1), | |
| + GROUP(uart_c_rx, 1), | |
| + GROUP(uart_c_cts, 1), | |
| + GROUP(uart_c_rts, 1), | |
| + GROUP(pwm_a, 1), | |
| + GROUP(i2c2_sda_x, 1), | |
| + GROUP(i2c2_sck_x, 1), | |
| + GROUP(pwm_d, 1), | |
| + | |
| + /* Bank X func2 */ | |
| + GROUP(clk12_24_x, 2), | |
| + | |
| + /* Bank W func1 */ | |
| + GROUP(hdmirx_a_hpd, 1), | |
| + GROUP(hdmirx_a_det, 1), | |
| + GROUP(hdmirx_a_sda, 1), | |
| + GROUP(hdmirx_a_sck, 1), | |
| + GROUP(hdmirx_c_hpd, 1), | |
| + GROUP(hdmirx_c_det, 1), | |
| + GROUP(hdmirx_c_sda, 1), | |
| + GROUP(hdmirx_c_sck, 1), | |
| + GROUP(hdmirx_b_hpd, 1), | |
| + GROUP(hdmirx_b_det, 1), | |
| + GROUP(hdmirx_b_sda, 1), | |
| + GROUP(hdmirx_b_sck, 1), | |
| + GROUP(cec_a, 1), | |
| + GROUP(hdmitx_sda_w13, 1), | |
| + GROUP(hdmitx_sck_w14, 1), | |
| + GROUP(hdmitx_hpd_in, 1), | |
| + GROUP(cec_b, 1), | |
| + | |
| + /* Bank W func2 */ | |
| + GROUP(uart_ao_a_tx_w2, 2), | |
| + GROUP(uart_ao_a_rx_w3, 2), | |
| + GROUP(uart_ao_a_tx_w6, 2), | |
| + GROUP(uart_ao_a_rx_w7, 2), | |
| + GROUP(uart_ao_a_tx_w10, 2), | |
| + GROUP(uart_ao_a_rx_w11, 2), | |
| + | |
| + /* Bank W func3 */ | |
| + GROUP(hdmitx_sda_w2, 3), | |
| + GROUP(hdmitx_sck_w3, 3), | |
| + | |
| + /* Bank D func1 */ | |
| + GROUP(uart_ao_a_tx_d0, 1), | |
| + GROUP(uart_ao_a_rx_d1, 1), | |
| + GROUP(i2c0_ao_sck_d, 1), | |
| + GROUP(i2c0_ao_sda_d, 1), | |
| + GROUP(remote_out_d4, 1), | |
| + GROUP(remote_in, 1), | |
| + GROUP(jtag_a_clk, 1), | |
| + GROUP(jtag_a_tms, 1), | |
| + GROUP(jtag_a_tdi, 1), | |
| + GROUP(jtag_a_tdo, 1), | |
| + GROUP(gen_clk_out_d, 1), | |
| + GROUP(pwm_ao_g_d11, 1), | |
| + GROUP(wd_rsto, 1), | |
| + | |
| + /* Bank D func2 */ | |
| + GROUP(i2c0_slave_ao_sck, 2), | |
| + GROUP(i2c0_slave_ao_sda, 2), | |
| + GROUP(rtc_clk_in, 2), | |
| + GROUP(pwm_ao_h_d5, 2), | |
| + GROUP(pwm_ao_c_d, 2), | |
| + GROUP(pwm_ao_g_d7, 2), | |
| + GROUP(spdif_out_d, 2), | |
| + GROUP(spdif_in_d, 2), | |
| + GROUP(pwm_ao_h_d10, 2), | |
| + | |
| + /* Bank D func3 */ | |
| + GROUP(uart_ao_b_tx, 3), | |
| + GROUP(uart_ao_b_rx, 3), | |
| + GROUP(uart_ao_b_cts, 3), | |
| + GROUP(pwm_ao_c_hiz, 3), | |
| + GROUP(pwm_ao_g_hiz, 3), | |
| + GROUP(uart_ao_b_rts, 3), | |
| + | |
| + /* Bank D func4 */ | |
| + GROUP(remote_out_d6, 4), | |
| + | |
| + /* Bank E func1 */ | |
| + GROUP(pwm_ao_a, 1), | |
| + GROUP(pwm_ao_b, 1), | |
| + GROUP(pwm_ao_c_e, 1), | |
| + GROUP(pwm_ao_d, 1), | |
| + GROUP(pwm_ao_e, 1), | |
| + GROUP(pwm_ao_f, 1), | |
| + GROUP(pwm_ao_g_e, 1), | |
| + | |
| + /* Bank E func2 */ | |
| + GROUP(i2c0_ao_sck_e, 2), | |
| + GROUP(i2c0_ao_sda_e, 2), | |
| + GROUP(clk25m, 2), | |
| + GROUP(i2c1_ao_sck, 2), | |
| + GROUP(i2c1_ao_sda, 2), | |
| + GROUP(rtc_clk_out, 2), | |
| + | |
| + /* Bank E func3 */ | |
| + GROUP(clk12_24_e, 3), | |
| + | |
| + /* Bank Z func1 */ | |
| + GROUP(eth_mdio, 1), | |
| + GROUP(eth_mdc, 1), | |
| + GROUP(eth_rgmii_rx_clk, 1), | |
| + GROUP(eth_rx_dv, 1), | |
| + GROUP(eth_rxd0, 1), | |
| + GROUP(eth_rxd1, 1), | |
| + GROUP(eth_rxd2_rgmii, 1), | |
| + GROUP(eth_rxd3_rgmii, 1), | |
| + GROUP(eth_rgmii_tx_clk, 1), | |
| + GROUP(eth_txen, 1), | |
| + GROUP(eth_txd0, 1), | |
| + GROUP(eth_txd1, 1), | |
| + GROUP(eth_txd2_rgmii, 1), | |
| + GROUP(eth_txd3_rgmii, 1), | |
| + | |
| + /* Bank Z func2 */ | |
| + GROUP(iso7816_clk_z, 2), | |
| + GROUP(iso7816_data_z, 2), | |
| + GROUP(tsin_b_valid, 2), | |
| + GROUP(tsin_b_sop, 2), | |
| + GROUP(tsin_b_din0, 2), | |
| + GROUP(tsin_b_clk, 2), | |
| + GROUP(tsin_b_fail, 2), | |
| + GROUP(tsin_b_din1, 2), | |
| + GROUP(tsin_b_din2, 2), | |
| + GROUP(tsin_b_din3, 2), | |
| + GROUP(tsin_b_din4, 2), | |
| + GROUP(tsin_b_din5, 2), | |
| + GROUP(tsin_b_din6, 2), | |
| + GROUP(tsin_b_din7, 2), | |
| + | |
| + /* Bank Z func3 */ | |
| + GROUP(tsin_c_z_valid, 3), | |
| + GROUP(tsin_c_z_sop, 3), | |
| + GROUP(tsin_c_z_din0, 3), | |
| + GROUP(tsin_c_z_clk, 3), | |
| + GROUP(tsin_d_z_valid, 3), | |
| + GROUP(tsin_d_z_sop, 3), | |
| + GROUP(tsin_d_z_din0, 3), | |
| + GROUP(tsin_d_z_clk, 3), | |
| + | |
| + /* Bank Z func4 */ | |
| + GROUP(spi4_mosi, 4), | |
| + GROUP(spi4_miso, 4), | |
| + GROUP(spi4_sclk, 4), | |
| + GROUP(spi4_ss0, 4), | |
| + GROUP(spi5_mosi, 4), | |
| + GROUP(spi5_miso, 4), | |
| + GROUP(spi5_sclk, 4), | |
| + GROUP(spi5_ss0, 4), | |
| + | |
| + /* Bank T func1 */ | |
| + GROUP(mclk1, 1), | |
| + GROUP(tdm_sclk1, 1), | |
| + GROUP(tdm_fs1, 1), | |
| + GROUP(tdm_d2, 1), | |
| + GROUP(tdm_d3, 1), | |
| + GROUP(tdm_d4, 1), | |
| + GROUP(tdm_d5, 1), | |
| + GROUP(tdm_d6, 1), | |
| + GROUP(tdm_d7, 1), | |
| + GROUP(tdm_d8, 1), | |
| + GROUP(tdm_d9, 1), | |
| + GROUP(tdm_d10, 1), | |
| + GROUP(tdm_d11, 1), | |
| + GROUP(mclk2, 1), | |
| + GROUP(tdm_sclk2, 1), | |
| + GROUP(tdm_fs2, 1), | |
| + GROUP(i2c1_sck, 1), | |
| + GROUP(i2c1_sda, 1), | |
| + GROUP(spi0_mosi, 1), | |
| + GROUP(spi0_miso, 1), | |
| + GROUP(spi0_sclk, 1), | |
| + GROUP(spi0_ss0, 1), | |
| + GROUP(spi0_ss1, 1), | |
| + GROUP(spi0_ss2, 1), | |
| + | |
| + /* Bank T func2 */ | |
| + GROUP(spdif_in_t, 2), | |
| + GROUP(spdif_out_t, 2), | |
| + GROUP(iso7816_clk_t, 2), | |
| + GROUP(iso7816_data_t, 2), | |
| + GROUP(tsin_a_sop_t, 2), | |
| + GROUP(tsin_a_din0_t, 2), | |
| + GROUP(tsin_a_clk_t, 2), | |
| + GROUP(tsin_a_valid_t, 2), | |
| + GROUP(i2c0_sck_t, 2), | |
| + GROUP(i2c0_sda_t, 2), | |
| + GROUP(i2c2_sck_t, 2), | |
| + GROUP(i2c2_sda_t, 2), | |
| + | |
| + /* Bank T func3 */ | |
| + GROUP(spi3_mosi, 3), | |
| + GROUP(spi3_miso, 3), | |
| + GROUP(spi3_sclk, 3), | |
| + GROUP(spi3_ss0, 3), | |
| + | |
| + /* Bank M func1 */ | |
| + GROUP(tdm_d12, 1), | |
| + GROUP(tdm_d13, 1), | |
| + GROUP(tdm_d14, 1), | |
| + GROUP(tdm_d15, 1), | |
| + GROUP(tdm_sclk3, 1), | |
| + GROUP(tdm_fs3, 1), | |
| + GROUP(i2c3_sda_m, 1), | |
| + GROUP(i2c3_sck_m, 1), | |
| + GROUP(spi1_mosi_m, 1), | |
| + GROUP(spi1_miso_m, 1), | |
| + GROUP(spi1_sclk_m, 1), | |
| + GROUP(spi1_ss0_m, 1), | |
| + GROUP(spi1_ss1_m, 1), | |
| + GROUP(spi1_ss2_m, 1), | |
| + | |
| + /* Bank M func2 */ | |
| + GROUP(pdm_din1_m0, 2), | |
| + GROUP(pdm_din2, 2), | |
| + GROUP(pdm_din3, 2), | |
| + GROUP(pdm_dclk, 2), | |
| + GROUP(pdm_din0, 2), | |
| + GROUP(pdm_din1_m5, 2), | |
| + GROUP(uart_d_tx_m, 2), | |
| + GROUP(uart_d_rx_m, 2), | |
| + GROUP(uart_d_cts_m, 2), | |
| + GROUP(uart_d_rts_m, 2), | |
| + GROUP(i2c2_sda_m, 2), | |
| + GROUP(i2c2_sck_m, 2), | |
| + | |
| + /* Bank Y func1 */ | |
| + GROUP(spi2_mosi, 1), | |
| + GROUP(spi2_miso, 1), | |
| + GROUP(spi2_sclk, 1), | |
| + GROUP(spi2_ss0, 1), | |
| + GROUP(spi2_ss1, 1), | |
| + GROUP(spi2_ss2, 1), | |
| + GROUP(uart_e_tx, 1), | |
| + GROUP(uart_e_rx, 1), | |
| + GROUP(uart_e_cts, 1), | |
| + GROUP(uart_e_rts, 1), | |
| + GROUP(uart_d_cts_y, 1), | |
| + GROUP(uart_d_rts_y, 1), | |
| + GROUP(uart_d_tx_y, 1), | |
| + GROUP(uart_d_rx_y, 1), | |
| + GROUP(i2c4_sck_y, 1), | |
| + GROUP(i2c4_sda_y, 1), | |
| + GROUP(i2c5_sck, 1), | |
| + GROUP(i2c5_sda, 1), | |
| + | |
| + /* Bank Y func2 */ | |
| + GROUP(tsin_c_y_sop, 2), | |
| + GROUP(tsin_c_y_din0, 2), | |
| + GROUP(tsin_c_y_clk, 2), | |
| + GROUP(tsin_c_y_valid, 2), | |
| + GROUP(tsin_d_y_sop, 2), | |
| + GROUP(tsin_d_y_din0, 2), | |
| + GROUP(tsin_d_y_clk, 2), | |
| + GROUP(tsin_d_y_valid, 2), | |
| + GROUP(pcieck_reqn_y, 2), | |
| + | |
| + /* Bank Y func3 */ | |
| + GROUP(pwm_e, 3), | |
| + GROUP(hsync, 3), | |
| + GROUP(vsync, 3), | |
| + GROUP(pwm_f, 3), | |
| + GROUP(sync_3d_out, 3), | |
| + GROUP(vx1_a_htpdn, 3), | |
| + GROUP(vx1_b_htpdn, 3), | |
| + GROUP(vx1_a_lockn, 3), | |
| + GROUP(vx1_b_lockn, 3), | |
| + GROUP(pwm_vs_y, 3), | |
| + | |
| + /* Bank Y func4 */ | |
| + GROUP(edp_a_hpd, 4), | |
| + GROUP(edp_b_hpd, 4), | |
| + | |
| + /* Bank H func1 */ | |
| + GROUP(mic_mute_key, 1), | |
| + GROUP(mic_mute_led, 1), | |
| + GROUP(i2c3_sck_h, 1), | |
| + GROUP(i2c3_sda_h, 1), | |
| + GROUP(i2c4_sck_h, 1), | |
| + GROUP(i2c4_sda_h, 1), | |
| + GROUP(eth_link_led, 1), | |
| + GROUP(eth_act_led, 1), | |
| + | |
| + /* Bank H func2 */ | |
| + GROUP(pwm_vs_h, 2), | |
| + GROUP(uart_f_tx, 2), | |
| + GROUP(uart_f_rx, 2), | |
| + GROUP(uart_f_cts, 2), | |
| + GROUP(uart_f_rts, 2), | |
| + GROUP(i2c0_sda_h, 2), | |
| + GROUP(i2c0_sck_h, 2), | |
| + | |
| + /* Bank H func3 */ | |
| + GROUP(pcieck_reqn_h, 3), | |
| +}; | |
| + | |
| +static const char * const gpio_periphs_groups[] = { | |
| + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", "GPIOB_5", | |
| + "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", "GPIOB_10", | |
| + "GPIOB_11", "GPIOB_12", | |
| + | |
| + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", "GPIOC_5", | |
| + "GPIOC_6", | |
| + | |
| + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", "GPIOX_5", | |
| + "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11", | |
| + "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17", | |
| + "GPIOX_18", "GPIOX_19", | |
| + | |
| + "GPIOW_0", "GPIOW_1", "GPIOW_2", "GPIOW_3", "GPIOW_4", "GPIOW_5", | |
| + "GPIOW_6", "GPIOW_7", "GPIOW_8", "GPIOW_9", "GPIOW_10", "GPIOW_11", | |
| + "GPIOW_12", "GPIOW_13", "GPIOW_14", "GPIOW_15", "GPIOW_16", | |
| + | |
| + "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", "GPIOD_5", | |
| + "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", "GPIOD_10", "GPIOD_11", | |
| + "GPIOD_12", | |
| + | |
| + "GPIOE_0", "GPIOE_1", "GPIOE_2", "GPIOE_3", "GPIOE_4", "GPIOE_5", | |
| + "GPIOE_6", | |
| + | |
| + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", "GPIOZ_5", | |
| + "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", "GPIOZ_10", "GPIOZ_11", | |
| + "GPIOZ_12", "GPIOZ_13", | |
| + | |
| + "GPIOT_0", "GPIOT_1", "GPIOT_2", "GPIOT_3", "GPIOT_4", "GPIOT_5", | |
| + "GPIOT_6", "GPIOT_7", "GPIOT_8", "GPIOT_9", "GPIOT_10", "GPIOT_11", | |
| + "GPIOT_12", "GPIOT_13", "GPIOT_14", "GPIOT_15", "GPIOT_16", | |
| + "GPIOT_17", "GPIOT_18", "GPIOT_19", "GPIOT_20", "GPIOT_21", | |
| + "GPIOT_22", "GPIOT_23", | |
| + | |
| + "GPIOM_0", "GPIOM_1", "GPIOM_2", "GPIOM_3", "GPIOM_4", "GPIOM_5", | |
| + "GPIOM_6", "GPIOM_7", "GPIOM_8", "GPIOM_9", "GPIOM_10", "GPIOM_11", | |
| + "GPIOM_12", "GPIOM_13", | |
| + | |
| + "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4", "GPIOY_5", | |
| + "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9", "GPIOY_10", "GPIOY_11", | |
| + "GPIOY_12", "GPIOY_13", "GPIOY_14", "GPIOY_15", "GPIOY_16", | |
| + "GPIOY_17", "GPIOY_18", | |
| + | |
| + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", "GPIOH_5", | |
| + "GPIOH_6", "GPIOH_7", | |
| + | |
| + "GPIO_TEST_N", | |
| +}; | |
| + | |
| +static const char * const emmc_groups[] = { | |
| + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", | |
| + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", | |
| + "emmc_clk", "emmc_cmd", "emmc_nand_ds", | |
| +}; | |
| + | |
| +static const char * const nor_groups[] = { | |
| + "nor_hold", "nor_d", "nor_q", "nor_c", "nor_wp", "nor_cs", | |
| +}; | |
| + | |
| +static const char * const sdcard_groups[] = { | |
| + "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", "sdcard_clk", | |
| + "sdcard_cmd", | |
| +}; | |
| + | |
| +static const char * const sdio_groups[] = { | |
| + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd", | |
| +}; | |
| + | |
| +static const char * const gen_clk_groups[] = { | |
| + "gen_clk_out_c", "gen_clk_out_d", | |
| +}; | |
| + | |
| +static const char * const jtag_a_groups[] = { | |
| + "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo", | |
| +}; | |
| + | |
| +static const char * const jtag_b_groups[] = { | |
| + "jtag_b_tdo", "jtag_b_tdi", "jtag_b_clk", "jtag_b_tms", | |
| +}; | |
| + | |
| +static const char * const uart_c_groups[] = { | |
| + "uart_c_tx", "uart_c_rx", "uart_c_cts", "uart_c_rts", | |
| +}; | |
| + | |
| +static const char * const uart_d_groups[] = { | |
| + "uart_d_tx_m", "uart_d_rx_m", "uart_d_cts_m", "uart_d_rts_m", | |
| + "uart_d_rts_y", "uart_d_tx_y", "uart_d_rx_y", "uart_d_cts_y", | |
| +}; | |
| + | |
| +static const char * const uart_e_groups[] = { | |
| + "uart_e_tx", "uart_e_rx", "uart_e_cts", "uart_e_rts", | |
| +}; | |
| + | |
| +static const char * const uart_f_groups[] = { | |
| + "uart_f_tx", "uart_f_rx", "uart_f_cts", "uart_f_rts", | |
| +}; | |
| + | |
| +static const char * const uart_ao_a_groups[] = { | |
| + "uart_ao_a_rx_c", "uart_ao_a_tx_c", "uart_ao_a_tx_w2", | |
| + "uart_ao_a_rx_w3", "uart_ao_a_tx_w6", "uart_ao_a_rx_w7", | |
| + "uart_ao_a_tx_w10", "uart_ao_a_rx_w11", "uart_ao_a_tx_d0", | |
| + "uart_ao_a_rx_d1", | |
| +}; | |
| + | |
| +static const char * const uart_ao_b_groups[] = { | |
| + "uart_ao_b_tx", "uart_ao_b_rx", "uart_ao_b_cts", "uart_ao_b_rts", | |
| +}; | |
| + | |
| +static const char * const spi0_groups[] = { | |
| + "spi0_mosi", "spi0_miso", "spi0_sclk", "spi0_ss0", "spi0_ss1", | |
| + "spi0_ss2", | |
| +}; | |
| + | |
| +static const char * const spi1_groups[] = { | |
| + "spi1_mosi_c", "spi1_miso_c", "spi1_sclk_c", "spi1_ss0_c", | |
| + "spi1_mosi_m", "spi1_miso_m", "spi1_sclk_m", "spi1_ss0_m", | |
| + "spi1_ss1_m", "spi1_ss2_m", | |
| +}; | |
| + | |
| +static const char * const spi2_groups[] = { | |
| + "spi2_mosi", "spi2_miso", "spi2_sclk", "spi2_ss0", "spi2_ss1", | |
| + "spi2_ss2", | |
| +}; | |
| + | |
| +static const char * const spi3_groups[] = { | |
| + "spi3_mosi", "spi3_miso", "spi3_sclk", "spi3_ss0", | |
| +}; | |
| + | |
| +static const char * const spi4_groups[] = { | |
| + "spi4_mosi", "spi4_miso", "spi4_sclk", "spi4_ss0", | |
| +}; | |
| + | |
| +static const char * const spi5_groups[] = { | |
| + "spi5_mosi", "spi5_miso", "spi5_sclk", "spi5_ss0", | |
| +}; | |
| + | |
| +static const char * const pwm_a_groups[] = { | |
| + "pwm_a", | |
| +}; | |
| + | |
| +static const char * const pwm_b_groups[] = { | |
| + "pwm_b", | |
| +}; | |
| + | |
| +static const char * const pwm_c_groups[] = { | |
| + "pwm_c", | |
| +}; | |
| + | |
| +static const char * const pwm_d_groups[] = { | |
| + "pwm_d", | |
| +}; | |
| + | |
| +static const char * const pwm_e_groups[] = { | |
| + "pwm_e", | |
| +}; | |
| + | |
| +static const char * const pwm_f_groups[] = { | |
| + "pwm_f", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_c_hiz_groups[] = { | |
| + "pwm_ao_c_hiz", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_g_hiz_groups[] = { | |
| + "pwm_ao_g_hiz", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_a_groups[] = { | |
| + "pwm_ao_a", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_b_groups[] = { | |
| + "pwm_ao_b", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_c_groups[] = { | |
| + "pwm_ao_c_d", "pwm_ao_c_e", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_d_groups[] = { | |
| + "pwm_ao_d", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_e_groups[] = { | |
| + "pwm_ao_e", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_f_groups[] = { | |
| + "pwm_ao_f", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_h_groups[] = { | |
| + "pwm_ao_h_d5", "pwm_ao_h_d10", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_g_groups[] = { | |
| + "pwm_ao_g_d11", "pwm_ao_g_d7", "pwm_ao_g_e", | |
| +}; | |
| + | |
| +static const char * const pwm_vs_groups[] = { | |
| + "pwm_vs_y", "pwm_vs_h", | |
| +}; | |
| + | |
| +static const char * const tdm_groups[] = { | |
| + "tdm_d0", "tdm_d1", "tdm_fs0", "tdm_sclk0", "tdm_sclk1", "tdm_fs1", | |
| + "tdm_d2", "tdm_d3", "tdm_d4", "tdm_d5", "tdm_d6", "tdm_d7", | |
| + "tdm_d8", "tdm_d9", "tdm_d10", "tdm_d11", "tdm_sclk2", "tdm_fs2", | |
| + "tdm_d12", "tdm_d13", "tdm_d14", "tdm_d15", "tdm_sclk3", "tdm_fs3", | |
| +}; | |
| + | |
| +static const char * const i2c0_slave_ao_groups[] = { | |
| + "i2c0_slave_ao_sck", "i2c0_slave_ao_sda", | |
| +}; | |
| + | |
| +static const char * const i2c0_ao_groups[] = { | |
| + "i2c0_ao_sck_d", "i2c0_ao_sda_d", | |
| + "i2c0_ao_sck_e", "i2c0_ao_sda_e", | |
| +}; | |
| + | |
| +static const char * const i2c1_ao_groups[] = { | |
| + "i2c1_ao_sck", "i2c1_ao_sda", | |
| +}; | |
| + | |
| +static const char * const i2c0_groups[] = { | |
| + "i2c0_sck_t", "i2c0_sda_t", "i2c0_sck_h", "i2c0_sda_h", | |
| +}; | |
| + | |
| +static const char * const i2c1_groups[] = { | |
| + "i2c1_sck", "i2c1_sda", | |
| +}; | |
| + | |
| +static const char * const i2c2_groups[] = { | |
| + "i2c2_sda_x", "i2c2_sck_x", | |
| + "i2c2_sda_t", "i2c2_sck_t", | |
| + "i2c2_sda_m", "i2c2_sck_m", | |
| +}; | |
| + | |
| +static const char * const i2c3_groups[] = { | |
| + "i2c3_sda_m", "i2c3_sck_m", "i2c3_sck_h", "i2c3_sda_h", | |
| +}; | |
| + | |
| +static const char * const i2c4_groups[] = { | |
| + "i2c4_sck_y", "i2c4_sda_y", "i2c4_sck_h", "i2c4_sda_h", | |
| +}; | |
| + | |
| +static const char * const i2c5_groups[] = { | |
| + "i2c5_sck", "i2c5_sda", | |
| +}; | |
| + | |
| +static const char * const clk12_24_groups[] = { | |
| + "clk12_24_x", "clk12_24_e", | |
| +}; | |
| + | |
| +static const char * const hdmirx_a_groups[] = { | |
| + "hdmirx_a_hpd", "hdmirx_a_det", "hdmirx_a_sda", "hdmirx_a_sck", | |
| +}; | |
| + | |
| +static const char * const hdmirx_b_groups[] = { | |
| + "hdmirx_b_hpd", "hdmirx_b_det", "hdmirx_b_sda", "hdmirx_b_sck", | |
| +}; | |
| + | |
| +static const char * const hdmirx_c_groups[] = { | |
| + "hdmirx_c_hpd", "hdmirx_c_det", "hdmirx_c_sda", "hdmirx_c_sck", | |
| +}; | |
| + | |
| +static const char * const cec_a_groups[] = { | |
| + "cec_a", | |
| +}; | |
| + | |
| +static const char * const cec_b_groups[] = { | |
| + "cec_b", | |
| +}; | |
| + | |
| +static const char * const hdmitx_groups[] = { | |
| + "hdmitx_sda_w13", "hdmitx_sck_w14", "hdmitx_hpd_in", | |
| + "hdmitx_sda_w2", "hdmitx_sck_w3", | |
| +}; | |
| + | |
| +static const char * const remote_out_groups[] = { | |
| + "remote_out_d4", "remote_out_d6", | |
| +}; | |
| + | |
| +static const char * const remote_in_groups[] = { | |
| + "remote_in", | |
| +}; | |
| + | |
| +static const char * const wd_rsto_groups[] = { | |
| + "wd_rsto", | |
| +}; | |
| + | |
| +static const char * const rtc_clk_groups[] = { | |
| + "rtc_clk_in", "rtc_clk_out", | |
| +}; | |
| + | |
| +static const char * const spdif_out_groups[] = { | |
| + "spdif_out_d", "spdif_out_t", | |
| +}; | |
| + | |
| +static const char * const spdif_in_groups[] = { | |
| + "spdif_in_d", "spdif_in_t", | |
| +}; | |
| + | |
| +static const char * const clk25m_groups[] = { | |
| + "clk25m", | |
| +}; | |
| + | |
| +static const char * const eth_groups[] = { | |
| + "eth_mdio", "eth_mdc", "eth_rgmii_rx_clk", "eth_rx_dv", "eth_rxd0", | |
| + "eth_rxd1", "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", | |
| + "eth_txen", "eth_txd0", "eth_txd1", "eth_txd2_rgmii", | |
| + "eth_txd3_rgmii", "eth_link_led", "eth_act_led", | |
| +}; | |
| + | |
| +static const char * const iso7816_groups[] = { | |
| + "iso7816_clk_z", "iso7816_data_z", | |
| + "iso7816_clk_t", "iso7816_data_t", | |
| +}; | |
| + | |
| +static const char * const tsin_a_groups[] = { | |
| + "tsin_a_sop_t", "tsin_a_din0_t", "tsin_a_clk_t", "tsin_a_valid_t", | |
| +}; | |
| + | |
| +static const char * const tsin_b_groups[] = { | |
| + "tsin_b_valid", "tsin_b_sop", "tsin_b_din0", "tsin_b_clk", | |
| + "tsin_b_fail", "tsin_b_din1", "tsin_b_din2", "tsin_b_din3", | |
| + "tsin_b_din4", "tsin_b_din5", "tsin_b_din6", "tsin_b_din7", | |
| +}; | |
| + | |
| +static const char * const tsin_c_groups[] = { | |
| + "tsin_c_z_valid", "tsin_c_z_sop", "tsin_c_z_din0", "tsin_c_z_clk", | |
| + "tsin_c_y_sop", "tsin_c_y_din0", "tsin_c_y_clk", "tsin_c_y_valid", | |
| +}; | |
| + | |
| +static const char * const tsin_d_groups[] = { | |
| + "tsin_d_z_valid", "tsin_d_z_sop", "tsin_d_z_din0", "tsin_d_z_clk", | |
| + "tsin_d_y_sop", "tsin_d_y_din0", "tsin_d_y_clk", "tsin_d_y_valid", | |
| +}; | |
| + | |
| +static const char * const mclk_groups[] = { | |
| + "mclk1", "mclk2", | |
| +}; | |
| + | |
| +static const char * const pdm_groups[] = { | |
| + "pdm_din1_m0", "pdm_din2", "pdm_din3", "pdm_dclk", "pdm_din0", | |
| + "pdm_din1_m5", | |
| +}; | |
| + | |
| +static const char * const pcieck_groups[] = { | |
| + "pcieck_reqn_y", "pcieck_reqn_h", | |
| +}; | |
| + | |
| +static const char * const hsync_groups[] = { | |
| + "hsync", | |
| +}; | |
| + | |
| +static const char * const vsync_groups[] = { | |
| + "vsync", | |
| +}; | |
| + | |
| +static const char * const sync_3d_groups[] = { | |
| + "sync_3d_out", | |
| +}; | |
| + | |
| +static const char * const vx1_a_groups[] = { | |
| + "vx1_a_htpdn", "vx1_a_lockn", | |
| +}; | |
| + | |
| +static const char * const vx1_b_groups[] = { | |
| + "vx1_b_htpdn", "vx1_b_lockn", | |
| +}; | |
| + | |
| +static const char * const edp_a_groups[] = { | |
| + "edp_a_hpd", | |
| +}; | |
| + | |
| +static const char * const edp_b_groups[] = { | |
| + "edp_b_hpd", | |
| +}; | |
| + | |
| +static const char * const mic_mute_groups[] = { | |
| + "mic_mute_key", "mic_mute_led", | |
| +}; | |
| + | |
| +static const struct meson_pmx_func t7_periphs_functions[] = { | |
| + FUNCTION(gpio_periphs), | |
| + FUNCTION(emmc), | |
| + FUNCTION(nor), | |
| + FUNCTION(sdcard), | |
| + FUNCTION(sdio), | |
| + FUNCTION(gen_clk), | |
| + FUNCTION(jtag_a), | |
| + FUNCTION(jtag_b), | |
| + FUNCTION(uart_c), | |
| + FUNCTION(uart_d), | |
| + FUNCTION(uart_e), | |
| + FUNCTION(uart_f), | |
| + FUNCTION(uart_ao_a), | |
| + FUNCTION(uart_ao_b), | |
| + FUNCTION(spi0), | |
| + FUNCTION(spi1), | |
| + FUNCTION(spi2), | |
| + FUNCTION(spi3), | |
| + FUNCTION(spi4), | |
| + FUNCTION(spi5), | |
| + FUNCTION(pwm_a), | |
| + FUNCTION(pwm_b), | |
| + FUNCTION(pwm_c), | |
| + FUNCTION(pwm_d), | |
| + FUNCTION(pwm_e), | |
| + FUNCTION(pwm_f), | |
| + FUNCTION(pwm_ao_c_hiz), | |
| + FUNCTION(pwm_ao_g_hiz), | |
| + FUNCTION(pwm_ao_a), | |
| + FUNCTION(pwm_ao_b), | |
| + FUNCTION(pwm_ao_c), | |
| + FUNCTION(pwm_ao_d), | |
| + FUNCTION(pwm_ao_e), | |
| + FUNCTION(pwm_ao_f), | |
| + FUNCTION(pwm_ao_h), | |
| + FUNCTION(pwm_ao_g), | |
| + FUNCTION(pwm_vs), | |
| + FUNCTION(tdm), | |
| + FUNCTION(i2c0_slave_ao), | |
| + FUNCTION(i2c0_ao), | |
| + FUNCTION(i2c1_ao), | |
| + FUNCTION(i2c0), | |
| + FUNCTION(i2c1), | |
| + FUNCTION(i2c2), | |
| + FUNCTION(i2c3), | |
| + FUNCTION(i2c4), | |
| + FUNCTION(i2c5), | |
| + FUNCTION(clk12_24), | |
| + FUNCTION(hdmirx_a), | |
| + FUNCTION(hdmirx_b), | |
| + FUNCTION(hdmirx_c), | |
| + FUNCTION(cec_a), | |
| + FUNCTION(cec_b), | |
| + FUNCTION(hdmitx), | |
| + FUNCTION(remote_out), | |
| + FUNCTION(remote_in), | |
| + FUNCTION(wd_rsto), | |
| + FUNCTION(rtc_clk), | |
| + FUNCTION(spdif_out), | |
| + FUNCTION(spdif_in), | |
| + FUNCTION(clk25m), | |
| + FUNCTION(eth), | |
| + FUNCTION(iso7816), | |
| + FUNCTION(tsin_a), | |
| + FUNCTION(tsin_b), | |
| + FUNCTION(tsin_c), | |
| + FUNCTION(tsin_d), | |
| + FUNCTION(mclk), | |
| + FUNCTION(pdm), | |
| + FUNCTION(pcieck), | |
| + FUNCTION(hsync), | |
| + FUNCTION(vsync), | |
| + FUNCTION(sync_3d), | |
| + FUNCTION(vx1_a), | |
| + FUNCTION(vx1_b), | |
| + FUNCTION(edp_a), | |
| + FUNCTION(edp_b), | |
| + FUNCTION(mic_mute), | |
| +}; | |
| + | |
| +static const struct meson_bank t7_periphs_banks[] = { | |
| + /* name first last irq pullen pull dir out in ds */ | |
| + BANK_DS("D", GPIOD_0, GPIOD_12, 57, 69, | |
| + 0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0), | |
| + BANK_DS("E", GPIOE_0, GPIOE_6, 70, 76, | |
| + 0x0b, 0, 0x0c, 0, 0x0a, 0, 0x09, 0, 0x08, 0, 0x0f, 0), | |
| + BANK_DS("Z", GPIOZ_0, GPIOZ_13, 77, 90, | |
| + 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0, 0x17, 0), | |
| + BANK_DS("H", GPIOH_0, GPIOH_7, 148, 155, | |
| + 0x1b, 0, 0x1c, 0, 0x1a, 0, 0x19, 0, 0x18, 0, 0x1f, 0), | |
| + BANK_DS("C", GPIOC_0, GPIOC_6, 13, 19, | |
| + 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0), | |
| + BANK_DS("B", GPIOB_0, GPIOB_12, 0, 12, | |
| + 0x2b, 0, 0x2c, 0, 0x2a, 0, 0x29, 0, 0x28, 0, 0x2f, 0), | |
| + BANK_DS("X", GPIOX_0, GPIOX_19, 20, 39, | |
| + 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0), | |
| + BANK_DS("T", GPIOT_0, GPIOT_23, 91, 114, | |
| + 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0), | |
| + BANK_DS("Y", GPIOY_0, GPIOY_18, 129, 147, | |
| + 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0), | |
| + BANK_DS("W", GPIOW_0, GPIOW_16, 40, 56, | |
| + 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0), | |
| + BANK_DS("M", GPIOM_0, GPIOM_13, 115, 128, | |
| + 0x73, 0, 0x74, 0, 0x72, 0, 0x71, 0, 0x70, 0, 0x77, 0), | |
| + BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 156, 156, | |
| + 0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0), | |
| +}; | |
| + | |
| +static const struct meson_pmx_bank t7_periphs_pmx_banks[] = { | |
| + /* name first last reg offset */ | |
| + BANK_PMX("D", GPIOD_0, GPIOD_12, 0x0a, 0), | |
| + BANK_PMX("E", GPIOE_0, GPIOE_6, 0x0c, 0), | |
| + BANK_PMX("Z", GPIOZ_0, GPIOZ_13, 0x05, 0), | |
| + BANK_PMX("H", GPIOH_0, GPIOH_7, 0x08, 0), | |
| + BANK_PMX("C", GPIOC_0, GPIOC_6, 0x07, 0), | |
| + BANK_PMX("B", GPIOB_0, GPIOB_12, 0x00, 0), | |
| + BANK_PMX("X", GPIOX_0, GPIOX_19, 0x02, 0), | |
| + BANK_PMX("T", GPIOT_0, GPIOT_23, 0x0f, 0), | |
| + BANK_PMX("Y", GPIOY_0, GPIOY_18, 0x13, 0), | |
| + BANK_PMX("W", GPIOW_0, GPIOW_16, 0x16, 0), | |
| + BANK_PMX("M", GPIOM_0, GPIOM_13, 0x0d, 0), | |
| + BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0x09, 0), | |
| +}; | |
| + | |
| +static const struct meson_axg_pmx_data t7_periphs_pmx_banks_data = { | |
| + .pmx_banks = t7_periphs_pmx_banks, | |
| + .num_pmx_banks = ARRAY_SIZE(t7_periphs_pmx_banks), | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data t7_periphs_pinctrl_data = { | |
| + .name = "periphs-banks", | |
| + .pins = t7_periphs_pins, | |
| + .groups = t7_periphs_groups, | |
| + .funcs = t7_periphs_functions, | |
| + .banks = t7_periphs_banks, | |
| + .num_pins = ARRAY_SIZE(t7_periphs_pins), | |
| + .num_groups = ARRAY_SIZE(t7_periphs_groups), | |
| + .num_funcs = ARRAY_SIZE(t7_periphs_functions), | |
| + .num_banks = ARRAY_SIZE(t7_periphs_banks), | |
| + .pmx_ops = &meson_axg_pmx_ops, | |
| + .pmx_data = &t7_periphs_pmx_banks_data, | |
| + .parse_dt = &meson_a1_parse_dt_extra, | |
| +}; | |
| + | |
| +static const struct of_device_id t7_pinctrl_dt_match[] = { | |
| + { | |
| + .compatible = "amlogic,t7-periphs-pinctrl", | |
| + .data = &t7_periphs_pinctrl_data, | |
| + }, | |
| + { } | |
| +}; | |
| +MODULE_DEVICE_TABLE(of, t7_pinctrl_dt_match); | |
| + | |
| +static struct platform_driver t7_pinctrl_driver = { | |
| + .probe = meson_pinctrl_probe, | |
| + .driver = { | |
| + .name = "amlogic-t7-pinctrl", | |
| + .of_match_table = t7_pinctrl_dt_match, | |
| + }, | |
| +}; | |
| +module_platform_driver(t7_pinctrl_driver); | |
| + | |
| +MODULE_AUTHOR("Huqiang Qin <huqiang.qin@amlogic.com>"); | |
| +MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic T7 SoC"); | |
| +MODULE_LICENSE("Dual BSD/GPL"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-a1.c b/drivers/pinctrl/meson/pinctrl-meson-a1.c | |
| new file mode 100644 | |
| index 0000000000..20c4323d42 | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-a1.c | |
| @@ -0,0 +1,940 @@ | |
| +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | |
| +/* | |
| + * Pin controller and GPIO driver for Amlogic Meson A1 SoC. | |
| + * | |
| + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. | |
| + * Author: Qianggui Song <qianggui.song@amlogic.com> | |
| + */ | |
| + | |
| +#include <dt-bindings/gpio/meson-a1-gpio.h> | |
| +#include "pinctrl-meson.h" | |
| +#include "pinctrl-meson-axg-pmx.h" | |
| + | |
| +static const struct pinctrl_pin_desc meson_a1_periphs_pins[] = { | |
| + MESON_PIN(GPIOP_0), | |
| + MESON_PIN(GPIOP_1), | |
| + MESON_PIN(GPIOP_2), | |
| + MESON_PIN(GPIOP_3), | |
| + MESON_PIN(GPIOP_4), | |
| + MESON_PIN(GPIOP_5), | |
| + MESON_PIN(GPIOP_6), | |
| + MESON_PIN(GPIOP_7), | |
| + MESON_PIN(GPIOP_8), | |
| + MESON_PIN(GPIOP_9), | |
| + MESON_PIN(GPIOP_10), | |
| + MESON_PIN(GPIOP_11), | |
| + MESON_PIN(GPIOP_12), | |
| + MESON_PIN(GPIOB_0), | |
| + MESON_PIN(GPIOB_1), | |
| + MESON_PIN(GPIOB_2), | |
| + MESON_PIN(GPIOB_3), | |
| + MESON_PIN(GPIOB_4), | |
| + MESON_PIN(GPIOB_5), | |
| + MESON_PIN(GPIOB_6), | |
| + MESON_PIN(GPIOX_0), | |
| + MESON_PIN(GPIOX_1), | |
| + MESON_PIN(GPIOX_2), | |
| + MESON_PIN(GPIOX_3), | |
| + MESON_PIN(GPIOX_4), | |
| + MESON_PIN(GPIOX_5), | |
| + MESON_PIN(GPIOX_6), | |
| + MESON_PIN(GPIOX_7), | |
| + MESON_PIN(GPIOX_8), | |
| + MESON_PIN(GPIOX_9), | |
| + MESON_PIN(GPIOX_10), | |
| + MESON_PIN(GPIOX_11), | |
| + MESON_PIN(GPIOX_12), | |
| + MESON_PIN(GPIOX_13), | |
| + MESON_PIN(GPIOX_14), | |
| + MESON_PIN(GPIOX_15), | |
| + MESON_PIN(GPIOX_16), | |
| + MESON_PIN(GPIOF_0), | |
| + MESON_PIN(GPIOF_1), | |
| + MESON_PIN(GPIOF_2), | |
| + MESON_PIN(GPIOF_3), | |
| + MESON_PIN(GPIOF_4), | |
| + MESON_PIN(GPIOF_5), | |
| + MESON_PIN(GPIOF_6), | |
| + MESON_PIN(GPIOF_7), | |
| + MESON_PIN(GPIOF_8), | |
| + MESON_PIN(GPIOF_9), | |
| + MESON_PIN(GPIOF_10), | |
| + MESON_PIN(GPIOF_11), | |
| + MESON_PIN(GPIOF_12), | |
| + MESON_PIN(GPIOA_0), | |
| + MESON_PIN(GPIOA_1), | |
| + MESON_PIN(GPIOA_2), | |
| + MESON_PIN(GPIOA_3), | |
| + MESON_PIN(GPIOA_4), | |
| + MESON_PIN(GPIOA_5), | |
| + MESON_PIN(GPIOA_6), | |
| + MESON_PIN(GPIOA_7), | |
| + MESON_PIN(GPIOA_8), | |
| + MESON_PIN(GPIOA_9), | |
| + MESON_PIN(GPIOA_10), | |
| + MESON_PIN(GPIOA_11), | |
| +}; | |
| + | |
| +/* psram */ | |
| +static const unsigned int psram_clkn_pins[] = { GPIOP_0 }; | |
| +static const unsigned int psram_clkp_pins[] = { GPIOP_1 }; | |
| +static const unsigned int psram_ce_n_pins[] = { GPIOP_2 }; | |
| +static const unsigned int psram_rst_n_pins[] = { GPIOP_3 }; | |
| +static const unsigned int psram_adq0_pins[] = { GPIOP_4 }; | |
| +static const unsigned int psram_adq1_pins[] = { GPIOP_5 }; | |
| +static const unsigned int psram_adq2_pins[] = { GPIOP_6 }; | |
| +static const unsigned int psram_adq3_pins[] = { GPIOP_7 }; | |
| +static const unsigned int psram_adq4_pins[] = { GPIOP_8 }; | |
| +static const unsigned int psram_adq5_pins[] = { GPIOP_9 }; | |
| +static const unsigned int psram_adq6_pins[] = { GPIOP_10 }; | |
| +static const unsigned int psram_adq7_pins[] = { GPIOP_11 }; | |
| +static const unsigned int psram_dqs_dm_pins[] = { GPIOP_12 }; | |
| + | |
| +/* sdcard */ | |
| +static const unsigned int sdcard_d0_b_pins[] = { GPIOB_0 }; | |
| +static const unsigned int sdcard_d1_b_pins[] = { GPIOB_1 }; | |
| +static const unsigned int sdcard_d2_b_pins[] = { GPIOB_2 }; | |
| +static const unsigned int sdcard_d3_b_pins[] = { GPIOB_3 }; | |
| +static const unsigned int sdcard_clk_b_pins[] = { GPIOB_4 }; | |
| +static const unsigned int sdcard_cmd_b_pins[] = { GPIOB_5 }; | |
| + | |
| +static const unsigned int sdcard_d0_x_pins[] = { GPIOX_0 }; | |
| +static const unsigned int sdcard_d1_x_pins[] = { GPIOX_1 }; | |
| +static const unsigned int sdcard_d2_x_pins[] = { GPIOX_2 }; | |
| +static const unsigned int sdcard_d3_x_pins[] = { GPIOX_3 }; | |
| +static const unsigned int sdcard_clk_x_pins[] = { GPIOX_4 }; | |
| +static const unsigned int sdcard_cmd_x_pins[] = { GPIOX_5 }; | |
| + | |
| +/* spif */ | |
| +static const unsigned int spif_mo_pins[] = { GPIOB_0 }; | |
| +static const unsigned int spif_mi_pins[] = { GPIOB_1 }; | |
| +static const unsigned int spif_wp_n_pins[] = { GPIOB_2 }; | |
| +static const unsigned int spif_hold_n_pins[] = { GPIOB_3 }; | |
| +static const unsigned int spif_clk_pins[] = { GPIOB_4 }; | |
| +static const unsigned int spif_cs_pins[] = { GPIOB_5 }; | |
| + | |
| +/* i2c0 */ | |
| +static const unsigned int i2c0_sck_f9_pins[] = { GPIOF_9 }; | |
| +static const unsigned int i2c0_sda_f10_pins[] = { GPIOF_10 }; | |
| +static const unsigned int i2c0_sck_f11_pins[] = { GPIOF_11 }; | |
| +static const unsigned int i2c0_sda_f12_pins[] = { GPIOF_12 }; | |
| + | |
| +/* i2c1 */ | |
| +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_9 }; | |
| +static const unsigned int i2c1_sck_x_pins[] = { GPIOX_10 }; | |
| +static const unsigned int i2c1_sda_a_pins[] = { GPIOA_10 }; | |
| +static const unsigned int i2c1_sck_a_pins[] = { GPIOA_11 }; | |
| + | |
| +/* i2c2 */ | |
| +static const unsigned int i2c2_sck_x0_pins[] = { GPIOX_0 }; | |
| +static const unsigned int i2c2_sda_x1_pins[] = { GPIOX_1 }; | |
| +static const unsigned int i2c2_sck_x15_pins[] = { GPIOX_15 }; | |
| +static const unsigned int i2c2_sda_x16_pins[] = { GPIOX_16 }; | |
| +static const unsigned int i2c2_sck_a4_pins[] = { GPIOA_4 }; | |
| +static const unsigned int i2c2_sda_a5_pins[] = { GPIOA_5 }; | |
| +static const unsigned int i2c2_sck_a8_pins[] = { GPIOA_8 }; | |
| +static const unsigned int i2c2_sda_a9_pins[] = { GPIOA_9 }; | |
| + | |
| +/* i2c3 */ | |
| +static const unsigned int i2c3_sck_f_pins[] = { GPIOF_4 }; | |
| +static const unsigned int i2c3_sda_f_pins[] = { GPIOF_5 }; | |
| +static const unsigned int i2c3_sck_x_pins[] = { GPIOX_11 }; | |
| +static const unsigned int i2c3_sda_x_pins[] = { GPIOX_12 }; | |
| + | |
| +/* i2c slave */ | |
| +static const unsigned int i2c_slave_sck_a_pins[] = { GPIOA_10 }; | |
| +static const unsigned int i2c_slave_sda_a_pins[] = { GPIOA_11 }; | |
| +static const unsigned int i2c_slave_sck_f_pins[] = { GPIOF_11 }; | |
| +static const unsigned int i2c_slave_sda_f_pins[] = { GPIOF_12 }; | |
| + | |
| +/* uart_a */ | |
| +static const unsigned int uart_a_tx_pins[] = { GPIOX_11 }; | |
| +static const unsigned int uart_a_rx_pins[] = { GPIOX_12 }; | |
| +static const unsigned int uart_a_cts_pins[] = { GPIOX_13 }; | |
| +static const unsigned int uart_a_rts_pins[] = { GPIOX_14 }; | |
| + | |
| +/* uart_b */ | |
| +static const unsigned int uart_b_tx_x_pins[] = { GPIOX_7 }; | |
| +static const unsigned int uart_b_rx_x_pins[] = { GPIOX_8 }; | |
| +static const unsigned int uart_b_tx_f_pins[] = { GPIOF_0 }; | |
| +static const unsigned int uart_b_rx_f_pins[] = { GPIOF_1 }; | |
| + | |
| +/* uart_c */ | |
| +static const unsigned int uart_c_tx_x0_pins[] = { GPIOX_0 }; | |
| +static const unsigned int uart_c_rx_x1_pins[] = { GPIOX_1 }; | |
| +static const unsigned int uart_c_cts_pins[] = { GPIOX_2 }; | |
| +static const unsigned int uart_c_rts_pins[] = { GPIOX_3 }; | |
| +static const unsigned int uart_c_tx_x15_pins[] = { GPIOX_15 }; | |
| +static const unsigned int uart_c_rx_x16_pins[] = { GPIOX_16 }; | |
| + | |
| +/* pmw_a */ | |
| +static const unsigned int pwm_a_x6_pins[] = { GPIOX_6 }; | |
| +static const unsigned int pwm_a_x7_pins[] = { GPIOX_7 }; | |
| +static const unsigned int pwm_a_f6_pins[] = { GPIOF_6 }; | |
| +static const unsigned int pwm_a_f10_pins[] = { GPIOF_10 }; | |
| +static const unsigned int pwm_a_a_pins[] = { GPIOA_5 }; | |
| + | |
| +/* pmw_b */ | |
| +static const unsigned int pwm_b_x_pins[] = { GPIOX_8 }; | |
| +static const unsigned int pwm_b_f_pins[] = { GPIOF_7 }; | |
| +static const unsigned int pwm_b_a_pins[] = { GPIOA_11 }; | |
| + | |
| +/* pmw_c */ | |
| +static const unsigned int pwm_c_x_pins[] = { GPIOX_9 }; | |
| +static const unsigned int pwm_c_f3_pins[] = { GPIOF_3 }; | |
| +static const unsigned int pwm_c_f8_pins[] = { GPIOF_8 }; | |
| +static const unsigned int pwm_c_a_pins[] = { GPIOA_10 }; | |
| + | |
| +/* pwm_d */ | |
| +static const unsigned int pwm_d_x10_pins[] = { GPIOX_10 }; | |
| +static const unsigned int pwm_d_x13_pins[] = { GPIOX_13 }; | |
| +static const unsigned int pwm_d_x15_pins[] = { GPIOX_15 }; | |
| +static const unsigned int pwm_d_f_pins[] = { GPIOF_11 }; | |
| + | |
| +/* pwm_e */ | |
| +static const unsigned int pwm_e_p_pins[] = { GPIOP_3 }; | |
| +static const unsigned int pwm_e_x2_pins[] = { GPIOX_2 }; | |
| +static const unsigned int pwm_e_x14_pins[] = { GPIOX_14 }; | |
| +static const unsigned int pwm_e_x16_pins[] = { GPIOX_16 }; | |
| +static const unsigned int pwm_e_f_pins[] = { GPIOF_3 }; | |
| +static const unsigned int pwm_e_a_pins[] = { GPIOA_0 }; | |
| + | |
| +/* pwm_f */ | |
| +static const unsigned int pwm_f_b_pins[] = { GPIOB_6 }; | |
| +static const unsigned int pwm_f_x_pins[] = { GPIOX_3 }; | |
| +static const unsigned int pwm_f_f4_pins[] = { GPIOF_4 }; | |
| +static const unsigned int pwm_f_f12_pins[] = { GPIOF_12 }; | |
| + | |
| +/* pwm_a_hiz */ | |
| +static const unsigned int pwm_a_hiz_f8_pins[] = { GPIOF_8 }; | |
| +static const unsigned int pwm_a_hiz_f10_pins[] = { GPIOF_10 }; | |
| +static const unsigned int pmw_a_hiz_f6_pins[] = { GPIOF_6 }; | |
| + | |
| +/* pwm_b_hiz */ | |
| +static const unsigned int pwm_b_hiz_pins[] = { GPIOF_7 }; | |
| + | |
| +/* pmw_c_hiz */ | |
| +static const unsigned int pwm_c_hiz_pins[] = { GPIOF_8 }; | |
| + | |
| +/* tdm_a */ | |
| +static const unsigned int tdm_a_dout1_pins[] = { GPIOX_7 }; | |
| +static const unsigned int tdm_a_dout0_pins[] = { GPIOX_8 }; | |
| +static const unsigned int tdm_a_fs_pins[] = { GPIOX_9 }; | |
| +static const unsigned int tdm_a_sclk_pins[] = { GPIOX_10 }; | |
| +static const unsigned int tdm_a_din1_pins[] = { GPIOX_7 }; | |
| +static const unsigned int tdm_a_din0_pins[] = { GPIOX_8 }; | |
| +static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_9 }; | |
| +static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_10 }; | |
| + | |
| +/* spi_a */ | |
| +static const unsigned int spi_a_mosi_x2_pins[] = { GPIOX_2 }; | |
| +static const unsigned int spi_a_ss0_x3_pins[] = { GPIOX_3 }; | |
| +static const unsigned int spi_a_sclk_x4_pins[] = { GPIOX_4 }; | |
| +static const unsigned int spi_a_miso_x5_pins[] = { GPIOX_5 }; | |
| +static const unsigned int spi_a_mosi_x7_pins[] = { GPIOX_7 }; | |
| +static const unsigned int spi_a_miso_x8_pins[] = { GPIOX_8 }; | |
| +static const unsigned int spi_a_ss0_x9_pins[] = { GPIOX_9 }; | |
| +static const unsigned int spi_a_sclk_x10_pins[] = { GPIOX_10 }; | |
| + | |
| +static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_6 }; | |
| +static const unsigned int spi_a_miso_a_pins[] = { GPIOA_7 }; | |
| +static const unsigned int spi_a_ss0_a_pins[] = { GPIOA_8 }; | |
| +static const unsigned int spi_a_sclk_a_pins[] = { GPIOA_9 }; | |
| + | |
| +/* pdm */ | |
| +static const unsigned int pdm_din0_x_pins[] = { GPIOX_7 }; | |
| +static const unsigned int pdm_din1_x_pins[] = { GPIOX_8 }; | |
| +static const unsigned int pdm_din2_x_pins[] = { GPIOX_9 }; | |
| +static const unsigned int pdm_dclk_x_pins[] = { GPIOX_10 }; | |
| + | |
| +static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 }; | |
| +static const unsigned int pdm_din1_a_pins[] = { GPIOA_7 }; | |
| +static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 }; | |
| +static const unsigned int pdm_dclk_a_pins[] = { GPIOA_9 }; | |
| + | |
| +/* gen_clk */ | |
| +static const unsigned int gen_clk_x_pins[] = { GPIOX_7 }; | |
| +static const unsigned int gen_clk_f8_pins[] = { GPIOF_8 }; | |
| +static const unsigned int gen_clk_f10_pins[] = { GPIOF_10 }; | |
| +static const unsigned int gen_clk_a_pins[] = { GPIOA_11 }; | |
| + | |
| +/* jtag_a */ | |
| +static const unsigned int jtag_a_clk_pins[] = { GPIOF_4 }; | |
| +static const unsigned int jtag_a_tms_pins[] = { GPIOF_5 }; | |
| +static const unsigned int jtag_a_tdi_pins[] = { GPIOF_6 }; | |
| +static const unsigned int jtag_a_tdo_pins[] = { GPIOF_7 }; | |
| + | |
| +/* clk_32_in */ | |
| +static const unsigned int clk_32k_in_pins[] = { GPIOF_2 }; | |
| + | |
| +/* ir in */ | |
| +static const unsigned int remote_input_f_pins[] = { GPIOF_3 }; | |
| +static const unsigned int remote_input_a_pins[] = { GPIOA_11 }; | |
| + | |
| +/* ir out */ | |
| +static const unsigned int remote_out_pins[] = { GPIOF_5 }; | |
| + | |
| +/* spdif */ | |
| +static const unsigned int spdif_in_f6_pins[] = { GPIOF_6 }; | |
| +static const unsigned int spdif_in_f7_pins[] = { GPIOF_7 }; | |
| + | |
| +/* sw */ | |
| +static const unsigned int swclk_pins[] = { GPIOF_4 }; | |
| +static const unsigned int swdio_pins[] = { GPIOF_5 }; | |
| + | |
| +/* clk_25 */ | |
| +static const unsigned int clk25_pins[] = { GPIOF_10 }; | |
| + | |
| +/* cec_a */ | |
| +static const unsigned int cec_a_pins[] = { GPIOF_2 }; | |
| + | |
| +/* cec_b */ | |
| +static const unsigned int cec_b_pins[] = { GPIOF_2 }; | |
| + | |
| +/* clk12_24 */ | |
| +static const unsigned int clk12_24_pins[] = { GPIOF_10 }; | |
| + | |
| +/* mclk_0 */ | |
| +static const unsigned int mclk_0_pins[] = { GPIOA_0 }; | |
| + | |
| +/* tdm_b */ | |
| +static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 }; | |
| +static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 }; | |
| +static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 }; | |
| +static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 }; | |
| +static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 }; | |
| +static const unsigned int tdm_b_dout3_pins[] = { GPIOA_6 }; | |
| +static const unsigned int tdm_b_dout4_pins[] = { GPIOA_7 }; | |
| +static const unsigned int tdm_b_dout5_pins[] = { GPIOA_8 }; | |
| +static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_5 }; | |
| +static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_6 }; | |
| +static const unsigned int tdm_b_din0_pins[] = { GPIOA_7 }; | |
| +static const unsigned int tdm_b_din1_pins[] = { GPIOA_8 }; | |
| +static const unsigned int tdm_b_din2_pins[] = { GPIOA_9 }; | |
| + | |
| +/* mclk_vad */ | |
| +static const unsigned int mclk_vad_pins[] = { GPIOA_0 }; | |
| + | |
| +/* tdm_vad */ | |
| +static const unsigned int tdm_vad_sclk_a1_pins[] = { GPIOA_1 }; | |
| +static const unsigned int tdm_vad_fs_a2_pins[] = { GPIOA_2 }; | |
| +static const unsigned int tdm_vad_sclk_a5_pins[] = { GPIOA_5 }; | |
| +static const unsigned int tdm_vad_fs_a6_pins[] = { GPIOA_6 }; | |
| + | |
| +/* tst_out */ | |
| +static const unsigned int tst_out0_pins[] = { GPIOA_0 }; | |
| +static const unsigned int tst_out1_pins[] = { GPIOA_1 }; | |
| +static const unsigned int tst_out2_pins[] = { GPIOA_2 }; | |
| +static const unsigned int tst_out3_pins[] = { GPIOA_3 }; | |
| +static const unsigned int tst_out4_pins[] = { GPIOA_4 }; | |
| +static const unsigned int tst_out5_pins[] = { GPIOA_5 }; | |
| +static const unsigned int tst_out6_pins[] = { GPIOA_6 }; | |
| +static const unsigned int tst_out7_pins[] = { GPIOA_7 }; | |
| +static const unsigned int tst_out8_pins[] = { GPIOA_8 }; | |
| +static const unsigned int tst_out9_pins[] = { GPIOA_9 }; | |
| +static const unsigned int tst_out10_pins[] = { GPIOA_10 }; | |
| +static const unsigned int tst_out11_pins[] = { GPIOA_11 }; | |
| + | |
| +/* mute */ | |
| +static const unsigned int mute_key_pins[] = { GPIOA_4 }; | |
| +static const unsigned int mute_en_pins[] = { GPIOA_5 }; | |
| + | |
| +static const struct meson_pmx_group meson_a1_periphs_groups[] = { | |
| + GPIO_GROUP(GPIOP_0), | |
| + GPIO_GROUP(GPIOP_1), | |
| + GPIO_GROUP(GPIOP_2), | |
| + GPIO_GROUP(GPIOP_3), | |
| + GPIO_GROUP(GPIOP_4), | |
| + GPIO_GROUP(GPIOP_5), | |
| + GPIO_GROUP(GPIOP_6), | |
| + GPIO_GROUP(GPIOP_7), | |
| + GPIO_GROUP(GPIOP_8), | |
| + GPIO_GROUP(GPIOP_9), | |
| + GPIO_GROUP(GPIOP_10), | |
| + GPIO_GROUP(GPIOP_11), | |
| + GPIO_GROUP(GPIOP_12), | |
| + GPIO_GROUP(GPIOB_0), | |
| + GPIO_GROUP(GPIOB_1), | |
| + GPIO_GROUP(GPIOB_2), | |
| + GPIO_GROUP(GPIOB_3), | |
| + GPIO_GROUP(GPIOB_4), | |
| + GPIO_GROUP(GPIOB_5), | |
| + GPIO_GROUP(GPIOB_6), | |
| + GPIO_GROUP(GPIOX_0), | |
| + GPIO_GROUP(GPIOX_1), | |
| + GPIO_GROUP(GPIOX_2), | |
| + GPIO_GROUP(GPIOX_3), | |
| + GPIO_GROUP(GPIOX_4), | |
| + GPIO_GROUP(GPIOX_5), | |
| + GPIO_GROUP(GPIOX_6), | |
| + GPIO_GROUP(GPIOX_7), | |
| + GPIO_GROUP(GPIOX_8), | |
| + GPIO_GROUP(GPIOX_9), | |
| + GPIO_GROUP(GPIOX_10), | |
| + GPIO_GROUP(GPIOX_11), | |
| + GPIO_GROUP(GPIOX_12), | |
| + GPIO_GROUP(GPIOX_13), | |
| + GPIO_GROUP(GPIOX_14), | |
| + GPIO_GROUP(GPIOX_15), | |
| + GPIO_GROUP(GPIOX_16), | |
| + GPIO_GROUP(GPIOF_0), | |
| + GPIO_GROUP(GPIOF_1), | |
| + GPIO_GROUP(GPIOF_2), | |
| + GPIO_GROUP(GPIOF_3), | |
| + GPIO_GROUP(GPIOF_4), | |
| + GPIO_GROUP(GPIOF_5), | |
| + GPIO_GROUP(GPIOF_6), | |
| + GPIO_GROUP(GPIOF_7), | |
| + GPIO_GROUP(GPIOF_8), | |
| + GPIO_GROUP(GPIOF_9), | |
| + GPIO_GROUP(GPIOF_10), | |
| + GPIO_GROUP(GPIOF_11), | |
| + GPIO_GROUP(GPIOF_12), | |
| + GPIO_GROUP(GPIOA_0), | |
| + GPIO_GROUP(GPIOA_1), | |
| + GPIO_GROUP(GPIOA_2), | |
| + GPIO_GROUP(GPIOA_3), | |
| + GPIO_GROUP(GPIOA_4), | |
| + GPIO_GROUP(GPIOA_5), | |
| + GPIO_GROUP(GPIOA_6), | |
| + GPIO_GROUP(GPIOA_7), | |
| + GPIO_GROUP(GPIOA_8), | |
| + GPIO_GROUP(GPIOA_9), | |
| + GPIO_GROUP(GPIOA_10), | |
| + GPIO_GROUP(GPIOA_11), | |
| + | |
| + /* bank P func1 */ | |
| + GROUP(psram_clkn, 1), | |
| + GROUP(psram_clkp, 1), | |
| + GROUP(psram_ce_n, 1), | |
| + GROUP(psram_rst_n, 1), | |
| + GROUP(psram_adq0, 1), | |
| + GROUP(psram_adq1, 1), | |
| + GROUP(psram_adq2, 1), | |
| + GROUP(psram_adq3, 1), | |
| + GROUP(psram_adq4, 1), | |
| + GROUP(psram_adq5, 1), | |
| + GROUP(psram_adq6, 1), | |
| + GROUP(psram_adq7, 1), | |
| + GROUP(psram_dqs_dm, 1), | |
| + | |
| + /*bank P func2 */ | |
| + GROUP(pwm_e_p, 2), | |
| + | |
| + /*bank B func1 */ | |
| + GROUP(spif_mo, 1), | |
| + GROUP(spif_mi, 1), | |
| + GROUP(spif_wp_n, 1), | |
| + GROUP(spif_hold_n, 1), | |
| + GROUP(spif_clk, 1), | |
| + GROUP(spif_cs, 1), | |
| + GROUP(pwm_f_b, 1), | |
| + | |
| + /*bank B func2 */ | |
| + GROUP(sdcard_d0_b, 2), | |
| + GROUP(sdcard_d1_b, 2), | |
| + GROUP(sdcard_d2_b, 2), | |
| + GROUP(sdcard_d3_b, 2), | |
| + GROUP(sdcard_clk_b, 2), | |
| + GROUP(sdcard_cmd_b, 2), | |
| + | |
| + /*bank X func1 */ | |
| + GROUP(sdcard_d0_x, 1), | |
| + GROUP(sdcard_d1_x, 1), | |
| + GROUP(sdcard_d2_x, 1), | |
| + GROUP(sdcard_d3_x, 1), | |
| + GROUP(sdcard_clk_x, 1), | |
| + GROUP(sdcard_cmd_x, 1), | |
| + GROUP(pwm_a_x6, 1), | |
| + GROUP(tdm_a_dout1, 1), | |
| + GROUP(tdm_a_dout0, 1), | |
| + GROUP(tdm_a_fs, 1), | |
| + GROUP(tdm_a_sclk, 1), | |
| + GROUP(uart_a_tx, 1), | |
| + GROUP(uart_a_rx, 1), | |
| + GROUP(uart_a_cts, 1), | |
| + GROUP(uart_a_rts, 1), | |
| + GROUP(pwm_d_x15, 1), | |
| + GROUP(pwm_e_x16, 1), | |
| + | |
| + /*bank X func2 */ | |
| + GROUP(i2c2_sck_x0, 2), | |
| + GROUP(i2c2_sda_x1, 2), | |
| + GROUP(spi_a_mosi_x2, 2), | |
| + GROUP(spi_a_ss0_x3, 2), | |
| + GROUP(spi_a_sclk_x4, 2), | |
| + GROUP(spi_a_miso_x5, 2), | |
| + GROUP(tdm_a_din1, 2), | |
| + GROUP(tdm_a_din0, 2), | |
| + GROUP(tdm_a_slv_fs, 2), | |
| + GROUP(tdm_a_slv_sclk, 2), | |
| + GROUP(i2c3_sck_x, 2), | |
| + GROUP(i2c3_sda_x, 2), | |
| + GROUP(pwm_d_x13, 2), | |
| + GROUP(pwm_e_x14, 2), | |
| + GROUP(i2c2_sck_x15, 2), | |
| + GROUP(i2c2_sda_x16, 2), | |
| + | |
| + /*bank X func3 */ | |
| + GROUP(uart_c_tx_x0, 3), | |
| + GROUP(uart_c_rx_x1, 3), | |
| + GROUP(uart_c_cts, 3), | |
| + GROUP(uart_c_rts, 3), | |
| + GROUP(pdm_din0_x, 3), | |
| + GROUP(pdm_din1_x, 3), | |
| + GROUP(pdm_din2_x, 3), | |
| + GROUP(pdm_dclk_x, 3), | |
| + GROUP(uart_c_tx_x15, 3), | |
| + GROUP(uart_c_rx_x16, 3), | |
| + | |
| + /*bank X func4 */ | |
| + GROUP(pwm_e_x2, 4), | |
| + GROUP(pwm_f_x, 4), | |
| + GROUP(spi_a_mosi_x7, 4), | |
| + GROUP(spi_a_miso_x8, 4), | |
| + GROUP(spi_a_ss0_x9, 4), | |
| + GROUP(spi_a_sclk_x10, 4), | |
| + | |
| + /*bank X func5 */ | |
| + GROUP(uart_b_tx_x, 5), | |
| + GROUP(uart_b_rx_x, 5), | |
| + GROUP(i2c1_sda_x, 5), | |
| + GROUP(i2c1_sck_x, 5), | |
| + | |
| + /*bank X func6 */ | |
| + GROUP(pwm_a_x7, 6), | |
| + GROUP(pwm_b_x, 6), | |
| + GROUP(pwm_c_x, 6), | |
| + GROUP(pwm_d_x10, 6), | |
| + | |
| + /*bank X func7 */ | |
| + GROUP(gen_clk_x, 7), | |
| + | |
| + /*bank F func1 */ | |
| + GROUP(uart_b_tx_f, 1), | |
| + GROUP(uart_b_rx_f, 1), | |
| + GROUP(remote_input_f, 1), | |
| + GROUP(jtag_a_clk, 1), | |
| + GROUP(jtag_a_tms, 1), | |
| + GROUP(jtag_a_tdi, 1), | |
| + GROUP(jtag_a_tdo, 1), | |
| + GROUP(gen_clk_f8, 1), | |
| + GROUP(pwm_a_f10, 1), | |
| + GROUP(i2c0_sck_f11, 1), | |
| + GROUP(i2c0_sda_f12, 1), | |
| + | |
| + /*bank F func2 */ | |
| + GROUP(clk_32k_in, 2), | |
| + GROUP(pwm_e_f, 2), | |
| + GROUP(pwm_f_f4, 2), | |
| + GROUP(remote_out, 2), | |
| + GROUP(spdif_in_f6, 2), | |
| + GROUP(spdif_in_f7, 2), | |
| + GROUP(pwm_a_hiz_f8, 2), | |
| + GROUP(pwm_a_hiz_f10, 2), | |
| + GROUP(pwm_d_f, 2), | |
| + GROUP(pwm_f_f12, 2), | |
| + | |
| + /*bank F func3 */ | |
| + GROUP(pwm_c_f3, 3), | |
| + GROUP(swclk, 3), | |
| + GROUP(swdio, 3), | |
| + GROUP(pwm_a_f6, 3), | |
| + GROUP(pwm_b_f, 3), | |
| + GROUP(pwm_c_f8, 3), | |
| + GROUP(clk25, 3), | |
| + GROUP(i2c_slave_sck_f, 3), | |
| + GROUP(i2c_slave_sda_f, 3), | |
| + | |
| + /*bank F func4 */ | |
| + GROUP(cec_a, 4), | |
| + GROUP(i2c3_sck_f, 4), | |
| + GROUP(i2c3_sda_f, 4), | |
| + GROUP(pmw_a_hiz_f6, 4), | |
| + GROUP(pwm_b_hiz, 4), | |
| + GROUP(pwm_c_hiz, 4), | |
| + GROUP(i2c0_sck_f9, 4), | |
| + GROUP(i2c0_sda_f10, 4), | |
| + | |
| + /*bank F func5 */ | |
| + GROUP(cec_b, 5), | |
| + GROUP(clk12_24, 5), | |
| + | |
| + /*bank F func7 */ | |
| + GROUP(gen_clk_f10, 7), | |
| + | |
| + /*bank A func1 */ | |
| + GROUP(mclk_0, 1), | |
| + GROUP(tdm_b_sclk, 1), | |
| + GROUP(tdm_b_fs, 1), | |
| + GROUP(tdm_b_dout0, 1), | |
| + GROUP(tdm_b_dout1, 1), | |
| + GROUP(tdm_b_dout2, 1), | |
| + GROUP(tdm_b_dout3, 1), | |
| + GROUP(tdm_b_dout4, 1), | |
| + GROUP(tdm_b_dout5, 1), | |
| + GROUP(remote_input_a, 1), | |
| + | |
| + /*bank A func2 */ | |
| + GROUP(pwm_e_a, 2), | |
| + GROUP(tdm_b_slv_sclk, 2), | |
| + GROUP(tdm_b_slv_fs, 2), | |
| + GROUP(tdm_b_din0, 2), | |
| + GROUP(tdm_b_din1, 2), | |
| + GROUP(tdm_b_din2, 2), | |
| + GROUP(i2c1_sda_a, 2), | |
| + GROUP(i2c1_sck_a, 2), | |
| + | |
| + /*bank A func3 */ | |
| + GROUP(i2c2_sck_a4, 3), | |
| + GROUP(i2c2_sda_a5, 3), | |
| + GROUP(pdm_din2_a, 3), | |
| + GROUP(pdm_din1_a, 3), | |
| + GROUP(pdm_din0_a, 3), | |
| + GROUP(pdm_dclk_a, 3), | |
| + GROUP(pwm_c_a, 3), | |
| + GROUP(pwm_b_a, 3), | |
| + | |
| + /*bank A func4 */ | |
| + GROUP(pwm_a_a, 4), | |
| + GROUP(spi_a_mosi_a, 4), | |
| + GROUP(spi_a_miso_a, 4), | |
| + GROUP(spi_a_ss0_a, 4), | |
| + GROUP(spi_a_sclk_a, 4), | |
| + GROUP(i2c_slave_sck_a, 4), | |
| + GROUP(i2c_slave_sda_a, 4), | |
| + | |
| + /*bank A func5 */ | |
| + GROUP(mclk_vad, 5), | |
| + GROUP(tdm_vad_sclk_a1, 5), | |
| + GROUP(tdm_vad_fs_a2, 5), | |
| + GROUP(tdm_vad_sclk_a5, 5), | |
| + GROUP(tdm_vad_fs_a6, 5), | |
| + GROUP(i2c2_sck_a8, 5), | |
| + GROUP(i2c2_sda_a9, 5), | |
| + | |
| + /*bank A func6 */ | |
| + GROUP(tst_out0, 6), | |
| + GROUP(tst_out1, 6), | |
| + GROUP(tst_out2, 6), | |
| + GROUP(tst_out3, 6), | |
| + GROUP(tst_out4, 6), | |
| + GROUP(tst_out5, 6), | |
| + GROUP(tst_out6, 6), | |
| + GROUP(tst_out7, 6), | |
| + GROUP(tst_out8, 6), | |
| + GROUP(tst_out9, 6), | |
| + GROUP(tst_out10, 6), | |
| + GROUP(tst_out11, 6), | |
| + | |
| + /*bank A func7 */ | |
| + GROUP(mute_key, 7), | |
| + GROUP(mute_en, 7), | |
| + GROUP(gen_clk_a, 7), | |
| +}; | |
| + | |
| +static const char * const gpio_periphs_groups[] = { | |
| + "GPIOP_0", "GPIOP_1", "GPIOP_2", "GPIOP_3", "GPIOP_4", | |
| + "GPIOP_5", "GPIOP_6", "GPIOP_7", "GPIOP_8", "GPIOP_9", | |
| + "GPIOP_10", "GPIOP_11", "GPIOP_12", | |
| + | |
| + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", | |
| + "GPIOB_5", "GPIOB_6", | |
| + | |
| + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", | |
| + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", | |
| + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", | |
| + "GPIOX_15", "GPIOX_16", | |
| + | |
| + "GPIOF_0", "GPIOF_1", "GPIOF_2", "GPIOF_3", "GPIOF_4", | |
| + "GPIOF_5", "GPIOF_6", "GPIOF_7", "GPIOF_8", "GPIOF_9", | |
| + "GPIOF_10", "GPIOF_11", "GPIOF_12", | |
| + | |
| + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", | |
| + "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9", | |
| + "GPIOA_10", "GPIOA_11", | |
| +}; | |
| + | |
| +static const char * const psram_groups[] = { | |
| + "psram_clkn", "psram_clkp", "psram_ce_n", "psram_rst_n", "psram_adq0", | |
| + "psram_adq1", "psram_adq2", "psram_adq3", "psram_adq4", "psram_adq5", | |
| + "psram_adq6", "psram_adq7", "psram_dqs_dm", | |
| +}; | |
| + | |
| +static const char * const pwm_a_groups[] = { | |
| + "pwm_a_x6", "pwm_a_x7", "pwm_a_f10", "pwm_a_f6", "pwm_a_a", | |
| +}; | |
| + | |
| +static const char * const pwm_b_groups[] = { | |
| + "pwm_b_x", "pwm_b_f", "pwm_b_a", | |
| +}; | |
| + | |
| +static const char * const pwm_c_groups[] = { | |
| + "pwm_c_x", "pwm_c_f3", "pwm_c_f8", "pwm_c_a", | |
| +}; | |
| + | |
| +static const char * const pwm_d_groups[] = { | |
| + "pwm_d_x15", "pwm_d_x13", "pwm_d_x10", "pwm_d_f", | |
| +}; | |
| + | |
| +static const char * const pwm_e_groups[] = { | |
| + "pwm_e_p", "pwm_e_x16", "pwm_e_x14", "pwm_e_x2", "pwm_e_f", | |
| + "pwm_e_a", | |
| +}; | |
| + | |
| +static const char * const pwm_f_groups[] = { | |
| + "pwm_f_b", "pwm_f_x", "pwm_f_f4", "pwm_f_f12", | |
| +}; | |
| + | |
| +static const char * const pwm_a_hiz_groups[] = { | |
| + "pwm_a_hiz_f8", "pwm_a_hiz_f10", "pwm_a_hiz_f6", | |
| +}; | |
| + | |
| +static const char * const pwm_b_hiz_groups[] = { | |
| + "pwm_b_hiz", | |
| +}; | |
| + | |
| +static const char * const pwm_c_hiz_groups[] = { | |
| + "pwm_c_hiz", | |
| +}; | |
| + | |
| +static const char * const spif_groups[] = { | |
| + "spif_mo", "spif_mi", "spif_wp_n", "spif_hold_n", "spif_clk", | |
| + "spif_cs", | |
| +}; | |
| + | |
| +static const char * const sdcard_groups[] = { | |
| + "sdcard_d0_b", "sdcard_d1_b", "sdcard_d2_b", "sdcard_d3_b", | |
| + "sdcard_clk_b", "sdcard_cmd_b", | |
| + | |
| + "sdcard_d0_x", "sdcard_d1_x", "sdcard_d2_x", "sdcard_d3_x", | |
| + "sdcard_clk_x", "sdcard_cmd_x", | |
| +}; | |
| + | |
| +static const char * const tdm_a_groups[] = { | |
| + "tdm_a_din0", "tdm_a_din1", "tdm_a_fs", "tdm_a_sclk", | |
| + "tdm_a_slv_fs", "tdm_a_slv_sclk", "tdm_a_dout0", "tdm_a_dout1", | |
| +}; | |
| + | |
| +static const char * const uart_a_groups[] = { | |
| + "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts", | |
| +}; | |
| + | |
| +static const char * const uart_b_groups[] = { | |
| + "uart_b_tx_x", "uart_b_rx_x", "uart_b_tx_f", "uart_b_rx_f", | |
| +}; | |
| + | |
| +static const char * const uart_c_groups[] = { | |
| + "uart_c_tx_x0", "uart_c_rx_x1", "uart_c_cts", "uart_c_rts", | |
| + "uart_c_tx_x15", "uart_c_rx_x16", | |
| +}; | |
| + | |
| +static const char * const i2c0_groups[] = { | |
| + "i2c0_sck_f11", "i2c0_sda_f12", "i2c0_sck_f9", "i2c0_sda_f10", | |
| +}; | |
| + | |
| +static const char * const i2c1_groups[] = { | |
| + "i2c1_sda_x", "i2c1_sck_x", "i2c1_sda_a", "i2c1_sck_a", | |
| +}; | |
| + | |
| +static const char * const i2c2_groups[] = { | |
| + "i2c2_sck_x0", "i2c2_sda_x1", "i2c2_sck_x15", "i2c2_sda_x16", | |
| + "i2c2_sck_a4", "i2c2_sda_a5", "i2c2_sck_a8", "i2c2_sda_a9", | |
| +}; | |
| + | |
| +static const char * const i2c3_groups[] = { | |
| + "i2c3_sck_x", "i2c3_sda_x", "i2c3_sck_f", "i2c3_sda_f", | |
| +}; | |
| + | |
| +static const char * const spi_a_groups[] = { | |
| + "spi_a_mosi_x2", "spi_a_ss0_x3", "spi_a_sclk_x4", "spi_a_miso_x5", | |
| + "spi_a_mosi_x7", "spi_a_miso_x8", "spi_a_ss0_x9", "spi_a_sclk_x10", | |
| + | |
| + "spi_a_mosi_a", "spi_a_miso_a", "spi_a_ss0_a", "spi_a_sclk_a", | |
| +}; | |
| + | |
| +static const char * const pdm_groups[] = { | |
| + "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_dclk_x", "pdm_din2_a", | |
| + "pdm_din1_a", "pdm_din0_a", "pdm_dclk_a", | |
| +}; | |
| + | |
| +static const char * const gen_clk_groups[] = { | |
| + "gen_clk_x", "gen_clk_f8", "gen_clk_f10", "gen_clk_a", | |
| +}; | |
| + | |
| +static const char * const remote_input_groups[] = { | |
| + "remote_input_f", | |
| + "remote_input_a", | |
| +}; | |
| + | |
| +static const char * const jtag_a_groups[] = { | |
| + "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo", | |
| +}; | |
| + | |
| +static const char * const clk_32k_in_groups[] = { | |
| + "clk_32k_in", | |
| +}; | |
| + | |
| +static const char * const remote_out_groups[] = { | |
| + "remote_out", | |
| +}; | |
| + | |
| +static const char * const spdif_in_groups[] = { | |
| + "spdif_in_f6", "spdif_in_f7", | |
| +}; | |
| + | |
| +static const char * const sw_groups[] = { | |
| + "swclk", "swdio", | |
| +}; | |
| + | |
| +static const char * const clk25_groups[] = { | |
| + "clk_25", | |
| +}; | |
| + | |
| +static const char * const cec_a_groups[] = { | |
| + "cec_a", | |
| +}; | |
| + | |
| +static const char * const cec_b_groups[] = { | |
| + "cec_b", | |
| +}; | |
| + | |
| +static const char * const clk12_24_groups[] = { | |
| + "clk12_24", | |
| +}; | |
| + | |
| +static const char * const mclk_0_groups[] = { | |
| + "mclk_0", | |
| +}; | |
| + | |
| +static const char * const tdm_b_groups[] = { | |
| + "tdm_b_din0", "tdm_b_din1", "tdm_b_din2", | |
| + "tdm_b_sclk", "tdm_b_fs", "tdm_b_dout0", "tdm_b_dout1", | |
| + "tdm_b_dout2", "tdm_b_dout3", "tdm_b_dout4", "tdm_b_dout5", | |
| + "tdm_b_slv_sclk", "tdm_b_slv_fs", | |
| +}; | |
| + | |
| +static const char * const mclk_vad_groups[] = { | |
| + "mclk_vad", | |
| +}; | |
| + | |
| +static const char * const tdm_vad_groups[] = { | |
| + "tdm_vad_sclk_a1", "tdm_vad_fs_a2", "tdm_vad_sclk_a5", "tdm_vad_fs_a6", | |
| +}; | |
| + | |
| +static const char * const tst_out_groups[] = { | |
| + "tst_out0", "tst_out1", "tst_out2", "tst_out3", | |
| + "tst_out4", "tst_out5", "tst_out6", "tst_out7", | |
| + "tst_out8", "tst_out9", "tst_out10", "tst_out11", | |
| +}; | |
| + | |
| +static const char * const mute_groups[] = { | |
| + "mute_key", "mute_en", | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson_a1_periphs_functions[] = { | |
| + FUNCTION(gpio_periphs), | |
| + FUNCTION(psram), | |
| + FUNCTION(pwm_a), | |
| + FUNCTION(pwm_b), | |
| + FUNCTION(pwm_c), | |
| + FUNCTION(pwm_d), | |
| + FUNCTION(pwm_e), | |
| + FUNCTION(pwm_f), | |
| + FUNCTION(pwm_a_hiz), | |
| + FUNCTION(pwm_b_hiz), | |
| + FUNCTION(pwm_c_hiz), | |
| + FUNCTION(spif), | |
| + FUNCTION(sdcard), | |
| + FUNCTION(tdm_a), | |
| + FUNCTION(uart_a), | |
| + FUNCTION(uart_b), | |
| + FUNCTION(uart_c), | |
| + FUNCTION(i2c0), | |
| + FUNCTION(i2c1), | |
| + FUNCTION(i2c2), | |
| + FUNCTION(i2c3), | |
| + FUNCTION(spi_a), | |
| + FUNCTION(pdm), | |
| + FUNCTION(gen_clk), | |
| + FUNCTION(remote_input), | |
| + FUNCTION(jtag_a), | |
| + FUNCTION(clk_32k_in), | |
| + FUNCTION(remote_out), | |
| + FUNCTION(spdif_in), | |
| + FUNCTION(sw), | |
| + FUNCTION(clk25), | |
| + FUNCTION(cec_a), | |
| + FUNCTION(cec_b), | |
| + FUNCTION(clk12_24), | |
| + FUNCTION(mclk_0), | |
| + FUNCTION(tdm_b), | |
| + FUNCTION(mclk_vad), | |
| + FUNCTION(tdm_vad), | |
| + FUNCTION(tst_out), | |
| + FUNCTION(mute), | |
| +}; | |
| + | |
| +static const struct meson_bank meson_a1_periphs_banks[] = { | |
| + /* name first last irq pullen pull dir out in ds*/ | |
| + BANK_DS("P", GPIOP_0, GPIOP_12, 0, 12, 0x3, 0, 0x4, 0, | |
| + 0x2, 0, 0x1, 0, 0x0, 0, 0x5, 0), | |
| + BANK_DS("B", GPIOB_0, GPIOB_6, 13, 19, 0x13, 0, 0x14, 0, | |
| + 0x12, 0, 0x11, 0, 0x10, 0, 0x15, 0), | |
| + BANK_DS("X", GPIOX_0, GPIOX_16, 20, 36, 0x23, 0, 0x24, 0, | |
| + 0x22, 0, 0x21, 0, 0x20, 0, 0x25, 0), | |
| + BANK_DS("F", GPIOF_0, GPIOF_12, 37, 49, 0x33, 0, 0x34, 0, | |
| + 0x32, 0, 0x31, 0, 0x30, 0, 0x35, 0), | |
| + BANK_DS("A", GPIOA_0, GPIOA_11, 50, 61, 0x43, 0, 0x44, 0, | |
| + 0x42, 0, 0x41, 0, 0x40, 0, 0x45, 0), | |
| +}; | |
| + | |
| +static const struct meson_pmx_bank meson_a1_periphs_pmx_banks[] = { | |
| + /* name first lask reg offset */ | |
| + BANK_PMX("P", GPIOP_0, GPIOP_12, 0x0, 0), | |
| + BANK_PMX("B", GPIOB_0, GPIOB_6, 0x2, 0), | |
| + BANK_PMX("X", GPIOX_0, GPIOX_16, 0x3, 0), | |
| + BANK_PMX("F", GPIOF_0, GPIOF_12, 0x6, 0), | |
| + BANK_PMX("A", GPIOA_0, GPIOA_11, 0x8, 0), | |
| +}; | |
| + | |
| +static const struct meson_axg_pmx_data meson_a1_periphs_pmx_banks_data = { | |
| + .pmx_banks = meson_a1_periphs_pmx_banks, | |
| + .num_pmx_banks = ARRAY_SIZE(meson_a1_periphs_pmx_banks), | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data meson_a1_periphs_pinctrl_data = { | |
| + .name = "periphs-banks", | |
| + .pins = meson_a1_periphs_pins, | |
| + .groups = meson_a1_periphs_groups, | |
| + .funcs = meson_a1_periphs_functions, | |
| + .banks = meson_a1_periphs_banks, | |
| + .num_pins = ARRAY_SIZE(meson_a1_periphs_pins), | |
| + .num_groups = ARRAY_SIZE(meson_a1_periphs_groups), | |
| + .num_funcs = ARRAY_SIZE(meson_a1_periphs_functions), | |
| + .num_banks = ARRAY_SIZE(meson_a1_periphs_banks), | |
| + .pmx_ops = &meson_axg_pmx_ops, | |
| + .pmx_data = &meson_a1_periphs_pmx_banks_data, | |
| + .parse_dt = &meson_a1_parse_dt_extra, | |
| +}; | |
| + | |
| +static const struct of_device_id meson_a1_pinctrl_dt_match[] = { | |
| + { | |
| + .compatible = "amlogic,meson-a1-periphs-pinctrl", | |
| + .data = &meson_a1_periphs_pinctrl_data, | |
| + }, | |
| + { }, | |
| +}; | |
| +MODULE_DEVICE_TABLE(of, meson_a1_pinctrl_dt_match); | |
| + | |
| +static struct platform_driver meson_a1_pinctrl_driver = { | |
| + .probe = meson_pinctrl_probe, | |
| + .driver = { | |
| + .name = "meson-a1-pinctrl", | |
| + .of_match_table = meson_a1_pinctrl_dt_match, | |
| + }, | |
| +}; | |
| + | |
| +module_platform_driver(meson_a1_pinctrl_driver); | |
| +MODULE_DESCRIPTION("Amlogic Meson A1 SoC pinctrl driver"); | |
| +MODULE_LICENSE("Dual BSD/GPL"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | |
| new file mode 100644 | |
| index 0000000000..00c3829216 | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | |
| @@ -0,0 +1,121 @@ | |
| +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | |
| +/* | |
| + * Second generation of pinmux driver for Amlogic Meson-AXG SoC. | |
| + * | |
| + * Copyright (c) 2017 Baylibre SAS. | |
| + * Author: Jerome Brunet <jbrunet@baylibre.com> | |
| + * | |
| + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. | |
| + * Author: Xingyu Chen <xingyu.chen@amlogic.com> | |
| + */ | |
| + | |
| +/* | |
| + * This new generation of pinctrl IP is mainly adopted by the | |
| + * Meson-AXG SoC and later series, which use 4-width continuous | |
| + * register bit to select the function for each pin. | |
| + * | |
| + * The value 0 is always selecting the GPIO mode, while other | |
| + * values (start from 1) for selecting the function mode. | |
| + */ | |
| +#include <linux/device.h> | |
| +#include <linux/regmap.h> | |
| +#include <linux/pinctrl/pinctrl.h> | |
| +#include <linux/pinctrl/pinmux.h> | |
| + | |
| +#include "pinctrl-meson.h" | |
| +#include "pinctrl-meson-axg-pmx.h" | |
| + | |
| +static int meson_axg_pmx_get_bank(struct meson_pinctrl *pc, | |
| + unsigned int pin, | |
| + const struct meson_pmx_bank **bank) | |
| +{ | |
| + int i; | |
| + const struct meson_axg_pmx_data *pmx = pc->data->pmx_data; | |
| + | |
| + for (i = 0; i < pmx->num_pmx_banks; i++) | |
| + if (pin >= pmx->pmx_banks[i].first && | |
| + pin <= pmx->pmx_banks[i].last) { | |
| + *bank = &pmx->pmx_banks[i]; | |
| + return 0; | |
| + } | |
| + | |
| + return -EINVAL; | |
| +} | |
| + | |
| +static int meson_pmx_calc_reg_and_offset(const struct meson_pmx_bank *bank, | |
| + unsigned int pin, unsigned int *reg, | |
| + unsigned int *offset) | |
| +{ | |
| + int shift; | |
| + | |
| + shift = pin - bank->first; | |
| + | |
| + *reg = bank->reg + (bank->offset + (shift << 2)) / 32; | |
| + *offset = (bank->offset + (shift << 2)) % 32; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int meson_axg_pmx_update_function(struct meson_pinctrl *pc, | |
| + unsigned int pin, unsigned int func) | |
| +{ | |
| + const struct meson_pmx_bank *bank; | |
| + int ret; | |
| + int reg; | |
| + int offset; | |
| + | |
| + ret = meson_axg_pmx_get_bank(pc, pin, &bank); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + meson_pmx_calc_reg_and_offset(bank, pin, ®, &offset); | |
| + | |
| + ret = regmap_update_bits(pc->reg_mux, reg << 2, | |
| + 0xf << offset, (func & 0xf) << offset); | |
| + | |
| + return ret; | |
| +} | |
| + | |
| +static int meson_axg_pmx_set_mux(struct pinctrl_dev *pcdev, | |
| + unsigned int func_num, unsigned int group_num) | |
| +{ | |
| + int i; | |
| + int ret; | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| + const struct meson_pmx_func *func = &pc->data->funcs[func_num]; | |
| + const struct meson_pmx_group *group = &pc->data->groups[group_num]; | |
| + struct meson_pmx_axg_data *pmx_data = | |
| + (struct meson_pmx_axg_data *)group->data; | |
| + | |
| + dev_dbg(pc->dev, "enable function %s, group %s\n", func->name, | |
| + group->name); | |
| + | |
| + for (i = 0; i < group->num_pins; i++) { | |
| + ret = meson_axg_pmx_update_function(pc, group->pins[i], | |
| + pmx_data->func); | |
| + if (ret) | |
| + return ret; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int meson_axg_pmx_request_gpio(struct pinctrl_dev *pcdev, | |
| + struct pinctrl_gpio_range *range, unsigned int offset) | |
| +{ | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| + | |
| + return meson_axg_pmx_update_function(pc, offset, 0); | |
| +} | |
| + | |
| +const struct pinmux_ops meson_axg_pmx_ops = { | |
| + .set_mux = meson_axg_pmx_set_mux, | |
| + .get_functions_count = meson_pmx_get_funcs_count, | |
| + .get_function_name = meson_pmx_get_func_name, | |
| + .get_function_groups = meson_pmx_get_groups, | |
| + .gpio_request_enable = meson_axg_pmx_request_gpio, | |
| +}; | |
| +EXPORT_SYMBOL_GPL(meson_axg_pmx_ops); | |
| + | |
| +MODULE_DESCRIPTION("Amlogic Meson AXG second generation pinmux driver"); | |
| +MODULE_LICENSE("Dual BSD/GPL"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h | |
| new file mode 100644 | |
| index 0000000000..63b9d471e9 | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h | |
| @@ -0,0 +1,62 @@ | |
| +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ | |
| +/* | |
| + * Copyright (c) 2017 Baylibre SAS. | |
| + * Author: Jerome Brunet <jbrunet@baylibre.com> | |
| + * | |
| + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. | |
| + * Author: Xingyu Chen <xingyu.chen@amlogic.com> | |
| + * | |
| + */ | |
| + | |
| +struct meson_pmx_bank { | |
| + const char *name; | |
| + unsigned int first; | |
| + unsigned int last; | |
| + unsigned int reg; | |
| + unsigned int offset; | |
| +}; | |
| + | |
| +struct meson_axg_pmx_data { | |
| + const struct meson_pmx_bank *pmx_banks; | |
| + unsigned int num_pmx_banks; | |
| +}; | |
| + | |
| +#define BANK_PMX(n, f, l, r, o) \ | |
| + { \ | |
| + .name = n, \ | |
| + .first = f, \ | |
| + .last = l, \ | |
| + .reg = r, \ | |
| + .offset = o, \ | |
| + } | |
| + | |
| +struct meson_pmx_axg_data { | |
| + unsigned int func; | |
| +}; | |
| + | |
| +#define PMX_DATA(f) \ | |
| + { \ | |
| + .func = f, \ | |
| + } | |
| + | |
| +#define GROUP(grp, f) \ | |
| + { \ | |
| + .name = #grp, \ | |
| + .pins = grp ## _pins, \ | |
| + .num_pins = ARRAY_SIZE(grp ## _pins), \ | |
| + .data = (const struct meson_pmx_axg_data[]){ \ | |
| + PMX_DATA(f), \ | |
| + }, \ | |
| + } | |
| + | |
| +#define GPIO_GROUP(gpio) \ | |
| + { \ | |
| + .name = #gpio, \ | |
| + .pins = (const unsigned int[]){ gpio }, \ | |
| + .num_pins = 1, \ | |
| + .data = (const struct meson_pmx_axg_data[]){ \ | |
| + PMX_DATA(0), \ | |
| + }, \ | |
| + } | |
| + | |
| +extern const struct pinmux_ops meson_axg_pmx_ops; | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c | |
| new file mode 100644 | |
| index 0000000000..fa2df48963 | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c | |
| @@ -0,0 +1,1095 @@ | |
| +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | |
| +/* | |
| + * Pin controller and GPIO driver for Amlogic Meson AXG SoC. | |
| + * | |
| + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. | |
| + * Author: Xingyu Chen <xingyu.chen@amlogic.com> | |
| + */ | |
| + | |
| +#include <dt-bindings/gpio/meson-axg-gpio.h> | |
| +#include "pinctrl-meson.h" | |
| +#include "pinctrl-meson-axg-pmx.h" | |
| + | |
| +static const struct pinctrl_pin_desc meson_axg_periphs_pins[] = { | |
| + MESON_PIN(GPIOZ_0), | |
| + MESON_PIN(GPIOZ_1), | |
| + MESON_PIN(GPIOZ_2), | |
| + MESON_PIN(GPIOZ_3), | |
| + MESON_PIN(GPIOZ_4), | |
| + MESON_PIN(GPIOZ_5), | |
| + MESON_PIN(GPIOZ_6), | |
| + MESON_PIN(GPIOZ_7), | |
| + MESON_PIN(GPIOZ_8), | |
| + MESON_PIN(GPIOZ_9), | |
| + MESON_PIN(GPIOZ_10), | |
| + MESON_PIN(BOOT_0), | |
| + MESON_PIN(BOOT_1), | |
| + MESON_PIN(BOOT_2), | |
| + MESON_PIN(BOOT_3), | |
| + MESON_PIN(BOOT_4), | |
| + MESON_PIN(BOOT_5), | |
| + MESON_PIN(BOOT_6), | |
| + MESON_PIN(BOOT_7), | |
| + MESON_PIN(BOOT_8), | |
| + MESON_PIN(BOOT_9), | |
| + MESON_PIN(BOOT_10), | |
| + MESON_PIN(BOOT_11), | |
| + MESON_PIN(BOOT_12), | |
| + MESON_PIN(BOOT_13), | |
| + MESON_PIN(BOOT_14), | |
| + MESON_PIN(GPIOA_0), | |
| + MESON_PIN(GPIOA_1), | |
| + MESON_PIN(GPIOA_2), | |
| + MESON_PIN(GPIOA_3), | |
| + MESON_PIN(GPIOA_4), | |
| + MESON_PIN(GPIOA_5), | |
| + MESON_PIN(GPIOA_6), | |
| + MESON_PIN(GPIOA_7), | |
| + MESON_PIN(GPIOA_8), | |
| + MESON_PIN(GPIOA_9), | |
| + MESON_PIN(GPIOA_10), | |
| + MESON_PIN(GPIOA_11), | |
| + MESON_PIN(GPIOA_12), | |
| + MESON_PIN(GPIOA_13), | |
| + MESON_PIN(GPIOA_14), | |
| + MESON_PIN(GPIOA_15), | |
| + MESON_PIN(GPIOA_16), | |
| + MESON_PIN(GPIOA_17), | |
| + MESON_PIN(GPIOA_18), | |
| + MESON_PIN(GPIOA_19), | |
| + MESON_PIN(GPIOA_20), | |
| + MESON_PIN(GPIOX_0), | |
| + MESON_PIN(GPIOX_1), | |
| + MESON_PIN(GPIOX_2), | |
| + MESON_PIN(GPIOX_3), | |
| + MESON_PIN(GPIOX_4), | |
| + MESON_PIN(GPIOX_5), | |
| + MESON_PIN(GPIOX_6), | |
| + MESON_PIN(GPIOX_7), | |
| + MESON_PIN(GPIOX_8), | |
| + MESON_PIN(GPIOX_9), | |
| + MESON_PIN(GPIOX_10), | |
| + MESON_PIN(GPIOX_11), | |
| + MESON_PIN(GPIOX_12), | |
| + MESON_PIN(GPIOX_13), | |
| + MESON_PIN(GPIOX_14), | |
| + MESON_PIN(GPIOX_15), | |
| + MESON_PIN(GPIOX_16), | |
| + MESON_PIN(GPIOX_17), | |
| + MESON_PIN(GPIOX_18), | |
| + MESON_PIN(GPIOX_19), | |
| + MESON_PIN(GPIOX_20), | |
| + MESON_PIN(GPIOX_21), | |
| + MESON_PIN(GPIOX_22), | |
| + MESON_PIN(GPIOY_0), | |
| + MESON_PIN(GPIOY_1), | |
| + MESON_PIN(GPIOY_2), | |
| + MESON_PIN(GPIOY_3), | |
| + MESON_PIN(GPIOY_4), | |
| + MESON_PIN(GPIOY_5), | |
| + MESON_PIN(GPIOY_6), | |
| + MESON_PIN(GPIOY_7), | |
| + MESON_PIN(GPIOY_8), | |
| + MESON_PIN(GPIOY_9), | |
| + MESON_PIN(GPIOY_10), | |
| + MESON_PIN(GPIOY_11), | |
| + MESON_PIN(GPIOY_12), | |
| + MESON_PIN(GPIOY_13), | |
| + MESON_PIN(GPIOY_14), | |
| + MESON_PIN(GPIOY_15), | |
| +}; | |
| + | |
| +static const struct pinctrl_pin_desc meson_axg_aobus_pins[] = { | |
| + MESON_PIN(GPIOAO_0), | |
| + MESON_PIN(GPIOAO_1), | |
| + MESON_PIN(GPIOAO_2), | |
| + MESON_PIN(GPIOAO_3), | |
| + MESON_PIN(GPIOAO_4), | |
| + MESON_PIN(GPIOAO_5), | |
| + MESON_PIN(GPIOAO_6), | |
| + MESON_PIN(GPIOAO_7), | |
| + MESON_PIN(GPIOAO_8), | |
| + MESON_PIN(GPIOAO_9), | |
| + MESON_PIN(GPIOAO_10), | |
| + MESON_PIN(GPIOAO_11), | |
| + MESON_PIN(GPIOAO_12), | |
| + MESON_PIN(GPIOAO_13), | |
| + MESON_PIN(GPIO_TEST_N), | |
| +}; | |
| + | |
| +/* emmc */ | |
| +static const unsigned int emmc_nand_d0_pins[] = {BOOT_0}; | |
| +static const unsigned int emmc_nand_d1_pins[] = {BOOT_1}; | |
| +static const unsigned int emmc_nand_d2_pins[] = {BOOT_2}; | |
| +static const unsigned int emmc_nand_d3_pins[] = {BOOT_3}; | |
| +static const unsigned int emmc_nand_d4_pins[] = {BOOT_4}; | |
| +static const unsigned int emmc_nand_d5_pins[] = {BOOT_5}; | |
| +static const unsigned int emmc_nand_d6_pins[] = {BOOT_6}; | |
| +static const unsigned int emmc_nand_d7_pins[] = {BOOT_7}; | |
| + | |
| +static const unsigned int emmc_clk_pins[] = {BOOT_8}; | |
| +static const unsigned int emmc_cmd_pins[] = {BOOT_10}; | |
| +static const unsigned int emmc_ds_pins[] = {BOOT_13}; | |
| + | |
| +/* nand */ | |
| +static const unsigned int nand_ce0_pins[] = {BOOT_8}; | |
| +static const unsigned int nand_ale_pins[] = {BOOT_9}; | |
| +static const unsigned int nand_cle_pins[] = {BOOT_10}; | |
| +static const unsigned int nand_wen_clk_pins[] = {BOOT_11}; | |
| +static const unsigned int nand_ren_wr_pins[] = {BOOT_12}; | |
| +static const unsigned int nand_rb0_pins[] = {BOOT_13}; | |
| + | |
| +/* nor */ | |
| +static const unsigned int nor_hold_pins[] = {BOOT_3}; | |
| +static const unsigned int nor_d_pins[] = {BOOT_4}; | |
| +static const unsigned int nor_q_pins[] = {BOOT_5}; | |
| +static const unsigned int nor_c_pins[] = {BOOT_6}; | |
| +static const unsigned int nor_wp_pins[] = {BOOT_9}; | |
| +static const unsigned int nor_cs_pins[] = {BOOT_14}; | |
| + | |
| +/* sdio */ | |
| +static const unsigned int sdio_d0_pins[] = {GPIOX_0}; | |
| +static const unsigned int sdio_d1_pins[] = {GPIOX_1}; | |
| +static const unsigned int sdio_d2_pins[] = {GPIOX_2}; | |
| +static const unsigned int sdio_d3_pins[] = {GPIOX_3}; | |
| +static const unsigned int sdio_clk_pins[] = {GPIOX_4}; | |
| +static const unsigned int sdio_cmd_pins[] = {GPIOX_5}; | |
| + | |
| +/* spi0 */ | |
| +static const unsigned int spi0_clk_pins[] = {GPIOZ_0}; | |
| +static const unsigned int spi0_mosi_pins[] = {GPIOZ_1}; | |
| +static const unsigned int spi0_miso_pins[] = {GPIOZ_2}; | |
| +static const unsigned int spi0_ss0_pins[] = {GPIOZ_3}; | |
| +static const unsigned int spi0_ss1_pins[] = {GPIOZ_4}; | |
| +static const unsigned int spi0_ss2_pins[] = {GPIOZ_5}; | |
| + | |
| +/* spi1 */ | |
| +static const unsigned int spi1_clk_x_pins[] = {GPIOX_19}; | |
| +static const unsigned int spi1_mosi_x_pins[] = {GPIOX_17}; | |
| +static const unsigned int spi1_miso_x_pins[] = {GPIOX_18}; | |
| +static const unsigned int spi1_ss0_x_pins[] = {GPIOX_16}; | |
| + | |
| +static const unsigned int spi1_clk_a_pins[] = {GPIOA_4}; | |
| +static const unsigned int spi1_mosi_a_pins[] = {GPIOA_2}; | |
| +static const unsigned int spi1_miso_a_pins[] = {GPIOA_3}; | |
| +static const unsigned int spi1_ss0_a_pins[] = {GPIOA_5}; | |
| +static const unsigned int spi1_ss1_pins[] = {GPIOA_6}; | |
| + | |
| +/* i2c0 */ | |
| +static const unsigned int i2c0_sck_pins[] = {GPIOZ_6}; | |
| +static const unsigned int i2c0_sda_pins[] = {GPIOZ_7}; | |
| + | |
| +/* i2c1 */ | |
| +static const unsigned int i2c1_sck_z_pins[] = {GPIOZ_8}; | |
| +static const unsigned int i2c1_sda_z_pins[] = {GPIOZ_9}; | |
| + | |
| +static const unsigned int i2c1_sck_x_pins[] = {GPIOX_16}; | |
| +static const unsigned int i2c1_sda_x_pins[] = {GPIOX_17}; | |
| + | |
| +/* i2c2 */ | |
| +static const unsigned int i2c2_sck_x_pins[] = {GPIOX_18}; | |
| +static const unsigned int i2c2_sda_x_pins[] = {GPIOX_19}; | |
| + | |
| +static const unsigned int i2c2_sda_a_pins[] = {GPIOA_17}; | |
| +static const unsigned int i2c2_sck_a_pins[] = {GPIOA_18}; | |
| + | |
| +/* i2c3 */ | |
| +static const unsigned int i2c3_sda_a6_pins[] = {GPIOA_6}; | |
| +static const unsigned int i2c3_sck_a7_pins[] = {GPIOA_7}; | |
| + | |
| +static const unsigned int i2c3_sda_a12_pins[] = {GPIOA_12}; | |
| +static const unsigned int i2c3_sck_a13_pins[] = {GPIOA_13}; | |
| + | |
| +static const unsigned int i2c3_sda_a19_pins[] = {GPIOA_19}; | |
| +static const unsigned int i2c3_sck_a20_pins[] = {GPIOA_20}; | |
| + | |
| +/* uart_a */ | |
| +static const unsigned int uart_rts_a_pins[] = {GPIOX_11}; | |
| +static const unsigned int uart_cts_a_pins[] = {GPIOX_10}; | |
| +static const unsigned int uart_tx_a_pins[] = {GPIOX_8}; | |
| +static const unsigned int uart_rx_a_pins[] = {GPIOX_9}; | |
| + | |
| +/* uart_b */ | |
| +static const unsigned int uart_rts_b_z_pins[] = {GPIOZ_0}; | |
| +static const unsigned int uart_cts_b_z_pins[] = {GPIOZ_1}; | |
| +static const unsigned int uart_tx_b_z_pins[] = {GPIOZ_2}; | |
| +static const unsigned int uart_rx_b_z_pins[] = {GPIOZ_3}; | |
| + | |
| +static const unsigned int uart_rts_b_x_pins[] = {GPIOX_18}; | |
| +static const unsigned int uart_cts_b_x_pins[] = {GPIOX_19}; | |
| +static const unsigned int uart_tx_b_x_pins[] = {GPIOX_16}; | |
| +static const unsigned int uart_rx_b_x_pins[] = {GPIOX_17}; | |
| + | |
| +/* uart_ao_b */ | |
| +static const unsigned int uart_ao_tx_b_z_pins[] = {GPIOZ_8}; | |
| +static const unsigned int uart_ao_rx_b_z_pins[] = {GPIOZ_9}; | |
| +static const unsigned int uart_ao_cts_b_z_pins[] = {GPIOZ_6}; | |
| +static const unsigned int uart_ao_rts_b_z_pins[] = {GPIOZ_7}; | |
| + | |
| +/* pwm_a */ | |
| +static const unsigned int pwm_a_z_pins[] = {GPIOZ_5}; | |
| + | |
| +static const unsigned int pwm_a_x18_pins[] = {GPIOX_18}; | |
| +static const unsigned int pwm_a_x20_pins[] = {GPIOX_20}; | |
| + | |
| +static const unsigned int pwm_a_a_pins[] = {GPIOA_14}; | |
| + | |
| +/* pwm_b */ | |
| +static const unsigned int pwm_b_z_pins[] = {GPIOZ_4}; | |
| + | |
| +static const unsigned int pwm_b_x_pins[] = {GPIOX_19}; | |
| + | |
| +static const unsigned int pwm_b_a_pins[] = {GPIOA_15}; | |
| + | |
| +/* pwm_c */ | |
| +static const unsigned int pwm_c_x10_pins[] = {GPIOX_10}; | |
| +static const unsigned int pwm_c_x17_pins[] = {GPIOX_17}; | |
| + | |
| +static const unsigned int pwm_c_a_pins[] = {GPIOA_16}; | |
| + | |
| +/* pwm_d */ | |
| +static const unsigned int pwm_d_x11_pins[] = {GPIOX_11}; | |
| +static const unsigned int pwm_d_x16_pins[] = {GPIOX_16}; | |
| + | |
| +/* pwm_vs */ | |
| +static const unsigned int pwm_vs_pins[] = {GPIOA_0}; | |
| + | |
| +/* spdif_in */ | |
| +static const unsigned int spdif_in_z_pins[] = {GPIOZ_4}; | |
| + | |
| +static const unsigned int spdif_in_a1_pins[] = {GPIOA_1}; | |
| +static const unsigned int spdif_in_a7_pins[] = {GPIOA_7}; | |
| +static const unsigned int spdif_in_a19_pins[] = {GPIOA_19}; | |
| +static const unsigned int spdif_in_a20_pins[] = {GPIOA_20}; | |
| + | |
| +/* spdif_out */ | |
| +static const unsigned int spdif_out_z_pins[] = {GPIOZ_5}; | |
| + | |
| +static const unsigned int spdif_out_a1_pins[] = {GPIOA_1}; | |
| +static const unsigned int spdif_out_a11_pins[] = {GPIOA_11}; | |
| +static const unsigned int spdif_out_a19_pins[] = {GPIOA_19}; | |
| +static const unsigned int spdif_out_a20_pins[] = {GPIOA_20}; | |
| + | |
| +/* jtag_ee */ | |
| +static const unsigned int jtag_tdo_x_pins[] = {GPIOX_0}; | |
| +static const unsigned int jtag_tdi_x_pins[] = {GPIOX_1}; | |
| +static const unsigned int jtag_clk_x_pins[] = {GPIOX_4}; | |
| +static const unsigned int jtag_tms_x_pins[] = {GPIOX_5}; | |
| + | |
| +/* eth */ | |
| +static const unsigned int eth_txd0_x_pins[] = {GPIOX_8}; | |
| +static const unsigned int eth_txd1_x_pins[] = {GPIOX_9}; | |
| +static const unsigned int eth_txen_x_pins[] = {GPIOX_10}; | |
| +static const unsigned int eth_rgmii_rx_clk_x_pins[] = {GPIOX_12}; | |
| +static const unsigned int eth_rxd0_x_pins[] = {GPIOX_13}; | |
| +static const unsigned int eth_rxd1_x_pins[] = {GPIOX_14}; | |
| +static const unsigned int eth_rx_dv_x_pins[] = {GPIOX_15}; | |
| +static const unsigned int eth_mdio_x_pins[] = {GPIOX_21}; | |
| +static const unsigned int eth_mdc_x_pins[] = {GPIOX_22}; | |
| + | |
| +static const unsigned int eth_txd0_y_pins[] = {GPIOY_10}; | |
| +static const unsigned int eth_txd1_y_pins[] = {GPIOY_11}; | |
| +static const unsigned int eth_txen_y_pins[] = {GPIOY_9}; | |
| +static const unsigned int eth_rgmii_rx_clk_y_pins[] = {GPIOY_2}; | |
| +static const unsigned int eth_rxd0_y_pins[] = {GPIOY_4}; | |
| +static const unsigned int eth_rxd1_y_pins[] = {GPIOY_5}; | |
| +static const unsigned int eth_rx_dv_y_pins[] = {GPIOY_3}; | |
| +static const unsigned int eth_mdio_y_pins[] = {GPIOY_0}; | |
| +static const unsigned int eth_mdc_y_pins[] = {GPIOY_1}; | |
| + | |
| +static const unsigned int eth_rxd2_rgmii_pins[] = {GPIOY_6}; | |
| +static const unsigned int eth_rxd3_rgmii_pins[] = {GPIOY_7}; | |
| +static const unsigned int eth_rgmii_tx_clk_pins[] = {GPIOY_8}; | |
| +static const unsigned int eth_txd2_rgmii_pins[] = {GPIOY_12}; | |
| +static const unsigned int eth_txd3_rgmii_pins[] = {GPIOY_13}; | |
| + | |
| +/* pdm */ | |
| +static const unsigned int pdm_dclk_a14_pins[] = {GPIOA_14}; | |
| +static const unsigned int pdm_dclk_a19_pins[] = {GPIOA_19}; | |
| +static const unsigned int pdm_din0_pins[] = {GPIOA_15}; | |
| +static const unsigned int pdm_din1_pins[] = {GPIOA_16}; | |
| +static const unsigned int pdm_din2_pins[] = {GPIOA_17}; | |
| +static const unsigned int pdm_din3_pins[] = {GPIOA_18}; | |
| + | |
| +/* mclk */ | |
| +static const unsigned int mclk_c_pins[] = {GPIOA_0}; | |
| +static const unsigned int mclk_b_pins[] = {GPIOA_1}; | |
| + | |
| +/* tdm */ | |
| +static const unsigned int tdma_sclk_pins[] = {GPIOX_12}; | |
| +static const unsigned int tdma_sclk_slv_pins[] = {GPIOX_12}; | |
| +static const unsigned int tdma_fs_pins[] = {GPIOX_13}; | |
| +static const unsigned int tdma_fs_slv_pins[] = {GPIOX_13}; | |
| +static const unsigned int tdma_din0_pins[] = {GPIOX_14}; | |
| +static const unsigned int tdma_dout0_x14_pins[] = {GPIOX_14}; | |
| +static const unsigned int tdma_dout0_x15_pins[] = {GPIOX_15}; | |
| +static const unsigned int tdma_dout1_pins[] = {GPIOX_15}; | |
| +static const unsigned int tdma_din1_pins[] = {GPIOX_15}; | |
| + | |
| +static const unsigned int tdmc_sclk_pins[] = {GPIOA_2}; | |
| +static const unsigned int tdmc_sclk_slv_pins[] = {GPIOA_2}; | |
| +static const unsigned int tdmc_fs_pins[] = {GPIOA_3}; | |
| +static const unsigned int tdmc_fs_slv_pins[] = {GPIOA_3}; | |
| +static const unsigned int tdmc_din0_pins[] = {GPIOA_4}; | |
| +static const unsigned int tdmc_dout0_pins[] = {GPIOA_4}; | |
| +static const unsigned int tdmc_din1_pins[] = {GPIOA_5}; | |
| +static const unsigned int tdmc_dout1_pins[] = {GPIOA_5}; | |
| +static const unsigned int tdmc_din2_pins[] = {GPIOA_6}; | |
| +static const unsigned int tdmc_dout2_pins[] = {GPIOA_6}; | |
| +static const unsigned int tdmc_din3_pins[] = {GPIOA_7}; | |
| +static const unsigned int tdmc_dout3_pins[] = {GPIOA_7}; | |
| + | |
| +static const unsigned int tdmb_sclk_pins[] = {GPIOA_8}; | |
| +static const unsigned int tdmb_sclk_slv_pins[] = {GPIOA_8}; | |
| +static const unsigned int tdmb_fs_pins[] = {GPIOA_9}; | |
| +static const unsigned int tdmb_fs_slv_pins[] = {GPIOA_9}; | |
| +static const unsigned int tdmb_din0_pins[] = {GPIOA_10}; | |
| +static const unsigned int tdmb_dout0_pins[] = {GPIOA_10}; | |
| +static const unsigned int tdmb_din1_pins[] = {GPIOA_11}; | |
| +static const unsigned int tdmb_dout1_pins[] = {GPIOA_11}; | |
| +static const unsigned int tdmb_din2_pins[] = {GPIOA_12}; | |
| +static const unsigned int tdmb_dout2_pins[] = {GPIOA_12}; | |
| +static const unsigned int tdmb_din3_pins[] = {GPIOA_13}; | |
| +static const unsigned int tdmb_dout3_pins[] = {GPIOA_13}; | |
| + | |
| +static const struct meson_pmx_group meson_axg_periphs_groups[] = { | |
| + GPIO_GROUP(GPIOZ_0), | |
| + GPIO_GROUP(GPIOZ_1), | |
| + GPIO_GROUP(GPIOZ_2), | |
| + GPIO_GROUP(GPIOZ_3), | |
| + GPIO_GROUP(GPIOZ_4), | |
| + GPIO_GROUP(GPIOZ_5), | |
| + GPIO_GROUP(GPIOZ_6), | |
| + GPIO_GROUP(GPIOZ_7), | |
| + GPIO_GROUP(GPIOZ_8), | |
| + GPIO_GROUP(GPIOZ_9), | |
| + GPIO_GROUP(GPIOZ_10), | |
| + | |
| + GPIO_GROUP(BOOT_0), | |
| + GPIO_GROUP(BOOT_1), | |
| + GPIO_GROUP(BOOT_2), | |
| + GPIO_GROUP(BOOT_3), | |
| + GPIO_GROUP(BOOT_4), | |
| + GPIO_GROUP(BOOT_5), | |
| + GPIO_GROUP(BOOT_6), | |
| + GPIO_GROUP(BOOT_7), | |
| + GPIO_GROUP(BOOT_8), | |
| + GPIO_GROUP(BOOT_9), | |
| + GPIO_GROUP(BOOT_10), | |
| + GPIO_GROUP(BOOT_11), | |
| + GPIO_GROUP(BOOT_12), | |
| + GPIO_GROUP(BOOT_13), | |
| + GPIO_GROUP(BOOT_14), | |
| + | |
| + GPIO_GROUP(GPIOA_0), | |
| + GPIO_GROUP(GPIOA_1), | |
| + GPIO_GROUP(GPIOA_2), | |
| + GPIO_GROUP(GPIOA_3), | |
| + GPIO_GROUP(GPIOA_4), | |
| + GPIO_GROUP(GPIOA_5), | |
| + GPIO_GROUP(GPIOA_6), | |
| + GPIO_GROUP(GPIOA_7), | |
| + GPIO_GROUP(GPIOA_8), | |
| + GPIO_GROUP(GPIOA_9), | |
| + GPIO_GROUP(GPIOA_10), | |
| + GPIO_GROUP(GPIOA_11), | |
| + GPIO_GROUP(GPIOA_12), | |
| + GPIO_GROUP(GPIOA_13), | |
| + GPIO_GROUP(GPIOA_14), | |
| + GPIO_GROUP(GPIOA_15), | |
| + GPIO_GROUP(GPIOA_16), | |
| + GPIO_GROUP(GPIOA_17), | |
| + GPIO_GROUP(GPIOA_18), | |
| + GPIO_GROUP(GPIOA_19), | |
| + GPIO_GROUP(GPIOA_20), | |
| + | |
| + GPIO_GROUP(GPIOX_0), | |
| + GPIO_GROUP(GPIOX_1), | |
| + GPIO_GROUP(GPIOX_2), | |
| + GPIO_GROUP(GPIOX_3), | |
| + GPIO_GROUP(GPIOX_4), | |
| + GPIO_GROUP(GPIOX_5), | |
| + GPIO_GROUP(GPIOX_6), | |
| + GPIO_GROUP(GPIOX_7), | |
| + GPIO_GROUP(GPIOX_8), | |
| + GPIO_GROUP(GPIOX_9), | |
| + GPIO_GROUP(GPIOX_10), | |
| + GPIO_GROUP(GPIOX_11), | |
| + GPIO_GROUP(GPIOX_12), | |
| + GPIO_GROUP(GPIOX_13), | |
| + GPIO_GROUP(GPIOX_14), | |
| + GPIO_GROUP(GPIOX_15), | |
| + GPIO_GROUP(GPIOX_16), | |
| + GPIO_GROUP(GPIOX_17), | |
| + GPIO_GROUP(GPIOX_18), | |
| + GPIO_GROUP(GPIOX_19), | |
| + GPIO_GROUP(GPIOX_20), | |
| + GPIO_GROUP(GPIOX_21), | |
| + GPIO_GROUP(GPIOX_22), | |
| + | |
| + GPIO_GROUP(GPIOY_0), | |
| + GPIO_GROUP(GPIOY_1), | |
| + GPIO_GROUP(GPIOY_2), | |
| + GPIO_GROUP(GPIOY_3), | |
| + GPIO_GROUP(GPIOY_4), | |
| + GPIO_GROUP(GPIOY_5), | |
| + GPIO_GROUP(GPIOY_6), | |
| + GPIO_GROUP(GPIOY_7), | |
| + GPIO_GROUP(GPIOY_8), | |
| + GPIO_GROUP(GPIOY_9), | |
| + GPIO_GROUP(GPIOY_10), | |
| + GPIO_GROUP(GPIOY_11), | |
| + GPIO_GROUP(GPIOY_12), | |
| + GPIO_GROUP(GPIOY_13), | |
| + GPIO_GROUP(GPIOY_14), | |
| + GPIO_GROUP(GPIOY_15), | |
| + | |
| + /* bank BOOT */ | |
| + GROUP(emmc_nand_d0, 1), | |
| + GROUP(emmc_nand_d1, 1), | |
| + GROUP(emmc_nand_d2, 1), | |
| + GROUP(emmc_nand_d3, 1), | |
| + GROUP(emmc_nand_d4, 1), | |
| + GROUP(emmc_nand_d5, 1), | |
| + GROUP(emmc_nand_d6, 1), | |
| + GROUP(emmc_nand_d7, 1), | |
| + GROUP(emmc_clk, 1), | |
| + GROUP(emmc_cmd, 1), | |
| + GROUP(emmc_ds, 1), | |
| + GROUP(nand_ce0, 2), | |
| + GROUP(nand_ale, 2), | |
| + GROUP(nand_cle, 2), | |
| + GROUP(nand_wen_clk, 2), | |
| + GROUP(nand_ren_wr, 2), | |
| + GROUP(nand_rb0, 2), | |
| + GROUP(nor_hold, 3), | |
| + GROUP(nor_d, 3), | |
| + GROUP(nor_q, 3), | |
| + GROUP(nor_c, 3), | |
| + GROUP(nor_wp, 3), | |
| + GROUP(nor_cs, 3), | |
| + | |
| + /* bank GPIOZ */ | |
| + GROUP(spi0_clk, 1), | |
| + GROUP(spi0_mosi, 1), | |
| + GROUP(spi0_miso, 1), | |
| + GROUP(spi0_ss0, 1), | |
| + GROUP(spi0_ss1, 1), | |
| + GROUP(spi0_ss2, 1), | |
| + GROUP(i2c0_sck, 1), | |
| + GROUP(i2c0_sda, 1), | |
| + GROUP(i2c1_sck_z, 1), | |
| + GROUP(i2c1_sda_z, 1), | |
| + GROUP(uart_rts_b_z, 2), | |
| + GROUP(uart_cts_b_z, 2), | |
| + GROUP(uart_tx_b_z, 2), | |
| + GROUP(uart_rx_b_z, 2), | |
| + GROUP(pwm_a_z, 2), | |
| + GROUP(pwm_b_z, 2), | |
| + GROUP(spdif_in_z, 3), | |
| + GROUP(spdif_out_z, 3), | |
| + GROUP(uart_ao_tx_b_z, 2), | |
| + GROUP(uart_ao_rx_b_z, 2), | |
| + GROUP(uart_ao_cts_b_z, 2), | |
| + GROUP(uart_ao_rts_b_z, 2), | |
| + | |
| + /* bank GPIOX */ | |
| + GROUP(sdio_d0, 1), | |
| + GROUP(sdio_d1, 1), | |
| + GROUP(sdio_d2, 1), | |
| + GROUP(sdio_d3, 1), | |
| + GROUP(sdio_clk, 1), | |
| + GROUP(sdio_cmd, 1), | |
| + GROUP(i2c1_sck_x, 1), | |
| + GROUP(i2c1_sda_x, 1), | |
| + GROUP(i2c2_sck_x, 1), | |
| + GROUP(i2c2_sda_x, 1), | |
| + GROUP(uart_rts_a, 1), | |
| + GROUP(uart_cts_a, 1), | |
| + GROUP(uart_tx_a, 1), | |
| + GROUP(uart_rx_a, 1), | |
| + GROUP(uart_rts_b_x, 2), | |
| + GROUP(uart_cts_b_x, 2), | |
| + GROUP(uart_tx_b_x, 2), | |
| + GROUP(uart_rx_b_x, 2), | |
| + GROUP(jtag_tdo_x, 2), | |
| + GROUP(jtag_tdi_x, 2), | |
| + GROUP(jtag_clk_x, 2), | |
| + GROUP(jtag_tms_x, 2), | |
| + GROUP(spi1_clk_x, 4), | |
| + GROUP(spi1_mosi_x, 4), | |
| + GROUP(spi1_miso_x, 4), | |
| + GROUP(spi1_ss0_x, 4), | |
| + GROUP(pwm_a_x18, 3), | |
| + GROUP(pwm_a_x20, 1), | |
| + GROUP(pwm_b_x, 3), | |
| + GROUP(pwm_c_x10, 3), | |
| + GROUP(pwm_c_x17, 3), | |
| + GROUP(pwm_d_x11, 3), | |
| + GROUP(pwm_d_x16, 3), | |
| + GROUP(eth_txd0_x, 4), | |
| + GROUP(eth_txd1_x, 4), | |
| + GROUP(eth_txen_x, 4), | |
| + GROUP(eth_rgmii_rx_clk_x, 4), | |
| + GROUP(eth_rxd0_x, 4), | |
| + GROUP(eth_rxd1_x, 4), | |
| + GROUP(eth_rx_dv_x, 4), | |
| + GROUP(eth_mdio_x, 4), | |
| + GROUP(eth_mdc_x, 4), | |
| + GROUP(tdma_sclk, 1), | |
| + GROUP(tdma_sclk_slv, 2), | |
| + GROUP(tdma_fs, 1), | |
| + GROUP(tdma_fs_slv, 2), | |
| + GROUP(tdma_din0, 1), | |
| + GROUP(tdma_dout0_x14, 2), | |
| + GROUP(tdma_dout0_x15, 1), | |
| + GROUP(tdma_dout1, 2), | |
| + GROUP(tdma_din1, 3), | |
| + | |
| + /* bank GPIOY */ | |
| + GROUP(eth_txd0_y, 1), | |
| + GROUP(eth_txd1_y, 1), | |
| + GROUP(eth_txen_y, 1), | |
| + GROUP(eth_rgmii_rx_clk_y, 1), | |
| + GROUP(eth_rxd0_y, 1), | |
| + GROUP(eth_rxd1_y, 1), | |
| + GROUP(eth_rx_dv_y, 1), | |
| + GROUP(eth_mdio_y, 1), | |
| + GROUP(eth_mdc_y, 1), | |
| + GROUP(eth_rxd2_rgmii, 1), | |
| + GROUP(eth_rxd3_rgmii, 1), | |
| + GROUP(eth_rgmii_tx_clk, 1), | |
| + GROUP(eth_txd2_rgmii, 1), | |
| + GROUP(eth_txd3_rgmii, 1), | |
| + | |
| + /* bank GPIOA */ | |
| + GROUP(spdif_out_a1, 4), | |
| + GROUP(spdif_out_a11, 3), | |
| + GROUP(spdif_out_a19, 2), | |
| + GROUP(spdif_out_a20, 1), | |
| + GROUP(spdif_in_a1, 3), | |
| + GROUP(spdif_in_a7, 3), | |
| + GROUP(spdif_in_a19, 1), | |
| + GROUP(spdif_in_a20, 2), | |
| + GROUP(spi1_clk_a, 3), | |
| + GROUP(spi1_mosi_a, 3), | |
| + GROUP(spi1_miso_a, 3), | |
| + GROUP(spi1_ss0_a, 3), | |
| + GROUP(spi1_ss1, 3), | |
| + GROUP(pwm_a_a, 3), | |
| + GROUP(pwm_b_a, 3), | |
| + GROUP(pwm_c_a, 3), | |
| + GROUP(pwm_vs, 2), | |
| + GROUP(i2c2_sda_a, 3), | |
| + GROUP(i2c2_sck_a, 3), | |
| + GROUP(i2c3_sda_a6, 4), | |
| + GROUP(i2c3_sck_a7, 4), | |
| + GROUP(i2c3_sda_a12, 4), | |
| + GROUP(i2c3_sck_a13, 4), | |
| + GROUP(i2c3_sda_a19, 4), | |
| + GROUP(i2c3_sck_a20, 4), | |
| + GROUP(pdm_dclk_a14, 1), | |
| + GROUP(pdm_dclk_a19, 3), | |
| + GROUP(pdm_din0, 1), | |
| + GROUP(pdm_din1, 1), | |
| + GROUP(pdm_din2, 1), | |
| + GROUP(pdm_din3, 1), | |
| + GROUP(mclk_c, 1), | |
| + GROUP(mclk_b, 1), | |
| + GROUP(tdmc_sclk, 1), | |
| + GROUP(tdmc_sclk_slv, 2), | |
| + GROUP(tdmc_fs, 1), | |
| + GROUP(tdmc_fs_slv, 2), | |
| + GROUP(tdmc_din0, 2), | |
| + GROUP(tdmc_dout0, 1), | |
| + GROUP(tdmc_din1, 2), | |
| + GROUP(tdmc_dout1, 1), | |
| + GROUP(tdmc_din2, 2), | |
| + GROUP(tdmc_dout2, 1), | |
| + GROUP(tdmc_din3, 2), | |
| + GROUP(tdmc_dout3, 1), | |
| + GROUP(tdmb_sclk, 1), | |
| + GROUP(tdmb_sclk_slv, 2), | |
| + GROUP(tdmb_fs, 1), | |
| + GROUP(tdmb_fs_slv, 2), | |
| + GROUP(tdmb_din0, 2), | |
| + GROUP(tdmb_dout0, 1), | |
| + GROUP(tdmb_din1, 2), | |
| + GROUP(tdmb_dout1, 1), | |
| + GROUP(tdmb_din2, 2), | |
| + GROUP(tdmb_dout2, 1), | |
| + GROUP(tdmb_din3, 2), | |
| + GROUP(tdmb_dout3, 1), | |
| +}; | |
| + | |
| +/* uart_ao_a */ | |
| +static const unsigned int uart_ao_tx_a_pins[] = {GPIOAO_0}; | |
| +static const unsigned int uart_ao_rx_a_pins[] = {GPIOAO_1}; | |
| +static const unsigned int uart_ao_cts_a_pins[] = {GPIOAO_2}; | |
| +static const unsigned int uart_ao_rts_a_pins[] = {GPIOAO_3}; | |
| + | |
| +/* uart_ao_b */ | |
| +static const unsigned int uart_ao_tx_b_pins[] = {GPIOAO_4}; | |
| +static const unsigned int uart_ao_rx_b_pins[] = {GPIOAO_5}; | |
| +static const unsigned int uart_ao_cts_b_pins[] = {GPIOAO_2}; | |
| +static const unsigned int uart_ao_rts_b_pins[] = {GPIOAO_3}; | |
| + | |
| +/* i2c_ao */ | |
| +static const unsigned int i2c_ao_sck_4_pins[] = {GPIOAO_4}; | |
| +static const unsigned int i2c_ao_sda_5_pins[] = {GPIOAO_5}; | |
| +static const unsigned int i2c_ao_sck_8_pins[] = {GPIOAO_8}; | |
| +static const unsigned int i2c_ao_sda_9_pins[] = {GPIOAO_9}; | |
| +static const unsigned int i2c_ao_sck_10_pins[] = {GPIOAO_10}; | |
| +static const unsigned int i2c_ao_sda_11_pins[] = {GPIOAO_11}; | |
| + | |
| +/* i2c_ao_slave */ | |
| +static const unsigned int i2c_ao_slave_sck_pins[] = {GPIOAO_10}; | |
| +static const unsigned int i2c_ao_slave_sda_pins[] = {GPIOAO_11}; | |
| + | |
| +/* ir_in */ | |
| +static const unsigned int remote_input_ao_pins[] = {GPIOAO_6}; | |
| + | |
| +/* ir_out */ | |
| +static const unsigned int remote_out_ao_pins[] = {GPIOAO_7}; | |
| + | |
| +/* pwm_ao_a */ | |
| +static const unsigned int pwm_ao_a_pins[] = {GPIOAO_3}; | |
| + | |
| +/* pwm_ao_b */ | |
| +static const unsigned int pwm_ao_b_ao2_pins[] = {GPIOAO_2}; | |
| +static const unsigned int pwm_ao_b_ao12_pins[] = {GPIOAO_12}; | |
| + | |
| +/* pwm_ao_c */ | |
| +static const unsigned int pwm_ao_c_ao8_pins[] = {GPIOAO_8}; | |
| +static const unsigned int pwm_ao_c_ao13_pins[] = {GPIOAO_13}; | |
| + | |
| +/* pwm_ao_d */ | |
| +static const unsigned int pwm_ao_d_pins[] = {GPIOAO_9}; | |
| + | |
| +/* jtag_ao */ | |
| +static const unsigned int jtag_ao_tdi_pins[] = {GPIOAO_3}; | |
| +static const unsigned int jtag_ao_tdo_pins[] = {GPIOAO_4}; | |
| +static const unsigned int jtag_ao_clk_pins[] = {GPIOAO_5}; | |
| +static const unsigned int jtag_ao_tms_pins[] = {GPIOAO_7}; | |
| + | |
| +/* gen_clk */ | |
| +static const unsigned int gen_clk_ee_pins[] = {GPIOAO_13}; | |
| + | |
| +static const struct meson_pmx_group meson_axg_aobus_groups[] = { | |
| + GPIO_GROUP(GPIOAO_0), | |
| + GPIO_GROUP(GPIOAO_1), | |
| + GPIO_GROUP(GPIOAO_2), | |
| + GPIO_GROUP(GPIOAO_3), | |
| + GPIO_GROUP(GPIOAO_4), | |
| + GPIO_GROUP(GPIOAO_5), | |
| + GPIO_GROUP(GPIOAO_6), | |
| + GPIO_GROUP(GPIOAO_7), | |
| + GPIO_GROUP(GPIOAO_8), | |
| + GPIO_GROUP(GPIOAO_9), | |
| + GPIO_GROUP(GPIOAO_10), | |
| + GPIO_GROUP(GPIOAO_11), | |
| + GPIO_GROUP(GPIOAO_12), | |
| + GPIO_GROUP(GPIOAO_13), | |
| + GPIO_GROUP(GPIO_TEST_N), | |
| + | |
| + /* bank AO */ | |
| + GROUP(uart_ao_tx_a, 1), | |
| + GROUP(uart_ao_rx_a, 1), | |
| + GROUP(uart_ao_cts_a, 2), | |
| + GROUP(uart_ao_rts_a, 2), | |
| + GROUP(uart_ao_tx_b, 1), | |
| + GROUP(uart_ao_rx_b, 1), | |
| + GROUP(uart_ao_cts_b, 1), | |
| + GROUP(uart_ao_rts_b, 1), | |
| + GROUP(i2c_ao_sck_4, 2), | |
| + GROUP(i2c_ao_sda_5, 2), | |
| + GROUP(i2c_ao_sck_8, 2), | |
| + GROUP(i2c_ao_sda_9, 2), | |
| + GROUP(i2c_ao_sck_10, 2), | |
| + GROUP(i2c_ao_sda_11, 2), | |
| + GROUP(i2c_ao_slave_sck, 1), | |
| + GROUP(i2c_ao_slave_sda, 1), | |
| + GROUP(remote_input_ao, 1), | |
| + GROUP(remote_out_ao, 1), | |
| + GROUP(pwm_ao_a, 3), | |
| + GROUP(pwm_ao_b_ao2, 3), | |
| + GROUP(pwm_ao_b_ao12, 3), | |
| + GROUP(pwm_ao_c_ao8, 3), | |
| + GROUP(pwm_ao_c_ao13, 3), | |
| + GROUP(pwm_ao_d, 3), | |
| + GROUP(jtag_ao_tdi, 4), | |
| + GROUP(jtag_ao_tdo, 4), | |
| + GROUP(jtag_ao_clk, 4), | |
| + GROUP(jtag_ao_tms, 4), | |
| + GROUP(gen_clk_ee, 4), | |
| +}; | |
| + | |
| +static const char * const gpio_periphs_groups[] = { | |
| + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", | |
| + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", | |
| + "GPIOZ_10", | |
| + | |
| + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", | |
| + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", | |
| + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", | |
| + | |
| + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", | |
| + "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9", | |
| + "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14", | |
| + "GPIOA_15", "GPIOA_16", "GPIOA_17", "GPIOA_18", "GPIOA_19", | |
| + "GPIOA_20", | |
| + | |
| + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", | |
| + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", | |
| + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", | |
| + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", | |
| + "GPIOX_20", "GPIOX_21", "GPIOX_22", | |
| + | |
| + "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4", | |
| + "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9", | |
| + "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14", | |
| + "GPIOY_15", | |
| +}; | |
| + | |
| +static const char * const emmc_groups[] = { | |
| + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", | |
| + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", | |
| + "emmc_nand_d6", "emmc_nand_d7", | |
| + "emmc_clk", "emmc_cmd", "emmc_ds", | |
| +}; | |
| + | |
| +static const char * const nand_groups[] = { | |
| + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", | |
| + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", | |
| + "emmc_nand_d6", "emmc_nand_d7", | |
| + "nand_ce0", "nand_ale", "nand_cle", | |
| + "nand_wen_clk", "nand_ren_wr", "nand_rb0", | |
| +}; | |
| + | |
| +static const char * const nor_groups[] = { | |
| + "nor_d", "nor_q", "nor_c", "nor_cs", | |
| + "nor_hold", "nor_wp", | |
| +}; | |
| + | |
| +static const char * const sdio_groups[] = { | |
| + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", | |
| + "sdio_cmd", "sdio_clk", | |
| +}; | |
| + | |
| +static const char * const spi0_groups[] = { | |
| + "spi0_clk", "spi0_mosi", "spi0_miso", "spi0_ss0", | |
| + "spi0_ss1", "spi0_ss2" | |
| +}; | |
| + | |
| +static const char * const spi1_groups[] = { | |
| + "spi1_clk_x", "spi1_mosi_x", "spi1_miso_x", "spi1_ss0_x", | |
| + "spi1_clk_a", "spi1_mosi_a", "spi1_miso_a", "spi1_ss0_a", | |
| + "spi1_ss1" | |
| +}; | |
| + | |
| +static const char * const uart_a_groups[] = { | |
| + "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a", | |
| +}; | |
| + | |
| +static const char * const uart_b_groups[] = { | |
| + "uart_tx_b_z", "uart_rx_b_z", "uart_cts_b_z", "uart_rts_b_z", | |
| + "uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x", | |
| +}; | |
| + | |
| +static const char * const uart_ao_b_z_groups[] = { | |
| + "uart_ao_tx_b_z", "uart_ao_rx_b_z", | |
| + "uart_ao_cts_b_z", "uart_ao_rts_b_z", | |
| +}; | |
| + | |
| +static const char * const i2c0_groups[] = { | |
| + "i2c0_sck", "i2c0_sda", | |
| +}; | |
| + | |
| +static const char * const i2c1_groups[] = { | |
| + "i2c1_sck_z", "i2c1_sda_z", | |
| + "i2c1_sck_x", "i2c1_sda_x", | |
| +}; | |
| + | |
| +static const char * const i2c2_groups[] = { | |
| + "i2c2_sck_x", "i2c2_sda_x", | |
| + "i2c2_sda_a", "i2c2_sck_a", | |
| +}; | |
| + | |
| +static const char * const i2c3_groups[] = { | |
| + "i2c3_sda_a6", "i2c3_sck_a7", | |
| + "i2c3_sda_a12", "i2c3_sck_a13", | |
| + "i2c3_sda_a19", "i2c3_sck_a20", | |
| +}; | |
| + | |
| +static const char * const eth_groups[] = { | |
| + "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", | |
| + "eth_txd2_rgmii", "eth_txd3_rgmii", | |
| + "eth_txd0_x", "eth_txd1_x", "eth_txen_x", "eth_rgmii_rx_clk_x", | |
| + "eth_rxd0_x", "eth_rxd1_x", "eth_rx_dv_x", "eth_mdio_x", | |
| + "eth_mdc_x", | |
| + "eth_txd0_y", "eth_txd1_y", "eth_txen_y", "eth_rgmii_rx_clk_y", | |
| + "eth_rxd0_y", "eth_rxd1_y", "eth_rx_dv_y", "eth_mdio_y", | |
| + "eth_mdc_y", | |
| +}; | |
| + | |
| +static const char * const pwm_a_groups[] = { | |
| + "pwm_a_z", "pwm_a_x18", "pwm_a_x20", "pwm_a_a", | |
| +}; | |
| + | |
| +static const char * const pwm_b_groups[] = { | |
| + "pwm_b_z", "pwm_b_x", "pwm_b_a", | |
| +}; | |
| + | |
| +static const char * const pwm_c_groups[] = { | |
| + "pwm_c_x10", "pwm_c_x17", "pwm_c_a", | |
| +}; | |
| + | |
| +static const char * const pwm_d_groups[] = { | |
| + "pwm_d_x11", "pwm_d_x16", | |
| +}; | |
| + | |
| +static const char * const pwm_vs_groups[] = { | |
| + "pwm_vs", | |
| +}; | |
| + | |
| +static const char * const spdif_out_groups[] = { | |
| + "spdif_out_z", "spdif_out_a1", "spdif_out_a11", | |
| + "spdif_out_a19", "spdif_out_a20", | |
| +}; | |
| + | |
| +static const char * const spdif_in_groups[] = { | |
| + "spdif_in_z", "spdif_in_a1", "spdif_in_a7", | |
| + "spdif_in_a19", "spdif_in_a20", | |
| +}; | |
| + | |
| +static const char * const jtag_ee_groups[] = { | |
| + "jtag_tdo_x", "jtag_tdi_x", "jtag_clk_x", | |
| + "jtag_tms_x", | |
| +}; | |
| + | |
| +static const char * const pdm_groups[] = { | |
| + "pdm_din0", "pdm_din1", "pdm_din2", "pdm_din3", | |
| + "pdm_dclk_a14", "pdm_dclk_a19", | |
| +}; | |
| + | |
| +static const char * const gpio_aobus_groups[] = { | |
| + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", | |
| + "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", | |
| + "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13", | |
| + "GPIO_TEST_N", | |
| +}; | |
| + | |
| +static const char * const uart_ao_a_groups[] = { | |
| + "uart_ao_tx_a", "uart_ao_rx_a", "uart_ao_cts_a", "uart_ao_rts_a", | |
| +}; | |
| + | |
| +static const char * const uart_ao_b_groups[] = { | |
| + "uart_ao_tx_b", "uart_ao_rx_b", "uart_ao_cts_b", "uart_ao_rts_b", | |
| +}; | |
| + | |
| +static const char * const i2c_ao_groups[] = { | |
| + "i2c_ao_sck_4", "i2c_ao_sda_5", | |
| + "i2c_ao_sck_8", "i2c_ao_sda_9", | |
| + "i2c_ao_sck_10", "i2c_ao_sda_11", | |
| +}; | |
| + | |
| +static const char * const i2c_ao_slave_groups[] = { | |
| + "i2c_ao_slave_sck", "i2c_ao_slave_sda", | |
| +}; | |
| + | |
| +static const char * const remote_input_ao_groups[] = { | |
| + "remote_input_ao", | |
| +}; | |
| + | |
| +static const char * const remote_out_ao_groups[] = { | |
| + "remote_out_ao", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_a_groups[] = { | |
| + "pwm_ao_a", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_b_groups[] = { | |
| + "pwm_ao_b_ao2", "pwm_ao_b_ao12", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_c_groups[] = { | |
| + "pwm_ao_c_ao8", "pwm_ao_c_ao13", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_d_groups[] = { | |
| + "pwm_ao_d", | |
| +}; | |
| + | |
| +static const char * const jtag_ao_groups[] = { | |
| + "jtag_ao_tdi", "jtag_ao_tdo", "jtag_ao_clk", "jtag_ao_tms", | |
| +}; | |
| + | |
| +static const char * const mclk_c_groups[] = { | |
| + "mclk_c", | |
| +}; | |
| + | |
| +static const char * const mclk_b_groups[] = { | |
| + "mclk_b", | |
| +}; | |
| + | |
| +static const char * const tdma_groups[] = { | |
| + "tdma_sclk", "tdma_sclk_slv", "tdma_fs", "tdma_fs_slv", | |
| + "tdma_din0", "tdma_dout0_x14", "tdma_dout0_x15", "tdma_dout1", | |
| + "tdma_din1", | |
| +}; | |
| + | |
| +static const char * const tdmc_groups[] = { | |
| + "tdmc_sclk", "tdmc_sclk_slv", "tdmc_fs", "tdmc_fs_slv", | |
| + "tdmc_din0", "tdmc_dout0", "tdmc_din1", "tdmc_dout1", | |
| + "tdmc_din2", "tdmc_dout2", "tdmc_din3", "tdmc_dout3", | |
| +}; | |
| + | |
| +static const char * const tdmb_groups[] = { | |
| + "tdmb_sclk", "tdmb_sclk_slv", "tdmb_fs", "tdmb_fs_slv", | |
| + "tdmb_din0", "tdmb_dout0", "tdmb_din1", "tdmb_dout1", | |
| + "tdmb_din2", "tdmb_dout2", "tdmb_din3", "tdmb_dout3", | |
| +}; | |
| + | |
| +static const char * const gen_clk_ee_groups[] = { | |
| + "gen_clk_ee", | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson_axg_periphs_functions[] = { | |
| + FUNCTION(gpio_periphs), | |
| + FUNCTION(emmc), | |
| + FUNCTION(nor), | |
| + FUNCTION(spi0), | |
| + FUNCTION(spi1), | |
| + FUNCTION(sdio), | |
| + FUNCTION(nand), | |
| + FUNCTION(uart_a), | |
| + FUNCTION(uart_b), | |
| + FUNCTION(uart_ao_b_z), | |
| + FUNCTION(i2c0), | |
| + FUNCTION(i2c1), | |
| + FUNCTION(i2c2), | |
| + FUNCTION(i2c3), | |
| + FUNCTION(eth), | |
| + FUNCTION(pwm_a), | |
| + FUNCTION(pwm_b), | |
| + FUNCTION(pwm_c), | |
| + FUNCTION(pwm_d), | |
| + FUNCTION(pwm_vs), | |
| + FUNCTION(spdif_out), | |
| + FUNCTION(spdif_in), | |
| + FUNCTION(jtag_ee), | |
| + FUNCTION(pdm), | |
| + FUNCTION(mclk_b), | |
| + FUNCTION(mclk_c), | |
| + FUNCTION(tdma), | |
| + FUNCTION(tdmb), | |
| + FUNCTION(tdmc), | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson_axg_aobus_functions[] = { | |
| + FUNCTION(gpio_aobus), | |
| + FUNCTION(uart_ao_a), | |
| + FUNCTION(uart_ao_b), | |
| + FUNCTION(i2c_ao), | |
| + FUNCTION(i2c_ao_slave), | |
| + FUNCTION(remote_input_ao), | |
| + FUNCTION(remote_out_ao), | |
| + FUNCTION(pwm_ao_a), | |
| + FUNCTION(pwm_ao_b), | |
| + FUNCTION(pwm_ao_c), | |
| + FUNCTION(pwm_ao_d), | |
| + FUNCTION(jtag_ao), | |
| + FUNCTION(gen_clk_ee), | |
| +}; | |
| + | |
| +static const struct meson_bank meson_axg_periphs_banks[] = { | |
| + /* name first last irq pullen pull dir out in */ | |
| + BANK("Z", GPIOZ_0, GPIOZ_10, 14, 24, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), | |
| + BANK("BOOT", BOOT_0, BOOT_14, 25, 39, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), | |
| + BANK("A", GPIOA_0, GPIOA_20, 40, 60, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), | |
| + BANK("X", GPIOX_0, GPIOX_22, 61, 83, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), | |
| + BANK("Y", GPIOY_0, GPIOY_15, 84, 99, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), | |
| +}; | |
| + | |
| +static const struct meson_bank meson_axg_aobus_banks[] = { | |
| + /* name first last irq pullen pull dir out in */ | |
| + BANK("AO", GPIOAO_0, GPIOAO_13, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0), | |
| +}; | |
| + | |
| +static const struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = { | |
| + /* name first lask reg offset */ | |
| + BANK_PMX("Z", GPIOZ_0, GPIOZ_10, 0x2, 0), | |
| + BANK_PMX("BOOT", BOOT_0, BOOT_14, 0x0, 0), | |
| + BANK_PMX("A", GPIOA_0, GPIOA_20, 0xb, 0), | |
| + BANK_PMX("X", GPIOX_0, GPIOX_22, 0x4, 0), | |
| + BANK_PMX("Y", GPIOY_0, GPIOY_15, 0x8, 0), | |
| +}; | |
| + | |
| +static const struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = { | |
| + .pmx_banks = meson_axg_periphs_pmx_banks, | |
| + .num_pmx_banks = ARRAY_SIZE(meson_axg_periphs_pmx_banks), | |
| +}; | |
| + | |
| +static const struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = { | |
| + BANK_PMX("AO", GPIOAO_0, GPIOAO_13, 0x0, 0), | |
| +}; | |
| + | |
| +static const struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = { | |
| + .pmx_banks = meson_axg_aobus_pmx_banks, | |
| + .num_pmx_banks = ARRAY_SIZE(meson_axg_aobus_pmx_banks), | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = { | |
| + .name = "periphs-banks", | |
| + .pins = meson_axg_periphs_pins, | |
| + .groups = meson_axg_periphs_groups, | |
| + .funcs = meson_axg_periphs_functions, | |
| + .banks = meson_axg_periphs_banks, | |
| + .num_pins = ARRAY_SIZE(meson_axg_periphs_pins), | |
| + .num_groups = ARRAY_SIZE(meson_axg_periphs_groups), | |
| + .num_funcs = ARRAY_SIZE(meson_axg_periphs_functions), | |
| + .num_banks = ARRAY_SIZE(meson_axg_periphs_banks), | |
| + .pmx_ops = &meson_axg_pmx_ops, | |
| + .pmx_data = &meson_axg_periphs_pmx_banks_data, | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = { | |
| + .name = "aobus-banks", | |
| + .pins = meson_axg_aobus_pins, | |
| + .groups = meson_axg_aobus_groups, | |
| + .funcs = meson_axg_aobus_functions, | |
| + .banks = meson_axg_aobus_banks, | |
| + .num_pins = ARRAY_SIZE(meson_axg_aobus_pins), | |
| + .num_groups = ARRAY_SIZE(meson_axg_aobus_groups), | |
| + .num_funcs = ARRAY_SIZE(meson_axg_aobus_functions), | |
| + .num_banks = ARRAY_SIZE(meson_axg_aobus_banks), | |
| + .pmx_ops = &meson_axg_pmx_ops, | |
| + .pmx_data = &meson_axg_aobus_pmx_banks_data, | |
| + .parse_dt = meson8_aobus_parse_dt_extra, | |
| +}; | |
| + | |
| +static const struct of_device_id meson_axg_pinctrl_dt_match[] = { | |
| + { | |
| + .compatible = "amlogic,meson-axg-periphs-pinctrl", | |
| + .data = &meson_axg_periphs_pinctrl_data, | |
| + }, | |
| + { | |
| + .compatible = "amlogic,meson-axg-aobus-pinctrl", | |
| + .data = &meson_axg_aobus_pinctrl_data, | |
| + }, | |
| + { }, | |
| +}; | |
| +MODULE_DEVICE_TABLE(of, meson_axg_pinctrl_dt_match); | |
| + | |
| +static struct platform_driver meson_axg_pinctrl_driver = { | |
| + .probe = meson_pinctrl_probe, | |
| + .driver = { | |
| + .name = "meson-axg-pinctrl", | |
| + .of_match_table = meson_axg_pinctrl_dt_match, | |
| + }, | |
| +}; | |
| + | |
| +module_platform_driver(meson_axg_pinctrl_driver); | |
| +MODULE_DESCRIPTION("Amlogic Meson AXG pinctrl driver"); | |
| +MODULE_LICENSE("Dual BSD/GPL"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c | |
| new file mode 100644 | |
| index 0000000000..117e72b4ff | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c | |
| @@ -0,0 +1,1454 @@ | |
| +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | |
| +/* | |
| + * Pin controller and GPIO driver for Amlogic Meson G12A SoC. | |
| + * | |
| + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. | |
| + * Author: Xingyu Chen <xingyu.chen@amlogic.com> | |
| + * Author: Yixun Lan <yixun.lan@amlogic.com> | |
| + */ | |
| + | |
| +#include <dt-bindings/gpio/meson-g12a-gpio.h> | |
| +#include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h> | |
| +#include "pinctrl-meson.h" | |
| +#include "pinctrl-meson-axg-pmx.h" | |
| + | |
| +static const struct pinctrl_pin_desc meson_g12a_periphs_pins[] = { | |
| + MESON_PIN(GPIOZ_0), | |
| + MESON_PIN(GPIOZ_1), | |
| + MESON_PIN(GPIOZ_2), | |
| + MESON_PIN(GPIOZ_3), | |
| + MESON_PIN(GPIOZ_4), | |
| + MESON_PIN(GPIOZ_5), | |
| + MESON_PIN(GPIOZ_6), | |
| + MESON_PIN(GPIOZ_7), | |
| + MESON_PIN(GPIOZ_8), | |
| + MESON_PIN(GPIOZ_9), | |
| + MESON_PIN(GPIOZ_10), | |
| + MESON_PIN(GPIOZ_11), | |
| + MESON_PIN(GPIOZ_12), | |
| + MESON_PIN(GPIOZ_13), | |
| + MESON_PIN(GPIOZ_14), | |
| + MESON_PIN(GPIOZ_15), | |
| + MESON_PIN(GPIOH_0), | |
| + MESON_PIN(GPIOH_1), | |
| + MESON_PIN(GPIOH_2), | |
| + MESON_PIN(GPIOH_3), | |
| + MESON_PIN(GPIOH_4), | |
| + MESON_PIN(GPIOH_5), | |
| + MESON_PIN(GPIOH_6), | |
| + MESON_PIN(GPIOH_7), | |
| + MESON_PIN(GPIOH_8), | |
| + MESON_PIN(BOOT_0), | |
| + MESON_PIN(BOOT_1), | |
| + MESON_PIN(BOOT_2), | |
| + MESON_PIN(BOOT_3), | |
| + MESON_PIN(BOOT_4), | |
| + MESON_PIN(BOOT_5), | |
| + MESON_PIN(BOOT_6), | |
| + MESON_PIN(BOOT_7), | |
| + MESON_PIN(BOOT_8), | |
| + MESON_PIN(BOOT_9), | |
| + MESON_PIN(BOOT_10), | |
| + MESON_PIN(BOOT_11), | |
| + MESON_PIN(BOOT_12), | |
| + MESON_PIN(BOOT_13), | |
| + MESON_PIN(BOOT_14), | |
| + MESON_PIN(BOOT_15), | |
| + MESON_PIN(GPIOC_0), | |
| + MESON_PIN(GPIOC_1), | |
| + MESON_PIN(GPIOC_2), | |
| + MESON_PIN(GPIOC_3), | |
| + MESON_PIN(GPIOC_4), | |
| + MESON_PIN(GPIOC_5), | |
| + MESON_PIN(GPIOC_6), | |
| + MESON_PIN(GPIOC_7), | |
| + MESON_PIN(GPIOA_0), | |
| + MESON_PIN(GPIOA_1), | |
| + MESON_PIN(GPIOA_2), | |
| + MESON_PIN(GPIOA_3), | |
| + MESON_PIN(GPIOA_4), | |
| + MESON_PIN(GPIOA_5), | |
| + MESON_PIN(GPIOA_6), | |
| + MESON_PIN(GPIOA_7), | |
| + MESON_PIN(GPIOA_8), | |
| + MESON_PIN(GPIOA_9), | |
| + MESON_PIN(GPIOA_10), | |
| + MESON_PIN(GPIOA_11), | |
| + MESON_PIN(GPIOA_12), | |
| + MESON_PIN(GPIOA_13), | |
| + MESON_PIN(GPIOA_14), | |
| + MESON_PIN(GPIOA_15), | |
| + MESON_PIN(GPIOX_0), | |
| + MESON_PIN(GPIOX_1), | |
| + MESON_PIN(GPIOX_2), | |
| + MESON_PIN(GPIOX_3), | |
| + MESON_PIN(GPIOX_4), | |
| + MESON_PIN(GPIOX_5), | |
| + MESON_PIN(GPIOX_6), | |
| + MESON_PIN(GPIOX_7), | |
| + MESON_PIN(GPIOX_8), | |
| + MESON_PIN(GPIOX_9), | |
| + MESON_PIN(GPIOX_10), | |
| + MESON_PIN(GPIOX_11), | |
| + MESON_PIN(GPIOX_12), | |
| + MESON_PIN(GPIOX_13), | |
| + MESON_PIN(GPIOX_14), | |
| + MESON_PIN(GPIOX_15), | |
| + MESON_PIN(GPIOX_16), | |
| + MESON_PIN(GPIOX_17), | |
| + MESON_PIN(GPIOX_18), | |
| + MESON_PIN(GPIOX_19), | |
| +}; | |
| + | |
| +static const struct pinctrl_pin_desc meson_g12a_aobus_pins[] = { | |
| + MESON_PIN(GPIOAO_0), | |
| + MESON_PIN(GPIOAO_1), | |
| + MESON_PIN(GPIOAO_2), | |
| + MESON_PIN(GPIOAO_3), | |
| + MESON_PIN(GPIOAO_4), | |
| + MESON_PIN(GPIOAO_5), | |
| + MESON_PIN(GPIOAO_6), | |
| + MESON_PIN(GPIOAO_7), | |
| + MESON_PIN(GPIOAO_8), | |
| + MESON_PIN(GPIOAO_9), | |
| + MESON_PIN(GPIOAO_10), | |
| + MESON_PIN(GPIOAO_11), | |
| + MESON_PIN(GPIOE_0), | |
| + MESON_PIN(GPIOE_1), | |
| + MESON_PIN(GPIOE_2), | |
| +}; | |
| + | |
| +/* emmc */ | |
| +static const unsigned int emmc_nand_d0_pins[] = { BOOT_0 }; | |
| +static const unsigned int emmc_nand_d1_pins[] = { BOOT_1 }; | |
| +static const unsigned int emmc_nand_d2_pins[] = { BOOT_2 }; | |
| +static const unsigned int emmc_nand_d3_pins[] = { BOOT_3 }; | |
| +static const unsigned int emmc_nand_d4_pins[] = { BOOT_4 }; | |
| +static const unsigned int emmc_nand_d5_pins[] = { BOOT_5 }; | |
| +static const unsigned int emmc_nand_d6_pins[] = { BOOT_6 }; | |
| +static const unsigned int emmc_nand_d7_pins[] = { BOOT_7 }; | |
| +static const unsigned int emmc_clk_pins[] = { BOOT_8 }; | |
| +static const unsigned int emmc_cmd_pins[] = { BOOT_10 }; | |
| +static const unsigned int emmc_nand_ds_pins[] = { BOOT_13 }; | |
| + | |
| +/* nand */ | |
| +static const unsigned int nand_wen_clk_pins[] = { BOOT_8 }; | |
| +static const unsigned int nand_ale_pins[] = { BOOT_9 }; | |
| +static const unsigned int nand_cle_pins[] = { BOOT_10 }; | |
| +static const unsigned int nand_ce0_pins[] = { BOOT_11 }; | |
| +static const unsigned int nand_ren_wr_pins[] = { BOOT_12 }; | |
| +static const unsigned int nand_rb0_pins[] = { BOOT_14 }; | |
| +static const unsigned int nand_ce1_pins[] = { BOOT_15 }; | |
| + | |
| +/* nor */ | |
| +static const unsigned int nor_hold_pins[] = { BOOT_3 }; | |
| +static const unsigned int nor_d_pins[] = { BOOT_4 }; | |
| +static const unsigned int nor_q_pins[] = { BOOT_5 }; | |
| +static const unsigned int nor_c_pins[] = { BOOT_6 }; | |
| +static const unsigned int nor_wp_pins[] = { BOOT_7 }; | |
| +static const unsigned int nor_cs_pins[] = { BOOT_14 }; | |
| + | |
| +/* sdio */ | |
| +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; | |
| +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; | |
| +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; | |
| +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; | |
| +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; | |
| +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; | |
| + | |
| +/* sdcard */ | |
| +static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 }; | |
| +static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 }; | |
| +static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 }; | |
| +static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 }; | |
| +static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 }; | |
| + | |
| +static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_7 }; | |
| + | |
| +/* spi0 */ | |
| +static const unsigned int spi0_mosi_c_pins[] = { GPIOC_0 }; | |
| +static const unsigned int spi0_miso_c_pins[] = { GPIOC_1 }; | |
| +static const unsigned int spi0_ss0_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int spi0_clk_c_pins[] = { GPIOC_3 }; | |
| + | |
| +static const unsigned int spi0_mosi_x_pins[] = { GPIOX_8 }; | |
| +static const unsigned int spi0_miso_x_pins[] = { GPIOX_9 }; | |
| +static const unsigned int spi0_ss0_x_pins[] = { GPIOX_10 }; | |
| +static const unsigned int spi0_clk_x_pins[] = { GPIOX_11 }; | |
| + | |
| +/* spi1 */ | |
| +static const unsigned int spi1_mosi_pins[] = { GPIOH_4 }; | |
| +static const unsigned int spi1_miso_pins[] = { GPIOH_5 }; | |
| +static const unsigned int spi1_ss0_pins[] = { GPIOH_6 }; | |
| +static const unsigned int spi1_clk_pins[] = { GPIOH_7 }; | |
| + | |
| +/* i2c0 */ | |
| +static const unsigned int i2c0_sda_c_pins[] = { GPIOC_5 }; | |
| +static const unsigned int i2c0_sck_c_pins[] = { GPIOC_6 }; | |
| +static const unsigned int i2c0_sda_z0_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int i2c0_sck_z1_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int i2c0_sda_z7_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int i2c0_sck_z8_pins[] = { GPIOZ_8 }; | |
| + | |
| +/* i2c1 */ | |
| +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_10 }; | |
| +static const unsigned int i2c1_sck_x_pins[] = { GPIOX_11 }; | |
| +static const unsigned int i2c1_sda_h2_pins[] = { GPIOH_2 }; | |
| +static const unsigned int i2c1_sck_h3_pins[] = { GPIOH_3 }; | |
| +static const unsigned int i2c1_sda_h6_pins[] = { GPIOH_6 }; | |
| +static const unsigned int i2c1_sck_h7_pins[] = { GPIOH_7 }; | |
| + | |
| +/* i2c2 */ | |
| +static const unsigned int i2c2_sda_x_pins[] = { GPIOX_17 }; | |
| +static const unsigned int i2c2_sck_x_pins[] = { GPIOX_18 }; | |
| +static const unsigned int i2c2_sda_z_pins[] = { GPIOZ_14 }; | |
| +static const unsigned int i2c2_sck_z_pins[] = { GPIOZ_15 }; | |
| + | |
| +/* i2c3 */ | |
| +static const unsigned int i2c3_sda_h_pins[] = { GPIOH_0 }; | |
| +static const unsigned int i2c3_sck_h_pins[] = { GPIOH_1 }; | |
| +static const unsigned int i2c3_sda_a_pins[] = { GPIOA_14 }; | |
| +static const unsigned int i2c3_sck_a_pins[] = { GPIOA_15 }; | |
| + | |
| +/* uart_a */ | |
| +static const unsigned int uart_a_tx_pins[] = { GPIOX_12 }; | |
| +static const unsigned int uart_a_rx_pins[] = { GPIOX_13 }; | |
| +static const unsigned int uart_a_cts_pins[] = { GPIOX_14 }; | |
| +static const unsigned int uart_a_rts_pins[] = { GPIOX_15 }; | |
| + | |
| +/* uart_b */ | |
| +static const unsigned int uart_b_tx_pins[] = { GPIOX_6 }; | |
| +static const unsigned int uart_b_rx_pins[] = { GPIOX_7 }; | |
| + | |
| +/* uart_c */ | |
| +static const unsigned int uart_c_rts_pins[] = { GPIOH_4 }; | |
| +static const unsigned int uart_c_cts_pins[] = { GPIOH_5 }; | |
| +static const unsigned int uart_c_rx_pins[] = { GPIOH_6 }; | |
| +static const unsigned int uart_c_tx_pins[] = { GPIOH_7 }; | |
| + | |
| +/* uart_ao_a_c */ | |
| +static const unsigned int uart_ao_a_rx_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int uart_ao_a_tx_c_pins[] = { GPIOC_3 }; | |
| + | |
| +/* iso7816 */ | |
| +static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 }; | |
| +static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 }; | |
| +static const unsigned int iso7816_clk_x_pins[] = { GPIOX_8 }; | |
| +static const unsigned int iso7816_data_x_pins[] = { GPIOX_9 }; | |
| +static const unsigned int iso7816_clk_h_pins[] = { GPIOH_6 }; | |
| +static const unsigned int iso7816_data_h_pins[] = { GPIOH_7 }; | |
| +static const unsigned int iso7816_clk_z_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int iso7816_data_z_pins[] = { GPIOZ_1 }; | |
| + | |
| +/* eth */ | |
| +static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int eth_rgmii_rx_clk_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 }; | |
| +static const unsigned int eth_txen_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int eth_txd0_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int eth_txd1_pins[] = { GPIOZ_11 }; | |
| +static const unsigned int eth_txd2_rgmii_pins[] = { GPIOZ_12 }; | |
| +static const unsigned int eth_txd3_rgmii_pins[] = { GPIOZ_13 }; | |
| +static const unsigned int eth_link_led_pins[] = { GPIOZ_14 }; | |
| +static const unsigned int eth_act_led_pins[] = { GPIOZ_15 }; | |
| + | |
| +/* pwm_a */ | |
| +static const unsigned int pwm_a_pins[] = { GPIOX_6 }; | |
| + | |
| +/* pwm_b */ | |
| +static const unsigned int pwm_b_x7_pins[] = { GPIOX_7 }; | |
| +static const unsigned int pwm_b_x19_pins[] = { GPIOX_19 }; | |
| +static const unsigned int pwm_b_z0_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int pwm_b_z13_pins[] = { GPIOZ_13 }; | |
| +static const unsigned int pwm_b_h_pins[] = { GPIOH_7 }; | |
| + | |
| +/* pwm_c */ | |
| +static const unsigned int pwm_c_c_pins[] = { GPIOC_4 }; | |
| +static const unsigned int pwm_c_x5_pins[] = { GPIOX_5 }; | |
| +static const unsigned int pwm_c_x8_pins[] = { GPIOX_8 }; | |
| +static const unsigned int pwm_c_z_pins[] = { GPIOZ_1 }; | |
| + | |
| +/* pwm_d */ | |
| +static const unsigned int pwm_d_x3_pins[] = { GPIOX_3 }; | |
| +static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 }; | |
| +static const unsigned int pwm_d_z_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int pwm_d_a_pins[] = { GPIOA_4 }; | |
| + | |
| +/* pwm_e */ | |
| +static const unsigned int pwm_e_pins[] = { GPIOX_16 }; | |
| + | |
| +/* pwm_f */ | |
| +static const unsigned int pwm_f_z_pins[] = { GPIOZ_12 }; | |
| +static const unsigned int pwm_f_a_pins[] = { GPIOA_11 }; | |
| +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; | |
| +static const unsigned int pwm_f_h_pins[] = { GPIOH_5 }; | |
| + | |
| +/* cec_ao */ | |
| +static const unsigned int cec_ao_a_h_pins[] = { GPIOH_3 }; | |
| +static const unsigned int cec_ao_b_h_pins[] = { GPIOH_3 }; | |
| + | |
| +/* jtag_b */ | |
| +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 }; | |
| +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 }; | |
| +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 }; | |
| +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 }; | |
| + | |
| +/* bt565_a */ | |
| +static const unsigned int bt565_a_vs_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int bt565_a_hs_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int bt565_a_clk_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int bt565_a_din0_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int bt565_a_din1_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int bt565_a_din2_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int bt565_a_din3_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int bt565_a_din4_pins[] = { GPIOZ_8 }; | |
| +static const unsigned int bt565_a_din5_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int bt565_a_din6_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int bt565_a_din7_pins[] = { GPIOZ_11 }; | |
| + | |
| +/* tsin_a */ | |
| +static const unsigned int tsin_a_valid_pins[] = { GPIOX_2 }; | |
| +static const unsigned int tsin_a_sop_pins[] = { GPIOX_1 }; | |
| +static const unsigned int tsin_a_din0_pins[] = { GPIOX_0 }; | |
| +static const unsigned int tsin_a_clk_pins[] = { GPIOX_3 }; | |
| + | |
| +/* tsin_b */ | |
| +static const unsigned int tsin_b_valid_x_pins[] = { GPIOX_9 }; | |
| +static const unsigned int tsin_b_sop_x_pins[] = { GPIOX_8 }; | |
| +static const unsigned int tsin_b_din0_x_pins[] = { GPIOX_10 }; | |
| +static const unsigned int tsin_b_clk_x_pins[] = { GPIOX_11 }; | |
| + | |
| +static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int tsin_b_sop_z_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int tsin_b_din0_z_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int tsin_b_clk_z_pins[] = { GPIOZ_5 }; | |
| + | |
| +static const unsigned int tsin_b_fail_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int tsin_b_din1_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int tsin_b_din2_pins[] = { GPIOZ_8 }; | |
| +static const unsigned int tsin_b_din3_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int tsin_b_din4_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int tsin_b_din5_pins[] = { GPIOZ_11 }; | |
| +static const unsigned int tsin_b_din6_pins[] = { GPIOZ_12 }; | |
| +static const unsigned int tsin_b_din7_pins[] = { GPIOZ_13 }; | |
| + | |
| +/* hdmitx */ | |
| +static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 }; | |
| +static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 }; | |
| +static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 }; | |
| + | |
| +/* pdm */ | |
| +static const unsigned int pdm_din0_c_pins[] = { GPIOC_0 }; | |
| +static const unsigned int pdm_din1_c_pins[] = { GPIOC_1 }; | |
| +static const unsigned int pdm_din2_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int pdm_din3_c_pins[] = { GPIOC_3 }; | |
| +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 }; | |
| + | |
| +static const unsigned int pdm_din0_x_pins[] = { GPIOX_0 }; | |
| +static const unsigned int pdm_din1_x_pins[] = { GPIOX_1 }; | |
| +static const unsigned int pdm_din2_x_pins[] = { GPIOX_2 }; | |
| +static const unsigned int pdm_din3_x_pins[] = { GPIOX_3 }; | |
| +static const unsigned int pdm_dclk_x_pins[] = { GPIOX_4 }; | |
| + | |
| +static const unsigned int pdm_din0_z_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int pdm_din1_z_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int pdm_din2_z_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int pdm_din3_z_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_6 }; | |
| + | |
| +static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 }; | |
| +static const unsigned int pdm_din1_a_pins[] = { GPIOA_9 }; | |
| +static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 }; | |
| +static const unsigned int pdm_din3_a_pins[] = { GPIOA_5 }; | |
| +static const unsigned int pdm_dclk_a_pins[] = { GPIOA_7 }; | |
| + | |
| +/* spdif_in */ | |
| +static const unsigned int spdif_in_h_pins[] = { GPIOH_5 }; | |
| +static const unsigned int spdif_in_a10_pins[] = { GPIOA_10 }; | |
| +static const unsigned int spdif_in_a12_pins[] = { GPIOA_12 }; | |
| + | |
| +/* spdif_out */ | |
| +static const unsigned int spdif_out_h_pins[] = { GPIOH_4 }; | |
| +static const unsigned int spdif_out_a11_pins[] = { GPIOA_11 }; | |
| +static const unsigned int spdif_out_a13_pins[] = { GPIOA_13 }; | |
| + | |
| +/* mclk0 */ | |
| +static const unsigned int mclk0_a_pins[] = { GPIOA_0 }; | |
| + | |
| +/* mclk1 */ | |
| +static const unsigned int mclk1_x_pins[] = { GPIOX_5 }; | |
| +static const unsigned int mclk1_z_pins[] = { GPIOZ_8 }; | |
| +static const unsigned int mclk1_a_pins[] = { GPIOA_11 }; | |
| + | |
| +/* tdm */ | |
| +static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_11 }; | |
| +static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_10 }; | |
| +static const unsigned int tdm_a_sclk_pins[] = { GPIOX_11 }; | |
| +static const unsigned int tdm_a_fs_pins[] = { GPIOX_10 }; | |
| +static const unsigned int tdm_a_din0_pins[] = { GPIOX_9 }; | |
| +static const unsigned int tdm_a_din1_pins[] = { GPIOX_8 }; | |
| +static const unsigned int tdm_a_dout0_pins[] = { GPIOX_9 }; | |
| +static const unsigned int tdm_a_dout1_pins[] = { GPIOX_8 }; | |
| + | |
| +static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_1 }; | |
| +static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_2 }; | |
| +static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 }; | |
| +static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 }; | |
| +static const unsigned int tdm_b_din0_pins[] = { GPIOA_3 }; | |
| +static const unsigned int tdm_b_din1_pins[] = { GPIOA_4 }; | |
| +static const unsigned int tdm_b_din2_pins[] = { GPIOA_5 }; | |
| +static const unsigned int tdm_b_din3_a_pins[] = { GPIOA_6 }; | |
| +static const unsigned int tdm_b_din3_h_pins[] = { GPIOH_5 }; | |
| +static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 }; | |
| +static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 }; | |
| +static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 }; | |
| +static const unsigned int tdm_b_dout3_a_pins[] = { GPIOA_6 }; | |
| +static const unsigned int tdm_b_dout3_h_pins[] = { GPIOH_5 }; | |
| + | |
| +static const unsigned int tdm_c_slv_sclk_a_pins[] = { GPIOA_12 }; | |
| +static const unsigned int tdm_c_slv_fs_a_pins[] = { GPIOA_13 }; | |
| +static const unsigned int tdm_c_slv_sclk_z_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int tdm_c_slv_fs_z_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int tdm_c_sclk_a_pins[] = { GPIOA_12 }; | |
| +static const unsigned int tdm_c_fs_a_pins[] = { GPIOA_13 }; | |
| +static const unsigned int tdm_c_sclk_z_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int tdm_c_fs_z_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int tdm_c_din0_a_pins[] = { GPIOA_10 }; | |
| +static const unsigned int tdm_c_din1_a_pins[] = { GPIOA_9 }; | |
| +static const unsigned int tdm_c_din2_a_pins[] = { GPIOA_8 }; | |
| +static const unsigned int tdm_c_din3_a_pins[] = { GPIOA_7 }; | |
| +static const unsigned int tdm_c_din0_z_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int tdm_c_din1_z_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int tdm_c_din2_z_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int tdm_c_din3_z_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int tdm_c_dout0_a_pins[] = { GPIOA_10 }; | |
| +static const unsigned int tdm_c_dout1_a_pins[] = { GPIOA_9 }; | |
| +static const unsigned int tdm_c_dout2_a_pins[] = { GPIOA_8 }; | |
| +static const unsigned int tdm_c_dout3_a_pins[] = { GPIOA_7 }; | |
| +static const unsigned int tdm_c_dout0_z_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int tdm_c_dout1_z_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int tdm_c_dout2_z_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int tdm_c_dout3_z_pins[] = { GPIOZ_5 }; | |
| + | |
| +static const unsigned int pcie_clkreqn_pins[] = { GPIOC_7 }; | |
| + | |
| +static const struct meson_pmx_group meson_g12a_periphs_groups[] = { | |
| + GPIO_GROUP(GPIOZ_0), | |
| + GPIO_GROUP(GPIOZ_1), | |
| + GPIO_GROUP(GPIOZ_2), | |
| + GPIO_GROUP(GPIOZ_3), | |
| + GPIO_GROUP(GPIOZ_4), | |
| + GPIO_GROUP(GPIOZ_5), | |
| + GPIO_GROUP(GPIOZ_6), | |
| + GPIO_GROUP(GPIOZ_7), | |
| + GPIO_GROUP(GPIOZ_8), | |
| + GPIO_GROUP(GPIOZ_9), | |
| + GPIO_GROUP(GPIOZ_10), | |
| + GPIO_GROUP(GPIOZ_11), | |
| + GPIO_GROUP(GPIOZ_12), | |
| + GPIO_GROUP(GPIOZ_13), | |
| + GPIO_GROUP(GPIOZ_14), | |
| + GPIO_GROUP(GPIOZ_15), | |
| + GPIO_GROUP(GPIOH_0), | |
| + GPIO_GROUP(GPIOH_1), | |
| + GPIO_GROUP(GPIOH_2), | |
| + GPIO_GROUP(GPIOH_3), | |
| + GPIO_GROUP(GPIOH_4), | |
| + GPIO_GROUP(GPIOH_5), | |
| + GPIO_GROUP(GPIOH_6), | |
| + GPIO_GROUP(GPIOH_7), | |
| + GPIO_GROUP(GPIOH_8), | |
| + GPIO_GROUP(BOOT_0), | |
| + GPIO_GROUP(BOOT_1), | |
| + GPIO_GROUP(BOOT_2), | |
| + GPIO_GROUP(BOOT_3), | |
| + GPIO_GROUP(BOOT_4), | |
| + GPIO_GROUP(BOOT_5), | |
| + GPIO_GROUP(BOOT_6), | |
| + GPIO_GROUP(BOOT_7), | |
| + GPIO_GROUP(BOOT_8), | |
| + GPIO_GROUP(BOOT_9), | |
| + GPIO_GROUP(BOOT_10), | |
| + GPIO_GROUP(BOOT_11), | |
| + GPIO_GROUP(BOOT_12), | |
| + GPIO_GROUP(BOOT_13), | |
| + GPIO_GROUP(BOOT_14), | |
| + GPIO_GROUP(BOOT_15), | |
| + GPIO_GROUP(GPIOC_0), | |
| + GPIO_GROUP(GPIOC_1), | |
| + GPIO_GROUP(GPIOC_2), | |
| + GPIO_GROUP(GPIOC_3), | |
| + GPIO_GROUP(GPIOC_4), | |
| + GPIO_GROUP(GPIOC_5), | |
| + GPIO_GROUP(GPIOC_6), | |
| + GPIO_GROUP(GPIOC_7), | |
| + GPIO_GROUP(GPIOA_0), | |
| + GPIO_GROUP(GPIOA_1), | |
| + GPIO_GROUP(GPIOA_2), | |
| + GPIO_GROUP(GPIOA_3), | |
| + GPIO_GROUP(GPIOA_4), | |
| + GPIO_GROUP(GPIOA_5), | |
| + GPIO_GROUP(GPIOA_6), | |
| + GPIO_GROUP(GPIOA_7), | |
| + GPIO_GROUP(GPIOA_8), | |
| + GPIO_GROUP(GPIOA_9), | |
| + GPIO_GROUP(GPIOA_10), | |
| + GPIO_GROUP(GPIOA_11), | |
| + GPIO_GROUP(GPIOA_12), | |
| + GPIO_GROUP(GPIOA_13), | |
| + GPIO_GROUP(GPIOA_14), | |
| + GPIO_GROUP(GPIOA_15), | |
| + GPIO_GROUP(GPIOX_0), | |
| + GPIO_GROUP(GPIOX_1), | |
| + GPIO_GROUP(GPIOX_2), | |
| + GPIO_GROUP(GPIOX_3), | |
| + GPIO_GROUP(GPIOX_4), | |
| + GPIO_GROUP(GPIOX_5), | |
| + GPIO_GROUP(GPIOX_6), | |
| + GPIO_GROUP(GPIOX_7), | |
| + GPIO_GROUP(GPIOX_8), | |
| + GPIO_GROUP(GPIOX_9), | |
| + GPIO_GROUP(GPIOX_10), | |
| + GPIO_GROUP(GPIOX_11), | |
| + GPIO_GROUP(GPIOX_12), | |
| + GPIO_GROUP(GPIOX_13), | |
| + GPIO_GROUP(GPIOX_14), | |
| + GPIO_GROUP(GPIOX_15), | |
| + GPIO_GROUP(GPIOX_16), | |
| + GPIO_GROUP(GPIOX_17), | |
| + GPIO_GROUP(GPIOX_18), | |
| + GPIO_GROUP(GPIOX_19), | |
| + | |
| + /* bank BOOT */ | |
| + GROUP(emmc_nand_d0, 1), | |
| + GROUP(emmc_nand_d1, 1), | |
| + GROUP(emmc_nand_d2, 1), | |
| + GROUP(emmc_nand_d3, 1), | |
| + GROUP(emmc_nand_d4, 1), | |
| + GROUP(emmc_nand_d5, 1), | |
| + GROUP(emmc_nand_d6, 1), | |
| + GROUP(emmc_nand_d7, 1), | |
| + GROUP(emmc_clk, 1), | |
| + GROUP(emmc_cmd, 1), | |
| + GROUP(emmc_nand_ds, 1), | |
| + GROUP(nand_ce0, 2), | |
| + GROUP(nand_ale, 2), | |
| + GROUP(nand_cle, 2), | |
| + GROUP(nand_wen_clk, 2), | |
| + GROUP(nand_ren_wr, 2), | |
| + GROUP(nand_rb0, 2), | |
| + GROUP(nand_ce1, 2), | |
| + GROUP(nor_hold, 3), | |
| + GROUP(nor_d, 3), | |
| + GROUP(nor_q, 3), | |
| + GROUP(nor_c, 3), | |
| + GROUP(nor_wp, 3), | |
| + GROUP(nor_cs, 3), | |
| + | |
| + /* bank GPIOZ */ | |
| + GROUP(sdcard_d0_z, 5), | |
| + GROUP(sdcard_d1_z, 5), | |
| + GROUP(sdcard_d2_z, 5), | |
| + GROUP(sdcard_d3_z, 5), | |
| + GROUP(sdcard_clk_z, 5), | |
| + GROUP(sdcard_cmd_z, 5), | |
| + GROUP(i2c0_sda_z0, 4), | |
| + GROUP(i2c0_sck_z1, 4), | |
| + GROUP(i2c0_sda_z7, 7), | |
| + GROUP(i2c0_sck_z8, 7), | |
| + GROUP(i2c2_sda_z, 3), | |
| + GROUP(i2c2_sck_z, 3), | |
| + GROUP(iso7816_clk_z, 3), | |
| + GROUP(iso7816_data_z, 3), | |
| + GROUP(eth_mdio, 1), | |
| + GROUP(eth_mdc, 1), | |
| + GROUP(eth_rgmii_rx_clk, 1), | |
| + GROUP(eth_rx_dv, 1), | |
| + GROUP(eth_rxd0, 1), | |
| + GROUP(eth_rxd1, 1), | |
| + GROUP(eth_rxd2_rgmii, 1), | |
| + GROUP(eth_rxd3_rgmii, 1), | |
| + GROUP(eth_rgmii_tx_clk, 1), | |
| + GROUP(eth_txen, 1), | |
| + GROUP(eth_txd0, 1), | |
| + GROUP(eth_txd1, 1), | |
| + GROUP(eth_txd2_rgmii, 1), | |
| + GROUP(eth_txd3_rgmii, 1), | |
| + GROUP(eth_link_led, 1), | |
| + GROUP(eth_act_led, 1), | |
| + GROUP(bt565_a_vs, 2), | |
| + GROUP(bt565_a_hs, 2), | |
| + GROUP(bt565_a_clk, 2), | |
| + GROUP(bt565_a_din0, 2), | |
| + GROUP(bt565_a_din1, 2), | |
| + GROUP(bt565_a_din2, 2), | |
| + GROUP(bt565_a_din3, 2), | |
| + GROUP(bt565_a_din4, 2), | |
| + GROUP(bt565_a_din5, 2), | |
| + GROUP(bt565_a_din6, 2), | |
| + GROUP(bt565_a_din7, 2), | |
| + GROUP(tsin_b_valid_z, 3), | |
| + GROUP(tsin_b_sop_z, 3), | |
| + GROUP(tsin_b_din0_z, 3), | |
| + GROUP(tsin_b_clk_z, 3), | |
| + GROUP(tsin_b_fail, 3), | |
| + GROUP(tsin_b_din1, 3), | |
| + GROUP(tsin_b_din2, 3), | |
| + GROUP(tsin_b_din3, 3), | |
| + GROUP(tsin_b_din4, 3), | |
| + GROUP(tsin_b_din5, 3), | |
| + GROUP(tsin_b_din6, 3), | |
| + GROUP(tsin_b_din7, 3), | |
| + GROUP(pdm_din0_z, 7), | |
| + GROUP(pdm_din1_z, 7), | |
| + GROUP(pdm_din2_z, 7), | |
| + GROUP(pdm_din3_z, 7), | |
| + GROUP(pdm_dclk_z, 7), | |
| + GROUP(tdm_c_slv_sclk_z, 6), | |
| + GROUP(tdm_c_slv_fs_z, 6), | |
| + GROUP(tdm_c_din0_z, 6), | |
| + GROUP(tdm_c_din1_z, 6), | |
| + GROUP(tdm_c_din2_z, 6), | |
| + GROUP(tdm_c_din3_z, 6), | |
| + GROUP(tdm_c_sclk_z, 4), | |
| + GROUP(tdm_c_fs_z, 4), | |
| + GROUP(tdm_c_dout0_z, 4), | |
| + GROUP(tdm_c_dout1_z, 4), | |
| + GROUP(tdm_c_dout2_z, 4), | |
| + GROUP(tdm_c_dout3_z, 4), | |
| + GROUP(mclk1_z, 4), | |
| + GROUP(pwm_f_z, 5), | |
| + | |
| + /* bank GPIOX */ | |
| + GROUP(sdio_d0, 1), | |
| + GROUP(sdio_d1, 1), | |
| + GROUP(sdio_d2, 1), | |
| + GROUP(sdio_d3, 1), | |
| + GROUP(sdio_clk, 1), | |
| + GROUP(sdio_cmd, 1), | |
| + GROUP(spi0_mosi_x, 4), | |
| + GROUP(spi0_miso_x, 4), | |
| + GROUP(spi0_ss0_x, 4), | |
| + GROUP(spi0_clk_x, 4), | |
| + GROUP(i2c1_sda_x, 5), | |
| + GROUP(i2c1_sck_x, 5), | |
| + GROUP(i2c2_sda_x, 1), | |
| + GROUP(i2c2_sck_x, 1), | |
| + GROUP(uart_a_tx, 1), | |
| + GROUP(uart_a_rx, 1), | |
| + GROUP(uart_a_cts, 1), | |
| + GROUP(uart_a_rts, 1), | |
| + GROUP(uart_b_tx, 2), | |
| + GROUP(uart_b_rx, 2), | |
| + GROUP(iso7816_clk_x, 6), | |
| + GROUP(iso7816_data_x, 6), | |
| + GROUP(pwm_a, 1), | |
| + GROUP(pwm_b_x7, 4), | |
| + GROUP(pwm_b_x19, 1), | |
| + GROUP(pwm_b_z0, 5), | |
| + GROUP(pwm_b_z13, 5), | |
| + GROUP(pwm_b_h, 5), | |
| + GROUP(pwm_c_x5, 4), | |
| + GROUP(pwm_c_x8, 5), | |
| + GROUP(pwm_c_c, 5), | |
| + GROUP(pwm_c_z, 5), | |
| + GROUP(pwm_d_z, 4), | |
| + GROUP(pwm_d_a, 3), | |
| + GROUP(pwm_d_x3, 4), | |
| + GROUP(pwm_d_x6, 4), | |
| + GROUP(pwm_e, 1), | |
| + GROUP(pwm_f_a, 3), | |
| + GROUP(pwm_f_h, 4), | |
| + GROUP(pwm_f_x, 1), | |
| + GROUP(pwm_f_z, 5), | |
| + GROUP(tsin_a_valid, 3), | |
| + GROUP(tsin_a_sop, 3), | |
| + GROUP(tsin_a_din0, 3), | |
| + GROUP(tsin_a_clk, 3), | |
| + GROUP(tsin_b_valid_x, 3), | |
| + GROUP(tsin_b_sop_x, 3), | |
| + GROUP(tsin_b_din0_x, 3), | |
| + GROUP(tsin_b_clk_x, 3), | |
| + GROUP(pdm_din0_x, 2), | |
| + GROUP(pdm_din1_x, 2), | |
| + GROUP(pdm_din2_x, 2), | |
| + GROUP(pdm_din3_x, 2), | |
| + GROUP(pdm_dclk_x, 2), | |
| + GROUP(tdm_a_slv_sclk, 2), | |
| + GROUP(tdm_a_slv_fs, 2), | |
| + GROUP(tdm_a_din0, 2), | |
| + GROUP(tdm_a_din1, 2), | |
| + GROUP(tdm_a_sclk, 1), | |
| + GROUP(tdm_a_fs, 1), | |
| + GROUP(tdm_a_dout0, 1), | |
| + GROUP(tdm_a_dout1, 1), | |
| + GROUP(mclk1_x, 2), | |
| + | |
| + /* bank GPIOC */ | |
| + GROUP(sdcard_d0_c, 1), | |
| + GROUP(sdcard_d1_c, 1), | |
| + GROUP(sdcard_d2_c, 1), | |
| + GROUP(sdcard_d3_c, 1), | |
| + GROUP(sdcard_clk_c, 1), | |
| + GROUP(sdcard_cmd_c, 1), | |
| + GROUP(spi0_mosi_c, 5), | |
| + GROUP(spi0_miso_c, 5), | |
| + GROUP(spi0_ss0_c, 5), | |
| + GROUP(spi0_clk_c, 5), | |
| + GROUP(i2c0_sda_c, 3), | |
| + GROUP(i2c0_sck_c, 3), | |
| + GROUP(uart_ao_a_rx_c, 2), | |
| + GROUP(uart_ao_a_tx_c, 2), | |
| + GROUP(iso7816_clk_c, 5), | |
| + GROUP(iso7816_data_c, 5), | |
| + GROUP(pwm_c_c, 5), | |
| + GROUP(jtag_b_tdo, 2), | |
| + GROUP(jtag_b_tdi, 2), | |
| + GROUP(jtag_b_clk, 2), | |
| + GROUP(jtag_b_tms, 2), | |
| + GROUP(pdm_din0_c, 4), | |
| + GROUP(pdm_din1_c, 4), | |
| + GROUP(pdm_din2_c, 4), | |
| + GROUP(pdm_din3_c, 4), | |
| + GROUP(pdm_dclk_c, 4), | |
| + GROUP(pcie_clkreqn, 1), | |
| + | |
| + /* bank GPIOH */ | |
| + GROUP(spi1_mosi, 3), | |
| + GROUP(spi1_miso, 3), | |
| + GROUP(spi1_ss0, 3), | |
| + GROUP(spi1_clk, 3), | |
| + GROUP(i2c1_sda_h2, 2), | |
| + GROUP(i2c1_sck_h3, 2), | |
| + GROUP(i2c1_sda_h6, 4), | |
| + GROUP(i2c1_sck_h7, 4), | |
| + GROUP(i2c3_sda_h, 2), | |
| + GROUP(i2c3_sck_h, 2), | |
| + GROUP(uart_c_tx, 2), | |
| + GROUP(uart_c_rx, 2), | |
| + GROUP(uart_c_cts, 2), | |
| + GROUP(uart_c_rts, 2), | |
| + GROUP(iso7816_clk_h, 1), | |
| + GROUP(iso7816_data_h, 1), | |
| + GROUP(pwm_f_h, 4), | |
| + GROUP(cec_ao_a_h, 4), | |
| + GROUP(cec_ao_b_h, 5), | |
| + GROUP(hdmitx_sda, 1), | |
| + GROUP(hdmitx_sck, 1), | |
| + GROUP(hdmitx_hpd_in, 1), | |
| + GROUP(spdif_out_h, 1), | |
| + GROUP(spdif_in_h, 1), | |
| + GROUP(tdm_b_din3_h, 6), | |
| + GROUP(tdm_b_dout3_h, 5), | |
| + | |
| + /* bank GPIOA */ | |
| + GROUP(i2c3_sda_a, 2), | |
| + GROUP(i2c3_sck_a, 2), | |
| + GROUP(pdm_din0_a, 1), | |
| + GROUP(pdm_din1_a, 1), | |
| + GROUP(pdm_din2_a, 1), | |
| + GROUP(pdm_din3_a, 1), | |
| + GROUP(pdm_dclk_a, 1), | |
| + GROUP(spdif_in_a10, 1), | |
| + GROUP(spdif_in_a12, 1), | |
| + GROUP(spdif_out_a11, 1), | |
| + GROUP(spdif_out_a13, 1), | |
| + GROUP(tdm_b_slv_sclk, 2), | |
| + GROUP(tdm_b_slv_fs, 2), | |
| + GROUP(tdm_b_din0, 2), | |
| + GROUP(tdm_b_din1, 2), | |
| + GROUP(tdm_b_din2, 2), | |
| + GROUP(tdm_b_din3_a, 2), | |
| + GROUP(tdm_b_sclk, 1), | |
| + GROUP(tdm_b_fs, 1), | |
| + GROUP(tdm_b_dout0, 1), | |
| + GROUP(tdm_b_dout1, 1), | |
| + GROUP(tdm_b_dout2, 3), | |
| + GROUP(tdm_b_dout3_a, 3), | |
| + GROUP(tdm_c_slv_sclk_a, 3), | |
| + GROUP(tdm_c_slv_fs_a, 3), | |
| + GROUP(tdm_c_din0_a, 3), | |
| + GROUP(tdm_c_din1_a, 3), | |
| + GROUP(tdm_c_din2_a, 3), | |
| + GROUP(tdm_c_din3_a, 3), | |
| + GROUP(tdm_c_sclk_a, 2), | |
| + GROUP(tdm_c_fs_a, 2), | |
| + GROUP(tdm_c_dout0_a, 2), | |
| + GROUP(tdm_c_dout1_a, 2), | |
| + GROUP(tdm_c_dout2_a, 2), | |
| + GROUP(tdm_c_dout3_a, 2), | |
| + GROUP(mclk0_a, 1), | |
| + GROUP(mclk1_a, 2), | |
| + GROUP(pwm_f_a, 3), | |
| +}; | |
| + | |
| +/* uart_ao_a */ | |
| +static const unsigned int uart_ao_a_tx_pins[] = { GPIOAO_0 }; | |
| +static const unsigned int uart_ao_a_rx_pins[] = { GPIOAO_1 }; | |
| +static const unsigned int uart_ao_a_cts_pins[] = { GPIOE_0 }; | |
| +static const unsigned int uart_ao_a_rts_pins[] = { GPIOE_1 }; | |
| + | |
| +/* uart_ao_b */ | |
| +static const unsigned int uart_ao_b_tx_2_pins[] = { GPIOAO_2 }; | |
| +static const unsigned int uart_ao_b_rx_3_pins[] = { GPIOAO_3 }; | |
| +static const unsigned int uart_ao_b_tx_8_pins[] = { GPIOAO_8 }; | |
| +static const unsigned int uart_ao_b_rx_9_pins[] = { GPIOAO_9 }; | |
| +static const unsigned int uart_ao_b_cts_pins[] = { GPIOE_0 }; | |
| +static const unsigned int uart_ao_b_rts_pins[] = { GPIOE_1 }; | |
| + | |
| +/* i2c_ao */ | |
| +static const unsigned int i2c_ao_sck_pins[] = { GPIOAO_2 }; | |
| +static const unsigned int i2c_ao_sda_pins[] = { GPIOAO_3 }; | |
| + | |
| +static const unsigned int i2c_ao_sck_e_pins[] = { GPIOE_0 }; | |
| +static const unsigned int i2c_ao_sda_e_pins[] = { GPIOE_1 }; | |
| + | |
| +/* i2c_ao_slave */ | |
| +static const unsigned int i2c_ao_slave_sck_pins[] = { GPIOAO_2 }; | |
| +static const unsigned int i2c_ao_slave_sda_pins[] = { GPIOAO_3 }; | |
| + | |
| +/* ir_in */ | |
| +static const unsigned int remote_ao_input_pins[] = { GPIOAO_5 }; | |
| + | |
| +/* ir_out */ | |
| +static const unsigned int remote_ao_out_pins[] = { GPIOAO_4 }; | |
| + | |
| +/* pwm_a_e */ | |
| +static const unsigned int pwm_a_e_pins[] = { GPIOE_2 }; | |
| + | |
| +/* pwm_ao_a */ | |
| +static const unsigned int pwm_ao_a_pins[] = { GPIOAO_11 }; | |
| +static const unsigned int pwm_ao_a_hiz_pins[] = { GPIOAO_11 }; | |
| + | |
| +/* pwm_ao_b */ | |
| +static const unsigned int pwm_ao_b_pins[] = { GPIOE_0 }; | |
| + | |
| +/* pwm_ao_c */ | |
| +static const unsigned int pwm_ao_c_4_pins[] = { GPIOAO_4 }; | |
| +static const unsigned int pwm_ao_c_hiz_pins[] = { GPIOAO_4 }; | |
| +static const unsigned int pwm_ao_c_6_pins[] = { GPIOAO_6 }; | |
| + | |
| +/* pwm_ao_d */ | |
| +static const unsigned int pwm_ao_d_5_pins[] = { GPIOAO_5 }; | |
| +static const unsigned int pwm_ao_d_10_pins[] = { GPIOAO_10 }; | |
| +static const unsigned int pwm_ao_d_e_pins[] = { GPIOE_1 }; | |
| + | |
| +/* jtag_a */ | |
| +static const unsigned int jtag_a_tdi_pins[] = { GPIOAO_8 }; | |
| +static const unsigned int jtag_a_tdo_pins[] = { GPIOAO_9 }; | |
| +static const unsigned int jtag_a_clk_pins[] = { GPIOAO_6 }; | |
| +static const unsigned int jtag_a_tms_pins[] = { GPIOAO_7 }; | |
| + | |
| +/* cec_ao */ | |
| +static const unsigned int cec_ao_a_pins[] = { GPIOAO_10 }; | |
| +static const unsigned int cec_ao_b_pins[] = { GPIOAO_10 }; | |
| + | |
| +/* tsin_ao_a */ | |
| +static const unsigned int tsin_ao_asop_pins[] = { GPIOAO_6 }; | |
| +static const unsigned int tsin_ao_adin0_pins[] = { GPIOAO_7 }; | |
| +static const unsigned int tsin_ao_aclk_pins[] = { GPIOAO_8 }; | |
| +static const unsigned int tsin_ao_a_valid_pins[] = { GPIOAO_9 }; | |
| + | |
| +/* spdif_ao_out */ | |
| +static const unsigned int spdif_ao_out_pins[] = { GPIOAO_10 }; | |
| + | |
| +/* tdm_ao_b */ | |
| +static const unsigned int tdm_ao_b_slv_fs_pins[] = { GPIOAO_7 }; | |
| +static const unsigned int tdm_ao_b_slv_sclk_pins[] = { GPIOAO_8 }; | |
| +static const unsigned int tdm_ao_b_fs_pins[] = { GPIOAO_7 }; | |
| +static const unsigned int tdm_ao_b_sclk_pins[] = { GPIOAO_8 }; | |
| +static const unsigned int tdm_ao_b_din0_pins[] = { GPIOAO_4 }; | |
| +static const unsigned int tdm_ao_b_din1_pins[] = { GPIOAO_10 }; | |
| +static const unsigned int tdm_ao_b_din2_pins[] = { GPIOAO_6 }; | |
| +static const unsigned int tdm_ao_b_dout0_pins[] = { GPIOAO_4 }; | |
| +static const unsigned int tdm_ao_b_dout1_pins[] = { GPIOAO_10 }; | |
| +static const unsigned int tdm_ao_b_dout2_pins[] = { GPIOAO_6 }; | |
| + | |
| +/* mclk0_ao */ | |
| +static const unsigned int mclk0_ao_pins[] = { GPIOAO_9 }; | |
| + | |
| +static const struct meson_pmx_group meson_g12a_aobus_groups[] = { | |
| + GPIO_GROUP(GPIOAO_0), | |
| + GPIO_GROUP(GPIOAO_1), | |
| + GPIO_GROUP(GPIOAO_2), | |
| + GPIO_GROUP(GPIOAO_3), | |
| + GPIO_GROUP(GPIOAO_4), | |
| + GPIO_GROUP(GPIOAO_5), | |
| + GPIO_GROUP(GPIOAO_6), | |
| + GPIO_GROUP(GPIOAO_7), | |
| + GPIO_GROUP(GPIOAO_8), | |
| + GPIO_GROUP(GPIOAO_9), | |
| + GPIO_GROUP(GPIOAO_10), | |
| + GPIO_GROUP(GPIOAO_11), | |
| + GPIO_GROUP(GPIOE_0), | |
| + GPIO_GROUP(GPIOE_1), | |
| + GPIO_GROUP(GPIOE_2), | |
| + | |
| + /* bank AO */ | |
| + GROUP(uart_ao_a_tx, 1), | |
| + GROUP(uart_ao_a_rx, 1), | |
| + GROUP(uart_ao_a_cts, 1), | |
| + GROUP(uart_ao_a_rts, 1), | |
| + GROUP(uart_ao_b_tx_2, 2), | |
| + GROUP(uart_ao_b_rx_3, 2), | |
| + GROUP(uart_ao_b_tx_8, 3), | |
| + GROUP(uart_ao_b_rx_9, 3), | |
| + GROUP(uart_ao_b_cts, 2), | |
| + GROUP(uart_ao_b_rts, 2), | |
| + GROUP(i2c_ao_sck, 1), | |
| + GROUP(i2c_ao_sda, 1), | |
| + GROUP(i2c_ao_sck_e, 4), | |
| + GROUP(i2c_ao_sda_e, 4), | |
| + GROUP(i2c_ao_slave_sck, 3), | |
| + GROUP(i2c_ao_slave_sda, 3), | |
| + GROUP(remote_ao_input, 1), | |
| + GROUP(remote_ao_out, 1), | |
| + GROUP(pwm_a_e, 3), | |
| + GROUP(pwm_ao_a, 3), | |
| + GROUP(pwm_ao_a_hiz, 2), | |
| + GROUP(pwm_ao_b, 3), | |
| + GROUP(pwm_ao_c_4, 3), | |
| + GROUP(pwm_ao_c_hiz, 4), | |
| + GROUP(pwm_ao_c_6, 3), | |
| + GROUP(pwm_ao_d_5, 3), | |
| + GROUP(pwm_ao_d_10, 3), | |
| + GROUP(pwm_ao_d_e, 3), | |
| + GROUP(jtag_a_tdi, 1), | |
| + GROUP(jtag_a_tdo, 1), | |
| + GROUP(jtag_a_clk, 1), | |
| + GROUP(jtag_a_tms, 1), | |
| + GROUP(cec_ao_a, 1), | |
| + GROUP(cec_ao_b, 2), | |
| + GROUP(tsin_ao_asop, 4), | |
| + GROUP(tsin_ao_adin0, 4), | |
| + GROUP(tsin_ao_aclk, 4), | |
| + GROUP(tsin_ao_a_valid, 4), | |
| + GROUP(spdif_ao_out, 4), | |
| + GROUP(tdm_ao_b_dout0, 5), | |
| + GROUP(tdm_ao_b_dout1, 5), | |
| + GROUP(tdm_ao_b_dout2, 5), | |
| + GROUP(tdm_ao_b_fs, 5), | |
| + GROUP(tdm_ao_b_sclk, 5), | |
| + GROUP(tdm_ao_b_din0, 6), | |
| + GROUP(tdm_ao_b_din1, 6), | |
| + GROUP(tdm_ao_b_din2, 6), | |
| + GROUP(tdm_ao_b_slv_fs, 6), | |
| + GROUP(tdm_ao_b_slv_sclk, 6), | |
| + GROUP(mclk0_ao, 5), | |
| +}; | |
| + | |
| +static const char * const gpio_periphs_groups[] = { | |
| + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", | |
| + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", | |
| + "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14", | |
| + "GPIOZ_15", | |
| + | |
| + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", | |
| + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", | |
| + | |
| + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", | |
| + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", | |
| + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", | |
| + "BOOT_15", | |
| + | |
| + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", | |
| + "GPIOC_5", "GPIOC_6", "GPIOC_7", | |
| + | |
| + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", | |
| + "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9", | |
| + "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14", | |
| + "GPIOA_15", | |
| + | |
| + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", | |
| + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", | |
| + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", | |
| + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", | |
| +}; | |
| + | |
| +static const char * const emmc_groups[] = { | |
| + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", | |
| + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", | |
| + "emmc_nand_d6", "emmc_nand_d7", | |
| + "emmc_clk", "emmc_cmd", "emmc_nand_ds", | |
| +}; | |
| + | |
| +static const char * const nand_groups[] = { | |
| + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", | |
| + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", | |
| + "emmc_nand_d6", "emmc_nand_d7", | |
| + "nand_ce0", "nand_ale", "nand_cle", | |
| + "nand_wen_clk", "nand_ren_wr", "nand_rb0", | |
| + "emmc_nand_ds", "nand_ce1", | |
| +}; | |
| + | |
| +static const char * const nor_groups[] = { | |
| + "nor_d", "nor_q", "nor_c", "nor_cs", | |
| + "nor_hold", "nor_wp", | |
| +}; | |
| + | |
| +static const char * const sdio_groups[] = { | |
| + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", | |
| + "sdio_cmd", "sdio_clk", "sdio_dummy", | |
| +}; | |
| + | |
| +static const char * const sdcard_groups[] = { | |
| + "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c", | |
| + "sdcard_clk_c", "sdcard_cmd_c", | |
| + "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z", | |
| + "sdcard_clk_z", "sdcard_cmd_z", | |
| +}; | |
| + | |
| +static const char * const spi0_groups[] = { | |
| + "spi0_mosi_c", "spi0_miso_c", "spi0_ss0_c", "spi0_clk_c", | |
| + "spi0_mosi_x", "spi0_miso_x", "spi0_ss0_x", "spi0_clk_x", | |
| +}; | |
| + | |
| +static const char * const spi1_groups[] = { | |
| + "spi1_mosi", "spi1_miso", "spi1_ss0", "spi1_clk", | |
| +}; | |
| + | |
| +static const char * const i2c0_groups[] = { | |
| + "i2c0_sda_c", "i2c0_sck_c", | |
| + "i2c0_sda_z0", "i2c0_sck_z1", | |
| + "i2c0_sda_z7", "i2c0_sck_z8", | |
| +}; | |
| + | |
| +static const char * const i2c1_groups[] = { | |
| + "i2c1_sda_x", "i2c1_sck_x", | |
| + "i2c1_sda_h2", "i2c1_sck_h3", | |
| + "i2c1_sda_h6", "i2c1_sck_h7", | |
| +}; | |
| + | |
| +static const char * const i2c2_groups[] = { | |
| + "i2c2_sda_x", "i2c2_sck_x", | |
| + "i2c2_sda_z", "i2c2_sck_z", | |
| +}; | |
| + | |
| +static const char * const i2c3_groups[] = { | |
| + "i2c3_sda_h", "i2c3_sck_h", | |
| + "i2c3_sda_a", "i2c3_sck_a", | |
| +}; | |
| + | |
| +static const char * const uart_a_groups[] = { | |
| + "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts", | |
| +}; | |
| + | |
| +static const char * const uart_b_groups[] = { | |
| + "uart_b_tx", "uart_b_rx", | |
| +}; | |
| + | |
| +static const char * const uart_c_groups[] = { | |
| + "uart_c_tx", "uart_c_rx", "uart_c_cts", "uart_c_rts", | |
| +}; | |
| + | |
| +static const char * const uart_ao_a_c_groups[] = { | |
| + "uart_ao_a_rx_c", "uart_ao_a_tx_c", | |
| +}; | |
| + | |
| +static const char * const iso7816_groups[] = { | |
| + "iso7816_clk_c", "iso7816_data_c", | |
| + "iso7816_clk_x", "iso7816_data_x", | |
| + "iso7816_clk_h", "iso7816_data_h", | |
| + "iso7816_clk_z", "iso7816_data_z", | |
| +}; | |
| + | |
| +static const char * const eth_groups[] = { | |
| + "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", | |
| + "eth_txd2_rgmii", "eth_txd3_rgmii", "eth_rgmii_rx_clk", | |
| + "eth_txd0", "eth_txd1", "eth_txen", "eth_mdc", | |
| + "eth_rxd0", "eth_rxd1", "eth_rx_dv", "eth_mdio", | |
| + "eth_link_led", "eth_act_led", | |
| +}; | |
| + | |
| +static const char * const pwm_a_groups[] = { | |
| + "pwm_a", | |
| +}; | |
| + | |
| +static const char * const pwm_b_groups[] = { | |
| + "pwm_b_h", "pwm_b_x7", "pwm_b_x19", "pwm_b_z0", "pwm_b_z13" | |
| +}; | |
| + | |
| +static const char * const pwm_c_groups[] = { | |
| + "pwm_c_c", "pwm_c_x5", "pwm_c_x8", "pwm_c_z", | |
| +}; | |
| + | |
| +static const char * const pwm_d_groups[] = { | |
| + "pwm_d_a", "pwm_d_x3", "pwm_d_x6", "pwm_d_z", | |
| +}; | |
| + | |
| +static const char * const pwm_e_groups[] = { | |
| + "pwm_e", | |
| +}; | |
| + | |
| +static const char * const pwm_f_groups[] = { | |
| + "pwm_f_z", "pwm_f_a", "pwm_f_x", "pwm_f_h", | |
| +}; | |
| + | |
| +static const char * const cec_ao_a_h_groups[] = { | |
| + "cec_ao_a_h", | |
| +}; | |
| + | |
| +static const char * const cec_ao_b_h_groups[] = { | |
| + "cec_ao_b_h", | |
| +}; | |
| + | |
| +static const char * const jtag_b_groups[] = { | |
| + "jtag_b_tdi", "jtag_b_tdo", "jtag_b_clk", "jtag_b_tms", | |
| +}; | |
| + | |
| +static const char * const bt565_a_groups[] = { | |
| + "bt565_a_vs", "bt565_a_hs", "bt565_a_clk", | |
| + "bt565_a_din0", "bt565_a_din1", "bt565_a_din2", | |
| + "bt565_a_din3", "bt565_a_din4", "bt565_a_din5", | |
| + "bt565_a_din6", "bt565_a_din7", | |
| +}; | |
| + | |
| +static const char * const tsin_a_groups[] = { | |
| + "tsin_a_valid", "tsin_a_sop", "tsin_a_din0", | |
| + "tsin_a_clk", | |
| +}; | |
| + | |
| +static const char * const tsin_b_groups[] = { | |
| + "tsin_b_valid_x", "tsin_b_sop_x", "tsin_b_din0_x", "tsin_b_clk_x", | |
| + "tsin_b_valid_z", "tsin_b_sop_z", "tsin_b_din0_z", "tsin_b_clk_z", | |
| + "tsin_b_fail", "tsin_b_din1", "tsin_b_din2", "tsin_b_din3", | |
| + "tsin_b_din4", "tsin_b_din5", "tsin_b_din6", "tsin_b_din7", | |
| +}; | |
| + | |
| +static const char * const hdmitx_groups[] = { | |
| + "hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in", | |
| +}; | |
| + | |
| +static const char * const pdm_groups[] = { | |
| + "pdm_din0_c", "pdm_din1_c", "pdm_din2_c", "pdm_din3_c", | |
| + "pdm_dclk_c", | |
| + "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_din3_x", | |
| + "pdm_dclk_x", | |
| + "pdm_din0_z", "pdm_din1_z", "pdm_din2_z", "pdm_din3_z", | |
| + "pdm_dclk_z", | |
| + "pdm_din0_a", "pdm_din1_a", "pdm_din2_a", "pdm_din3_a", | |
| + "pdm_dclk_a", | |
| +}; | |
| + | |
| +static const char * const spdif_in_groups[] = { | |
| + "spdif_in_h", "spdif_in_a10", "spdif_in_a12", | |
| +}; | |
| + | |
| +static const char * const spdif_out_groups[] = { | |
| + "spdif_out_h", "spdif_out_a11", "spdif_out_a13", | |
| +}; | |
| + | |
| +static const char * const mclk0_groups[] = { | |
| + "mclk0_a", | |
| +}; | |
| + | |
| +static const char * const mclk1_groups[] = { | |
| + "mclk1_x", "mclk1_z", "mclk1_a", | |
| +}; | |
| + | |
| +static const char * const tdm_a_groups[] = { | |
| + "tdm_a_slv_sclk", "tdm_a_slv_fs", "tdm_a_sclk", "tdm_a_fs", | |
| + "tdm_a_din0", "tdm_a_din1", "tdm_a_dout0", "tdm_a_dout1", | |
| +}; | |
| + | |
| +static const char * const tdm_b_groups[] = { | |
| + "tdm_b_slv_sclk", "tdm_b_slv_fs", "tdm_b_sclk", "tdm_b_fs", | |
| + "tdm_b_din0", "tdm_b_din1", "tdm_b_din2", | |
| + "tdm_b_din3_a", "tdm_b_din3_h", | |
| + "tdm_b_dout0", "tdm_b_dout1", "tdm_b_dout2", | |
| + "tdm_b_dout3_a", "tdm_b_dout3_h", | |
| +}; | |
| + | |
| +static const char * const tdm_c_groups[] = { | |
| + "tdm_c_slv_sclk_a", "tdm_c_slv_fs_a", | |
| + "tdm_c_slv_sclk_z", "tdm_c_slv_fs_z", | |
| + "tdm_c_sclk_a", "tdm_c_fs_a", | |
| + "tdm_c_sclk_z", "tdm_c_fs_z", | |
| + "tdm_c_din0_a", "tdm_c_din1_a", | |
| + "tdm_c_din2_a", "tdm_c_din3_a", | |
| + "tdm_c_din0_z", "tdm_c_din1_z", | |
| + "tdm_c_din2_z", "tdm_c_din3_z", | |
| + "tdm_c_dout0_a", "tdm_c_dout1_a", | |
| + "tdm_c_dout2_a", "tdm_c_dout3_a", | |
| + "tdm_c_dout0_z", "tdm_c_dout1_z", | |
| + "tdm_c_dout2_z", "tdm_c_dout3_z", | |
| +}; | |
| + | |
| +static const char * const pcie_clkreqn_groups[] = { | |
| + "pcie_clkreqn" | |
| +}; | |
| + | |
| +static const char * const gpio_aobus_groups[] = { | |
| + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", | |
| + "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", | |
| + "GPIOAO_10", "GPIOAO_11", "GPIOE_0", "GPIOE_1", "GPIOE_2", | |
| +}; | |
| + | |
| +static const char * const uart_ao_a_groups[] = { | |
| + "uart_ao_a_tx", "uart_ao_a_rx", | |
| + "uart_ao_a_cts", "uart_ao_a_rts", | |
| +}; | |
| + | |
| +static const char * const uart_ao_b_groups[] = { | |
| + "uart_ao_b_tx_2", "uart_ao_b_rx_3", | |
| + "uart_ao_b_tx_8", "uart_ao_b_rx_9", | |
| + "uart_ao_b_cts", "uart_ao_b_rts", | |
| +}; | |
| + | |
| +static const char * const i2c_ao_groups[] = { | |
| + "i2c_ao_sck", "i2c_ao_sda", | |
| + "i2c_ao_sck_e", "i2c_ao_sda_e", | |
| +}; | |
| + | |
| +static const char * const i2c_ao_slave_groups[] = { | |
| + "i2c_ao_slave_sck", "i2c_ao_slave_sda", | |
| +}; | |
| + | |
| +static const char * const remote_ao_input_groups[] = { | |
| + "remote_ao_input", | |
| +}; | |
| + | |
| +static const char * const remote_ao_out_groups[] = { | |
| + "remote_ao_out", | |
| +}; | |
| + | |
| +static const char * const pwm_a_e_groups[] = { | |
| + "pwm_a_e", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_a_groups[] = { | |
| + "pwm_ao_a", "pwm_ao_a_hiz", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_b_groups[] = { | |
| + "pwm_ao_b", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_c_groups[] = { | |
| + "pwm_ao_c_4", "pwm_ao_c_hiz", | |
| + "pwm_ao_c_6", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_d_groups[] = { | |
| + "pwm_ao_d_5", "pwm_ao_d_10", "pwm_ao_d_e", | |
| +}; | |
| + | |
| +static const char * const jtag_a_groups[] = { | |
| + "jtag_a_tdi", "jtag_a_tdo", "jtag_a_clk", "jtag_a_tms", | |
| +}; | |
| + | |
| +static const char * const cec_ao_a_groups[] = { | |
| + "cec_ao_a", | |
| +}; | |
| + | |
| +static const char * const cec_ao_b_groups[] = { | |
| + "cec_ao_b", | |
| +}; | |
| + | |
| +static const char * const tsin_ao_a_groups[] = { | |
| + "tsin_ao_asop", "tsin_ao_adin0", "tsin_ao_aclk", "tsin_ao_a_valid", | |
| +}; | |
| + | |
| +static const char * const spdif_ao_out_groups[] = { | |
| + "spdif_ao_out", | |
| +}; | |
| + | |
| +static const char * const tdm_ao_b_groups[] = { | |
| + "tdm_ao_b_dout0", "tdm_ao_b_dout1", "tdm_ao_b_dout2", | |
| + "tdm_ao_b_fs", "tdm_ao_b_sclk", | |
| + "tdm_ao_b_din0", "tdm_ao_b_din1", "tdm_ao_b_din2", | |
| + "tdm_ao_b_slv_fs", "tdm_ao_b_slv_sclk", | |
| +}; | |
| + | |
| +static const char * const mclk0_ao_groups[] = { | |
| + "mclk0_ao", | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson_g12a_periphs_functions[] = { | |
| + FUNCTION(gpio_periphs), | |
| + FUNCTION(emmc), | |
| + FUNCTION(nor), | |
| + FUNCTION(spi0), | |
| + FUNCTION(spi1), | |
| + FUNCTION(sdio), | |
| + FUNCTION(nand), | |
| + FUNCTION(sdcard), | |
| + FUNCTION(i2c0), | |
| + FUNCTION(i2c1), | |
| + FUNCTION(i2c2), | |
| + FUNCTION(i2c3), | |
| + FUNCTION(uart_a), | |
| + FUNCTION(uart_b), | |
| + FUNCTION(uart_c), | |
| + FUNCTION(uart_ao_a_c), | |
| + FUNCTION(iso7816), | |
| + FUNCTION(eth), | |
| + FUNCTION(pwm_a), | |
| + FUNCTION(pwm_b), | |
| + FUNCTION(pwm_c), | |
| + FUNCTION(pwm_d), | |
| + FUNCTION(pwm_e), | |
| + FUNCTION(pwm_f), | |
| + FUNCTION(cec_ao_a_h), | |
| + FUNCTION(cec_ao_b_h), | |
| + FUNCTION(jtag_b), | |
| + FUNCTION(bt565_a), | |
| + FUNCTION(tsin_a), | |
| + FUNCTION(tsin_b), | |
| + FUNCTION(hdmitx), | |
| + FUNCTION(pdm), | |
| + FUNCTION(spdif_out), | |
| + FUNCTION(spdif_in), | |
| + FUNCTION(mclk0), | |
| + FUNCTION(mclk1), | |
| + FUNCTION(tdm_a), | |
| + FUNCTION(tdm_b), | |
| + FUNCTION(tdm_c), | |
| + FUNCTION(pcie_clkreqn), | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson_g12a_aobus_functions[] = { | |
| + FUNCTION(gpio_aobus), | |
| + FUNCTION(uart_ao_a), | |
| + FUNCTION(uart_ao_b), | |
| + FUNCTION(i2c_ao), | |
| + FUNCTION(i2c_ao_slave), | |
| + FUNCTION(remote_ao_input), | |
| + FUNCTION(remote_ao_out), | |
| + FUNCTION(pwm_a_e), | |
| + FUNCTION(pwm_ao_a), | |
| + FUNCTION(pwm_ao_b), | |
| + FUNCTION(pwm_ao_c), | |
| + FUNCTION(pwm_ao_d), | |
| + FUNCTION(jtag_a), | |
| + FUNCTION(cec_ao_a), | |
| + FUNCTION(cec_ao_b), | |
| + FUNCTION(tsin_ao_a), | |
| + FUNCTION(spdif_ao_out), | |
| + FUNCTION(tdm_ao_b), | |
| + FUNCTION(mclk0_ao), | |
| +}; | |
| + | |
| +static const struct meson_bank meson_g12a_periphs_banks[] = { | |
| + /* name first last irq pullen pull dir out in ds */ | |
| + BANK_DS("Z", GPIOZ_0, GPIOZ_15, IRQID_GPIOZ_0, IRQID_GPIOZ_15, | |
| + 4, 0, 4, 0, 12, 0, 13, 0, 14, 0, 5, 0), | |
| + BANK_DS("H", GPIOH_0, GPIOH_8, IRQID_GPIOH_0, IRQID_GPIOH_8, | |
| + 3, 0, 3, 0, 9, 0, 10, 0, 11, 0, 4, 0), | |
| + BANK_DS("BOOT", BOOT_0, BOOT_15, IRQID_BOOT_0, IRQID_BOOT_15, | |
| + 0, 0, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0), | |
| + BANK_DS("C", GPIOC_0, GPIOC_7, IRQID_GPIOC_0, IRQID_GPIOC_7, | |
| + 1, 0, 1, 0, 3, 0, 4, 0, 5, 0, 1, 0), | |
| + BANK_DS("A", GPIOA_0, GPIOA_15, IRQID_GPIOA_0, IRQID_GPIOA_15, | |
| + 5, 0, 5, 0, 16, 0, 17, 0, 18, 0, 6, 0), | |
| + BANK_DS("X", GPIOX_0, GPIOX_19, IRQID_GPIOX_0, IRQID_GPIOX_19, | |
| + 2, 0, 2, 0, 6, 0, 7, 0, 8, 0, 2, 0), | |
| +}; | |
| + | |
| +static const struct meson_bank meson_g12a_aobus_banks[] = { | |
| + /* name first last irq pullen pull dir out in ds */ | |
| + BANK_DS("AO", GPIOAO_0, GPIOAO_11, IRQID_GPIOAO_0, IRQID_GPIOAO_11, | |
| + 3, 0, 2, 0, 0, 0, 4, 0, 1, 0, 0, 0), | |
| + /* GPIOE actually located in the AO bank */ | |
| + BANK_DS("E", GPIOE_0, GPIOE_2, IRQID_GPIOE_0, IRQID_GPIOE_2, | |
| + 3, 16, 2, 16, 0, 16, 4, 16, 1, 16, 1, 0), | |
| +}; | |
| + | |
| +static const struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = { | |
| + /* name first last reg offset */ | |
| + BANK_PMX("Z", GPIOZ_0, GPIOZ_15, 0x6, 0), | |
| + BANK_PMX("H", GPIOH_0, GPIOH_8, 0xb, 0), | |
| + BANK_PMX("BOOT", BOOT_0, BOOT_15, 0x0, 0), | |
| + BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0), | |
| + BANK_PMX("A", GPIOA_0, GPIOA_15, 0xd, 0), | |
| + BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0), | |
| +}; | |
| + | |
| +static const struct meson_axg_pmx_data meson_g12a_periphs_pmx_banks_data = { | |
| + .pmx_banks = meson_g12a_periphs_pmx_banks, | |
| + .num_pmx_banks = ARRAY_SIZE(meson_g12a_periphs_pmx_banks), | |
| +}; | |
| + | |
| +static const struct meson_pmx_bank meson_g12a_aobus_pmx_banks[] = { | |
| + BANK_PMX("AO", GPIOAO_0, GPIOAO_11, 0x0, 0), | |
| + BANK_PMX("E", GPIOE_0, GPIOE_2, 0x1, 16), | |
| +}; | |
| + | |
| +static const struct meson_axg_pmx_data meson_g12a_aobus_pmx_banks_data = { | |
| + .pmx_banks = meson_g12a_aobus_pmx_banks, | |
| + .num_pmx_banks = ARRAY_SIZE(meson_g12a_aobus_pmx_banks), | |
| +}; | |
| + | |
| +static int meson_g12a_aobus_parse_dt_extra(struct meson_pinctrl *pc) | |
| +{ | |
| + pc->reg_pull = pc->reg_gpio; | |
| + pc->reg_pullen = pc->reg_gpio; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static const struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = { | |
| + .name = "periphs-banks", | |
| + .pins = meson_g12a_periphs_pins, | |
| + .groups = meson_g12a_periphs_groups, | |
| + .funcs = meson_g12a_periphs_functions, | |
| + .banks = meson_g12a_periphs_banks, | |
| + .num_pins = ARRAY_SIZE(meson_g12a_periphs_pins), | |
| + .num_groups = ARRAY_SIZE(meson_g12a_periphs_groups), | |
| + .num_funcs = ARRAY_SIZE(meson_g12a_periphs_functions), | |
| + .num_banks = ARRAY_SIZE(meson_g12a_periphs_banks), | |
| + .pmx_ops = &meson_axg_pmx_ops, | |
| + .pmx_data = &meson_g12a_periphs_pmx_banks_data, | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = { | |
| + .name = "aobus-banks", | |
| + .pins = meson_g12a_aobus_pins, | |
| + .groups = meson_g12a_aobus_groups, | |
| + .funcs = meson_g12a_aobus_functions, | |
| + .banks = meson_g12a_aobus_banks, | |
| + .num_pins = ARRAY_SIZE(meson_g12a_aobus_pins), | |
| + .num_groups = ARRAY_SIZE(meson_g12a_aobus_groups), | |
| + .num_funcs = ARRAY_SIZE(meson_g12a_aobus_functions), | |
| + .num_banks = ARRAY_SIZE(meson_g12a_aobus_banks), | |
| + .pmx_ops = &meson_axg_pmx_ops, | |
| + .pmx_data = &meson_g12a_aobus_pmx_banks_data, | |
| + .parse_dt = meson_g12a_aobus_parse_dt_extra, | |
| +}; | |
| + | |
| +static const struct of_device_id meson_g12a_pinctrl_dt_match[] = { | |
| + { | |
| + .compatible = "amlogic,meson-g12a-periphs-pinctrl", | |
| + .data = &meson_g12a_periphs_pinctrl_data, | |
| + }, | |
| + { | |
| + .compatible = "amlogic,meson-g12a-aobus-pinctrl", | |
| + .data = &meson_g12a_aobus_pinctrl_data, | |
| + }, | |
| + { }, | |
| +}; | |
| +MODULE_DEVICE_TABLE(of, meson_g12a_pinctrl_dt_match); | |
| + | |
| +static struct platform_driver meson_g12a_pinctrl_driver = { | |
| + .probe = meson_pinctrl_probe, | |
| + .driver = { | |
| + .name = "meson-g12a-pinctrl", | |
| + .of_match_table = meson_g12a_pinctrl_dt_match, | |
| + }, | |
| +}; | |
| + | |
| +module_platform_driver(meson_g12a_pinctrl_driver); | |
| +MODULE_DESCRIPTION("Amlogic Meson G12A SoC pinctrl driver"); | |
| +MODULE_LICENSE("Dual BSD/GPL"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c | |
| new file mode 100644 | |
| index 0000000000..4e8b9d7c2e | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c | |
| @@ -0,0 +1,914 @@ | |
| +// SPDX-License-Identifier: GPL-2.0-only | |
| +/* | |
| + * Pin controller and GPIO driver for Amlogic Meson GXBB. | |
| + * | |
| + * Copyright (C) 2016 Endless Mobile, Inc. | |
| + * Author: Carlo Caione <carlo@endlessm.com> | |
| + */ | |
| + | |
| +#include <dt-bindings/gpio/meson-gxbb-gpio.h> | |
| +#include "pinctrl-meson.h" | |
| +#include "pinctrl-meson8-pmx.h" | |
| + | |
| +static const struct pinctrl_pin_desc meson_gxbb_periphs_pins[] = { | |
| + MESON_PIN(GPIOZ_0), | |
| + MESON_PIN(GPIOZ_1), | |
| + MESON_PIN(GPIOZ_2), | |
| + MESON_PIN(GPIOZ_3), | |
| + MESON_PIN(GPIOZ_4), | |
| + MESON_PIN(GPIOZ_5), | |
| + MESON_PIN(GPIOZ_6), | |
| + MESON_PIN(GPIOZ_7), | |
| + MESON_PIN(GPIOZ_8), | |
| + MESON_PIN(GPIOZ_9), | |
| + MESON_PIN(GPIOZ_10), | |
| + MESON_PIN(GPIOZ_11), | |
| + MESON_PIN(GPIOZ_12), | |
| + MESON_PIN(GPIOZ_13), | |
| + MESON_PIN(GPIOZ_14), | |
| + MESON_PIN(GPIOZ_15), | |
| + | |
| + MESON_PIN(GPIOH_0), | |
| + MESON_PIN(GPIOH_1), | |
| + MESON_PIN(GPIOH_2), | |
| + MESON_PIN(GPIOH_3), | |
| + | |
| + MESON_PIN(BOOT_0), | |
| + MESON_PIN(BOOT_1), | |
| + MESON_PIN(BOOT_2), | |
| + MESON_PIN(BOOT_3), | |
| + MESON_PIN(BOOT_4), | |
| + MESON_PIN(BOOT_5), | |
| + MESON_PIN(BOOT_6), | |
| + MESON_PIN(BOOT_7), | |
| + MESON_PIN(BOOT_8), | |
| + MESON_PIN(BOOT_9), | |
| + MESON_PIN(BOOT_10), | |
| + MESON_PIN(BOOT_11), | |
| + MESON_PIN(BOOT_12), | |
| + MESON_PIN(BOOT_13), | |
| + MESON_PIN(BOOT_14), | |
| + MESON_PIN(BOOT_15), | |
| + MESON_PIN(BOOT_16), | |
| + MESON_PIN(BOOT_17), | |
| + | |
| + MESON_PIN(CARD_0), | |
| + MESON_PIN(CARD_1), | |
| + MESON_PIN(CARD_2), | |
| + MESON_PIN(CARD_3), | |
| + MESON_PIN(CARD_4), | |
| + MESON_PIN(CARD_5), | |
| + MESON_PIN(CARD_6), | |
| + | |
| + MESON_PIN(GPIODV_0), | |
| + MESON_PIN(GPIODV_1), | |
| + MESON_PIN(GPIODV_2), | |
| + MESON_PIN(GPIODV_3), | |
| + MESON_PIN(GPIODV_4), | |
| + MESON_PIN(GPIODV_5), | |
| + MESON_PIN(GPIODV_6), | |
| + MESON_PIN(GPIODV_7), | |
| + MESON_PIN(GPIODV_8), | |
| + MESON_PIN(GPIODV_9), | |
| + MESON_PIN(GPIODV_10), | |
| + MESON_PIN(GPIODV_11), | |
| + MESON_PIN(GPIODV_12), | |
| + MESON_PIN(GPIODV_13), | |
| + MESON_PIN(GPIODV_14), | |
| + MESON_PIN(GPIODV_15), | |
| + MESON_PIN(GPIODV_16), | |
| + MESON_PIN(GPIODV_17), | |
| + MESON_PIN(GPIODV_18), | |
| + MESON_PIN(GPIODV_19), | |
| + MESON_PIN(GPIODV_20), | |
| + MESON_PIN(GPIODV_21), | |
| + MESON_PIN(GPIODV_22), | |
| + MESON_PIN(GPIODV_23), | |
| + MESON_PIN(GPIODV_24), | |
| + MESON_PIN(GPIODV_25), | |
| + MESON_PIN(GPIODV_26), | |
| + MESON_PIN(GPIODV_27), | |
| + MESON_PIN(GPIODV_28), | |
| + MESON_PIN(GPIODV_29), | |
| + | |
| + MESON_PIN(GPIOY_0), | |
| + MESON_PIN(GPIOY_1), | |
| + MESON_PIN(GPIOY_2), | |
| + MESON_PIN(GPIOY_3), | |
| + MESON_PIN(GPIOY_4), | |
| + MESON_PIN(GPIOY_5), | |
| + MESON_PIN(GPIOY_6), | |
| + MESON_PIN(GPIOY_7), | |
| + MESON_PIN(GPIOY_8), | |
| + MESON_PIN(GPIOY_9), | |
| + MESON_PIN(GPIOY_10), | |
| + MESON_PIN(GPIOY_11), | |
| + MESON_PIN(GPIOY_12), | |
| + MESON_PIN(GPIOY_13), | |
| + MESON_PIN(GPIOY_14), | |
| + MESON_PIN(GPIOY_15), | |
| + MESON_PIN(GPIOY_16), | |
| + | |
| + MESON_PIN(GPIOX_0), | |
| + MESON_PIN(GPIOX_1), | |
| + MESON_PIN(GPIOX_2), | |
| + MESON_PIN(GPIOX_3), | |
| + MESON_PIN(GPIOX_4), | |
| + MESON_PIN(GPIOX_5), | |
| + MESON_PIN(GPIOX_6), | |
| + MESON_PIN(GPIOX_7), | |
| + MESON_PIN(GPIOX_8), | |
| + MESON_PIN(GPIOX_9), | |
| + MESON_PIN(GPIOX_10), | |
| + MESON_PIN(GPIOX_11), | |
| + MESON_PIN(GPIOX_12), | |
| + MESON_PIN(GPIOX_13), | |
| + MESON_PIN(GPIOX_14), | |
| + MESON_PIN(GPIOX_15), | |
| + MESON_PIN(GPIOX_16), | |
| + MESON_PIN(GPIOX_17), | |
| + MESON_PIN(GPIOX_18), | |
| + MESON_PIN(GPIOX_19), | |
| + MESON_PIN(GPIOX_20), | |
| + MESON_PIN(GPIOX_21), | |
| + MESON_PIN(GPIOX_22), | |
| + | |
| + MESON_PIN(GPIOCLK_0), | |
| + MESON_PIN(GPIOCLK_1), | |
| + MESON_PIN(GPIOCLK_2), | |
| + MESON_PIN(GPIOCLK_3), | |
| +}; | |
| + | |
| +static const unsigned int emmc_nand_d07_pins[] = { | |
| + BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7, | |
| +}; | |
| +static const unsigned int emmc_clk_pins[] = { BOOT_8 }; | |
| +static const unsigned int emmc_cmd_pins[] = { BOOT_10 }; | |
| +static const unsigned int emmc_ds_pins[] = { BOOT_15 }; | |
| + | |
| +static const unsigned int nor_d_pins[] = { BOOT_11 }; | |
| +static const unsigned int nor_q_pins[] = { BOOT_12 }; | |
| +static const unsigned int nor_c_pins[] = { BOOT_13 }; | |
| +static const unsigned int nor_cs_pins[] = { BOOT_15 }; | |
| + | |
| +static const unsigned int spi_sclk_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int spi_ss0_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int spi_miso_pins[] = { GPIOZ_12 }; | |
| +static const unsigned int spi_mosi_pins[] = { GPIOZ_13 }; | |
| + | |
| +static const unsigned int sdcard_d0_pins[] = { CARD_1 }; | |
| +static const unsigned int sdcard_d1_pins[] = { CARD_0 }; | |
| +static const unsigned int sdcard_d2_pins[] = { CARD_5 }; | |
| +static const unsigned int sdcard_d3_pins[] = { CARD_4 }; | |
| +static const unsigned int sdcard_cmd_pins[] = { CARD_3 }; | |
| +static const unsigned int sdcard_clk_pins[] = { CARD_2 }; | |
| + | |
| +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; | |
| +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; | |
| +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; | |
| +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; | |
| +static const unsigned int sdio_cmd_pins[] = { GPIOX_4 }; | |
| +static const unsigned int sdio_clk_pins[] = { GPIOX_5 }; | |
| +static const unsigned int sdio_irq_pins[] = { GPIOX_7 }; | |
| + | |
| +static const unsigned int nand_ce0_pins[] = { BOOT_8 }; | |
| +static const unsigned int nand_ce1_pins[] = { BOOT_9 }; | |
| +static const unsigned int nand_rb0_pins[] = { BOOT_10 }; | |
| +static const unsigned int nand_ale_pins[] = { BOOT_11 }; | |
| +static const unsigned int nand_cle_pins[] = { BOOT_12 }; | |
| +static const unsigned int nand_wen_clk_pins[] = { BOOT_13 }; | |
| +static const unsigned int nand_ren_wr_pins[] = { BOOT_14 }; | |
| +static const unsigned int nand_dqs_pins[] = { BOOT_15 }; | |
| + | |
| +static const unsigned int uart_tx_a_pins[] = { GPIOX_12 }; | |
| +static const unsigned int uart_rx_a_pins[] = { GPIOX_13 }; | |
| +static const unsigned int uart_cts_a_pins[] = { GPIOX_14 }; | |
| +static const unsigned int uart_rts_a_pins[] = { GPIOX_15 }; | |
| + | |
| +static const unsigned int uart_tx_b_pins[] = { GPIODV_24 }; | |
| +static const unsigned int uart_rx_b_pins[] = { GPIODV_25 }; | |
| +static const unsigned int uart_cts_b_pins[] = { GPIODV_26 }; | |
| +static const unsigned int uart_rts_b_pins[] = { GPIODV_27 }; | |
| + | |
| +static const unsigned int uart_tx_c_pins[] = { GPIOY_13 }; | |
| +static const unsigned int uart_rx_c_pins[] = { GPIOY_14 }; | |
| +static const unsigned int uart_cts_c_pins[] = { GPIOY_11 }; | |
| +static const unsigned int uart_rts_c_pins[] = { GPIOY_12 }; | |
| + | |
| +static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 }; | |
| +static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 }; | |
| + | |
| +static const unsigned int i2c_sck_b_pins[] = { GPIODV_27 }; | |
| +static const unsigned int i2c_sda_b_pins[] = { GPIODV_26 }; | |
| + | |
| +static const unsigned int i2c_sck_c_pins[] = { GPIODV_29 }; | |
| +static const unsigned int i2c_sda_c_pins[] = { GPIODV_28 }; | |
| + | |
| +static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int eth_clk_rx_clk_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int eth_rxd2_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int eth_rxd3_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 }; | |
| +static const unsigned int eth_tx_en_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int eth_txd0_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int eth_txd1_pins[] = { GPIOZ_11 }; | |
| +static const unsigned int eth_txd2_pins[] = { GPIOZ_12 }; | |
| +static const unsigned int eth_txd3_pins[] = { GPIOZ_13 }; | |
| + | |
| +static const unsigned int pwm_a_x_pins[] = { GPIOX_6 }; | |
| +static const unsigned int pwm_a_y_pins[] = { GPIOY_16 }; | |
| +static const unsigned int pwm_b_pins[] = { GPIODV_29 }; | |
| +static const unsigned int pwm_d_pins[] = { GPIODV_28 }; | |
| +static const unsigned int pwm_e_pins[] = { GPIOX_19 }; | |
| +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; | |
| +static const unsigned int pwm_f_y_pins[] = { GPIOY_15 }; | |
| + | |
| +static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 }; | |
| +static const unsigned int hdmi_sda_pins[] = { GPIOH_1 }; | |
| +static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; | |
| + | |
| +static const unsigned int tsin_a_d_valid_pins[] = { GPIOY_0 }; | |
| +static const unsigned int tsin_a_sop_pins[] = { GPIOY_1 }; | |
| +static const unsigned int tsin_a_clk_pins[] = { GPIOY_2 }; | |
| +static const unsigned int tsin_a_d0_pins[] = { GPIOY_3 }; | |
| +static const unsigned int tsin_a_dp_pins[] = { | |
| + GPIOY_4, GPIOY_5, GPIOY_6, GPIOY_7, GPIOY_8, GPIOY_9, GPIOY_10 | |
| +}; | |
| + | |
| +static const unsigned int tsin_a_fail_pins[] = { GPIOY_11 }; | |
| +static const unsigned int i2s_out_ch23_y_pins[] = { GPIOY_8 }; | |
| +static const unsigned int i2s_out_ch45_y_pins[] = { GPIOY_9 }; | |
| +static const unsigned int i2s_out_ch67_y_pins[] = { GPIOY_10 }; | |
| + | |
| +static const unsigned int tsin_b_d_valid_pins[] = { GPIOX_6 }; | |
| +static const unsigned int tsin_b_sop_pins[] = { GPIOX_7 }; | |
| +static const unsigned int tsin_b_clk_pins[] = { GPIOX_8 }; | |
| +static const unsigned int tsin_b_d0_pins[] = { GPIOX_9 }; | |
| + | |
| +static const unsigned int spdif_out_y_pins[] = { GPIOY_12 }; | |
| + | |
| +static const unsigned int gen_clk_out_pins[] = { GPIOY_15 }; | |
| + | |
| +static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = { | |
| + MESON_PIN(GPIOAO_0), | |
| + MESON_PIN(GPIOAO_1), | |
| + MESON_PIN(GPIOAO_2), | |
| + MESON_PIN(GPIOAO_3), | |
| + MESON_PIN(GPIOAO_4), | |
| + MESON_PIN(GPIOAO_5), | |
| + MESON_PIN(GPIOAO_6), | |
| + MESON_PIN(GPIOAO_7), | |
| + MESON_PIN(GPIOAO_8), | |
| + MESON_PIN(GPIOAO_9), | |
| + MESON_PIN(GPIOAO_10), | |
| + MESON_PIN(GPIOAO_11), | |
| + MESON_PIN(GPIOAO_12), | |
| + MESON_PIN(GPIOAO_13), | |
| + | |
| + MESON_PIN(GPIO_TEST_N), | |
| +}; | |
| + | |
| +static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 }; | |
| +static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 }; | |
| +static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 }; | |
| +static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 }; | |
| +static const unsigned int uart_tx_ao_b_pins[] = { GPIOAO_4 }; | |
| +static const unsigned int uart_rx_ao_b_pins[] = { GPIOAO_5 }; | |
| +static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 }; | |
| +static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 }; | |
| + | |
| +static const unsigned int i2c_sck_ao_pins[] = { GPIOAO_4 }; | |
| +static const unsigned int i2c_sda_ao_pins[] = { GPIOAO_5 }; | |
| +static const unsigned int i2c_slave_sck_ao_pins[] = {GPIOAO_4 }; | |
| +static const unsigned int i2c_slave_sda_ao_pins[] = {GPIOAO_5 }; | |
| + | |
| +static const unsigned int remote_input_ao_pins[] = { GPIOAO_7 }; | |
| + | |
| +static const unsigned int pwm_ao_a_3_pins[] = { GPIOAO_3 }; | |
| +static const unsigned int pwm_ao_a_6_pins[] = { GPIOAO_6 }; | |
| +static const unsigned int pwm_ao_a_12_pins[] = { GPIOAO_12 }; | |
| +static const unsigned int pwm_ao_b_pins[] = { GPIOAO_13 }; | |
| + | |
| +static const unsigned int i2s_am_clk_pins[] = { GPIOAO_8 }; | |
| +static const unsigned int i2s_out_ao_clk_pins[] = { GPIOAO_9 }; | |
| +static const unsigned int i2s_out_lr_clk_pins[] = { GPIOAO_10 }; | |
| +static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 }; | |
| +static const unsigned int i2s_out_ch23_ao_pins[] = { GPIOAO_12 }; | |
| +static const unsigned int i2s_out_ch45_ao_pins[] = { GPIOAO_13 }; | |
| +static const unsigned int i2s_out_ch67_ao_pins[] = { GPIO_TEST_N }; | |
| + | |
| +static const unsigned int spdif_out_ao_6_pins[] = { GPIOAO_6 }; | |
| +static const unsigned int spdif_out_ao_13_pins[] = { GPIOAO_13 }; | |
| + | |
| +static const unsigned int ao_cec_pins[] = { GPIOAO_12 }; | |
| +static const unsigned int ee_cec_pins[] = { GPIOAO_12 }; | |
| + | |
| +static const struct meson_pmx_group meson_gxbb_periphs_groups[] = { | |
| + GPIO_GROUP(GPIOZ_0), | |
| + GPIO_GROUP(GPIOZ_1), | |
| + GPIO_GROUP(GPIOZ_2), | |
| + GPIO_GROUP(GPIOZ_3), | |
| + GPIO_GROUP(GPIOZ_4), | |
| + GPIO_GROUP(GPIOZ_5), | |
| + GPIO_GROUP(GPIOZ_6), | |
| + GPIO_GROUP(GPIOZ_7), | |
| + GPIO_GROUP(GPIOZ_8), | |
| + GPIO_GROUP(GPIOZ_9), | |
| + GPIO_GROUP(GPIOZ_10), | |
| + GPIO_GROUP(GPIOZ_11), | |
| + GPIO_GROUP(GPIOZ_12), | |
| + GPIO_GROUP(GPIOZ_13), | |
| + GPIO_GROUP(GPIOZ_14), | |
| + GPIO_GROUP(GPIOZ_15), | |
| + | |
| + GPIO_GROUP(GPIOH_0), | |
| + GPIO_GROUP(GPIOH_1), | |
| + GPIO_GROUP(GPIOH_2), | |
| + GPIO_GROUP(GPIOH_3), | |
| + | |
| + GPIO_GROUP(BOOT_0), | |
| + GPIO_GROUP(BOOT_1), | |
| + GPIO_GROUP(BOOT_2), | |
| + GPIO_GROUP(BOOT_3), | |
| + GPIO_GROUP(BOOT_4), | |
| + GPIO_GROUP(BOOT_5), | |
| + GPIO_GROUP(BOOT_6), | |
| + GPIO_GROUP(BOOT_7), | |
| + GPIO_GROUP(BOOT_8), | |
| + GPIO_GROUP(BOOT_9), | |
| + GPIO_GROUP(BOOT_10), | |
| + GPIO_GROUP(BOOT_11), | |
| + GPIO_GROUP(BOOT_12), | |
| + GPIO_GROUP(BOOT_13), | |
| + GPIO_GROUP(BOOT_14), | |
| + GPIO_GROUP(BOOT_15), | |
| + GPIO_GROUP(BOOT_16), | |
| + GPIO_GROUP(BOOT_17), | |
| + | |
| + GPIO_GROUP(CARD_0), | |
| + GPIO_GROUP(CARD_1), | |
| + GPIO_GROUP(CARD_2), | |
| + GPIO_GROUP(CARD_3), | |
| + GPIO_GROUP(CARD_4), | |
| + GPIO_GROUP(CARD_5), | |
| + GPIO_GROUP(CARD_6), | |
| + | |
| + GPIO_GROUP(GPIODV_0), | |
| + GPIO_GROUP(GPIODV_1), | |
| + GPIO_GROUP(GPIODV_2), | |
| + GPIO_GROUP(GPIODV_3), | |
| + GPIO_GROUP(GPIODV_4), | |
| + GPIO_GROUP(GPIODV_5), | |
| + GPIO_GROUP(GPIODV_6), | |
| + GPIO_GROUP(GPIODV_7), | |
| + GPIO_GROUP(GPIODV_8), | |
| + GPIO_GROUP(GPIODV_9), | |
| + GPIO_GROUP(GPIODV_10), | |
| + GPIO_GROUP(GPIODV_11), | |
| + GPIO_GROUP(GPIODV_12), | |
| + GPIO_GROUP(GPIODV_13), | |
| + GPIO_GROUP(GPIODV_14), | |
| + GPIO_GROUP(GPIODV_15), | |
| + GPIO_GROUP(GPIODV_16), | |
| + GPIO_GROUP(GPIODV_17), | |
| + GPIO_GROUP(GPIODV_19), | |
| + GPIO_GROUP(GPIODV_20), | |
| + GPIO_GROUP(GPIODV_21), | |
| + GPIO_GROUP(GPIODV_22), | |
| + GPIO_GROUP(GPIODV_23), | |
| + GPIO_GROUP(GPIODV_24), | |
| + GPIO_GROUP(GPIODV_25), | |
| + GPIO_GROUP(GPIODV_26), | |
| + GPIO_GROUP(GPIODV_27), | |
| + GPIO_GROUP(GPIODV_28), | |
| + GPIO_GROUP(GPIODV_29), | |
| + | |
| + GPIO_GROUP(GPIOY_0), | |
| + GPIO_GROUP(GPIOY_1), | |
| + GPIO_GROUP(GPIOY_2), | |
| + GPIO_GROUP(GPIOY_3), | |
| + GPIO_GROUP(GPIOY_4), | |
| + GPIO_GROUP(GPIOY_5), | |
| + GPIO_GROUP(GPIOY_6), | |
| + GPIO_GROUP(GPIOY_7), | |
| + GPIO_GROUP(GPIOY_8), | |
| + GPIO_GROUP(GPIOY_9), | |
| + GPIO_GROUP(GPIOY_10), | |
| + GPIO_GROUP(GPIOY_11), | |
| + GPIO_GROUP(GPIOY_12), | |
| + GPIO_GROUP(GPIOY_13), | |
| + GPIO_GROUP(GPIOY_14), | |
| + GPIO_GROUP(GPIOY_15), | |
| + GPIO_GROUP(GPIOY_16), | |
| + | |
| + GPIO_GROUP(GPIOX_0), | |
| + GPIO_GROUP(GPIOX_1), | |
| + GPIO_GROUP(GPIOX_2), | |
| + GPIO_GROUP(GPIOX_3), | |
| + GPIO_GROUP(GPIOX_4), | |
| + GPIO_GROUP(GPIOX_5), | |
| + GPIO_GROUP(GPIOX_6), | |
| + GPIO_GROUP(GPIOX_7), | |
| + GPIO_GROUP(GPIOX_8), | |
| + GPIO_GROUP(GPIOX_9), | |
| + GPIO_GROUP(GPIOX_10), | |
| + GPIO_GROUP(GPIOX_11), | |
| + GPIO_GROUP(GPIOX_12), | |
| + GPIO_GROUP(GPIOX_13), | |
| + GPIO_GROUP(GPIOX_14), | |
| + GPIO_GROUP(GPIOX_15), | |
| + GPIO_GROUP(GPIOX_16), | |
| + GPIO_GROUP(GPIOX_17), | |
| + GPIO_GROUP(GPIOX_18), | |
| + GPIO_GROUP(GPIOX_19), | |
| + GPIO_GROUP(GPIOX_20), | |
| + GPIO_GROUP(GPIOX_21), | |
| + GPIO_GROUP(GPIOX_22), | |
| + | |
| + GPIO_GROUP(GPIOCLK_0), | |
| + GPIO_GROUP(GPIOCLK_1), | |
| + GPIO_GROUP(GPIOCLK_2), | |
| + GPIO_GROUP(GPIOCLK_3), | |
| + | |
| + GPIO_GROUP(GPIO_TEST_N), | |
| + | |
| + /* Bank X */ | |
| + GROUP(sdio_d0, 8, 5), | |
| + GROUP(sdio_d1, 8, 4), | |
| + GROUP(sdio_d2, 8, 3), | |
| + GROUP(sdio_d3, 8, 2), | |
| + GROUP(sdio_cmd, 8, 1), | |
| + GROUP(sdio_clk, 8, 0), | |
| + GROUP(sdio_irq, 8, 11), | |
| + GROUP(uart_tx_a, 4, 13), | |
| + GROUP(uart_rx_a, 4, 12), | |
| + GROUP(uart_cts_a, 4, 11), | |
| + GROUP(uart_rts_a, 4, 10), | |
| + GROUP(pwm_a_x, 3, 17), | |
| + GROUP(pwm_e, 2, 30), | |
| + GROUP(pwm_f_x, 3, 18), | |
| + GROUP(tsin_b_d_valid, 3, 9), | |
| + GROUP(tsin_b_sop, 3, 8), | |
| + GROUP(tsin_b_clk, 3, 10), | |
| + GROUP(tsin_b_d0, 3, 7), | |
| + | |
| + /* Bank Y */ | |
| + GROUP(uart_cts_c, 1, 17), | |
| + GROUP(uart_rts_c, 1, 16), | |
| + GROUP(uart_tx_c, 1, 19), | |
| + GROUP(uart_rx_c, 1, 18), | |
| + GROUP(tsin_a_fail, 3, 3), | |
| + GROUP(tsin_a_d_valid, 3, 2), | |
| + GROUP(tsin_a_sop, 3, 1), | |
| + GROUP(tsin_a_clk, 3, 0), | |
| + GROUP(tsin_a_d0, 3, 4), | |
| + GROUP(tsin_a_dp, 3, 5), | |
| + GROUP(pwm_a_y, 1, 21), | |
| + GROUP(pwm_f_y, 1, 20), | |
| + GROUP(i2s_out_ch23_y, 1, 5), | |
| + GROUP(i2s_out_ch45_y, 1, 6), | |
| + GROUP(i2s_out_ch67_y, 1, 7), | |
| + GROUP(spdif_out_y, 1, 9), | |
| + GROUP(gen_clk_out, 6, 15), | |
| + | |
| + /* Bank Z */ | |
| + GROUP(eth_mdio, 6, 1), | |
| + GROUP(eth_mdc, 6, 0), | |
| + GROUP(eth_clk_rx_clk, 6, 13), | |
| + GROUP(eth_rx_dv, 6, 12), | |
| + GROUP(eth_rxd0, 6, 11), | |
| + GROUP(eth_rxd1, 6, 10), | |
| + GROUP(eth_rxd2, 6, 9), | |
| + GROUP(eth_rxd3, 6, 8), | |
| + GROUP(eth_rgmii_tx_clk, 6, 7), | |
| + GROUP(eth_tx_en, 6, 6), | |
| + GROUP(eth_txd0, 6, 5), | |
| + GROUP(eth_txd1, 6, 4), | |
| + GROUP(eth_txd2, 6, 3), | |
| + GROUP(eth_txd3, 6, 2), | |
| + GROUP(spi_ss0, 5, 26), | |
| + GROUP(spi_sclk, 5, 27), | |
| + GROUP(spi_miso, 5, 28), | |
| + GROUP(spi_mosi, 5, 29), | |
| + | |
| + /* Bank H */ | |
| + GROUP(hdmi_hpd, 1, 26), | |
| + GROUP(hdmi_sda, 1, 25), | |
| + GROUP(hdmi_scl, 1, 24), | |
| + | |
| + /* Bank DV */ | |
| + GROUP(uart_tx_b, 2, 29), | |
| + GROUP(uart_rx_b, 2, 28), | |
| + GROUP(uart_cts_b, 2, 27), | |
| + GROUP(uart_rts_b, 2, 26), | |
| + GROUP(pwm_b, 3, 21), | |
| + GROUP(pwm_d, 3, 20), | |
| + GROUP(i2c_sck_a, 7, 27), | |
| + GROUP(i2c_sda_a, 7, 26), | |
| + GROUP(i2c_sck_b, 7, 25), | |
| + GROUP(i2c_sda_b, 7, 24), | |
| + GROUP(i2c_sck_c, 7, 23), | |
| + GROUP(i2c_sda_c, 7, 22), | |
| + | |
| + /* Bank BOOT */ | |
| + GROUP(emmc_nand_d07, 4, 30), | |
| + GROUP(emmc_clk, 4, 18), | |
| + GROUP(emmc_cmd, 4, 19), | |
| + GROUP(emmc_ds, 4, 31), | |
| + GROUP(nor_d, 5, 1), | |
| + GROUP(nor_q, 5, 3), | |
| + GROUP(nor_c, 5, 2), | |
| + GROUP(nor_cs, 5, 0), | |
| + GROUP(nand_ce0, 4, 26), | |
| + GROUP(nand_ce1, 4, 27), | |
| + GROUP(nand_rb0, 4, 25), | |
| + GROUP(nand_ale, 4, 24), | |
| + GROUP(nand_cle, 4, 23), | |
| + GROUP(nand_wen_clk, 4, 22), | |
| + GROUP(nand_ren_wr, 4, 21), | |
| + GROUP(nand_dqs, 4, 20), | |
| + | |
| + /* Bank CARD */ | |
| + GROUP(sdcard_d1, 2, 14), | |
| + GROUP(sdcard_d0, 2, 15), | |
| + GROUP(sdcard_d3, 2, 12), | |
| + GROUP(sdcard_d2, 2, 13), | |
| + GROUP(sdcard_cmd, 2, 10), | |
| + GROUP(sdcard_clk, 2, 11), | |
| +}; | |
| + | |
| +static const struct meson_pmx_group meson_gxbb_aobus_groups[] = { | |
| + GPIO_GROUP(GPIOAO_0), | |
| + GPIO_GROUP(GPIOAO_1), | |
| + GPIO_GROUP(GPIOAO_2), | |
| + GPIO_GROUP(GPIOAO_3), | |
| + GPIO_GROUP(GPIOAO_4), | |
| + GPIO_GROUP(GPIOAO_5), | |
| + GPIO_GROUP(GPIOAO_6), | |
| + GPIO_GROUP(GPIOAO_7), | |
| + GPIO_GROUP(GPIOAO_8), | |
| + GPIO_GROUP(GPIOAO_9), | |
| + GPIO_GROUP(GPIOAO_10), | |
| + GPIO_GROUP(GPIOAO_11), | |
| + GPIO_GROUP(GPIOAO_12), | |
| + GPIO_GROUP(GPIOAO_13), | |
| + | |
| + /* bank AO */ | |
| + GROUP(uart_tx_ao_b, 0, 24), | |
| + GROUP(uart_rx_ao_b, 0, 25), | |
| + GROUP(uart_tx_ao_a, 0, 12), | |
| + GROUP(uart_rx_ao_a, 0, 11), | |
| + GROUP(uart_cts_ao_a, 0, 10), | |
| + GROUP(uart_rts_ao_a, 0, 9), | |
| + GROUP(uart_cts_ao_b, 0, 8), | |
| + GROUP(uart_rts_ao_b, 0, 7), | |
| + GROUP(i2c_sck_ao, 0, 6), | |
| + GROUP(i2c_sda_ao, 0, 5), | |
| + GROUP(i2c_slave_sck_ao, 0, 2), | |
| + GROUP(i2c_slave_sda_ao, 0, 1), | |
| + GROUP(remote_input_ao, 0, 0), | |
| + GROUP(pwm_ao_a_3, 0, 22), | |
| + GROUP(pwm_ao_a_6, 0, 18), | |
| + GROUP(pwm_ao_a_12, 0, 17), | |
| + GROUP(pwm_ao_b, 0, 3), | |
| + GROUP(i2s_am_clk, 0, 30), | |
| + GROUP(i2s_out_ao_clk, 0, 29), | |
| + GROUP(i2s_out_lr_clk, 0, 28), | |
| + GROUP(i2s_out_ch01_ao, 0, 27), | |
| + GROUP(i2s_out_ch23_ao, 1, 0), | |
| + GROUP(i2s_out_ch45_ao, 1, 1), | |
| + GROUP(spdif_out_ao_6, 0, 16), | |
| + GROUP(spdif_out_ao_13, 0, 4), | |
| + GROUP(ao_cec, 0, 15), | |
| + GROUP(ee_cec, 0, 14), | |
| + | |
| + /* test n pin */ | |
| + GROUP(i2s_out_ch67_ao, 1, 2), | |
| +}; | |
| + | |
| +static const char * const gpio_periphs_groups[] = { | |
| + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", | |
| + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", | |
| + "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14", | |
| + "GPIOZ_15", | |
| + | |
| + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", | |
| + | |
| + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", | |
| + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", | |
| + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", | |
| + "BOOT_15", "BOOT_16", "BOOT_17", | |
| + | |
| + "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4", | |
| + "CARD_5", "CARD_6", | |
| + | |
| + "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4", | |
| + "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9", | |
| + "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14", | |
| + "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19", | |
| + "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24", | |
| + "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29", | |
| + | |
| + "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4", | |
| + "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9", | |
| + "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14", | |
| + "GPIOY_15", "GPIOY_16", | |
| + | |
| + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", | |
| + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", | |
| + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", | |
| + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", | |
| + "GPIOX_20", "GPIOX_21", "GPIOX_22", | |
| +}; | |
| + | |
| +static const char * const tsin_a_groups[] = { | |
| + "tsin_a_clk", "tsin_a_sop", "tsin_a_d_valid", "tsin_a_d0", | |
| + "tsin_a_dp", "tsin_a_fail", | |
| +}; | |
| + | |
| +static const char * const tsin_b_groups[] = { | |
| + "tsin_b_clk", "tsin_b_sop", "tsin_b_d_valid", "tsin_b_d0", | |
| +}; | |
| + | |
| +static const char * const emmc_groups[] = { | |
| + "emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds", | |
| +}; | |
| + | |
| +static const char * const nor_groups[] = { | |
| + "nor_d", "nor_q", "nor_c", "nor_cs", | |
| +}; | |
| + | |
| +static const char * const spi_groups[] = { | |
| + "spi_mosi", "spi_miso", "spi_ss0", "spi_sclk", | |
| +}; | |
| + | |
| +static const char * const sdcard_groups[] = { | |
| + "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", | |
| + "sdcard_cmd", "sdcard_clk", | |
| +}; | |
| + | |
| +static const char * const sdio_groups[] = { | |
| + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", | |
| + "sdio_cmd", "sdio_clk", "sdio_irq", | |
| +}; | |
| + | |
| +static const char * const nand_groups[] = { | |
| + "emmc_nand_d07", "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", | |
| + "nand_cle", "nand_wen_clk", "nand_ren_wr", "nand_dqs", | |
| +}; | |
| + | |
| +static const char * const uart_a_groups[] = { | |
| + "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a", | |
| +}; | |
| + | |
| +static const char * const uart_b_groups[] = { | |
| + "uart_tx_b", "uart_rx_b", "uart_cts_b", "uart_rts_b", | |
| +}; | |
| + | |
| +static const char * const uart_c_groups[] = { | |
| + "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c", | |
| +}; | |
| + | |
| +static const char * const i2c_a_groups[] = { | |
| + "i2c_sck_a", "i2c_sda_a", | |
| +}; | |
| + | |
| +static const char * const i2c_b_groups[] = { | |
| + "i2c_sck_b", "i2c_sda_b", | |
| +}; | |
| + | |
| +static const char * const i2c_c_groups[] = { | |
| + "i2c_sck_c", "i2c_sda_c", | |
| +}; | |
| + | |
| +static const char * const eth_groups[] = { | |
| + "eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv", | |
| + "eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3", | |
| + "eth_rgmii_tx_clk", "eth_tx_en", | |
| + "eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3", | |
| +}; | |
| + | |
| +static const char * const pwm_a_x_groups[] = { | |
| + "pwm_a_x", | |
| +}; | |
| + | |
| +static const char * const pwm_a_y_groups[] = { | |
| + "pwm_a_y", | |
| +}; | |
| + | |
| +static const char * const pwm_b_groups[] = { | |
| + "pwm_b", | |
| +}; | |
| + | |
| +static const char * const pwm_d_groups[] = { | |
| + "pwm_d", | |
| +}; | |
| + | |
| +static const char * const pwm_e_groups[] = { | |
| + "pwm_e", | |
| +}; | |
| + | |
| +static const char * const pwm_f_x_groups[] = { | |
| + "pwm_f_x", | |
| +}; | |
| + | |
| +static const char * const pwm_f_y_groups[] = { | |
| + "pwm_f_y", | |
| +}; | |
| + | |
| +static const char * const hdmi_hpd_groups[] = { | |
| + "hdmi_hpd", | |
| +}; | |
| + | |
| +static const char * const hdmi_i2c_groups[] = { | |
| + "hdmi_sda", "hdmi_scl", | |
| +}; | |
| + | |
| +static const char * const i2s_out_groups[] = { | |
| + "i2s_out_ch23_y", "i2s_out_ch45_y", "i2s_out_ch67_y", | |
| +}; | |
| + | |
| +static const char * const spdif_out_groups[] = { | |
| + "spdif_out_y", | |
| +}; | |
| + | |
| +static const char * const gen_clk_out_groups[] = { | |
| + "gen_clk_out", | |
| +}; | |
| + | |
| +static const char * const gpio_aobus_groups[] = { | |
| + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", | |
| + "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", | |
| + "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13", | |
| + | |
| + "GPIO_TEST_N", | |
| +}; | |
| + | |
| +static const char * const uart_ao_groups[] = { | |
| + "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a", | |
| +}; | |
| + | |
| +static const char * const uart_ao_b_groups[] = { | |
| + "uart_tx_ao_b", "uart_rx_ao_b", "uart_cts_ao_b", "uart_rts_ao_b", | |
| +}; | |
| + | |
| +static const char * const i2c_ao_groups[] = { | |
| + "i2c_sck_ao", "i2c_sda_ao", | |
| +}; | |
| + | |
| +static const char * const i2c_slave_ao_groups[] = { | |
| + "i2c_slave_sck_ao", "i2c_slave_sda_ao", | |
| +}; | |
| + | |
| +static const char * const remote_input_ao_groups[] = { | |
| + "remote_input_ao", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_a_3_groups[] = { | |
| + "pwm_ao_a_3", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_a_6_groups[] = { | |
| + "pwm_ao_a_6", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_a_12_groups[] = { | |
| + "pwm_ao_a_12", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_b_groups[] = { | |
| + "pwm_ao_b", | |
| +}; | |
| + | |
| +static const char * const i2s_out_ao_groups[] = { | |
| + "i2s_am_clk", "i2s_out_ao_clk", "i2s_out_lr_clk", | |
| + "i2s_out_ch01_ao", "i2s_out_ch23_ao", "i2s_out_ch45_ao", | |
| + "i2s_out_ch67_ao", | |
| +}; | |
| + | |
| +static const char * const spdif_out_ao_groups[] = { | |
| + "spdif_out_ao_6", "spdif_out_ao_13", | |
| +}; | |
| + | |
| +static const char * const cec_ao_groups[] = { | |
| + "ao_cec", "ee_cec", | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson_gxbb_periphs_functions[] = { | |
| + FUNCTION(gpio_periphs), | |
| + FUNCTION(emmc), | |
| + FUNCTION(nor), | |
| + FUNCTION(spi), | |
| + FUNCTION(sdcard), | |
| + FUNCTION(sdio), | |
| + FUNCTION(nand), | |
| + FUNCTION(uart_a), | |
| + FUNCTION(uart_b), | |
| + FUNCTION(uart_c), | |
| + FUNCTION(i2c_a), | |
| + FUNCTION(i2c_b), | |
| + FUNCTION(i2c_c), | |
| + FUNCTION(eth), | |
| + FUNCTION(pwm_a_x), | |
| + FUNCTION(pwm_a_y), | |
| + FUNCTION(pwm_b), | |
| + FUNCTION(pwm_d), | |
| + FUNCTION(pwm_e), | |
| + FUNCTION(pwm_f_x), | |
| + FUNCTION(pwm_f_y), | |
| + FUNCTION(hdmi_hpd), | |
| + FUNCTION(hdmi_i2c), | |
| + FUNCTION(i2s_out), | |
| + FUNCTION(spdif_out), | |
| + FUNCTION(gen_clk_out), | |
| + FUNCTION(tsin_a), | |
| + FUNCTION(tsin_b), | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson_gxbb_aobus_functions[] = { | |
| + FUNCTION(gpio_aobus), | |
| + FUNCTION(uart_ao), | |
| + FUNCTION(uart_ao_b), | |
| + FUNCTION(i2c_ao), | |
| + FUNCTION(i2c_slave_ao), | |
| + FUNCTION(remote_input_ao), | |
| + FUNCTION(pwm_ao_a_3), | |
| + FUNCTION(pwm_ao_a_6), | |
| + FUNCTION(pwm_ao_a_12), | |
| + FUNCTION(pwm_ao_b), | |
| + FUNCTION(i2s_out_ao), | |
| + FUNCTION(spdif_out_ao), | |
| + FUNCTION(cec_ao), | |
| +}; | |
| + | |
| +static const struct meson_bank meson_gxbb_periphs_banks[] = { | |
| + /* name first last irq pullen pull dir out in */ | |
| + BANK("X", GPIOX_0, GPIOX_22, 106, 128, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), | |
| + BANK("Y", GPIOY_0, GPIOY_16, 89, 105, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), | |
| + BANK("DV", GPIODV_0, GPIODV_29, 59, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), | |
| + BANK("H", GPIOH_0, GPIOH_3, 30, 33, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), | |
| + BANK("Z", GPIOZ_0, GPIOZ_15, 14, 29, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), | |
| + BANK("CARD", CARD_0, CARD_6, 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), | |
| + BANK("BOOT", BOOT_0, BOOT_17, 34, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), | |
| + BANK("CLK", GPIOCLK_0, GPIOCLK_3, 129, 132, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), | |
| +}; | |
| + | |
| +static const struct meson_bank meson_gxbb_aobus_banks[] = { | |
| + /* name first last irq pullen pull dir out in */ | |
| + BANK("AO", GPIOAO_0, GPIOAO_13, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0), | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { | |
| + .name = "periphs-banks", | |
| + .pins = meson_gxbb_periphs_pins, | |
| + .groups = meson_gxbb_periphs_groups, | |
| + .funcs = meson_gxbb_periphs_functions, | |
| + .banks = meson_gxbb_periphs_banks, | |
| + .num_pins = ARRAY_SIZE(meson_gxbb_periphs_pins), | |
| + .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups), | |
| + .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions), | |
| + .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks), | |
| + .pmx_ops = &meson8_pmx_ops, | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { | |
| + .name = "aobus-banks", | |
| + .pins = meson_gxbb_aobus_pins, | |
| + .groups = meson_gxbb_aobus_groups, | |
| + .funcs = meson_gxbb_aobus_functions, | |
| + .banks = meson_gxbb_aobus_banks, | |
| + .num_pins = ARRAY_SIZE(meson_gxbb_aobus_pins), | |
| + .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups), | |
| + .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions), | |
| + .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks), | |
| + .pmx_ops = &meson8_pmx_ops, | |
| + .parse_dt = meson8_aobus_parse_dt_extra, | |
| +}; | |
| + | |
| +static const struct of_device_id meson_gxbb_pinctrl_dt_match[] = { | |
| + { | |
| + .compatible = "amlogic,meson-gxbb-periphs-pinctrl", | |
| + .data = &meson_gxbb_periphs_pinctrl_data, | |
| + }, | |
| + { | |
| + .compatible = "amlogic,meson-gxbb-aobus-pinctrl", | |
| + .data = &meson_gxbb_aobus_pinctrl_data, | |
| + }, | |
| + { }, | |
| +}; | |
| +MODULE_DEVICE_TABLE(of, meson_gxbb_pinctrl_dt_match); | |
| + | |
| +static struct platform_driver meson_gxbb_pinctrl_driver = { | |
| + .probe = meson_pinctrl_probe, | |
| + .driver = { | |
| + .name = "meson-gxbb-pinctrl", | |
| + .of_match_table = meson_gxbb_pinctrl_dt_match, | |
| + }, | |
| +}; | |
| +module_platform_driver(meson_gxbb_pinctrl_driver); | |
| +MODULE_DESCRIPTION("Amlogic Meson GXBB pinctrl driver"); | |
| +MODULE_LICENSE("GPL v2"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c | |
| new file mode 100644 | |
| index 0000000000..a75762e4d2 | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c | |
| @@ -0,0 +1,885 @@ | |
| +// SPDX-License-Identifier: GPL-2.0-only | |
| +/* | |
| + * Pin controller and GPIO driver for Amlogic Meson GXL. | |
| + * | |
| + * Copyright (C) 2016 Endless Mobile, Inc. | |
| + * Author: Carlo Caione <carlo@endlessm.com> | |
| + */ | |
| + | |
| +#include <dt-bindings/gpio/meson-gxl-gpio.h> | |
| +#include "pinctrl-meson.h" | |
| +#include "pinctrl-meson8-pmx.h" | |
| + | |
| +static const struct pinctrl_pin_desc meson_gxl_periphs_pins[] = { | |
| + MESON_PIN(GPIOZ_0), | |
| + MESON_PIN(GPIOZ_1), | |
| + MESON_PIN(GPIOZ_2), | |
| + MESON_PIN(GPIOZ_3), | |
| + MESON_PIN(GPIOZ_4), | |
| + MESON_PIN(GPIOZ_5), | |
| + MESON_PIN(GPIOZ_6), | |
| + MESON_PIN(GPIOZ_7), | |
| + MESON_PIN(GPIOZ_8), | |
| + MESON_PIN(GPIOZ_9), | |
| + MESON_PIN(GPIOZ_10), | |
| + MESON_PIN(GPIOZ_11), | |
| + MESON_PIN(GPIOZ_12), | |
| + MESON_PIN(GPIOZ_13), | |
| + MESON_PIN(GPIOZ_14), | |
| + MESON_PIN(GPIOZ_15), | |
| + | |
| + MESON_PIN(GPIOH_0), | |
| + MESON_PIN(GPIOH_1), | |
| + MESON_PIN(GPIOH_2), | |
| + MESON_PIN(GPIOH_3), | |
| + MESON_PIN(GPIOH_4), | |
| + MESON_PIN(GPIOH_5), | |
| + MESON_PIN(GPIOH_6), | |
| + MESON_PIN(GPIOH_7), | |
| + MESON_PIN(GPIOH_8), | |
| + MESON_PIN(GPIOH_9), | |
| + | |
| + MESON_PIN(BOOT_0), | |
| + MESON_PIN(BOOT_1), | |
| + MESON_PIN(BOOT_2), | |
| + MESON_PIN(BOOT_3), | |
| + MESON_PIN(BOOT_4), | |
| + MESON_PIN(BOOT_5), | |
| + MESON_PIN(BOOT_6), | |
| + MESON_PIN(BOOT_7), | |
| + MESON_PIN(BOOT_8), | |
| + MESON_PIN(BOOT_9), | |
| + MESON_PIN(BOOT_10), | |
| + MESON_PIN(BOOT_11), | |
| + MESON_PIN(BOOT_12), | |
| + MESON_PIN(BOOT_13), | |
| + MESON_PIN(BOOT_14), | |
| + MESON_PIN(BOOT_15), | |
| + | |
| + MESON_PIN(CARD_0), | |
| + MESON_PIN(CARD_1), | |
| + MESON_PIN(CARD_2), | |
| + MESON_PIN(CARD_3), | |
| + MESON_PIN(CARD_4), | |
| + MESON_PIN(CARD_5), | |
| + MESON_PIN(CARD_6), | |
| + | |
| + MESON_PIN(GPIODV_0), | |
| + MESON_PIN(GPIODV_1), | |
| + MESON_PIN(GPIODV_2), | |
| + MESON_PIN(GPIODV_3), | |
| + MESON_PIN(GPIODV_4), | |
| + MESON_PIN(GPIODV_5), | |
| + MESON_PIN(GPIODV_6), | |
| + MESON_PIN(GPIODV_7), | |
| + MESON_PIN(GPIODV_8), | |
| + MESON_PIN(GPIODV_9), | |
| + MESON_PIN(GPIODV_10), | |
| + MESON_PIN(GPIODV_11), | |
| + MESON_PIN(GPIODV_12), | |
| + MESON_PIN(GPIODV_13), | |
| + MESON_PIN(GPIODV_14), | |
| + MESON_PIN(GPIODV_15), | |
| + MESON_PIN(GPIODV_16), | |
| + MESON_PIN(GPIODV_17), | |
| + MESON_PIN(GPIODV_18), | |
| + MESON_PIN(GPIODV_19), | |
| + MESON_PIN(GPIODV_20), | |
| + MESON_PIN(GPIODV_21), | |
| + MESON_PIN(GPIODV_22), | |
| + MESON_PIN(GPIODV_23), | |
| + MESON_PIN(GPIODV_24), | |
| + MESON_PIN(GPIODV_25), | |
| + MESON_PIN(GPIODV_26), | |
| + MESON_PIN(GPIODV_27), | |
| + MESON_PIN(GPIODV_28), | |
| + MESON_PIN(GPIODV_29), | |
| + | |
| + MESON_PIN(GPIOX_0), | |
| + MESON_PIN(GPIOX_1), | |
| + MESON_PIN(GPIOX_2), | |
| + MESON_PIN(GPIOX_3), | |
| + MESON_PIN(GPIOX_4), | |
| + MESON_PIN(GPIOX_5), | |
| + MESON_PIN(GPIOX_6), | |
| + MESON_PIN(GPIOX_7), | |
| + MESON_PIN(GPIOX_8), | |
| + MESON_PIN(GPIOX_9), | |
| + MESON_PIN(GPIOX_10), | |
| + MESON_PIN(GPIOX_11), | |
| + MESON_PIN(GPIOX_12), | |
| + MESON_PIN(GPIOX_13), | |
| + MESON_PIN(GPIOX_14), | |
| + MESON_PIN(GPIOX_15), | |
| + MESON_PIN(GPIOX_16), | |
| + MESON_PIN(GPIOX_17), | |
| + MESON_PIN(GPIOX_18), | |
| + | |
| + MESON_PIN(GPIOCLK_0), | |
| + MESON_PIN(GPIOCLK_1), | |
| +}; | |
| + | |
| +static const unsigned int emmc_nand_d07_pins[] = { | |
| + BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7, | |
| +}; | |
| +static const unsigned int emmc_clk_pins[] = { BOOT_8 }; | |
| +static const unsigned int emmc_cmd_pins[] = { BOOT_10 }; | |
| +static const unsigned int emmc_ds_pins[] = { BOOT_15 }; | |
| + | |
| +static const unsigned int nor_d_pins[] = { BOOT_11 }; | |
| +static const unsigned int nor_q_pins[] = { BOOT_12 }; | |
| +static const unsigned int nor_c_pins[] = { BOOT_13 }; | |
| +static const unsigned int nor_cs_pins[] = { BOOT_15 }; | |
| + | |
| +static const unsigned int spi_mosi_pins[] = { GPIOX_8 }; | |
| +static const unsigned int spi_miso_pins[] = { GPIOX_9 }; | |
| +static const unsigned int spi_ss0_pins[] = { GPIOX_10 }; | |
| +static const unsigned int spi_sclk_pins[] = { GPIOX_11 }; | |
| + | |
| +static const unsigned int sdcard_d0_pins[] = { CARD_1 }; | |
| +static const unsigned int sdcard_d1_pins[] = { CARD_0 }; | |
| +static const unsigned int sdcard_d2_pins[] = { CARD_5 }; | |
| +static const unsigned int sdcard_d3_pins[] = { CARD_4 }; | |
| +static const unsigned int sdcard_cmd_pins[] = { CARD_3 }; | |
| +static const unsigned int sdcard_clk_pins[] = { CARD_2 }; | |
| + | |
| +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; | |
| +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; | |
| +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; | |
| +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; | |
| +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; | |
| +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; | |
| +static const unsigned int sdio_irq_pins[] = { GPIOX_7 }; | |
| + | |
| +static const unsigned int nand_ce0_pins[] = { BOOT_8 }; | |
| +static const unsigned int nand_ce1_pins[] = { BOOT_9 }; | |
| +static const unsigned int nand_rb0_pins[] = { BOOT_10 }; | |
| +static const unsigned int nand_ale_pins[] = { BOOT_11 }; | |
| +static const unsigned int nand_cle_pins[] = { BOOT_12 }; | |
| +static const unsigned int nand_wen_clk_pins[] = { BOOT_13 }; | |
| +static const unsigned int nand_ren_wr_pins[] = { BOOT_14 }; | |
| +static const unsigned int nand_dqs_pins[] = { BOOT_15 }; | |
| + | |
| +static const unsigned int uart_tx_a_pins[] = { GPIOX_12 }; | |
| +static const unsigned int uart_rx_a_pins[] = { GPIOX_13 }; | |
| +static const unsigned int uart_cts_a_pins[] = { GPIOX_14 }; | |
| +static const unsigned int uart_rts_a_pins[] = { GPIOX_15 }; | |
| + | |
| +static const unsigned int uart_tx_b_pins[] = { GPIODV_24 }; | |
| +static const unsigned int uart_rx_b_pins[] = { GPIODV_25 }; | |
| +static const unsigned int uart_cts_b_pins[] = { GPIODV_26 }; | |
| +static const unsigned int uart_rts_b_pins[] = { GPIODV_27 }; | |
| + | |
| +static const unsigned int uart_tx_c_pins[] = { GPIOX_8 }; | |
| +static const unsigned int uart_rx_c_pins[] = { GPIOX_9 }; | |
| +static const unsigned int uart_cts_c_pins[] = { GPIOX_10 }; | |
| +static const unsigned int uart_rts_c_pins[] = { GPIOX_11 }; | |
| + | |
| +static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 }; | |
| +static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 }; | |
| + | |
| +static const unsigned int i2c_sck_b_pins[] = { GPIODV_27 }; | |
| +static const unsigned int i2c_sda_b_pins[] = { GPIODV_26 }; | |
| + | |
| +static const unsigned int i2c_sck_c_pins[] = { GPIODV_29 }; | |
| +static const unsigned int i2c_sda_c_pins[] = { GPIODV_28 }; | |
| + | |
| +static const unsigned int i2c_sck_c_dv19_pins[] = { GPIODV_19 }; | |
| +static const unsigned int i2c_sda_c_dv18_pins[] = { GPIODV_18 }; | |
| + | |
| +static const unsigned int i2c_sck_d_pins[] = { GPIOX_11 }; | |
| +static const unsigned int i2c_sda_d_pins[] = { GPIOX_10 }; | |
| + | |
| +static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int eth_clk_rx_clk_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int eth_rxd2_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int eth_rxd3_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 }; | |
| +static const unsigned int eth_tx_en_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int eth_txd0_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int eth_txd1_pins[] = { GPIOZ_11 }; | |
| +static const unsigned int eth_txd2_pins[] = { GPIOZ_12 }; | |
| +static const unsigned int eth_txd3_pins[] = { GPIOZ_13 }; | |
| + | |
| +static const unsigned int pwm_a_pins[] = { GPIOX_6 }; | |
| + | |
| +static const unsigned int pwm_b_pins[] = { GPIODV_29 }; | |
| + | |
| +static const unsigned int pwm_c_pins[] = { GPIOZ_15 }; | |
| + | |
| +static const unsigned int pwm_d_pins[] = { GPIODV_28 }; | |
| + | |
| +static const unsigned int pwm_e_pins[] = { GPIOX_16 }; | |
| + | |
| +static const unsigned int pwm_f_clk_pins[] = { GPIOCLK_1 }; | |
| +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; | |
| + | |
| +static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 }; | |
| +static const unsigned int hdmi_sda_pins[] = { GPIOH_1 }; | |
| +static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; | |
| + | |
| +static const unsigned int i2s_am_clk_pins[] = { GPIOH_6 }; | |
| +static const unsigned int i2s_out_ao_clk_pins[] = { GPIOH_7 }; | |
| +static const unsigned int i2s_out_lr_clk_pins[] = { GPIOH_8 }; | |
| +static const unsigned int i2s_out_ch01_pins[] = { GPIOH_9 }; | |
| +static const unsigned int i2s_out_ch23_z_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int i2s_out_ch45_z_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int i2s_out_ch67_z_pins[] = { GPIOZ_7 }; | |
| + | |
| +static const unsigned int spdif_out_h_pins[] = { GPIOH_4 }; | |
| + | |
| +static const unsigned int eth_link_led_pins[] = { GPIOZ_14 }; | |
| +static const unsigned int eth_act_led_pins[] = { GPIOZ_15 }; | |
| + | |
| +static const unsigned int tsin_a_d0_pins[] = { GPIODV_0 }; | |
| +static const unsigned int tsin_a_clk_pins[] = { GPIODV_8 }; | |
| +static const unsigned int tsin_a_sop_pins[] = { GPIODV_9 }; | |
| +static const unsigned int tsin_a_d_valid_pins[] = { GPIODV_10 }; | |
| +static const unsigned int tsin_a_fail_pins[] = { GPIODV_11 }; | |
| +static const unsigned int tsin_a_dp_pins[] = { | |
| + GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7, | |
| +}; | |
| + | |
| +static const unsigned int tsin_b_clk_pins[] = { GPIOH_6 }; | |
| +static const unsigned int tsin_b_d0_pins[] = { GPIOH_7 }; | |
| +static const unsigned int tsin_b_sop_pins[] = { GPIOH_8 }; | |
| +static const unsigned int tsin_b_d_valid_pins[] = { GPIOH_9 }; | |
| + | |
| +static const unsigned int tsin_b_fail_z4_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int tsin_b_clk_z3_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int tsin_b_d0_z2_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int tsin_b_sop_z1_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int tsin_b_d_valid_z0_pins[] = { GPIOZ_0 }; | |
| + | |
| +static const struct pinctrl_pin_desc meson_gxl_aobus_pins[] = { | |
| + MESON_PIN(GPIOAO_0), | |
| + MESON_PIN(GPIOAO_1), | |
| + MESON_PIN(GPIOAO_2), | |
| + MESON_PIN(GPIOAO_3), | |
| + MESON_PIN(GPIOAO_4), | |
| + MESON_PIN(GPIOAO_5), | |
| + MESON_PIN(GPIOAO_6), | |
| + MESON_PIN(GPIOAO_7), | |
| + MESON_PIN(GPIOAO_8), | |
| + MESON_PIN(GPIOAO_9), | |
| + | |
| + MESON_PIN(GPIO_TEST_N), | |
| +}; | |
| + | |
| +static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 }; | |
| +static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 }; | |
| +static const unsigned int uart_tx_ao_b_0_pins[] = { GPIOAO_0 }; | |
| +static const unsigned int uart_rx_ao_b_1_pins[] = { GPIOAO_1 }; | |
| +static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 }; | |
| +static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 }; | |
| +static const unsigned int uart_tx_ao_b_pins[] = { GPIOAO_4 }; | |
| +static const unsigned int uart_rx_ao_b_pins[] = { GPIOAO_5 }; | |
| +static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 }; | |
| +static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 }; | |
| + | |
| +static const unsigned int i2c_sck_ao_pins[] = {GPIOAO_4 }; | |
| +static const unsigned int i2c_sda_ao_pins[] = {GPIOAO_5 }; | |
| +static const unsigned int i2c_slave_sck_ao_pins[] = {GPIOAO_4 }; | |
| +static const unsigned int i2c_slave_sda_ao_pins[] = {GPIOAO_5 }; | |
| + | |
| +static const unsigned int remote_input_ao_pins[] = {GPIOAO_7 }; | |
| + | |
| +static const unsigned int pwm_ao_a_3_pins[] = { GPIOAO_3 }; | |
| +static const unsigned int pwm_ao_a_8_pins[] = { GPIOAO_8 }; | |
| + | |
| +static const unsigned int pwm_ao_b_pins[] = { GPIOAO_9 }; | |
| +static const unsigned int pwm_ao_b_6_pins[] = { GPIOAO_6 }; | |
| + | |
| +static const unsigned int i2s_out_ch23_ao_pins[] = { GPIOAO_8 }; | |
| +static const unsigned int i2s_out_ch45_ao_pins[] = { GPIOAO_9 }; | |
| +static const unsigned int i2s_out_ch67_ao_pins[] = { GPIO_TEST_N }; | |
| + | |
| +static const unsigned int spdif_out_ao_6_pins[] = { GPIOAO_6 }; | |
| +static const unsigned int spdif_out_ao_9_pins[] = { GPIOAO_9 }; | |
| + | |
| +static const unsigned int ao_cec_pins[] = { GPIOAO_8 }; | |
| +static const unsigned int ee_cec_pins[] = { GPIOAO_8 }; | |
| + | |
| +static const struct meson_pmx_group meson_gxl_periphs_groups[] = { | |
| + GPIO_GROUP(GPIOZ_0), | |
| + GPIO_GROUP(GPIOZ_1), | |
| + GPIO_GROUP(GPIOZ_2), | |
| + GPIO_GROUP(GPIOZ_3), | |
| + GPIO_GROUP(GPIOZ_4), | |
| + GPIO_GROUP(GPIOZ_5), | |
| + GPIO_GROUP(GPIOZ_6), | |
| + GPIO_GROUP(GPIOZ_7), | |
| + GPIO_GROUP(GPIOZ_8), | |
| + GPIO_GROUP(GPIOZ_9), | |
| + GPIO_GROUP(GPIOZ_10), | |
| + GPIO_GROUP(GPIOZ_11), | |
| + GPIO_GROUP(GPIOZ_12), | |
| + GPIO_GROUP(GPIOZ_13), | |
| + GPIO_GROUP(GPIOZ_14), | |
| + GPIO_GROUP(GPIOZ_15), | |
| + | |
| + GPIO_GROUP(GPIOH_0), | |
| + GPIO_GROUP(GPIOH_1), | |
| + GPIO_GROUP(GPIOH_2), | |
| + GPIO_GROUP(GPIOH_3), | |
| + GPIO_GROUP(GPIOH_4), | |
| + GPIO_GROUP(GPIOH_5), | |
| + GPIO_GROUP(GPIOH_6), | |
| + GPIO_GROUP(GPIOH_7), | |
| + GPIO_GROUP(GPIOH_8), | |
| + GPIO_GROUP(GPIOH_9), | |
| + | |
| + GPIO_GROUP(BOOT_0), | |
| + GPIO_GROUP(BOOT_1), | |
| + GPIO_GROUP(BOOT_2), | |
| + GPIO_GROUP(BOOT_3), | |
| + GPIO_GROUP(BOOT_4), | |
| + GPIO_GROUP(BOOT_5), | |
| + GPIO_GROUP(BOOT_6), | |
| + GPIO_GROUP(BOOT_7), | |
| + GPIO_GROUP(BOOT_8), | |
| + GPIO_GROUP(BOOT_9), | |
| + GPIO_GROUP(BOOT_10), | |
| + GPIO_GROUP(BOOT_11), | |
| + GPIO_GROUP(BOOT_12), | |
| + GPIO_GROUP(BOOT_13), | |
| + GPIO_GROUP(BOOT_14), | |
| + GPIO_GROUP(BOOT_15), | |
| + | |
| + GPIO_GROUP(CARD_0), | |
| + GPIO_GROUP(CARD_1), | |
| + GPIO_GROUP(CARD_2), | |
| + GPIO_GROUP(CARD_3), | |
| + GPIO_GROUP(CARD_4), | |
| + GPIO_GROUP(CARD_5), | |
| + GPIO_GROUP(CARD_6), | |
| + | |
| + GPIO_GROUP(GPIODV_0), | |
| + GPIO_GROUP(GPIODV_1), | |
| + GPIO_GROUP(GPIODV_2), | |
| + GPIO_GROUP(GPIODV_3), | |
| + GPIO_GROUP(GPIODV_4), | |
| + GPIO_GROUP(GPIODV_5), | |
| + GPIO_GROUP(GPIODV_6), | |
| + GPIO_GROUP(GPIODV_7), | |
| + GPIO_GROUP(GPIODV_8), | |
| + GPIO_GROUP(GPIODV_9), | |
| + GPIO_GROUP(GPIODV_10), | |
| + GPIO_GROUP(GPIODV_11), | |
| + GPIO_GROUP(GPIODV_12), | |
| + GPIO_GROUP(GPIODV_13), | |
| + GPIO_GROUP(GPIODV_14), | |
| + GPIO_GROUP(GPIODV_15), | |
| + GPIO_GROUP(GPIODV_16), | |
| + GPIO_GROUP(GPIODV_17), | |
| + GPIO_GROUP(GPIODV_19), | |
| + GPIO_GROUP(GPIODV_20), | |
| + GPIO_GROUP(GPIODV_21), | |
| + GPIO_GROUP(GPIODV_22), | |
| + GPIO_GROUP(GPIODV_23), | |
| + GPIO_GROUP(GPIODV_24), | |
| + GPIO_GROUP(GPIODV_25), | |
| + GPIO_GROUP(GPIODV_26), | |
| + GPIO_GROUP(GPIODV_27), | |
| + GPIO_GROUP(GPIODV_28), | |
| + GPIO_GROUP(GPIODV_29), | |
| + | |
| + GPIO_GROUP(GPIOX_0), | |
| + GPIO_GROUP(GPIOX_1), | |
| + GPIO_GROUP(GPIOX_2), | |
| + GPIO_GROUP(GPIOX_3), | |
| + GPIO_GROUP(GPIOX_4), | |
| + GPIO_GROUP(GPIOX_5), | |
| + GPIO_GROUP(GPIOX_6), | |
| + GPIO_GROUP(GPIOX_7), | |
| + GPIO_GROUP(GPIOX_8), | |
| + GPIO_GROUP(GPIOX_9), | |
| + GPIO_GROUP(GPIOX_10), | |
| + GPIO_GROUP(GPIOX_11), | |
| + GPIO_GROUP(GPIOX_12), | |
| + GPIO_GROUP(GPIOX_13), | |
| + GPIO_GROUP(GPIOX_14), | |
| + GPIO_GROUP(GPIOX_15), | |
| + GPIO_GROUP(GPIOX_16), | |
| + GPIO_GROUP(GPIOX_17), | |
| + GPIO_GROUP(GPIOX_18), | |
| + | |
| + GPIO_GROUP(GPIOCLK_0), | |
| + GPIO_GROUP(GPIOCLK_1), | |
| + | |
| + GPIO_GROUP(GPIO_TEST_N), | |
| + | |
| + /* Bank X */ | |
| + GROUP(i2c_sda_d, 5, 5), | |
| + GROUP(i2c_sck_d, 5, 4), | |
| + GROUP(sdio_d0, 5, 31), | |
| + GROUP(sdio_d1, 5, 30), | |
| + GROUP(sdio_d2, 5, 29), | |
| + GROUP(sdio_d3, 5, 28), | |
| + GROUP(sdio_clk, 5, 27), | |
| + GROUP(sdio_cmd, 5, 26), | |
| + GROUP(sdio_irq, 5, 24), | |
| + GROUP(uart_tx_a, 5, 19), | |
| + GROUP(uart_rx_a, 5, 18), | |
| + GROUP(uart_cts_a, 5, 17), | |
| + GROUP(uart_rts_a, 5, 16), | |
| + GROUP(uart_tx_c, 5, 13), | |
| + GROUP(uart_rx_c, 5, 12), | |
| + GROUP(uart_cts_c, 5, 11), | |
| + GROUP(uart_rts_c, 5, 10), | |
| + GROUP(pwm_a, 5, 25), | |
| + GROUP(pwm_e, 5, 15), | |
| + GROUP(pwm_f_x, 5, 14), | |
| + GROUP(spi_mosi, 5, 3), | |
| + GROUP(spi_miso, 5, 2), | |
| + GROUP(spi_ss0, 5, 1), | |
| + GROUP(spi_sclk, 5, 0), | |
| + | |
| + /* Bank Z */ | |
| + GROUP(eth_mdio, 4, 23), | |
| + GROUP(eth_mdc, 4, 22), | |
| + GROUP(eth_clk_rx_clk, 4, 21), | |
| + GROUP(eth_rx_dv, 4, 20), | |
| + GROUP(eth_rxd0, 4, 19), | |
| + GROUP(eth_rxd1, 4, 18), | |
| + GROUP(eth_rxd2, 4, 17), | |
| + GROUP(eth_rxd3, 4, 16), | |
| + GROUP(eth_rgmii_tx_clk, 4, 15), | |
| + GROUP(eth_tx_en, 4, 14), | |
| + GROUP(eth_txd0, 4, 13), | |
| + GROUP(eth_txd1, 4, 12), | |
| + GROUP(eth_txd2, 4, 11), | |
| + GROUP(eth_txd3, 4, 10), | |
| + GROUP(tsin_b_fail_z4, 3, 15), | |
| + GROUP(tsin_b_clk_z3, 3, 16), | |
| + GROUP(tsin_b_d0_z2, 3, 17), | |
| + GROUP(tsin_b_sop_z1, 3, 18), | |
| + GROUP(tsin_b_d_valid_z0, 3, 19), | |
| + GROUP(pwm_c, 3, 20), | |
| + GROUP(i2s_out_ch23_z, 3, 26), | |
| + GROUP(i2s_out_ch45_z, 3, 25), | |
| + GROUP(i2s_out_ch67_z, 3, 24), | |
| + GROUP(eth_link_led, 4, 25), | |
| + GROUP(eth_act_led, 4, 24), | |
| + | |
| + /* Bank H */ | |
| + GROUP(hdmi_hpd, 6, 31), | |
| + GROUP(hdmi_sda, 6, 30), | |
| + GROUP(hdmi_scl, 6, 29), | |
| + GROUP(i2s_am_clk, 6, 26), | |
| + GROUP(i2s_out_ao_clk, 6, 25), | |
| + GROUP(i2s_out_lr_clk, 6, 24), | |
| + GROUP(i2s_out_ch01, 6, 23), | |
| + GROUP(spdif_out_h, 6, 28), | |
| + GROUP(tsin_b_d0, 6, 17), | |
| + GROUP(tsin_b_sop, 6, 18), | |
| + GROUP(tsin_b_d_valid, 6, 19), | |
| + GROUP(tsin_b_clk, 6, 20), | |
| + | |
| + /* Bank DV */ | |
| + GROUP(uart_tx_b, 2, 16), | |
| + GROUP(uart_rx_b, 2, 15), | |
| + GROUP(uart_cts_b, 2, 14), | |
| + GROUP(uart_rts_b, 2, 13), | |
| + GROUP(i2c_sda_c_dv18, 1, 17), | |
| + GROUP(i2c_sck_c_dv19, 1, 16), | |
| + GROUP(i2c_sda_a, 1, 15), | |
| + GROUP(i2c_sck_a, 1, 14), | |
| + GROUP(i2c_sda_b, 1, 13), | |
| + GROUP(i2c_sck_b, 1, 12), | |
| + GROUP(i2c_sda_c, 1, 11), | |
| + GROUP(i2c_sck_c, 1, 10), | |
| + GROUP(pwm_b, 2, 11), | |
| + GROUP(pwm_d, 2, 12), | |
| + GROUP(tsin_a_d0, 2, 4), | |
| + GROUP(tsin_a_dp, 2, 3), | |
| + GROUP(tsin_a_clk, 2, 2), | |
| + GROUP(tsin_a_sop, 2, 1), | |
| + GROUP(tsin_a_d_valid, 2, 0), | |
| + GROUP(tsin_a_fail, 1, 31), | |
| + | |
| + /* Bank BOOT */ | |
| + GROUP(emmc_nand_d07, 7, 31), | |
| + GROUP(emmc_clk, 7, 30), | |
| + GROUP(emmc_cmd, 7, 29), | |
| + GROUP(emmc_ds, 7, 28), | |
| + GROUP(nor_d, 7, 13), | |
| + GROUP(nor_q, 7, 12), | |
| + GROUP(nor_c, 7, 11), | |
| + GROUP(nor_cs, 7, 10), | |
| + GROUP(nand_ce0, 7, 7), | |
| + GROUP(nand_ce1, 7, 6), | |
| + GROUP(nand_rb0, 7, 5), | |
| + GROUP(nand_ale, 7, 4), | |
| + GROUP(nand_cle, 7, 3), | |
| + GROUP(nand_wen_clk, 7, 2), | |
| + GROUP(nand_ren_wr, 7, 1), | |
| + GROUP(nand_dqs, 7, 0), | |
| + | |
| + /* Bank CARD */ | |
| + GROUP(sdcard_d1, 6, 5), | |
| + GROUP(sdcard_d0, 6, 4), | |
| + GROUP(sdcard_d3, 6, 1), | |
| + GROUP(sdcard_d2, 6, 0), | |
| + GROUP(sdcard_cmd, 6, 2), | |
| + GROUP(sdcard_clk, 6, 3), | |
| + | |
| + /* Bank CLK */ | |
| + GROUP(pwm_f_clk, 8, 30), | |
| +}; | |
| + | |
| +static const struct meson_pmx_group meson_gxl_aobus_groups[] = { | |
| + GPIO_GROUP(GPIOAO_0), | |
| + GPIO_GROUP(GPIOAO_1), | |
| + GPIO_GROUP(GPIOAO_2), | |
| + GPIO_GROUP(GPIOAO_3), | |
| + GPIO_GROUP(GPIOAO_4), | |
| + GPIO_GROUP(GPIOAO_5), | |
| + GPIO_GROUP(GPIOAO_6), | |
| + GPIO_GROUP(GPIOAO_7), | |
| + GPIO_GROUP(GPIOAO_8), | |
| + GPIO_GROUP(GPIOAO_9), | |
| + | |
| + /* bank AO */ | |
| + GROUP(uart_tx_ao_b_0, 0, 26), | |
| + GROUP(uart_rx_ao_b_1, 0, 25), | |
| + GROUP(uart_tx_ao_b, 0, 24), | |
| + GROUP(uart_rx_ao_b, 0, 23), | |
| + GROUP(uart_tx_ao_a, 0, 12), | |
| + GROUP(uart_rx_ao_a, 0, 11), | |
| + GROUP(uart_cts_ao_a, 0, 10), | |
| + GROUP(uart_rts_ao_a, 0, 9), | |
| + GROUP(uart_cts_ao_b, 0, 8), | |
| + GROUP(uart_rts_ao_b, 0, 7), | |
| + GROUP(i2c_sck_ao, 0, 6), | |
| + GROUP(i2c_sda_ao, 0, 5), | |
| + GROUP(i2c_slave_sck_ao, 0, 2), | |
| + GROUP(i2c_slave_sda_ao, 0, 1), | |
| + GROUP(remote_input_ao, 0, 0), | |
| + GROUP(pwm_ao_a_3, 0, 22), | |
| + GROUP(pwm_ao_b_6, 0, 18), | |
| + GROUP(pwm_ao_a_8, 0, 17), | |
| + GROUP(pwm_ao_b, 0, 3), | |
| + GROUP(i2s_out_ch23_ao, 1, 0), | |
| + GROUP(i2s_out_ch45_ao, 1, 1), | |
| + GROUP(spdif_out_ao_6, 0, 16), | |
| + GROUP(spdif_out_ao_9, 0, 4), | |
| + GROUP(ao_cec, 0, 15), | |
| + GROUP(ee_cec, 0, 14), | |
| + | |
| + /* test n pin */ | |
| + GROUP(i2s_out_ch67_ao, 1, 2), | |
| +}; | |
| + | |
| +static const char * const gpio_periphs_groups[] = { | |
| + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", | |
| + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", | |
| + "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14", | |
| + "GPIOZ_15", | |
| + | |
| + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", | |
| + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", | |
| + | |
| + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", | |
| + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", | |
| + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", | |
| + "BOOT_15", | |
| + | |
| + "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4", | |
| + "CARD_5", "CARD_6", | |
| + | |
| + "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4", | |
| + "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9", | |
| + "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14", | |
| + "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19", | |
| + "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24", | |
| + "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29", | |
| + | |
| + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", | |
| + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", | |
| + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", | |
| + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", | |
| +}; | |
| + | |
| +static const char * const emmc_groups[] = { | |
| + "emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds", | |
| +}; | |
| + | |
| +static const char * const nor_groups[] = { | |
| + "nor_d", "nor_q", "nor_c", "nor_cs", | |
| +}; | |
| + | |
| +static const char * const spi_groups[] = { | |
| + "spi_mosi", "spi_miso", "spi_ss0", "spi_sclk", | |
| +}; | |
| + | |
| +static const char * const sdcard_groups[] = { | |
| + "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", | |
| + "sdcard_cmd", "sdcard_clk", | |
| +}; | |
| + | |
| +static const char * const sdio_groups[] = { | |
| + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", | |
| + "sdio_cmd", "sdio_clk", "sdio_irq", | |
| +}; | |
| + | |
| +static const char * const nand_groups[] = { | |
| + "emmc_nand_d07", "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", | |
| + "nand_cle", "nand_wen_clk", "nand_ren_wr", "nand_dqs", | |
| +}; | |
| + | |
| +static const char * const uart_a_groups[] = { | |
| + "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a", | |
| +}; | |
| + | |
| +static const char * const uart_b_groups[] = { | |
| + "uart_tx_b", "uart_rx_b", "uart_cts_b", "uart_rts_b", | |
| +}; | |
| + | |
| +static const char * const uart_c_groups[] = { | |
| + "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c", | |
| +}; | |
| + | |
| +static const char * const i2c_a_groups[] = { | |
| + "i2c_sck_a", "i2c_sda_a", | |
| +}; | |
| + | |
| +static const char * const i2c_b_groups[] = { | |
| + "i2c_sck_b", "i2c_sda_b", | |
| +}; | |
| + | |
| +static const char * const i2c_c_groups[] = { | |
| + "i2c_sck_c", "i2c_sda_c", "i2c_sda_c_dv18", "i2c_sck_c_dv19", | |
| +}; | |
| + | |
| +static const char * const i2c_d_groups[] = { | |
| + "i2c_sck_d", "i2c_sda_d", | |
| +}; | |
| + | |
| +static const char * const eth_groups[] = { | |
| + "eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv", | |
| + "eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3", | |
| + "eth_rgmii_tx_clk", "eth_tx_en", | |
| + "eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3", | |
| +}; | |
| + | |
| +static const char * const pwm_a_groups[] = { | |
| + "pwm_a", | |
| +}; | |
| + | |
| +static const char * const pwm_b_groups[] = { | |
| + "pwm_b", | |
| +}; | |
| + | |
| +static const char * const pwm_c_groups[] = { | |
| + "pwm_c", | |
| +}; | |
| + | |
| +static const char * const pwm_d_groups[] = { | |
| + "pwm_d", | |
| +}; | |
| + | |
| +static const char * const pwm_e_groups[] = { | |
| + "pwm_e", | |
| +}; | |
| + | |
| +static const char * const pwm_f_groups[] = { | |
| + "pwm_f_clk", "pwm_f_x", | |
| +}; | |
| + | |
| +static const char * const hdmi_hpd_groups[] = { | |
| + "hdmi_hpd", | |
| +}; | |
| + | |
| +static const char * const hdmi_i2c_groups[] = { | |
| + "hdmi_sda", "hdmi_scl", | |
| +}; | |
| + | |
| +static const char * const i2s_out_groups[] = { | |
| + "i2s_am_clk", "i2s_out_ao_clk", "i2s_out_lr_clk", | |
| + "i2s_out_ch01", "i2s_out_ch23_z", "i2s_out_ch45_z", "i2s_out_ch67_z", | |
| +}; | |
| + | |
| +static const char * const spdif_out_groups[] = { | |
| + "spdif_out_h", | |
| +}; | |
| + | |
| +static const char * const eth_led_groups[] = { | |
| + "eth_link_led", "eth_act_led", | |
| +}; | |
| + | |
| +static const char * const tsin_a_groups[] = { | |
| + "tsin_a_clk", "tsin_a_sop", | |
| + "tsin_a_d_valid", "tsin_a_d0", | |
| + "tsin_a_dp", "tsin_a_fail", | |
| +}; | |
| + | |
| +static const char * const tsin_b_groups[] = { | |
| + "tsin_b_clk", "tsin_b_sop", "tsin_b_d_valid", "tsin_b_d0", | |
| + "tsin_b_clk_z3", "tsin_b_sop_z1", "tsin_b_d_valid_z0", "tsin_b_d0_z2", | |
| + "tsin_b_fail_z4", | |
| +}; | |
| + | |
| +static const char * const gpio_aobus_groups[] = { | |
| + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", | |
| + "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", | |
| + | |
| + "GPIO_TEST_N", | |
| +}; | |
| + | |
| +static const char * const uart_ao_groups[] = { | |
| + "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a", | |
| +}; | |
| + | |
| +static const char * const uart_ao_b_groups[] = { | |
| + "uart_tx_ao_b", "uart_rx_ao_b", "uart_cts_ao_b", "uart_rts_ao_b", | |
| + "uart_tx_ao_b_0", "uart_rx_ao_b_1", | |
| +}; | |
| + | |
| +static const char * const i2c_ao_groups[] = { | |
| + "i2c_sck_ao", "i2c_sda_ao", | |
| +}; | |
| + | |
| +static const char * const i2c_slave_ao_groups[] = { | |
| + "i2c_slave_sck_ao", "i2c_slave_sda_ao", | |
| +}; | |
| + | |
| +static const char * const remote_input_ao_groups[] = { | |
| + "remote_input_ao", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_a_groups[] = { | |
| + "pwm_ao_a_3", "pwm_ao_a_8", | |
| +}; | |
| + | |
| +static const char * const pwm_ao_b_groups[] = { | |
| + "pwm_ao_b", "pwm_ao_b_6", | |
| +}; | |
| + | |
| +static const char * const i2s_out_ao_groups[] = { | |
| + "i2s_out_ch23_ao", "i2s_out_ch45_ao", "i2s_out_ch67_ao", | |
| +}; | |
| + | |
| +static const char * const spdif_out_ao_groups[] = { | |
| + "spdif_out_ao_6", "spdif_out_ao_9", | |
| +}; | |
| + | |
| +static const char * const cec_ao_groups[] = { | |
| + "ao_cec", "ee_cec", | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson_gxl_periphs_functions[] = { | |
| + FUNCTION(gpio_periphs), | |
| + FUNCTION(emmc), | |
| + FUNCTION(nor), | |
| + FUNCTION(spi), | |
| + FUNCTION(sdcard), | |
| + FUNCTION(sdio), | |
| + FUNCTION(nand), | |
| + FUNCTION(uart_a), | |
| + FUNCTION(uart_b), | |
| + FUNCTION(uart_c), | |
| + FUNCTION(i2c_a), | |
| + FUNCTION(i2c_b), | |
| + FUNCTION(i2c_c), | |
| + FUNCTION(i2c_d), | |
| + FUNCTION(eth), | |
| + FUNCTION(pwm_a), | |
| + FUNCTION(pwm_b), | |
| + FUNCTION(pwm_c), | |
| + FUNCTION(pwm_d), | |
| + FUNCTION(pwm_e), | |
| + FUNCTION(pwm_f), | |
| + FUNCTION(hdmi_hpd), | |
| + FUNCTION(hdmi_i2c), | |
| + FUNCTION(i2s_out), | |
| + FUNCTION(spdif_out), | |
| + FUNCTION(eth_led), | |
| + FUNCTION(tsin_a), | |
| + FUNCTION(tsin_b), | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson_gxl_aobus_functions[] = { | |
| + FUNCTION(gpio_aobus), | |
| + FUNCTION(uart_ao), | |
| + FUNCTION(uart_ao_b), | |
| + FUNCTION(i2c_ao), | |
| + FUNCTION(i2c_slave_ao), | |
| + FUNCTION(remote_input_ao), | |
| + FUNCTION(pwm_ao_a), | |
| + FUNCTION(pwm_ao_b), | |
| + FUNCTION(i2s_out_ao), | |
| + FUNCTION(spdif_out_ao), | |
| + FUNCTION(cec_ao), | |
| +}; | |
| + | |
| +static const struct meson_bank meson_gxl_periphs_banks[] = { | |
| + /* name first last irq pullen pull dir out in */ | |
| + BANK("X", GPIOX_0, GPIOX_18, 89, 107, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), | |
| + BANK("DV", GPIODV_0, GPIODV_29, 83, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), | |
| + BANK("H", GPIOH_0, GPIOH_9, 26, 35, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), | |
| + BANK("Z", GPIOZ_0, GPIOZ_15, 10, 25, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), | |
| + BANK("CARD", CARD_0, CARD_6, 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), | |
| + BANK("BOOT", BOOT_0, BOOT_15, 36, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), | |
| + BANK("CLK", GPIOCLK_0, GPIOCLK_1, 108, 109, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), | |
| +}; | |
| + | |
| +static const struct meson_bank meson_gxl_aobus_banks[] = { | |
| + /* name first last irq pullen pull dir out in */ | |
| + BANK("AO", GPIOAO_0, GPIOAO_9, 0, 9, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0), | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { | |
| + .name = "periphs-banks", | |
| + .pins = meson_gxl_periphs_pins, | |
| + .groups = meson_gxl_periphs_groups, | |
| + .funcs = meson_gxl_periphs_functions, | |
| + .banks = meson_gxl_periphs_banks, | |
| + .num_pins = ARRAY_SIZE(meson_gxl_periphs_pins), | |
| + .num_groups = ARRAY_SIZE(meson_gxl_periphs_groups), | |
| + .num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions), | |
| + .num_banks = ARRAY_SIZE(meson_gxl_periphs_banks), | |
| + .pmx_ops = &meson8_pmx_ops, | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { | |
| + .name = "aobus-banks", | |
| + .pins = meson_gxl_aobus_pins, | |
| + .groups = meson_gxl_aobus_groups, | |
| + .funcs = meson_gxl_aobus_functions, | |
| + .banks = meson_gxl_aobus_banks, | |
| + .num_pins = ARRAY_SIZE(meson_gxl_aobus_pins), | |
| + .num_groups = ARRAY_SIZE(meson_gxl_aobus_groups), | |
| + .num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions), | |
| + .num_banks = ARRAY_SIZE(meson_gxl_aobus_banks), | |
| + .pmx_ops = &meson8_pmx_ops, | |
| + .parse_dt = meson8_aobus_parse_dt_extra, | |
| +}; | |
| + | |
| +static const struct of_device_id meson_gxl_pinctrl_dt_match[] = { | |
| + { | |
| + .compatible = "amlogic,meson-gxl-periphs-pinctrl", | |
| + .data = &meson_gxl_periphs_pinctrl_data, | |
| + }, | |
| + { | |
| + .compatible = "amlogic,meson-gxl-aobus-pinctrl", | |
| + .data = &meson_gxl_aobus_pinctrl_data, | |
| + }, | |
| + { }, | |
| +}; | |
| +MODULE_DEVICE_TABLE(of, meson_gxl_pinctrl_dt_match); | |
| + | |
| +static struct platform_driver meson_gxl_pinctrl_driver = { | |
| + .probe = meson_pinctrl_probe, | |
| + .driver = { | |
| + .name = "meson-gxl-pinctrl", | |
| + .of_match_table = meson_gxl_pinctrl_dt_match, | |
| + }, | |
| +}; | |
| +module_platform_driver(meson_gxl_pinctrl_driver); | |
| +MODULE_DESCRIPTION("Amlogic Meson GXL pinctrl driver"); | |
| +MODULE_LICENSE("GPL v2"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-s4.c b/drivers/pinctrl/meson/pinctrl-meson-s4.c | |
| new file mode 100644 | |
| index 0000000000..872948699e | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-s4.c | |
| @@ -0,0 +1,1234 @@ | |
| +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | |
| +/* | |
| + * Pin controller and GPIO driver for Amlogic Meson S4 SoC. | |
| + * | |
| + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. | |
| + * Author: Qianggui Song <qianggui.song@amlogic.com> | |
| + */ | |
| + | |
| +#include <dt-bindings/gpio/meson-s4-gpio.h> | |
| +#include "pinctrl-meson.h" | |
| +#include "pinctrl-meson-axg-pmx.h" | |
| + | |
| +static const struct pinctrl_pin_desc meson_s4_periphs_pins[] = { | |
| + MESON_PIN(GPIOE_0), | |
| + MESON_PIN(GPIOE_1), | |
| + | |
| + MESON_PIN(GPIOB_0), | |
| + MESON_PIN(GPIOB_1), | |
| + MESON_PIN(GPIOB_2), | |
| + MESON_PIN(GPIOB_3), | |
| + MESON_PIN(GPIOB_4), | |
| + MESON_PIN(GPIOB_5), | |
| + MESON_PIN(GPIOB_6), | |
| + MESON_PIN(GPIOB_7), | |
| + MESON_PIN(GPIOB_8), | |
| + MESON_PIN(GPIOB_9), | |
| + MESON_PIN(GPIOB_10), | |
| + MESON_PIN(GPIOB_11), | |
| + MESON_PIN(GPIOB_12), | |
| + MESON_PIN(GPIOB_13), | |
| + | |
| + MESON_PIN(GPIOC_0), | |
| + MESON_PIN(GPIOC_1), | |
| + MESON_PIN(GPIOC_2), | |
| + MESON_PIN(GPIOC_3), | |
| + MESON_PIN(GPIOC_4), | |
| + MESON_PIN(GPIOC_5), | |
| + MESON_PIN(GPIOC_6), | |
| + MESON_PIN(GPIOC_7), | |
| + | |
| + MESON_PIN(GPIOD_0), | |
| + MESON_PIN(GPIOD_1), | |
| + MESON_PIN(GPIOD_2), | |
| + MESON_PIN(GPIOD_3), | |
| + MESON_PIN(GPIOD_4), | |
| + MESON_PIN(GPIOD_5), | |
| + MESON_PIN(GPIOD_6), | |
| + MESON_PIN(GPIOD_7), | |
| + MESON_PIN(GPIOD_8), | |
| + MESON_PIN(GPIOD_9), | |
| + MESON_PIN(GPIOD_10), | |
| + MESON_PIN(GPIOD_11), | |
| + | |
| + MESON_PIN(GPIOH_0), | |
| + MESON_PIN(GPIOH_1), | |
| + MESON_PIN(GPIOH_2), | |
| + MESON_PIN(GPIOH_3), | |
| + MESON_PIN(GPIOH_4), | |
| + MESON_PIN(GPIOH_5), | |
| + MESON_PIN(GPIOH_6), | |
| + MESON_PIN(GPIOH_7), | |
| + MESON_PIN(GPIOH_8), | |
| + MESON_PIN(GPIOH_9), | |
| + MESON_PIN(GPIOH_10), | |
| + MESON_PIN(GPIOH_11), | |
| + | |
| + MESON_PIN(GPIOX_0), | |
| + MESON_PIN(GPIOX_1), | |
| + MESON_PIN(GPIOX_2), | |
| + MESON_PIN(GPIOX_3), | |
| + MESON_PIN(GPIOX_4), | |
| + MESON_PIN(GPIOX_5), | |
| + MESON_PIN(GPIOX_6), | |
| + MESON_PIN(GPIOX_7), | |
| + MESON_PIN(GPIOX_8), | |
| + MESON_PIN(GPIOX_9), | |
| + MESON_PIN(GPIOX_10), | |
| + MESON_PIN(GPIOX_11), | |
| + MESON_PIN(GPIOX_12), | |
| + MESON_PIN(GPIOX_13), | |
| + MESON_PIN(GPIOX_14), | |
| + MESON_PIN(GPIOX_15), | |
| + MESON_PIN(GPIOX_16), | |
| + MESON_PIN(GPIOX_17), | |
| + MESON_PIN(GPIOX_18), | |
| + MESON_PIN(GPIOX_19), | |
| + | |
| + MESON_PIN(GPIOZ_0), | |
| + MESON_PIN(GPIOZ_1), | |
| + MESON_PIN(GPIOZ_2), | |
| + MESON_PIN(GPIOZ_3), | |
| + MESON_PIN(GPIOZ_4), | |
| + MESON_PIN(GPIOZ_5), | |
| + MESON_PIN(GPIOZ_6), | |
| + MESON_PIN(GPIOZ_7), | |
| + MESON_PIN(GPIOZ_8), | |
| + MESON_PIN(GPIOZ_9), | |
| + MESON_PIN(GPIOZ_10), | |
| + MESON_PIN(GPIOZ_11), | |
| + MESON_PIN(GPIOZ_12), | |
| + | |
| + MESON_PIN(GPIO_TEST_N), | |
| +}; | |
| + | |
| +/* BANK E func1 */ | |
| +static const unsigned int i2c0_sda_pins[] = { GPIOE_0 }; | |
| +static const unsigned int i2c0_scl_pins[] = { GPIOE_1 }; | |
| + | |
| +/* BANK E func2 */ | |
| +static const unsigned int uart_b_tx_e_pins[] = { GPIOE_0 }; | |
| +static const unsigned int uart_b_rx_e_pins[] = { GPIOE_1 }; | |
| + | |
| +/* BANK E func3 */ | |
| +static const unsigned int pwm_h_pins[] = { GPIOE_0 }; | |
| +static const unsigned int pwm_j_pins[] = { GPIOE_1 }; | |
| + | |
| +/* BANK B func1 */ | |
| +static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 }; | |
| +static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 }; | |
| +static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 }; | |
| +static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 }; | |
| +static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 }; | |
| +static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 }; | |
| +static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 }; | |
| +static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 }; | |
| +static const unsigned int emmc_clk_pins[] = { GPIOB_8 }; | |
| +static const unsigned int emmc_rst_pins[] = { GPIOB_9 }; | |
| +static const unsigned int emmc_cmd_pins[] = { GPIOB_10 }; | |
| +static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 }; | |
| + | |
| +/* Bank B func2 */ | |
| +static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 }; | |
| +static const unsigned int nand_ale_pins[] = { GPIOB_9 }; | |
| +static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 }; | |
| +static const unsigned int nand_cle_pins[] = { GPIOB_11 }; | |
| +static const unsigned int nand_ce0_pins[] = { GPIOB_12 }; | |
| + | |
| +/* Bank B func3 */ | |
| +static const unsigned int spif_hold_pins[] = { GPIOB_3 }; | |
| +static const unsigned int spif_mo_pins[] = { GPIOB_4 }; | |
| +static const unsigned int spif_mi_pins[] = { GPIOB_5 }; | |
| +static const unsigned int spif_clk_pins[] = { GPIOB_6 }; | |
| +static const unsigned int spif_wp_pins[] = { GPIOB_7 }; | |
| +static const unsigned int spif_cs_pins[] = { GPIOB_13 }; | |
| + | |
| +/* Bank C func1 */ | |
| +static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 }; | |
| +static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 }; | |
| +static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 }; | |
| +static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 }; | |
| +static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 }; | |
| +static const unsigned int sdcard_cd_pins[] = { GPIOC_6 }; | |
| + | |
| +/* Bank C func2 */ | |
| +static const unsigned int jtag_2_tdo_pins[] = { GPIOC_0 }; | |
| +static const unsigned int jtag_2_tdi_pins[] = { GPIOC_1 }; | |
| +static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 }; | |
| +static const unsigned int jtag_2_clk_pins[] = { GPIOC_4 }; | |
| +static const unsigned int jtag_2_tms_pins[] = { GPIOC_5 }; | |
| +static const unsigned int i2c1_sda_c_pins[] = { GPIOC_6 }; | |
| +static const unsigned int i2c1_scl_c_pins[] = { GPIOC_7 }; | |
| + | |
| +/* Bank C func3 */ | |
| +static const unsigned int pdm_din1_c_pins[] = { GPIOC_0 }; | |
| +static const unsigned int pdm_din0_c_pins[] = { GPIOC_1 }; | |
| +static const unsigned int i2c4_sda_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int i2c4_scl_c_pins[] = { GPIOC_3 }; | |
| +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 }; | |
| +static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 }; | |
| +static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 }; | |
| + | |
| +/* Bank C func4 */ | |
| +static const unsigned int tdm_d2_c_pins[] = { GPIOC_0 }; | |
| +static const unsigned int tdm_d3_c_pins[] = { GPIOC_1 }; | |
| +static const unsigned int tdm_fs1_c_pins[] = { GPIOC_2 }; | |
| +static const unsigned int tdm_sclk1_c_pins[] = { GPIOC_3 }; | |
| +static const unsigned int mclk_1_c_pins[] = { GPIOC_4 }; | |
| +static const unsigned int tdm_d4_c_pins[] = { GPIOC_5 }; | |
| +static const unsigned int tdm_d5_c_pins[] = { GPIOC_6 }; | |
| + | |
| +/* Bank D func1 */ | |
| +static const unsigned int uart_b_tx_d_pins[] = { GPIOD_0 }; | |
| +static const unsigned int uart_b_rx_d_pins[] = { GPIOD_1 }; | |
| +static const unsigned int uart_b_cts_d_pins[] = { GPIOD_2 }; | |
| +static const unsigned int uart_b_rts_d_pins[] = { GPIOD_3 }; | |
| +static const unsigned int remote_out_pins[] = { GPIOD_4 }; | |
| +static const unsigned int remote_in_pins[] = { GPIOD_5 }; | |
| +static const unsigned int jtag_1_clk_pins[] = { GPIOD_6 }; | |
| +static const unsigned int jtag_1_tms_pins[] = { GPIOD_7 }; | |
| +static const unsigned int jtag_1_tdi_pins[] = { GPIOD_8 }; | |
| +static const unsigned int jtag_1_tdo_pins[] = { GPIOD_9 }; | |
| +static const unsigned int clk12_24_pins[] = { GPIOD_10 }; | |
| +static const unsigned int pwm_g_hiz_pins[] = { GPIOD_11 }; | |
| + | |
| +/* Bank D func2 */ | |
| +static const unsigned int i2c4_sda_d_pins[] = { GPIOD_2 }; | |
| +static const unsigned int i2c4_scl_d_pins[] = { GPIOD_3 }; | |
| +static const unsigned int mclk_1_d_pins[] = { GPIOD_4 }; | |
| +static const unsigned int tdm_sclk1_d_pins[] = { GPIOD_6 }; | |
| +static const unsigned int tdm_fs1_d_pins[] = { GPIOD_7 }; | |
| +static const unsigned int tdm_d4_d_pins[] = { GPIOD_8 }; | |
| +static const unsigned int tdm_d3_d_pins[] = { GPIOD_9 }; | |
| +static const unsigned int tdm_d2_d_pins[] = { GPIOD_10 }; | |
| +static const unsigned int pwm_g_d_pins[] = { GPIOD_11 }; | |
| + | |
| +/* Bank D func3 */ | |
| +static const unsigned int uart_c_tx_pins[] = { GPIOD_2 }; | |
| +static const unsigned int uart_c_rx_pins[] = { GPIOD_3 }; | |
| +static const unsigned int pwm_b_d_pins[] = { GPIOD_4 }; | |
| +static const unsigned int pwm_a_d_pins[] = { GPIOD_6 }; | |
| +static const unsigned int pwm_c_d_pins[] = { GPIOD_7 }; | |
| +static const unsigned int pwm_d_d_pins[] = { GPIOD_8 }; | |
| +static const unsigned int pwm_i_d_pins[] = { GPIOD_9 }; | |
| + | |
| +/* Bank D func4 */ | |
| +static const unsigned int clk_32k_in_pins[] = { GPIOD_2 }; | |
| +static const unsigned int pwm_b_hiz_pins[] = { GPIOD_4 }; | |
| +static const unsigned int pwm_a_hiz_pins[] = { GPIOD_6 }; | |
| +static const unsigned int pwm_c_hiz_pins[] = { GPIOD_7 }; | |
| +static const unsigned int pdm_dclk_d_pins[] = { GPIOD_8 }; | |
| +static const unsigned int pdm_din0_d_pins[] = { GPIOD_9 }; | |
| +static const unsigned int pdm_din1_d_pins[] = { GPIOD_10 }; | |
| + | |
| +/* Bank D func5 */ | |
| +static const unsigned int mic_mute_en_pins[] = { GPIOD_2 }; | |
| +static const unsigned int mic_mute_key_pins[] = { GPIOD_3 }; | |
| +static const unsigned int i2c1_sda_d_pins[] = { GPIOD_6 }; | |
| +static const unsigned int i2c1_scl_d_pins[] = { GPIOD_7 }; | |
| +static const unsigned int i2c2_sda_d_pins[] = { GPIOD_10 }; | |
| +static const unsigned int i2c2_scl_d_pins[] = { GPIOD_11 }; | |
| + | |
| +/* Bank D func6 */ | |
| +static const unsigned int gen_clk_d_pins[] = { GPIOD_10 }; | |
| +static const unsigned int tsin_b_clk_c_pins[] = { GPIOD_6 }; | |
| +static const unsigned int tsin_b_sop_c_pins[] = { GPIOD_7 }; | |
| +static const unsigned int tsin_b_valid_c_pins[] = { GPIOD_8 }; | |
| +static const unsigned int tsin_b_d0_c_pins[] = { GPIOD_9 }; | |
| + | |
| +/* Bank H func1 */ | |
| +static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 }; | |
| +static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 }; | |
| +static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 }; | |
| +static const unsigned int ao_cec_a_pins[] = { GPIOH_3 }; | |
| +static const unsigned int spdif_out_h_pins[] = { GPIOH_4 }; | |
| +static const unsigned int spdif_in_pins[] = { GPIOH_5 }; | |
| +static const unsigned int i2c1_sda_h_pins[] = { GPIOH_6 }; | |
| +static const unsigned int i2c1_scl_h_pins[] = { GPIOH_7 }; | |
| +static const unsigned int i2c2_sda_h8_pins[] = { GPIOH_8 }; | |
| +static const unsigned int i2c2_scl_h9_pins[] = { GPIOH_9 }; | |
| +static const unsigned int eth_link_led_pins[] = { GPIOH_10 }; | |
| +static const unsigned int eth_act_led_pins[] = { GPIOH_11 }; | |
| + | |
| +/* Bank H func2 */ | |
| +static const unsigned int i2c2_sda_h0_pins[] = { GPIOH_0 }; | |
| +static const unsigned int i2c2_scl_h1_pins[] = { GPIOH_1 }; | |
| +static const unsigned int ao_cec_b_pins[] = { GPIOH_3 }; | |
| +static const unsigned int uart_d_tx_h_pins[] = { GPIOH_4 }; | |
| +static const unsigned int uart_d_rx_h_pins[] = { GPIOH_5 }; | |
| +static const unsigned int uart_d_cts_h_pins[] = { GPIOH_6 }; | |
| +static const unsigned int uart_d_rts_h_pins[] = { GPIOH_7 }; | |
| +static const unsigned int iso7816_clk_h_pins[] = { GPIOH_8 }; | |
| +static const unsigned int iso7816_data_h_pins[] = { GPIOH_9 }; | |
| +static const unsigned int uart_e_tx_h_pins[] = { GPIOH_10 }; | |
| +static const unsigned int uart_e_rx_h_pins[] = { GPIOH_11 }; | |
| + | |
| +/* Bank H func3 */ | |
| +static const unsigned int pwm_d_h_pins[] = { GPIOH_6 }; | |
| +static const unsigned int pwm_i_h_pins[] = { GPIOH_7 }; | |
| +static const unsigned int pdm_dclk_h_pins[] = { GPIOH_8 }; | |
| +static const unsigned int pdm_din0_h_pins[] = { GPIOH_9 }; | |
| +static const unsigned int pdm_din1_h_pins[] = { GPIOH_10 }; | |
| + | |
| +/* Bank H func4 */ | |
| +static const unsigned int mclk_1_h_pins[] = { GPIOH_4 }; | |
| +static const unsigned int tdm_sclk1_h_pins[] = { GPIOH_5 }; | |
| +static const unsigned int tdm_fs1_h_pins[] = { GPIOH_6 }; | |
| +static const unsigned int tdm_d2_h_pins[] = { GPIOH_7 }; | |
| +static const unsigned int tdm_d3_h_pins[] = { GPIOH_8 }; | |
| +static const unsigned int tdm_d4_h_pins[] = { GPIOH_9 }; | |
| + | |
| +/* Bank H func5 */ | |
| +static const unsigned int spi_a_miso_h_pins[] = { GPIOH_4 }; | |
| +static const unsigned int spi_a_mosi_h_pins[] = { GPIOH_5 }; | |
| +static const unsigned int spi_a_clk_h_pins[] = { GPIOH_6 }; | |
| +static const unsigned int spi_a_ss0_h_pins[] = { GPIOH_7 }; | |
| + | |
| +/* Bank H func6 */ | |
| +static const unsigned int gen_clk_h_pins[] = { GPIOH_11 }; | |
| +static const unsigned int tsin_b1_clk_pins[] = { GPIOH_4 }; | |
| +static const unsigned int tsin_b1_sop_pins[] = { GPIOH_5 }; | |
| +static const unsigned int tsin_b1_valid_pins[] = { GPIOH_6 }; | |
| +static const unsigned int tsin_b1_d0_pins[] = { GPIOH_7 }; | |
| + | |
| +/* Bank X func1 */ | |
| +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; | |
| +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; | |
| +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; | |
| +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; | |
| +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; | |
| +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; | |
| +static const unsigned int pwm_a_x_pins[] = { GPIOX_6 }; | |
| +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; | |
| +static const unsigned int tdm_d1_pins[] = { GPIOX_8 }; | |
| +static const unsigned int tdm_d0_pins[] = { GPIOX_9 }; | |
| +static const unsigned int tdm_fs0_pins[] = { GPIOX_10 }; | |
| +static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 }; | |
| +static const unsigned int uart_a_tx_pins[] = { GPIOX_12 }; | |
| +static const unsigned int uart_a_rx_pins[] = { GPIOX_13 }; | |
| +static const unsigned int uart_a_cts_pins[] = { GPIOX_14 }; | |
| +static const unsigned int uart_a_rts_pins[] = { GPIOX_15 }; | |
| +static const unsigned int pwm_e_x_pins[] = { GPIOX_16 }; | |
| +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_17 }; | |
| +static const unsigned int i2c1_scl_x_pins[] = { GPIOX_18 }; | |
| +static const unsigned int pwm_b_x_pins[] = { GPIOX_19 }; | |
| + | |
| +/* Bank X func2 */ | |
| +static const unsigned int pdm_din0_x_pins[] = { GPIOX_8 }; | |
| +static const unsigned int pdm_din1_x_pins[] = { GPIOX_9 }; | |
| +static const unsigned int pdm_dclk_x_pins[] = { GPIOX_11 }; | |
| + | |
| +/* Bank X func3 */ | |
| +static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_8 }; | |
| +static const unsigned int spi_a_miso_x_pins[] = { GPIOX_9 }; | |
| +static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_10 }; | |
| +static const unsigned int spi_a_clk_x_pins[] = { GPIOX_11 }; | |
| + | |
| +/* Bank X func4 */ | |
| +static const unsigned int pwm_c_x_pins[] = { GPIOX_8 }; | |
| +static const unsigned int i2c_slave_scl_pins[] = { GPIOX_10 }; | |
| +static const unsigned int i2c_slave_sda_pins[] = { GPIOX_11 }; | |
| + | |
| +/* Bank X func5 */ | |
| +static const unsigned int i2c3_sda_x_pins[] = { GPIOX_10 }; | |
| +static const unsigned int i2c3_scl_x_pins[] = { GPIOX_11 }; | |
| + | |
| +/* Bank Z func1 */ | |
| +static const unsigned int tdm_fs2_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int tdm_sclk2_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int tdm_d4_z_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int tdm_d5_z_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int tdm_d6_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int tdm_d7_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int mclk_2_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int spdif_out_z_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int dtv_a_if_agc_z10_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int uart_e_tx_z11_pins[] = { GPIOZ_11 }; | |
| +static const unsigned int uart_e_rx_z12_pins[] = { GPIOZ_12 }; | |
| + | |
| +/* Bank Z func2 */ | |
| +static const unsigned int tsin_a_clk_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int tsin_a_sop_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int tsin_a_valid_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int tsin_a_din0_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int dtv_a_if_agc_z6_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int dtv_b_if_agc_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int i2c3_sda_z_pins[] = { GPIOZ_8 }; | |
| +static const unsigned int i2c3_scl_z_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int dtv_a_rf_agc_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int dtv_b_rf_agc_pins[] = { GPIOZ_11 }; | |
| + | |
| +/* Bank Z func3 */ | |
| +static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int uart_e_tx_z8_pins[] = { GPIOZ_8 }; | |
| +static const unsigned int uart_e_rx_z9_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int pdm_din1_z_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int pdm_din0_z_pins[] = { GPIOZ_11 }; | |
| +static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_12 }; | |
| + | |
| +/* Bank Z func4 */ | |
| +static const unsigned int spi_a_miso_z_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int spi_a_mosi_z_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int spi_a_clk_z_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int spi_a_ss0_z_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int spi_a_ss1_z_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int spi_a_ss2_z_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int i2c4_scl_z_pins[] = { GPIOZ_11 }; | |
| +static const unsigned int i2c4_sda_z_pins[] = { GPIOZ_12 }; | |
| + | |
| +/* Bank Z func5 */ | |
| +static const unsigned int uart_d_tx_z_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int uart_d_rx_z_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int uart_d_cts_z_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int uart_d_rts_z_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int pwm_g_z_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int pwm_f_z_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int pwm_e_z_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int tsin_b_clk_z_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int tsin_b_sop_z_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_11 }; | |
| +static const unsigned int tsin_b_d0_z_pins[] = { GPIOZ_12 }; | |
| + | |
| +/* Bank Z func6 */ | |
| +static const unsigned int s2_demod_gpio7_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int s2_demod_gpio6_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int s2_demod_gpio5_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int s2_demod_gpio4_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int s2_demod_gpio3_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int s2_demod_gpio2_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int diseqc_out_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int s2_demod_gpio1_pins[] = { GPIOZ_8 }; | |
| +static const unsigned int s2_demod_gpio0_pins[] = { GPIOZ_12 }; | |
| + | |
| +/* Bank Z func7 */ | |
| +static const unsigned int gen_clk_z9_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int gen_clk_z12_pins[] = { GPIOZ_12 }; | |
| + | |
| +static const struct meson_pmx_group meson_s4_periphs_groups[] = { | |
| + GPIO_GROUP(GPIOE_0), | |
| + GPIO_GROUP(GPIOE_1), | |
| + | |
| + GPIO_GROUP(GPIOB_0), | |
| + GPIO_GROUP(GPIOB_1), | |
| + GPIO_GROUP(GPIOB_2), | |
| + GPIO_GROUP(GPIOB_3), | |
| + GPIO_GROUP(GPIOB_4), | |
| + GPIO_GROUP(GPIOB_5), | |
| + GPIO_GROUP(GPIOB_6), | |
| + GPIO_GROUP(GPIOB_7), | |
| + GPIO_GROUP(GPIOB_8), | |
| + GPIO_GROUP(GPIOB_9), | |
| + GPIO_GROUP(GPIOB_10), | |
| + GPIO_GROUP(GPIOB_11), | |
| + GPIO_GROUP(GPIOB_12), | |
| + GPIO_GROUP(GPIOB_13), | |
| + | |
| + GPIO_GROUP(GPIOC_0), | |
| + GPIO_GROUP(GPIOC_1), | |
| + GPIO_GROUP(GPIOC_2), | |
| + GPIO_GROUP(GPIOC_3), | |
| + GPIO_GROUP(GPIOC_4), | |
| + GPIO_GROUP(GPIOC_5), | |
| + GPIO_GROUP(GPIOC_6), | |
| + GPIO_GROUP(GPIOC_7), | |
| + | |
| + GPIO_GROUP(GPIOD_0), | |
| + GPIO_GROUP(GPIOD_1), | |
| + GPIO_GROUP(GPIOD_2), | |
| + GPIO_GROUP(GPIOD_3), | |
| + GPIO_GROUP(GPIOD_4), | |
| + GPIO_GROUP(GPIOD_5), | |
| + GPIO_GROUP(GPIOD_6), | |
| + GPIO_GROUP(GPIOD_7), | |
| + GPIO_GROUP(GPIOD_8), | |
| + GPIO_GROUP(GPIOD_9), | |
| + GPIO_GROUP(GPIOD_10), | |
| + GPIO_GROUP(GPIOD_11), | |
| + | |
| + GPIO_GROUP(GPIOH_0), | |
| + GPIO_GROUP(GPIOH_1), | |
| + GPIO_GROUP(GPIOH_2), | |
| + GPIO_GROUP(GPIOH_3), | |
| + GPIO_GROUP(GPIOH_4), | |
| + GPIO_GROUP(GPIOH_5), | |
| + GPIO_GROUP(GPIOH_6), | |
| + GPIO_GROUP(GPIOH_7), | |
| + GPIO_GROUP(GPIOH_8), | |
| + GPIO_GROUP(GPIOH_9), | |
| + GPIO_GROUP(GPIOH_10), | |
| + GPIO_GROUP(GPIOH_11), | |
| + | |
| + GPIO_GROUP(GPIOX_0), | |
| + GPIO_GROUP(GPIOX_1), | |
| + GPIO_GROUP(GPIOX_2), | |
| + GPIO_GROUP(GPIOX_3), | |
| + GPIO_GROUP(GPIOX_4), | |
| + GPIO_GROUP(GPIOX_5), | |
| + GPIO_GROUP(GPIOX_6), | |
| + GPIO_GROUP(GPIOX_7), | |
| + GPIO_GROUP(GPIOX_8), | |
| + GPIO_GROUP(GPIOX_9), | |
| + GPIO_GROUP(GPIOX_10), | |
| + GPIO_GROUP(GPIOX_11), | |
| + GPIO_GROUP(GPIOX_12), | |
| + GPIO_GROUP(GPIOX_13), | |
| + GPIO_GROUP(GPIOX_14), | |
| + GPIO_GROUP(GPIOX_15), | |
| + GPIO_GROUP(GPIOX_16), | |
| + GPIO_GROUP(GPIOX_17), | |
| + GPIO_GROUP(GPIOX_18), | |
| + GPIO_GROUP(GPIOX_19), | |
| + | |
| + GPIO_GROUP(GPIOZ_0), | |
| + GPIO_GROUP(GPIOZ_1), | |
| + GPIO_GROUP(GPIOZ_2), | |
| + GPIO_GROUP(GPIOZ_3), | |
| + GPIO_GROUP(GPIOZ_4), | |
| + GPIO_GROUP(GPIOZ_5), | |
| + GPIO_GROUP(GPIOZ_6), | |
| + GPIO_GROUP(GPIOZ_7), | |
| + GPIO_GROUP(GPIOZ_8), | |
| + GPIO_GROUP(GPIOZ_9), | |
| + GPIO_GROUP(GPIOZ_10), | |
| + GPIO_GROUP(GPIOZ_11), | |
| + GPIO_GROUP(GPIOZ_12), | |
| + | |
| + GPIO_GROUP(GPIO_TEST_N), | |
| + | |
| + /* BANK E func1 */ | |
| + GROUP(i2c0_sda, 1), | |
| + GROUP(i2c0_scl, 1), | |
| + | |
| + /* BANK E func2 */ | |
| + GROUP(uart_b_tx_e, 2), | |
| + GROUP(uart_b_rx_e, 2), | |
| + | |
| + /* BANK E func3 */ | |
| + GROUP(pwm_h, 3), | |
| + GROUP(pwm_j, 3), | |
| + | |
| + /* BANK B func1 */ | |
| + GROUP(emmc_nand_d0, 1), | |
| + GROUP(emmc_nand_d1, 1), | |
| + GROUP(emmc_nand_d2, 1), | |
| + GROUP(emmc_nand_d3, 1), | |
| + GROUP(emmc_nand_d4, 1), | |
| + GROUP(emmc_nand_d5, 1), | |
| + GROUP(emmc_nand_d6, 1), | |
| + GROUP(emmc_nand_d7, 1), | |
| + GROUP(emmc_clk, 1), | |
| + GROUP(emmc_rst, 1), | |
| + GROUP(emmc_cmd, 1), | |
| + GROUP(emmc_nand_ds, 1), | |
| + | |
| + /* Bank B func2 */ | |
| + GROUP(nand_wen_clk, 2), | |
| + GROUP(nand_ale, 2), | |
| + GROUP(nand_ren_wr, 2), | |
| + GROUP(nand_cle, 2), | |
| + GROUP(nand_ce0, 2), | |
| + | |
| + /* Bank B func3 */ | |
| + GROUP(spif_hold, 3), | |
| + GROUP(spif_mo, 3), | |
| + GROUP(spif_mi, 3), | |
| + GROUP(spif_clk, 3), | |
| + GROUP(spif_wp, 3), | |
| + GROUP(spif_cs, 3), | |
| + | |
| + /* Bank C func1 */ | |
| + GROUP(sdcard_d0_c, 1), | |
| + GROUP(sdcard_d1_c, 1), | |
| + GROUP(sdcard_d2_c, 1), | |
| + GROUP(sdcard_d3_c, 1), | |
| + GROUP(sdcard_clk_c, 1), | |
| + GROUP(sdcard_cmd_c, 1), | |
| + GROUP(sdcard_cd, 1), | |
| + | |
| + /* Bank C func2 */ | |
| + GROUP(jtag_2_tdo, 2), | |
| + GROUP(jtag_2_tdi, 2), | |
| + GROUP(uart_b_rx_c, 2), | |
| + GROUP(uart_b_tx_c, 2), | |
| + GROUP(jtag_2_clk, 2), | |
| + GROUP(jtag_2_tms, 2), | |
| + GROUP(i2c1_sda_c, 2), | |
| + GROUP(i2c1_scl_c, 2), | |
| + | |
| + /* Bank C func3 */ | |
| + GROUP(pdm_din1_c, 3), | |
| + GROUP(pdm_din0_c, 3), | |
| + GROUP(i2c4_sda_c, 3), | |
| + GROUP(i2c4_scl_c, 3), | |
| + GROUP(pdm_dclk_c, 3), | |
| + GROUP(iso7816_clk_c, 3), | |
| + GROUP(iso7816_data_c, 3), | |
| + | |
| + /* Bank C func4 */ | |
| + GROUP(tdm_d2_c, 4), | |
| + GROUP(tdm_d3_c, 4), | |
| + GROUP(tdm_fs1_c, 4), | |
| + GROUP(tdm_sclk1_c, 4), | |
| + GROUP(mclk_1_c, 4), | |
| + GROUP(tdm_d4_c, 4), | |
| + GROUP(tdm_d5_c, 4), | |
| + | |
| + /* Bank D func1 */ | |
| + GROUP(uart_b_tx_d, 1), | |
| + GROUP(uart_b_rx_d, 1), | |
| + GROUP(uart_b_cts_d, 1), | |
| + GROUP(uart_b_rts_d, 1), | |
| + GROUP(remote_out, 1), | |
| + GROUP(remote_in, 1), | |
| + GROUP(jtag_1_clk, 1), | |
| + GROUP(jtag_1_tms, 1), | |
| + GROUP(jtag_1_tdi, 1), | |
| + GROUP(jtag_1_tdo, 1), | |
| + GROUP(clk12_24, 1), | |
| + GROUP(pwm_g_hiz, 1), | |
| + | |
| + /* Bank D func2 */ | |
| + GROUP(i2c4_sda_d, 2), | |
| + GROUP(i2c4_scl_d, 2), | |
| + GROUP(mclk_1_d, 2), | |
| + GROUP(tdm_sclk1_d, 2), | |
| + GROUP(tdm_fs1_d, 2), | |
| + GROUP(tdm_d4_d, 2), | |
| + GROUP(tdm_d3_d, 2), | |
| + GROUP(tdm_d2_d, 2), | |
| + GROUP(pwm_g_d, 2), | |
| + | |
| + /* Bank D func3 */ | |
| + GROUP(uart_c_tx, 3), | |
| + GROUP(uart_c_rx, 3), | |
| + GROUP(pwm_b_d, 3), | |
| + GROUP(pwm_a_d, 3), | |
| + GROUP(pwm_c_d, 3), | |
| + GROUP(pwm_d_d, 3), | |
| + GROUP(pwm_i_d, 3), | |
| + | |
| + /* Bank D func4 */ | |
| + GROUP(clk_32k_in, 4), | |
| + GROUP(pwm_b_hiz, 4), | |
| + GROUP(pwm_a_hiz, 4), | |
| + GROUP(pwm_c_hiz, 4), | |
| + GROUP(pdm_dclk_d, 4), | |
| + GROUP(pdm_din0_d, 4), | |
| + GROUP(pdm_din1_d, 4), | |
| + | |
| + /* Bank D func5 */ | |
| + GROUP(mic_mute_en, 5), | |
| + GROUP(mic_mute_key, 5), | |
| + GROUP(i2c1_sda_d, 5), | |
| + GROUP(i2c1_scl_d, 5), | |
| + GROUP(i2c2_sda_d, 5), | |
| + GROUP(i2c2_scl_d, 5), | |
| + | |
| + /* Bank D func6 */ | |
| + GROUP(gen_clk_d, 6), | |
| + GROUP(tsin_b_clk_c, 6), | |
| + GROUP(tsin_b_sop_c, 6), | |
| + GROUP(tsin_b_valid_c, 6), | |
| + GROUP(tsin_b_d0_c, 6), | |
| + | |
| + /* Bank H func1 */ | |
| + GROUP(hdmitx_sda, 1), | |
| + GROUP(hdmitx_sck, 1), | |
| + GROUP(hdmitx_hpd_in, 1), | |
| + GROUP(ao_cec_a, 1), | |
| + GROUP(spdif_out_h, 1), | |
| + GROUP(spdif_in, 1), | |
| + GROUP(i2c1_sda_h, 1), | |
| + GROUP(i2c1_scl_h, 1), | |
| + GROUP(i2c2_sda_h8, 1), | |
| + GROUP(i2c2_scl_h9, 1), | |
| + GROUP(eth_link_led, 1), | |
| + GROUP(eth_act_led, 1), | |
| + | |
| + /* Bank H func2 */ | |
| + GROUP(i2c2_sda_h0, 2), | |
| + GROUP(i2c2_scl_h1, 2), | |
| + GROUP(ao_cec_b, 2), | |
| + GROUP(uart_d_tx_h, 2), | |
| + GROUP(uart_d_rx_h, 2), | |
| + GROUP(uart_d_cts_h, 2), | |
| + GROUP(uart_d_rts_h, 2), | |
| + GROUP(iso7816_clk_h, 2), | |
| + GROUP(iso7816_data_h, 2), | |
| + GROUP(uart_e_tx_h, 2), | |
| + GROUP(uart_e_rx_h, 2), | |
| + | |
| + /* Bank H func3 */ | |
| + GROUP(pwm_d_h, 3), | |
| + GROUP(pwm_i_h, 3), | |
| + GROUP(pdm_dclk_h, 3), | |
| + GROUP(pdm_din0_h, 3), | |
| + GROUP(pdm_din1_h, 3), | |
| + | |
| + /* Bank H func4 */ | |
| + GROUP(mclk_1_h, 4), | |
| + GROUP(tdm_sclk1_h, 4), | |
| + GROUP(tdm_fs1_h, 4), | |
| + GROUP(tdm_d2_h, 4), | |
| + GROUP(tdm_d3_h, 4), | |
| + GROUP(tdm_d4_h, 4), | |
| + | |
| + /* Bank H func5 */ | |
| + GROUP(spi_a_miso_h, 5), | |
| + GROUP(spi_a_mosi_h, 5), | |
| + GROUP(spi_a_clk_h, 5), | |
| + GROUP(spi_a_ss0_h, 5), | |
| + | |
| + /* Bank H func6 */ | |
| + GROUP(gen_clk_h, 6), | |
| + GROUP(tsin_b1_clk, 6), | |
| + GROUP(tsin_b1_sop, 6), | |
| + GROUP(tsin_b1_valid, 6), | |
| + GROUP(tsin_b1_d0, 6), | |
| + | |
| + /* Bank X func1 */ | |
| + GROUP(sdio_d0, 1), | |
| + GROUP(sdio_d1, 1), | |
| + GROUP(sdio_d2, 1), | |
| + GROUP(sdio_d3, 1), | |
| + GROUP(sdio_clk, 1), | |
| + GROUP(sdio_cmd, 1), | |
| + GROUP(pwm_a_x, 1), | |
| + GROUP(pwm_f_x, 1), | |
| + GROUP(tdm_d1, 1), | |
| + GROUP(tdm_d0, 1), | |
| + GROUP(tdm_fs0, 1), | |
| + GROUP(tdm_sclk0, 1), | |
| + GROUP(uart_a_tx, 1), | |
| + GROUP(uart_a_rx, 1), | |
| + GROUP(uart_a_cts, 1), | |
| + GROUP(uart_a_rts, 1), | |
| + GROUP(pwm_e_x, 1), | |
| + GROUP(i2c1_sda_x, 1), | |
| + GROUP(i2c1_scl_x, 1), | |
| + GROUP(pwm_b_x, 1), | |
| + | |
| + /* Bank X func2 */ | |
| + GROUP(pdm_din0_x, 2), | |
| + GROUP(pdm_din1_x, 2), | |
| + GROUP(pdm_dclk_x, 2), | |
| + | |
| + /* Bank X func3 */ | |
| + GROUP(spi_a_mosi_x, 3), | |
| + GROUP(spi_a_miso_x, 3), | |
| + GROUP(spi_a_ss0_x, 3), | |
| + GROUP(spi_a_clk_x, 3), | |
| + | |
| + /* Bank X func4 */ | |
| + GROUP(pwm_c_x, 4), | |
| + GROUP(i2c_slave_scl, 4), | |
| + GROUP(i2c_slave_sda, 4), | |
| + | |
| + /* Bank X func5 */ | |
| + GROUP(i2c3_sda_x, 5), | |
| + GROUP(i2c3_scl_x, 5), | |
| + | |
| + /* Bank Z func1 */ | |
| + GROUP(tdm_fs2, 1), | |
| + GROUP(tdm_sclk2, 1), | |
| + GROUP(tdm_d4_z, 1), | |
| + GROUP(tdm_d5_z, 1), | |
| + GROUP(tdm_d6, 1), | |
| + GROUP(tdm_d7, 1), | |
| + GROUP(mclk_2, 1), | |
| + GROUP(spdif_out_z, 1), | |
| + GROUP(dtv_a_if_agc_z10, 1), | |
| + GROUP(uart_e_tx_z11, 1), | |
| + GROUP(uart_e_rx_z12, 1), | |
| + | |
| + /* Bank Z func2 */ | |
| + GROUP(tsin_a_clk, 2), | |
| + GROUP(tsin_a_sop, 2), | |
| + GROUP(tsin_a_valid, 2), | |
| + GROUP(tsin_a_din0, 2), | |
| + GROUP(dtv_a_if_agc_z6, 2), | |
| + GROUP(dtv_b_if_agc, 2), | |
| + GROUP(i2c3_sda_z, 2), | |
| + GROUP(i2c3_scl_z, 2), | |
| + GROUP(dtv_a_rf_agc, 2), | |
| + GROUP(dtv_b_rf_agc, 2), | |
| + | |
| + /* Bank Z func3 */ | |
| + GROUP(sdcard_d0_z, 3), | |
| + GROUP(sdcard_d1_z, 3), | |
| + GROUP(sdcard_d2_z, 3), | |
| + GROUP(sdcard_d3_z, 3), | |
| + GROUP(sdcard_clk_z, 3), | |
| + GROUP(sdcard_cmd_z, 3), | |
| + GROUP(uart_e_tx_z8, 3), | |
| + GROUP(uart_e_rx_z9, 3), | |
| + GROUP(pdm_din1_z, 3), | |
| + GROUP(pdm_din0_z, 3), | |
| + GROUP(pdm_dclk_z, 3), | |
| + | |
| + /* Bank Z func4 */ | |
| + GROUP(spi_a_miso_z, 4), | |
| + GROUP(spi_a_mosi_z, 4), | |
| + GROUP(spi_a_clk_z, 4), | |
| + GROUP(spi_a_ss0_z, 4), | |
| + GROUP(spi_a_ss1_z, 4), | |
| + GROUP(spi_a_ss2_z, 4), | |
| + GROUP(i2c4_scl_z, 4), | |
| + GROUP(i2c4_sda_z, 4), | |
| + | |
| + /* Bank Z func5 */ | |
| + GROUP(uart_d_tx_z, 5), | |
| + GROUP(uart_d_rx_z, 5), | |
| + GROUP(uart_d_cts_z, 5), | |
| + GROUP(uart_d_rts_z, 5), | |
| + GROUP(pwm_g_z, 5), | |
| + GROUP(pwm_f_z, 5), | |
| + GROUP(pwm_e_z, 5), | |
| + GROUP(tsin_b_clk_z, 5), | |
| + GROUP(tsin_b_sop_z, 5), | |
| + GROUP(tsin_b_valid_z, 5), | |
| + GROUP(tsin_b_d0_z, 5), | |
| + | |
| + /* Bank Z func6 */ | |
| + GROUP(s2_demod_gpio7, 6), | |
| + GROUP(s2_demod_gpio6, 6), | |
| + GROUP(s2_demod_gpio5, 6), | |
| + GROUP(s2_demod_gpio4, 6), | |
| + GROUP(s2_demod_gpio3, 6), | |
| + GROUP(s2_demod_gpio2, 6), | |
| + GROUP(diseqc_out, 6), | |
| + GROUP(s2_demod_gpio1, 6), | |
| + GROUP(s2_demod_gpio0, 6), | |
| + | |
| + /* Bank Z func7 */ | |
| + GROUP(gen_clk_z9, 7), | |
| + GROUP(gen_clk_z12, 7), | |
| +}; | |
| + | |
| +static const char * const gpio_periphs_groups[] = { | |
| + "GPIOE_0", "GPIOE_1", | |
| + | |
| + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", "GPIOB_5", | |
| + "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", "GPIOB_10", "GPIOB_11", | |
| + "GPIOB_12", "GPIOB_13", | |
| + | |
| + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", "GPIOC_5", | |
| + "GPIOC_6", "GPIOC_7", | |
| + | |
| + "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", "GPIOD_5", | |
| + "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", "GPIOD_10", "GPIOD_11", | |
| + | |
| + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", "GPIOH_5", | |
| + "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", "GPIOH_10", "GPIOH_11", | |
| + | |
| + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", "GPIOX_5", | |
| + "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11", | |
| + "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17", | |
| + "GPIOX_18", "GPIOX_19", | |
| + | |
| + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", "GPIOZ_5", | |
| + "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", "GPIOZ_10", | |
| + "GPIOZ_11", "GPIOZ_12", | |
| + | |
| + "GPIO_TEST_N", | |
| +}; | |
| + | |
| +static const char * const i2c0_groups[] = { | |
| + "i2c0_sda", "i2c0_scl", | |
| +}; | |
| + | |
| +static const char * const i2c1_groups[] = { | |
| + "i2c1_sda_c", "i2c1_scl_c", | |
| + "i2c1_sda_d", "i2c1_scl_d", | |
| + "i2c1_sda_h", "i2c1_scl_h", | |
| + "i2c1_sda_x", "i2c1_scl_x", | |
| +}; | |
| + | |
| +static const char * const i2c2_groups[] = { | |
| + "i2c2_sda_d", "i2c2_scl_d", | |
| + "i2c2_sda_h8", "i2c2_scl_h9", | |
| + "i2c2_sda_h0", "i2c2_scl_h1l," | |
| +}; | |
| + | |
| +static const char * const i2c3_groups[] = { | |
| + "i2c3_sda_x", "i2c3_scl_x", | |
| + "i2c3_sda_z", "i2c3_scl_z", | |
| +}; | |
| + | |
| +static const char * const i2c4_groups[] = { | |
| + "i2c4_sda_c", "i2c4_scl_c", | |
| + "i2c4_sda_d", "i2c4_scl_d", | |
| + "i2c4_scl_z", "i2c4_sda_z", | |
| +}; | |
| + | |
| +static const char * const uart_a_groups[] = { | |
| + "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts", | |
| +}; | |
| + | |
| +static const char * const uart_b_groups[] = { | |
| + "uart_b_tx_e", "uart_b_rx_e", "uart_b_rx_c", "uart_b_tx_c", | |
| + "uart_b_tx_d", "uart_b_rx_d", "uart_b_cts_d", "uart_b_rts_d", | |
| +}; | |
| + | |
| +static const char * const uart_c_groups[] = { | |
| + "uart_c_tx", "uart_c_rx", | |
| +}; | |
| + | |
| +static const char * const uart_d_groups[] = { | |
| + "uart_d_tx_h", "uart_d_rx_h", "uart_d_cts_h", "uart_d_rts_h", | |
| + "uart_d_tx_z", "uart_d_rx_z", "uart_d_cts_z", "uart_d_rts_z", | |
| +}; | |
| + | |
| +static const char * const uart_e_groups[] = { | |
| + "uart_e_tx_h", "uart_e_rx_h", "uart_e_tx_z11", "uart_e_rx_z12", | |
| + "uart_e_tx_z8", "uart_e_rx_z9", | |
| +}; | |
| + | |
| +static const char * const emmc_groups[] = { | |
| + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", | |
| + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", | |
| + "emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds", | |
| +}; | |
| + | |
| +static const char * const nand_groups[] = { | |
| + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", | |
| + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", | |
| + "nand_wen_clk", "nand_ale", "nand_ren_wr", "nand_cle", "nand_ce0", | |
| +}; | |
| + | |
| +static const char * const spif_groups[] = { | |
| + "spif_hold", "spif_mo", "spif_mi", "spif_clk", "spif_wp", | |
| + "spif_cs", | |
| +}; | |
| + | |
| +static const char * const sdcard_groups[] = { | |
| + "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c", | |
| + "sdcard_clk_c", "sdcard_cmd_c", "sdcard_cd", | |
| + "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z", | |
| + "sdcard_clk_z", "sdcard_cmd_z", | |
| +}; | |
| + | |
| +static const char * const jtag_1_groups[] = { | |
| + "jtag_1_clk", "jtag_1_tms", "jtag_1_tdi", "jtag_1_tdo", | |
| +}; | |
| + | |
| +static const char * const jtag_2_groups[] = { | |
| + "jtag_2_tdo", "jtag_2_tdi", "jtag_2_clk", "jtag_2_tms", | |
| +}; | |
| + | |
| +static const char * const pdm_groups[] = { | |
| + "pdm_din1_c", "pdm_din0_c", "pdm_dclk_c", | |
| + "pdm_dclk_d", "pdm_din0_d", "pdm_din1_d", | |
| + "pdm_dclk_h", "pdm_din0_h", "pdm_din1_h", | |
| + "pdm_din0_x", "pdm_din1_x", "pdm_dclk_x", | |
| + "pdm_din1_z", "pdm_din0_z", "pdm_dclk_z", | |
| +}; | |
| + | |
| +static const char * const iso7816_groups[] = { | |
| + "iso7816_clk_c", "iso7816_data_c", | |
| + "iso7816_clk_h", "iso7816_data_h", | |
| +}; | |
| + | |
| +static const char * const tdm_groups[] = { | |
| + "tdm_d2_c", "tdm_d3_c", "tdm_fs1_c", "tdm_d4_c", "tdm_d5_c", "tdm_sclk1_c", | |
| + "tdm_fs1_d", "tdm_d4_d", "tdm_d3_d", "tdm_d2_d", "tdm_sclk1_d", | |
| + "tdm_sclk1_h", "tdm_fs1_h", "tdm_d2_h", "tdm_d3_h", "tdm_d4_h", | |
| + "tdm_d1", "tdm_d0", "tdm_fs0", "tdm_sclk0", "tdm_fs2", "tdm_sclk2", | |
| + "tdm_d4_z", "tdm_d5_z", "tdm_d6", "tdm_d7", | |
| +}; | |
| + | |
| +static const char * const mclk_1_groups[] = { | |
| + "mclk_1_c", "mclk_1_d", "mclk_1_h", "mclk_2", | |
| +}; | |
| + | |
| +static const char * const mclk_2_groups[] = { | |
| + "mclk_2", | |
| +}; | |
| + | |
| +static const char * const remote_out_groups[] = { | |
| + "remote_out", | |
| +}; | |
| + | |
| +static const char * const remote_in_groups[] = { | |
| + "remote_in", | |
| +}; | |
| + | |
| +static const char * const clk12_24_groups[] = { | |
| + "clk12_24", | |
| +}; | |
| + | |
| +static const char * const clk_32k_in_groups[] = { | |
| + "clk_32k_in", | |
| +}; | |
| + | |
| +static const char * const pwm_a_hiz_groups[] = { | |
| + "pwm_a_hiz", | |
| +}; | |
| + | |
| +static const char * const pwm_b_hiz_groups[] = { | |
| + "pwm_b_hiz", | |
| +}; | |
| + | |
| +static const char * const pwm_c_hiz_groups[] = { | |
| + "pwm_c_hiz", | |
| +}; | |
| + | |
| +static const char * const pwm_g_hiz_groups[] = { | |
| + "pwm_g_hiz", | |
| +}; | |
| + | |
| +static const char * const pwm_a_groups[] = { | |
| + "pwm_a_d", | |
| +}; | |
| + | |
| +static const char * const pwm_b_groups[] = { | |
| + "pwm_b_d", "pwm_b_x", | |
| +}; | |
| + | |
| +static const char * const pwm_c_groups[] = { | |
| + "pwm_c_d", "pwm_c_x", | |
| +}; | |
| + | |
| +static const char * const pwm_d_groups[] = { | |
| + "pwm_d_d", "pwm_d_h", | |
| +}; | |
| + | |
| +static const char * const pwm_e_groups[] = { | |
| + "pwm_e_x", "pwm_e_z", | |
| +}; | |
| + | |
| +static const char * const pwm_f_groups[] = { | |
| + "pwm_f_x", "pwm_f_z", | |
| +}; | |
| + | |
| +static const char * const pwm_g_groups[] = { | |
| + "pwm_g_d", "pwm_g_z", | |
| +}; | |
| + | |
| +static const char * const pwm_h_groups[] = { | |
| + "pwm_h", | |
| +}; | |
| + | |
| +static const char * const pwm_i_groups[] = { | |
| + "pwm_i_d", "pwm_i_h" | |
| +}; | |
| + | |
| +static const char * const pwm_j_groups[] = { | |
| + "pwm_j", | |
| +}; | |
| + | |
| +static const char * const mic_mute_groups[] = { | |
| + "mic_mute_en", "mic_mute_key", | |
| +}; | |
| + | |
| +static const char * const hdmitx_groups[] = { | |
| + "hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in", | |
| +}; | |
| + | |
| +static const char * const ao_cec_a_groups[] = { | |
| + "ao_cec_a", | |
| +}; | |
| + | |
| +static const char * const ao_cec_b_groups[] = { | |
| + "ao_cec_b", | |
| +}; | |
| + | |
| +static const char * const spdif_out_groups[] = { | |
| + "spdif_out_h", "spdif_out_z", | |
| +}; | |
| + | |
| +static const char * const spdif_in_groups[] = { | |
| + "spdif_in", | |
| +}; | |
| + | |
| +static const char * const eth_groups[] = { | |
| + "eth_link_led", "eth_act_led", | |
| +}; | |
| + | |
| +static const char * const spi_a_groups[] = { | |
| + "spi_a_miso_h", "spi_a_mosi_h", "spi_a_clk_h", "spi_a_ss0_h", | |
| + | |
| + "spi_a_mosi_x", "spi_a_miso_x", "spi_a_ss0_x", "spi_a_clk_x", | |
| + | |
| + "spi_a_miso_z", "spi_a_mosi_z", "spi_a_clk_z", "spi_a_ss0_z", | |
| + "spi_a_ss1_z", "spi_a_ss2_z", | |
| +}; | |
| + | |
| +static const char * const gen_clk_groups[] = { | |
| + "gen_clk_h", "gen_clk_z9", "gen_clk_z12", | |
| +}; | |
| + | |
| +static const char * const sdio_groups[] = { | |
| + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd", | |
| +}; | |
| + | |
| +static const char * const i2c_slave_groups[] = { | |
| + "i2c_slave_scl", "i2c_slave_sda", | |
| +}; | |
| + | |
| +static const char * const dtv_groups[] = { | |
| + "dtv_a_if_agc_z10", "dtv_a_if_agc_z6", "dtv_b_if_agc", | |
| + "dtv_a_rf_agc", "dtv_b_rf_agc", | |
| +}; | |
| + | |
| +static const char * const tsin_a_groups[] = { | |
| + "tsin_a_clk", "tsin_a_sop", "tsin_a_valid", "tsin_a_din0", | |
| +}; | |
| + | |
| +static const char * const tsin_b_groups[] = { | |
| + "tsin_b_clk_c", "tsin_b_sop_c", "tsin_b_valid_c", "tsin_b_d0_c", | |
| + "tsin_b_clk_z", "tsin_b_sop_z", "tsin_b_valid_z", "tsin_b_d0_z", | |
| +}; | |
| + | |
| +static const char * const tsin_b1_groups[] = { | |
| + "tsin_b1_clk", "tsin_b1_sop", "tsin_b1_valid", "tsin_b1_d0", | |
| +}; | |
| + | |
| +static const char * const diseqc_out_groups[] = { | |
| + "diseqc_out", | |
| +}; | |
| + | |
| +static const char * const s2_demod_groups[] = { | |
| + "s2_demod_gpio7", "s2_demod_gpio6", "s2_demod_gpio5", "s2_demod_gpio4", | |
| + "s2_demod_gpio3", "s2_demod_gpio2", "s2_demod_gpio1", "s2_demod_gpio0", | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson_s4_periphs_functions[] = { | |
| + FUNCTION(gpio_periphs), | |
| + FUNCTION(i2c0), | |
| + FUNCTION(i2c1), | |
| + FUNCTION(i2c2), | |
| + FUNCTION(i2c3), | |
| + FUNCTION(i2c4), | |
| + FUNCTION(uart_a), | |
| + FUNCTION(uart_b), | |
| + FUNCTION(uart_c), | |
| + FUNCTION(uart_d), | |
| + FUNCTION(uart_e), | |
| + FUNCTION(emmc), | |
| + FUNCTION(nand), | |
| + FUNCTION(spif), | |
| + FUNCTION(sdcard), | |
| + FUNCTION(jtag_1), | |
| + FUNCTION(jtag_2), | |
| + FUNCTION(pdm), | |
| + FUNCTION(iso7816), | |
| + FUNCTION(tdm), | |
| + FUNCTION(mclk_1), | |
| + FUNCTION(mclk_2), | |
| + FUNCTION(remote_out), | |
| + FUNCTION(remote_in), | |
| + FUNCTION(clk12_24), | |
| + FUNCTION(clk_32k_in), | |
| + FUNCTION(pwm_a_hiz), | |
| + FUNCTION(pwm_b_hiz), | |
| + FUNCTION(pwm_c_hiz), | |
| + FUNCTION(pwm_g_hiz), | |
| + FUNCTION(pwm_a), | |
| + FUNCTION(pwm_b), | |
| + FUNCTION(pwm_c), | |
| + FUNCTION(pwm_d), | |
| + FUNCTION(pwm_e), | |
| + FUNCTION(pwm_f), | |
| + FUNCTION(pwm_g), | |
| + FUNCTION(pwm_h), | |
| + FUNCTION(pwm_i), | |
| + FUNCTION(pwm_j), | |
| + FUNCTION(mic_mute), | |
| + FUNCTION(hdmitx), | |
| + FUNCTION(ao_cec_a), | |
| + FUNCTION(ao_cec_b), | |
| + FUNCTION(spdif_out), | |
| + FUNCTION(spdif_in), | |
| + FUNCTION(eth), | |
| + FUNCTION(spi_a), | |
| + FUNCTION(gen_clk), | |
| + FUNCTION(sdio), | |
| + FUNCTION(i2c_slave), | |
| + FUNCTION(dtv), | |
| + FUNCTION(tsin_a), | |
| + FUNCTION(tsin_b), | |
| + FUNCTION(tsin_b1), | |
| + FUNCTION(diseqc_out), | |
| + FUNCTION(s2_demod), | |
| +}; | |
| + | |
| +static const struct meson_bank meson_s4_periphs_banks[] = { | |
| + /* name first last irq pullen pull dir out in */ | |
| + BANK_DS("B", GPIOB_0, GPIOB_13, 0, 13, | |
| + 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0), | |
| + BANK_DS("C", GPIOC_0, GPIOC_7, 14, 21, | |
| + 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0), | |
| + BANK_DS("E", GPIOE_0, GPIOE_1, 22, 23, | |
| + 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0), | |
| + BANK_DS("D", GPIOD_0, GPIOD_11, 24, 35, | |
| + 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0), | |
| + BANK_DS("H", GPIOH_0, GPIOH_11, 36, 47, | |
| + 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0), | |
| + BANK_DS("X", GPIOX_0, GPIOX_19, 48, 67, | |
| + 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0, 0x17, 0), | |
| + BANK_DS("Z", GPIOZ_0, GPIOZ_12, 68, 80, | |
| + 0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0), | |
| + BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, -1, -1, | |
| + 0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0), | |
| +}; | |
| + | |
| +static const struct meson_pmx_bank meson_s4_periphs_pmx_banks[] = { | |
| + /*name first lask reg offset*/ | |
| + BANK_PMX("B", GPIOB_0, GPIOB_13, 0x00, 0), | |
| + BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0), | |
| + BANK_PMX("E", GPIOE_0, GPIOE_1, 0x12, 0), | |
| + BANK_PMX("D", GPIOD_0, GPIOD_11, 0x10, 0), | |
| + BANK_PMX("H", GPIOH_0, GPIOH_11, 0xb, 0), | |
| + BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0), | |
| + BANK_PMX("Z", GPIOZ_0, GPIOZ_12, 0x6, 0), | |
| + BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0) | |
| +}; | |
| + | |
| +static const struct meson_axg_pmx_data meson_s4_periphs_pmx_banks_data = { | |
| + .pmx_banks = meson_s4_periphs_pmx_banks, | |
| + .num_pmx_banks = ARRAY_SIZE(meson_s4_periphs_pmx_banks), | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data meson_s4_periphs_pinctrl_data = { | |
| + .name = "periphs-banks", | |
| + .pins = meson_s4_periphs_pins, | |
| + .groups = meson_s4_periphs_groups, | |
| + .funcs = meson_s4_periphs_functions, | |
| + .banks = meson_s4_periphs_banks, | |
| + .num_pins = ARRAY_SIZE(meson_s4_periphs_pins), | |
| + .num_groups = ARRAY_SIZE(meson_s4_periphs_groups), | |
| + .num_funcs = ARRAY_SIZE(meson_s4_periphs_functions), | |
| + .num_banks = ARRAY_SIZE(meson_s4_periphs_banks), | |
| + .pmx_ops = &meson_axg_pmx_ops, | |
| + .pmx_data = &meson_s4_periphs_pmx_banks_data, | |
| + .parse_dt = &meson_a1_parse_dt_extra, | |
| +}; | |
| + | |
| +static const struct of_device_id meson_s4_pinctrl_dt_match[] = { | |
| + { | |
| + .compatible = "amlogic,meson-s4-periphs-pinctrl", | |
| + .data = &meson_s4_periphs_pinctrl_data, | |
| + }, | |
| + { } | |
| +}; | |
| +MODULE_DEVICE_TABLE(of, meson_s4_pinctrl_dt_match); | |
| + | |
| +static struct platform_driver meson_s4_pinctrl_driver = { | |
| + .probe = meson_pinctrl_probe, | |
| + .driver = { | |
| + .name = "meson-s4-pinctrl", | |
| + .of_match_table = meson_s4_pinctrl_dt_match, | |
| + }, | |
| +}; | |
| +module_platform_driver(meson_s4_pinctrl_driver); | |
| + | |
| +MODULE_DESCRIPTION("Amlogic Meson S4 SoC pinctrl driver"); | |
| +MODULE_LICENSE("Dual BSD/GPL"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c | |
| new file mode 100644 | |
| index 0000000000..4507dc8b55 | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson.c | |
| @@ -0,0 +1,772 @@ | |
| +// SPDX-License-Identifier: GPL-2.0-only | |
| +/* | |
| + * Pin controller and GPIO driver for Amlogic Meson SoCs | |
| + * | |
| + * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | |
| + */ | |
| + | |
| +/* | |
| + * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, | |
| + * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and | |
| + * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a | |
| + * variable number of pins. | |
| + * | |
| + * The AO bank is special because it belongs to the Always-On power | |
| + * domain which can't be powered off; the bank also uses a set of | |
| + * registers different from the other banks. | |
| + * | |
| + * For each pin controller there are 4 different register ranges that | |
| + * control the following properties of the pins: | |
| + * 1) pin muxing | |
| + * 2) pull enable/disable | |
| + * 3) pull up/down | |
| + * 4) GPIO direction, output value, input value | |
| + * | |
| + * In some cases the register ranges for pull enable and pull | |
| + * direction are the same and thus there are only 3 register ranges. | |
| + * | |
| + * Since Meson G12A SoC, the ao register ranges for gpio, pull enable | |
| + * and pull direction are the same, so there are only 2 register ranges. | |
| + * | |
| + * For the pull and GPIO configuration every bank uses a contiguous | |
| + * set of bits in the register sets described above; the same register | |
| + * can be shared by more banks with different offsets. | |
| + * | |
| + * In addition to this there are some registers shared between all | |
| + * banks that control the IRQ functionality. This feature is not | |
| + * supported at the moment by the driver. | |
| + */ | |
| + | |
| +#include <linux/device.h> | |
| +#include <linux/gpio/driver.h> | |
| +#include <linux/init.h> | |
| +#include <linux/io.h> | |
| +#include <linux/of.h> | |
| +#include <linux/of_address.h> | |
| +#include <linux/pinctrl/pinconf-generic.h> | |
| +#include <linux/pinctrl/pinconf.h> | |
| +#include <linux/pinctrl/pinctrl.h> | |
| +#include <linux/pinctrl/pinmux.h> | |
| +#include <linux/platform_device.h> | |
| +#include <linux/property.h> | |
| +#include <linux/regmap.h> | |
| +#include <linux/seq_file.h> | |
| + | |
| +#include "../core.h" | |
| +#include "../pinctrl-utils.h" | |
| +#include "pinctrl-meson.h" | |
| + | |
| +static const unsigned int meson_bit_strides[] = { | |
| + 1, 1, 1, 1, 1, 2, 1 | |
| +}; | |
| + | |
| +/** | |
| + * meson_get_bank() - find the bank containing a given pin | |
| + * | |
| + * @pc: the pinctrl instance | |
| + * @pin: the pin number | |
| + * @bank: the found bank | |
| + * | |
| + * Return: 0 on success, a negative value on error | |
| + */ | |
| +static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, | |
| + const struct meson_bank **bank) | |
| +{ | |
| + int i; | |
| + | |
| + for (i = 0; i < pc->data->num_banks; i++) { | |
| + if (pin >= pc->data->banks[i].first && | |
| + pin <= pc->data->banks[i].last) { | |
| + *bank = &pc->data->banks[i]; | |
| + return 0; | |
| + } | |
| + } | |
| + | |
| + return -EINVAL; | |
| +} | |
| + | |
| +/** | |
| + * meson_calc_reg_and_bit() - calculate register and bit for a pin | |
| + * | |
| + * @bank: the bank containing the pin | |
| + * @pin: the pin number | |
| + * @reg_type: the type of register needed (pull-enable, pull, etc...) | |
| + * @reg: the computed register offset | |
| + * @bit: the computed bit | |
| + */ | |
| +static void meson_calc_reg_and_bit(const struct meson_bank *bank, | |
| + unsigned int pin, | |
| + enum meson_reg_type reg_type, | |
| + unsigned int *reg, unsigned int *bit) | |
| +{ | |
| + const struct meson_reg_desc *desc = &bank->regs[reg_type]; | |
| + | |
| + *bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type]; | |
| + *reg = (desc->reg + (*bit / 32)) * 4; | |
| + *bit &= 0x1f; | |
| +} | |
| + | |
| +static int meson_get_groups_count(struct pinctrl_dev *pcdev) | |
| +{ | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| + | |
| + return pc->data->num_groups; | |
| +} | |
| + | |
| +static const char *meson_get_group_name(struct pinctrl_dev *pcdev, | |
| + unsigned selector) | |
| +{ | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| + | |
| + return pc->data->groups[selector].name; | |
| +} | |
| + | |
| +static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, | |
| + const unsigned **pins, unsigned *num_pins) | |
| +{ | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| + | |
| + *pins = pc->data->groups[selector].pins; | |
| + *num_pins = pc->data->groups[selector].num_pins; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, | |
| + unsigned offset) | |
| +{ | |
| + seq_printf(s, " %s", dev_name(pcdev->dev)); | |
| +} | |
| + | |
| +static const struct pinctrl_ops meson_pctrl_ops = { | |
| + .get_groups_count = meson_get_groups_count, | |
| + .get_group_name = meson_get_group_name, | |
| + .get_group_pins = meson_get_group_pins, | |
| + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, | |
| + .dt_free_map = pinctrl_utils_free_map, | |
| + .pin_dbg_show = meson_pin_dbg_show, | |
| +}; | |
| + | |
| +int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) | |
| +{ | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| + | |
| + return pc->data->num_funcs; | |
| +} | |
| +EXPORT_SYMBOL_GPL(meson_pmx_get_funcs_count); | |
| + | |
| +const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, | |
| + unsigned selector) | |
| +{ | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| + | |
| + return pc->data->funcs[selector].name; | |
| +} | |
| +EXPORT_SYMBOL_GPL(meson_pmx_get_func_name); | |
| + | |
| +int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, | |
| + const char * const **groups, | |
| + unsigned * const num_groups) | |
| +{ | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| + | |
| + *groups = pc->data->funcs[selector].groups; | |
| + *num_groups = pc->data->funcs[selector].num_groups; | |
| + | |
| + return 0; | |
| +} | |
| +EXPORT_SYMBOL_GPL(meson_pmx_get_groups); | |
| + | |
| +static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc, | |
| + unsigned int pin, | |
| + unsigned int reg_type, | |
| + bool arg) | |
| +{ | |
| + const struct meson_bank *bank; | |
| + unsigned int reg, bit; | |
| + int ret; | |
| + | |
| + ret = meson_get_bank(pc, pin, &bank); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); | |
| + return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), | |
| + arg ? BIT(bit) : 0); | |
| +} | |
| + | |
| +static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc, | |
| + unsigned int pin, | |
| + unsigned int reg_type) | |
| +{ | |
| + const struct meson_bank *bank; | |
| + unsigned int reg, bit, val; | |
| + int ret; | |
| + | |
| + ret = meson_get_bank(pc, pin, &bank); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); | |
| + ret = regmap_read(pc->reg_gpio, reg, &val); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + return BIT(bit) & val ? 1 : 0; | |
| +} | |
| + | |
| +static int meson_pinconf_set_output(struct meson_pinctrl *pc, | |
| + unsigned int pin, | |
| + bool out) | |
| +{ | |
| + return meson_pinconf_set_gpio_bit(pc, pin, MESON_REG_DIR, !out); | |
| +} | |
| + | |
| +static int meson_pinconf_get_output(struct meson_pinctrl *pc, | |
| + unsigned int pin) | |
| +{ | |
| + int ret = meson_pinconf_get_gpio_bit(pc, pin, MESON_REG_DIR); | |
| + | |
| + if (ret < 0) | |
| + return ret; | |
| + | |
| + return !ret; | |
| +} | |
| + | |
| +static int meson_pinconf_set_drive(struct meson_pinctrl *pc, | |
| + unsigned int pin, | |
| + bool high) | |
| +{ | |
| + return meson_pinconf_set_gpio_bit(pc, pin, MESON_REG_OUT, high); | |
| +} | |
| + | |
| +static int meson_pinconf_get_drive(struct meson_pinctrl *pc, | |
| + unsigned int pin) | |
| +{ | |
| + return meson_pinconf_get_gpio_bit(pc, pin, MESON_REG_OUT); | |
| +} | |
| + | |
| +static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc, | |
| + unsigned int pin, | |
| + bool high) | |
| +{ | |
| + int ret; | |
| + | |
| + ret = meson_pinconf_set_output(pc, pin, true); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + return meson_pinconf_set_drive(pc, pin, high); | |
| +} | |
| + | |
| +static int meson_pinconf_disable_bias(struct meson_pinctrl *pc, | |
| + unsigned int pin) | |
| +{ | |
| + const struct meson_bank *bank; | |
| + unsigned int reg, bit = 0; | |
| + int ret; | |
| + | |
| + ret = meson_get_bank(pc, pin, &bank); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, ®, &bit); | |
| + ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin, | |
| + bool pull_up) | |
| +{ | |
| + const struct meson_bank *bank; | |
| + unsigned int reg, bit, val = 0; | |
| + int ret; | |
| + | |
| + ret = meson_get_bank(pc, pin, &bank); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + meson_calc_reg_and_bit(bank, pin, MESON_REG_PULL, ®, &bit); | |
| + if (pull_up) | |
| + val = BIT(bit); | |
| + | |
| + ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, ®, &bit); | |
| + ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit)); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc, | |
| + unsigned int pin, | |
| + u16 drive_strength_ua) | |
| +{ | |
| + const struct meson_bank *bank; | |
| + unsigned int reg, bit, ds_val; | |
| + int ret; | |
| + | |
| + if (!pc->reg_ds) { | |
| + dev_err(pc->dev, "drive-strength not supported\n"); | |
| + return -ENOTSUPP; | |
| + } | |
| + | |
| + ret = meson_get_bank(pc, pin, &bank); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + meson_calc_reg_and_bit(bank, pin, MESON_REG_DS, ®, &bit); | |
| + | |
| + if (drive_strength_ua <= 500) { | |
| + ds_val = MESON_PINCONF_DRV_500UA; | |
| + } else if (drive_strength_ua <= 2500) { | |
| + ds_val = MESON_PINCONF_DRV_2500UA; | |
| + } else if (drive_strength_ua <= 3000) { | |
| + ds_val = MESON_PINCONF_DRV_3000UA; | |
| + } else if (drive_strength_ua <= 4000) { | |
| + ds_val = MESON_PINCONF_DRV_4000UA; | |
| + } else { | |
| + dev_warn_once(pc->dev, | |
| + "pin %u: invalid drive-strength : %d , default to 4mA\n", | |
| + pin, drive_strength_ua); | |
| + ds_val = MESON_PINCONF_DRV_4000UA; | |
| + } | |
| + | |
| + ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, | |
| + unsigned long *configs, unsigned num_configs) | |
| +{ | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| + enum pin_config_param param; | |
| + unsigned int arg = 0; | |
| + int i, ret; | |
| + | |
| + for (i = 0; i < num_configs; i++) { | |
| + param = pinconf_to_config_param(configs[i]); | |
| + | |
| + switch (param) { | |
| + case PIN_CONFIG_DRIVE_STRENGTH_UA: | |
| + case PIN_CONFIG_OUTPUT_ENABLE: | |
| + case PIN_CONFIG_LEVEL: | |
| + arg = pinconf_to_config_argument(configs[i]); | |
| + break; | |
| + | |
| + default: | |
| + break; | |
| + } | |
| + | |
| + switch (param) { | |
| + case PIN_CONFIG_BIAS_DISABLE: | |
| + ret = meson_pinconf_disable_bias(pc, pin); | |
| + break; | |
| + case PIN_CONFIG_BIAS_PULL_UP: | |
| + ret = meson_pinconf_enable_bias(pc, pin, true); | |
| + break; | |
| + case PIN_CONFIG_BIAS_PULL_DOWN: | |
| + ret = meson_pinconf_enable_bias(pc, pin, false); | |
| + break; | |
| + case PIN_CONFIG_DRIVE_STRENGTH_UA: | |
| + ret = meson_pinconf_set_drive_strength(pc, pin, arg); | |
| + break; | |
| + case PIN_CONFIG_OUTPUT_ENABLE: | |
| + ret = meson_pinconf_set_output(pc, pin, arg); | |
| + break; | |
| + case PIN_CONFIG_LEVEL: | |
| + ret = meson_pinconf_set_output_drive(pc, pin, arg); | |
| + break; | |
| + default: | |
| + ret = -ENOTSUPP; | |
| + } | |
| + | |
| + if (ret) | |
| + return ret; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) | |
| +{ | |
| + const struct meson_bank *bank; | |
| + unsigned int reg, bit, val; | |
| + int ret, conf; | |
| + | |
| + ret = meson_get_bank(pc, pin, &bank); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, ®, &bit); | |
| + | |
| + ret = regmap_read(pc->reg_pullen, reg, &val); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + if (!(val & BIT(bit))) { | |
| + conf = PIN_CONFIG_BIAS_DISABLE; | |
| + } else { | |
| + meson_calc_reg_and_bit(bank, pin, MESON_REG_PULL, ®, &bit); | |
| + | |
| + ret = regmap_read(pc->reg_pull, reg, &val); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + if (val & BIT(bit)) | |
| + conf = PIN_CONFIG_BIAS_PULL_UP; | |
| + else | |
| + conf = PIN_CONFIG_BIAS_PULL_DOWN; | |
| + } | |
| + | |
| + return conf; | |
| +} | |
| + | |
| +static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc, | |
| + unsigned int pin, | |
| + u16 *drive_strength_ua) | |
| +{ | |
| + const struct meson_bank *bank; | |
| + unsigned int reg, bit; | |
| + unsigned int val; | |
| + int ret; | |
| + | |
| + if (!pc->reg_ds) | |
| + return -ENOTSUPP; | |
| + | |
| + ret = meson_get_bank(pc, pin, &bank); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + meson_calc_reg_and_bit(bank, pin, MESON_REG_DS, ®, &bit); | |
| + | |
| + ret = regmap_read(pc->reg_ds, reg, &val); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + switch ((val >> bit) & 0x3) { | |
| + case MESON_PINCONF_DRV_500UA: | |
| + *drive_strength_ua = 500; | |
| + break; | |
| + case MESON_PINCONF_DRV_2500UA: | |
| + *drive_strength_ua = 2500; | |
| + break; | |
| + case MESON_PINCONF_DRV_3000UA: | |
| + *drive_strength_ua = 3000; | |
| + break; | |
| + case MESON_PINCONF_DRV_4000UA: | |
| + *drive_strength_ua = 4000; | |
| + break; | |
| + default: | |
| + return -EINVAL; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, | |
| + unsigned long *config) | |
| +{ | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| + enum pin_config_param param = pinconf_to_config_param(*config); | |
| + u16 arg; | |
| + int ret; | |
| + | |
| + switch (param) { | |
| + case PIN_CONFIG_BIAS_DISABLE: | |
| + case PIN_CONFIG_BIAS_PULL_DOWN: | |
| + case PIN_CONFIG_BIAS_PULL_UP: | |
| + if (meson_pinconf_get_pull(pc, pin) == param) | |
| + arg = 60000; | |
| + else | |
| + return -EINVAL; | |
| + break; | |
| + case PIN_CONFIG_DRIVE_STRENGTH_UA: | |
| + ret = meson_pinconf_get_drive_strength(pc, pin, &arg); | |
| + if (ret) | |
| + return ret; | |
| + break; | |
| + case PIN_CONFIG_OUTPUT_ENABLE: | |
| + ret = meson_pinconf_get_output(pc, pin); | |
| + if (ret <= 0) | |
| + return -EINVAL; | |
| + arg = 1; | |
| + break; | |
| + case PIN_CONFIG_LEVEL: | |
| + ret = meson_pinconf_get_output(pc, pin); | |
| + if (ret <= 0) | |
| + return -EINVAL; | |
| + | |
| + ret = meson_pinconf_get_drive(pc, pin); | |
| + if (ret < 0) | |
| + return -EINVAL; | |
| + | |
| + arg = ret; | |
| + break; | |
| + | |
| + default: | |
| + return -ENOTSUPP; | |
| + } | |
| + | |
| + *config = pinconf_to_config_packed(param, arg); | |
| + dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, | |
| + unsigned int num_group, | |
| + unsigned long *configs, unsigned num_configs) | |
| +{ | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| + const struct meson_pmx_group *group = &pc->data->groups[num_group]; | |
| + int i; | |
| + | |
| + dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); | |
| + | |
| + for (i = 0; i < group->num_pins; i++) { | |
| + meson_pinconf_set(pcdev, group->pins[i], configs, | |
| + num_configs); | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, | |
| + unsigned int group, unsigned long *config) | |
| +{ | |
| + return -ENOTSUPP; | |
| +} | |
| + | |
| +static const struct pinconf_ops meson_pinconf_ops = { | |
| + .pin_config_get = meson_pinconf_get, | |
| + .pin_config_set = meson_pinconf_set, | |
| + .pin_config_group_get = meson_pinconf_group_get, | |
| + .pin_config_group_set = meson_pinconf_group_set, | |
| + .is_generic = true, | |
| +}; | |
| + | |
| +static int meson_gpio_get_direction(struct gpio_chip *chip, unsigned gpio) | |
| +{ | |
| + struct meson_pinctrl *pc = gpiochip_get_data(chip); | |
| + int ret; | |
| + | |
| + ret = meson_pinconf_get_output(pc, gpio); | |
| + if (ret < 0) | |
| + return ret; | |
| + | |
| + return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; | |
| +} | |
| + | |
| +static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) | |
| +{ | |
| + return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false); | |
| +} | |
| + | |
| +static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, | |
| + int value) | |
| +{ | |
| + return meson_pinconf_set_output_drive(gpiochip_get_data(chip), | |
| + gpio, value); | |
| +} | |
| + | |
| +static int meson_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) | |
| +{ | |
| + return meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value); | |
| +} | |
| + | |
| +static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) | |
| +{ | |
| + struct meson_pinctrl *pc = gpiochip_get_data(chip); | |
| + const struct meson_bank *bank; | |
| + unsigned int reg, bit, val; | |
| + int ret; | |
| + | |
| + ret = meson_get_bank(pc, gpio, &bank); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + meson_calc_reg_and_bit(bank, gpio, MESON_REG_IN, ®, &bit); | |
| + regmap_read(pc->reg_gpio, reg, &val); | |
| + | |
| + return !!(val & BIT(bit)); | |
| +} | |
| + | |
| +static int meson_gpiolib_register(struct meson_pinctrl *pc) | |
| +{ | |
| + int ret; | |
| + | |
| + pc->chip.label = pc->data->name; | |
| + pc->chip.parent = pc->dev; | |
| + pc->chip.fwnode = pc->fwnode; | |
| + pc->chip.request = gpiochip_generic_request; | |
| + pc->chip.free = gpiochip_generic_free; | |
| + pc->chip.set_config = gpiochip_generic_config; | |
| + pc->chip.get_direction = meson_gpio_get_direction; | |
| + pc->chip.direction_input = meson_gpio_direction_input; | |
| + pc->chip.direction_output = meson_gpio_direction_output; | |
| + pc->chip.get = meson_gpio_get; | |
| + pc->chip.set = meson_gpio_set; | |
| + pc->chip.base = -1; | |
| + pc->chip.ngpio = pc->data->num_pins; | |
| + pc->chip.can_sleep = true; | |
| + | |
| + ret = gpiochip_add_data(&pc->chip, pc); | |
| + if (ret) { | |
| + dev_err(pc->dev, "can't add gpio chip %s\n", | |
| + pc->data->name); | |
| + return ret; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static struct regmap_config meson_regmap_config = { | |
| + .reg_bits = 32, | |
| + .val_bits = 32, | |
| + .reg_stride = 4, | |
| +}; | |
| + | |
| +static struct regmap *meson_map_resource(struct meson_pinctrl *pc, | |
| + struct device_node *node, char *name) | |
| +{ | |
| + struct resource res; | |
| + void __iomem *base; | |
| + int i; | |
| + | |
| + i = of_property_match_string(node, "reg-names", name); | |
| + if (of_address_to_resource(node, i, &res)) | |
| + return NULL; | |
| + | |
| + base = devm_ioremap_resource(pc->dev, &res); | |
| + if (IS_ERR(base)) | |
| + return ERR_CAST(base); | |
| + | |
| + meson_regmap_config.max_register = resource_size(&res) - 4; | |
| + meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, | |
| + "%pOFn-%s", node, | |
| + name); | |
| + if (!meson_regmap_config.name) | |
| + return ERR_PTR(-ENOMEM); | |
| + | |
| + return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); | |
| +} | |
| + | |
| +static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc) | |
| +{ | |
| + struct device_node *gpio_np; | |
| + unsigned int chips; | |
| + | |
| + chips = gpiochip_node_count(pc->dev); | |
| + if (!chips) { | |
| + dev_err(pc->dev, "no gpio node found\n"); | |
| + return -EINVAL; | |
| + } | |
| + if (chips > 1) { | |
| + dev_err(pc->dev, "multiple gpio nodes\n"); | |
| + return -EINVAL; | |
| + } | |
| + | |
| + pc->fwnode = gpiochip_node_get_first(pc->dev); | |
| + gpio_np = to_of_node(pc->fwnode); | |
| + | |
| + pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); | |
| + if (IS_ERR_OR_NULL(pc->reg_mux)) { | |
| + dev_err(pc->dev, "mux registers not found\n"); | |
| + return pc->reg_mux ? PTR_ERR(pc->reg_mux) : -ENOENT; | |
| + } | |
| + | |
| + pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio"); | |
| + if (IS_ERR_OR_NULL(pc->reg_gpio)) { | |
| + dev_err(pc->dev, "gpio registers not found\n"); | |
| + return pc->reg_gpio ? PTR_ERR(pc->reg_gpio) : -ENOENT; | |
| + } | |
| + | |
| + pc->reg_pull = meson_map_resource(pc, gpio_np, "pull"); | |
| + if (IS_ERR(pc->reg_pull)) | |
| + pc->reg_pull = NULL; | |
| + | |
| + pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable"); | |
| + if (IS_ERR(pc->reg_pullen)) | |
| + pc->reg_pullen = NULL; | |
| + | |
| + pc->reg_ds = meson_map_resource(pc, gpio_np, "ds"); | |
| + if (IS_ERR(pc->reg_ds)) { | |
| + dev_dbg(pc->dev, "ds registers not found - skipping\n"); | |
| + pc->reg_ds = NULL; | |
| + } | |
| + | |
| + if (pc->data->parse_dt) | |
| + return pc->data->parse_dt(pc); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc) | |
| +{ | |
| + if (!pc->reg_pull) | |
| + return -EINVAL; | |
| + | |
| + pc->reg_pullen = pc->reg_pull; | |
| + | |
| + return 0; | |
| +} | |
| +EXPORT_SYMBOL_GPL(meson8_aobus_parse_dt_extra); | |
| + | |
| +int meson_a1_parse_dt_extra(struct meson_pinctrl *pc) | |
| +{ | |
| + pc->reg_pull = pc->reg_gpio; | |
| + pc->reg_pullen = pc->reg_gpio; | |
| + pc->reg_ds = pc->reg_gpio; | |
| + | |
| + return 0; | |
| +} | |
| +EXPORT_SYMBOL_GPL(meson_a1_parse_dt_extra); | |
| + | |
| +int meson_pinctrl_probe(struct platform_device *pdev) | |
| +{ | |
| + struct device *dev = &pdev->dev; | |
| + struct meson_pinctrl *pc; | |
| + int ret; | |
| + | |
| + pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); | |
| + if (!pc) | |
| + return -ENOMEM; | |
| + | |
| + pc->dev = dev; | |
| + pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev); | |
| + | |
| + ret = meson_pinctrl_parse_dt(pc); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + pc->desc.name = "pinctrl-meson"; | |
| + pc->desc.owner = THIS_MODULE; | |
| + pc->desc.pctlops = &meson_pctrl_ops; | |
| + pc->desc.pmxops = pc->data->pmx_ops; | |
| + pc->desc.confops = &meson_pinconf_ops; | |
| + pc->desc.pins = pc->data->pins; | |
| + pc->desc.npins = pc->data->num_pins; | |
| + | |
| + pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc); | |
| + if (IS_ERR(pc->pcdev)) { | |
| + dev_err(pc->dev, "can't register pinctrl device"); | |
| + return PTR_ERR(pc->pcdev); | |
| + } | |
| + | |
| + return meson_gpiolib_register(pc); | |
| +} | |
| +EXPORT_SYMBOL_GPL(meson_pinctrl_probe); | |
| + | |
| +MODULE_DESCRIPTION("Amlogic Meson SoCs core pinctrl driver"); | |
| +MODULE_LICENSE("GPL v2"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h | |
| new file mode 100644 | |
| index 0000000000..7883ea31a0 | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson.h | |
| @@ -0,0 +1,183 @@ | |
| +/* SPDX-License-Identifier: GPL-2.0-only */ | |
| +/* | |
| + * Pin controller and GPIO driver for Amlogic Meson SoCs | |
| + * | |
| + * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | |
| + */ | |
| + | |
| +#include <linux/gpio/driver.h> | |
| +#include <linux/pinctrl/pinctrl.h> | |
| +#include <linux/platform_device.h> | |
| +#include <linux/regmap.h> | |
| +#include <linux/types.h> | |
| +#include <linux/module.h> | |
| + | |
| +struct fwnode_handle; | |
| + | |
| +struct meson_pinctrl; | |
| + | |
| +/** | |
| + * struct meson_pmx_group - a pinmux group | |
| + * | |
| + * @name: group name | |
| + * @pins: pins in the group | |
| + * @num_pins: number of pins in the group | |
| + * @is_gpio: whether the group is a single GPIO group | |
| + * @reg: register offset for the group in the domain mux registers | |
| + * @bit bit index enabling the group | |
| + * @domain: index of the domain this group belongs to | |
| + */ | |
| +struct meson_pmx_group { | |
| + const char *name; | |
| + const unsigned int *pins; | |
| + unsigned int num_pins; | |
| + const void *data; | |
| +}; | |
| + | |
| +/** | |
| + * struct meson_pmx_func - a pinmux function | |
| + * | |
| + * @name: function name | |
| + * @groups: groups in the function | |
| + * @num_groups: number of groups in the function | |
| + */ | |
| +struct meson_pmx_func { | |
| + const char *name; | |
| + const char * const *groups; | |
| + unsigned int num_groups; | |
| +}; | |
| + | |
| +/** | |
| + * struct meson_reg_desc - a register descriptor | |
| + * | |
| + * @reg: register offset in the regmap | |
| + * @bit: bit index in register | |
| + * | |
| + * The structure describes the information needed to control pull, | |
| + * pull-enable, direction, etc. for a single pin | |
| + */ | |
| +struct meson_reg_desc { | |
| + unsigned int reg; | |
| + unsigned int bit; | |
| +}; | |
| + | |
| +/** | |
| + * enum meson_reg_type - type of registers encoded in @meson_reg_desc | |
| + */ | |
| +enum meson_reg_type { | |
| + MESON_REG_PULLEN, | |
| + MESON_REG_PULL, | |
| + MESON_REG_DIR, | |
| + MESON_REG_OUT, | |
| + MESON_REG_IN, | |
| + MESON_REG_DS, | |
| + MESON_NUM_REG, | |
| +}; | |
| + | |
| +/** | |
| + * enum meson_pinconf_drv - value of drive-strength supported | |
| + */ | |
| +enum meson_pinconf_drv { | |
| + MESON_PINCONF_DRV_500UA, | |
| + MESON_PINCONF_DRV_2500UA, | |
| + MESON_PINCONF_DRV_3000UA, | |
| + MESON_PINCONF_DRV_4000UA, | |
| +}; | |
| + | |
| +/** | |
| + * struct meson bank | |
| + * | |
| + * @name: bank name | |
| + * @first: first pin of the bank | |
| + * @last: last pin of the bank | |
| + * @irq: hwirq base number of the bank | |
| + * @regs: array of register descriptors | |
| + * | |
| + * A bank represents a set of pins controlled by a contiguous set of | |
| + * bits in the domain registers. The structure specifies which bits in | |
| + * the regmap control the different functionalities. Each member of | |
| + * the @regs array refers to the first pin of the bank. | |
| + */ | |
| +struct meson_bank { | |
| + const char *name; | |
| + unsigned int first; | |
| + unsigned int last; | |
| + int irq_first; | |
| + int irq_last; | |
| + struct meson_reg_desc regs[MESON_NUM_REG]; | |
| +}; | |
| + | |
| +struct meson_pinctrl_data { | |
| + const char *name; | |
| + const struct pinctrl_pin_desc *pins; | |
| + const struct meson_pmx_group *groups; | |
| + const struct meson_pmx_func *funcs; | |
| + unsigned int num_pins; | |
| + unsigned int num_groups; | |
| + unsigned int num_funcs; | |
| + const struct meson_bank *banks; | |
| + unsigned int num_banks; | |
| + const struct pinmux_ops *pmx_ops; | |
| + const void *pmx_data; | |
| + int (*parse_dt)(struct meson_pinctrl *pc); | |
| +}; | |
| + | |
| +struct meson_pinctrl { | |
| + struct device *dev; | |
| + struct pinctrl_dev *pcdev; | |
| + struct pinctrl_desc desc; | |
| + struct meson_pinctrl_data *data; | |
| + struct regmap *reg_mux; | |
| + struct regmap *reg_pullen; | |
| + struct regmap *reg_pull; | |
| + struct regmap *reg_gpio; | |
| + struct regmap *reg_ds; | |
| + struct gpio_chip chip; | |
| + struct fwnode_handle *fwnode; | |
| +}; | |
| + | |
| +#define FUNCTION(fn) \ | |
| + { \ | |
| + .name = #fn, \ | |
| + .groups = fn ## _groups, \ | |
| + .num_groups = ARRAY_SIZE(fn ## _groups), \ | |
| + } | |
| + | |
| +#define BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, \ | |
| + dsr, dsb) \ | |
| + { \ | |
| + .name = n, \ | |
| + .first = f, \ | |
| + .last = l, \ | |
| + .irq_first = fi, \ | |
| + .irq_last = li, \ | |
| + .regs = { \ | |
| + [MESON_REG_PULLEN] = { per, peb }, \ | |
| + [MESON_REG_PULL] = { pr, pb }, \ | |
| + [MESON_REG_DIR] = { dr, db }, \ | |
| + [MESON_REG_OUT] = { or, ob }, \ | |
| + [MESON_REG_IN] = { ir, ib }, \ | |
| + [MESON_REG_DS] = { dsr, dsb }, \ | |
| + }, \ | |
| + } | |
| + | |
| +#define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ | |
| + BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0) | |
| + | |
| +#define MESON_PIN(x) PINCTRL_PIN(x, #x) | |
| + | |
| +/* Common pmx functions */ | |
| +int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev); | |
| +const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, | |
| + unsigned selector); | |
| +int meson_pmx_get_groups(struct pinctrl_dev *pcdev, | |
| + unsigned selector, | |
| + const char * const **groups, | |
| + unsigned * const num_groups); | |
| + | |
| +/* Common probe function */ | |
| +int meson_pinctrl_probe(struct platform_device *pdev); | |
| +/* Common ao groups extra dt parse function for SoCs before g12a */ | |
| +int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc); | |
| +/* Common extra dt parse function for SoCs like A1 */ | |
| +int meson_a1_parse_dt_extra(struct meson_pinctrl *pc); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.c b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c | |
| new file mode 100644 | |
| index 0000000000..10adf52edd | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c | |
| @@ -0,0 +1,105 @@ | |
| +// SPDX-License-Identifier: GPL-2.0-only | |
| +/* | |
| + * First generation of pinmux driver for Amlogic Meson SoCs | |
| + * | |
| + * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | |
| + * Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com> | |
| + */ | |
| + | |
| +/* For this first generation of pinctrl driver every pinmux group can be | |
| + * enabled by a specific bit in the first register range. When all groups for | |
| + * a given pin are disabled the pin acts as a GPIO. | |
| + */ | |
| +#include <linux/device.h> | |
| +#include <linux/regmap.h> | |
| +#include <linux/pinctrl/pinctrl.h> | |
| +#include <linux/pinctrl/pinmux.h> | |
| + | |
| +#include "pinctrl-meson.h" | |
| +#include "pinctrl-meson8-pmx.h" | |
| + | |
| +/** | |
| + * meson8_pmx_disable_other_groups() - disable other groups using a given pin | |
| + * | |
| + * @pc: meson pin controller device | |
| + * @pin: number of the pin | |
| + * @sel_group: index of the selected group, or -1 if none | |
| + * | |
| + * The function disables all pinmux groups using a pin except the | |
| + * selected one. If @sel_group is -1 all groups are disabled, leaving | |
| + * the pin in GPIO mode. | |
| + */ | |
| +static void meson8_pmx_disable_other_groups(struct meson_pinctrl *pc, | |
| + unsigned int pin, int sel_group) | |
| +{ | |
| + const struct meson_pmx_group *group; | |
| + struct meson8_pmx_data *pmx_data; | |
| + int i, j; | |
| + | |
| + for (i = 0; i < pc->data->num_groups; i++) { | |
| + group = &pc->data->groups[i]; | |
| + pmx_data = (struct meson8_pmx_data *)group->data; | |
| + if (pmx_data->is_gpio || i == sel_group) | |
| + continue; | |
| + | |
| + for (j = 0; j < group->num_pins; j++) { | |
| + if (group->pins[j] == pin) { | |
| + /* We have found a group using the pin */ | |
| + regmap_update_bits(pc->reg_mux, | |
| + pmx_data->reg * 4, | |
| + BIT(pmx_data->bit), 0); | |
| + } | |
| + } | |
| + } | |
| +} | |
| + | |
| +static int meson8_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num, | |
| + unsigned group_num) | |
| +{ | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| + const struct meson_pmx_func *func = &pc->data->funcs[func_num]; | |
| + const struct meson_pmx_group *group = &pc->data->groups[group_num]; | |
| + struct meson8_pmx_data *pmx_data = | |
| + (struct meson8_pmx_data *)group->data; | |
| + int i, ret = 0; | |
| + | |
| + dev_dbg(pc->dev, "enable function %s, group %s\n", func->name, | |
| + group->name); | |
| + | |
| + /* | |
| + * Disable groups using the same pin. | |
| + * The selected group is not disabled to avoid glitches. | |
| + */ | |
| + for (i = 0; i < group->num_pins; i++) | |
| + meson8_pmx_disable_other_groups(pc, group->pins[i], group_num); | |
| + | |
| + /* Function 0 (GPIO) doesn't need any additional setting */ | |
| + if (func_num) | |
| + ret = regmap_update_bits(pc->reg_mux, pmx_data->reg * 4, | |
| + BIT(pmx_data->bit), | |
| + BIT(pmx_data->bit)); | |
| + | |
| + return ret; | |
| +} | |
| + | |
| +static int meson8_pmx_request_gpio(struct pinctrl_dev *pcdev, | |
| + struct pinctrl_gpio_range *range, | |
| + unsigned offset) | |
| +{ | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| + | |
| + meson8_pmx_disable_other_groups(pc, offset, -1); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +const struct pinmux_ops meson8_pmx_ops = { | |
| + .set_mux = meson8_pmx_set_mux, | |
| + .get_functions_count = meson_pmx_get_funcs_count, | |
| + .get_function_name = meson_pmx_get_func_name, | |
| + .get_function_groups = meson_pmx_get_groups, | |
| + .gpio_request_enable = meson8_pmx_request_gpio, | |
| +}; | |
| +EXPORT_SYMBOL_GPL(meson8_pmx_ops); | |
| +MODULE_DESCRIPTION("Amlogic Meson SoCs first generation pinmux driver"); | |
| +MODULE_LICENSE("GPL v2"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.h b/drivers/pinctrl/meson/pinctrl-meson8-pmx.h | |
| new file mode 100644 | |
| index 0000000000..9390dc2f80 | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.h | |
| @@ -0,0 +1,42 @@ | |
| +/* SPDX-License-Identifier: GPL-2.0-only */ | |
| +/* | |
| + * First generation of pinmux driver for Amlogic Meson SoCs | |
| + * | |
| + * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | |
| + * Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com> | |
| + */ | |
| + | |
| +struct meson8_pmx_data { | |
| + bool is_gpio; | |
| + unsigned int reg; | |
| + unsigned int bit; | |
| +}; | |
| + | |
| +#define PMX_DATA(r, b, g) \ | |
| + { \ | |
| + .reg = r, \ | |
| + .bit = b, \ | |
| + .is_gpio = g, \ | |
| + } | |
| + | |
| +#define GROUP(grp, r, b) \ | |
| + { \ | |
| + .name = #grp, \ | |
| + .pins = grp ## _pins, \ | |
| + .num_pins = ARRAY_SIZE(grp ## _pins), \ | |
| + .data = (const struct meson8_pmx_data[]){ \ | |
| + PMX_DATA(r, b, false), \ | |
| + }, \ | |
| + } | |
| + | |
| +#define GPIO_GROUP(gpio) \ | |
| + { \ | |
| + .name = #gpio, \ | |
| + .pins = (const unsigned int[]){ gpio }, \ | |
| + .num_pins = 1, \ | |
| + .data = (const struct meson8_pmx_data[]){ \ | |
| + PMX_DATA(0, 0, true), \ | |
| + }, \ | |
| + } | |
| + | |
| +extern const struct pinmux_ops meson8_pmx_ops; | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c | |
| new file mode 100644 | |
| index 0000000000..3da7f3799c | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson8.c | |
| @@ -0,0 +1,1136 @@ | |
| +// SPDX-License-Identifier: GPL-2.0-only | |
| +/* | |
| + * Pin controller and GPIO driver for Amlogic Meson8 and Meson8m2. | |
| + * | |
| + * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | |
| + */ | |
| + | |
| +#include <dt-bindings/gpio/meson8-gpio.h> | |
| +#include "pinctrl-meson.h" | |
| +#include "pinctrl-meson8-pmx.h" | |
| + | |
| +static const struct pinctrl_pin_desc meson8_cbus_pins[] = { | |
| + MESON_PIN(GPIOX_0), | |
| + MESON_PIN(GPIOX_1), | |
| + MESON_PIN(GPIOX_2), | |
| + MESON_PIN(GPIOX_3), | |
| + MESON_PIN(GPIOX_4), | |
| + MESON_PIN(GPIOX_5), | |
| + MESON_PIN(GPIOX_6), | |
| + MESON_PIN(GPIOX_7), | |
| + MESON_PIN(GPIOX_8), | |
| + MESON_PIN(GPIOX_9), | |
| + MESON_PIN(GPIOX_10), | |
| + MESON_PIN(GPIOX_11), | |
| + MESON_PIN(GPIOX_12), | |
| + MESON_PIN(GPIOX_13), | |
| + MESON_PIN(GPIOX_14), | |
| + MESON_PIN(GPIOX_15), | |
| + MESON_PIN(GPIOX_16), | |
| + MESON_PIN(GPIOX_17), | |
| + MESON_PIN(GPIOX_18), | |
| + MESON_PIN(GPIOX_19), | |
| + MESON_PIN(GPIOX_20), | |
| + MESON_PIN(GPIOX_21), | |
| + MESON_PIN(GPIOY_0), | |
| + MESON_PIN(GPIOY_1), | |
| + MESON_PIN(GPIOY_2), | |
| + MESON_PIN(GPIOY_3), | |
| + MESON_PIN(GPIOY_4), | |
| + MESON_PIN(GPIOY_5), | |
| + MESON_PIN(GPIOY_6), | |
| + MESON_PIN(GPIOY_7), | |
| + MESON_PIN(GPIOY_8), | |
| + MESON_PIN(GPIOY_9), | |
| + MESON_PIN(GPIOY_10), | |
| + MESON_PIN(GPIOY_11), | |
| + MESON_PIN(GPIOY_12), | |
| + MESON_PIN(GPIOY_13), | |
| + MESON_PIN(GPIOY_14), | |
| + MESON_PIN(GPIOY_15), | |
| + MESON_PIN(GPIOY_16), | |
| + MESON_PIN(GPIODV_0), | |
| + MESON_PIN(GPIODV_1), | |
| + MESON_PIN(GPIODV_2), | |
| + MESON_PIN(GPIODV_3), | |
| + MESON_PIN(GPIODV_4), | |
| + MESON_PIN(GPIODV_5), | |
| + MESON_PIN(GPIODV_6), | |
| + MESON_PIN(GPIODV_7), | |
| + MESON_PIN(GPIODV_8), | |
| + MESON_PIN(GPIODV_9), | |
| + MESON_PIN(GPIODV_10), | |
| + MESON_PIN(GPIODV_11), | |
| + MESON_PIN(GPIODV_12), | |
| + MESON_PIN(GPIODV_13), | |
| + MESON_PIN(GPIODV_14), | |
| + MESON_PIN(GPIODV_15), | |
| + MESON_PIN(GPIODV_16), | |
| + MESON_PIN(GPIODV_17), | |
| + MESON_PIN(GPIODV_18), | |
| + MESON_PIN(GPIODV_19), | |
| + MESON_PIN(GPIODV_20), | |
| + MESON_PIN(GPIODV_21), | |
| + MESON_PIN(GPIODV_22), | |
| + MESON_PIN(GPIODV_23), | |
| + MESON_PIN(GPIODV_24), | |
| + MESON_PIN(GPIODV_25), | |
| + MESON_PIN(GPIODV_26), | |
| + MESON_PIN(GPIODV_27), | |
| + MESON_PIN(GPIODV_28), | |
| + MESON_PIN(GPIODV_29), | |
| + MESON_PIN(GPIOH_0), | |
| + MESON_PIN(GPIOH_1), | |
| + MESON_PIN(GPIOH_2), | |
| + MESON_PIN(GPIOH_3), | |
| + MESON_PIN(GPIOH_4), | |
| + MESON_PIN(GPIOH_5), | |
| + MESON_PIN(GPIOH_6), | |
| + MESON_PIN(GPIOH_7), | |
| + MESON_PIN(GPIOH_8), | |
| + MESON_PIN(GPIOH_9), | |
| + MESON_PIN(GPIOZ_0), | |
| + MESON_PIN(GPIOZ_1), | |
| + MESON_PIN(GPIOZ_2), | |
| + MESON_PIN(GPIOZ_3), | |
| + MESON_PIN(GPIOZ_4), | |
| + MESON_PIN(GPIOZ_5), | |
| + MESON_PIN(GPIOZ_6), | |
| + MESON_PIN(GPIOZ_7), | |
| + MESON_PIN(GPIOZ_8), | |
| + MESON_PIN(GPIOZ_9), | |
| + MESON_PIN(GPIOZ_10), | |
| + MESON_PIN(GPIOZ_11), | |
| + MESON_PIN(GPIOZ_12), | |
| + MESON_PIN(GPIOZ_13), | |
| + MESON_PIN(GPIOZ_14), | |
| + MESON_PIN(CARD_0), | |
| + MESON_PIN(CARD_1), | |
| + MESON_PIN(CARD_2), | |
| + MESON_PIN(CARD_3), | |
| + MESON_PIN(CARD_4), | |
| + MESON_PIN(CARD_5), | |
| + MESON_PIN(CARD_6), | |
| + MESON_PIN(BOOT_0), | |
| + MESON_PIN(BOOT_1), | |
| + MESON_PIN(BOOT_2), | |
| + MESON_PIN(BOOT_3), | |
| + MESON_PIN(BOOT_4), | |
| + MESON_PIN(BOOT_5), | |
| + MESON_PIN(BOOT_6), | |
| + MESON_PIN(BOOT_7), | |
| + MESON_PIN(BOOT_8), | |
| + MESON_PIN(BOOT_9), | |
| + MESON_PIN(BOOT_10), | |
| + MESON_PIN(BOOT_11), | |
| + MESON_PIN(BOOT_12), | |
| + MESON_PIN(BOOT_13), | |
| + MESON_PIN(BOOT_14), | |
| + MESON_PIN(BOOT_15), | |
| + MESON_PIN(BOOT_16), | |
| + MESON_PIN(BOOT_17), | |
| + MESON_PIN(BOOT_18), | |
| +}; | |
| + | |
| +static const struct pinctrl_pin_desc meson8_aobus_pins[] = { | |
| + MESON_PIN(GPIOAO_0), | |
| + MESON_PIN(GPIOAO_1), | |
| + MESON_PIN(GPIOAO_2), | |
| + MESON_PIN(GPIOAO_3), | |
| + MESON_PIN(GPIOAO_4), | |
| + MESON_PIN(GPIOAO_5), | |
| + MESON_PIN(GPIOAO_6), | |
| + MESON_PIN(GPIOAO_7), | |
| + MESON_PIN(GPIOAO_8), | |
| + MESON_PIN(GPIOAO_9), | |
| + MESON_PIN(GPIOAO_10), | |
| + MESON_PIN(GPIOAO_11), | |
| + MESON_PIN(GPIOAO_12), | |
| + MESON_PIN(GPIOAO_13), | |
| + MESON_PIN(GPIO_BSD_EN), | |
| + MESON_PIN(GPIO_TEST_N), | |
| +}; | |
| + | |
| +/* bank X */ | |
| +static const unsigned int sd_d0_a_pins[] = { GPIOX_0 }; | |
| +static const unsigned int sd_d1_a_pins[] = { GPIOX_1 }; | |
| +static const unsigned int sd_d2_a_pins[] = { GPIOX_2 }; | |
| +static const unsigned int sd_d3_a_pins[] = { GPIOX_3 }; | |
| +static const unsigned int sd_clk_a_pins[] = { GPIOX_8 }; | |
| +static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 }; | |
| + | |
| +static const unsigned int sdxc_d0_a_pins[] = { GPIOX_0 }; | |
| +static const unsigned int sdxc_d13_a_pins[] = { GPIOX_1, GPIOX_2, GPIOX_3 }; | |
| +static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5, GPIOX_6, | |
| + GPIOX_7 }; | |
| +static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 }; | |
| +static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 }; | |
| + | |
| +static const unsigned int pcm_out_a_pins[] = { GPIOX_4 }; | |
| +static const unsigned int pcm_in_a_pins[] = { GPIOX_5 }; | |
| +static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 }; | |
| +static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 }; | |
| + | |
| +static const unsigned int uart_tx_a0_pins[] = { GPIOX_4 }; | |
| +static const unsigned int uart_rx_a0_pins[] = { GPIOX_5 }; | |
| +static const unsigned int uart_cts_a0_pins[] = { GPIOX_6 }; | |
| +static const unsigned int uart_rts_a0_pins[] = { GPIOX_7 }; | |
| + | |
| +static const unsigned int uart_tx_a1_pins[] = { GPIOX_12 }; | |
| +static const unsigned int uart_rx_a1_pins[] = { GPIOX_13 }; | |
| +static const unsigned int uart_cts_a1_pins[] = { GPIOX_14 }; | |
| +static const unsigned int uart_rts_a1_pins[] = { GPIOX_15 }; | |
| + | |
| +static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 }; | |
| +static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 }; | |
| +static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 }; | |
| +static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 }; | |
| + | |
| +static const unsigned int iso7816_det_pins[] = { GPIOX_16 }; | |
| +static const unsigned int iso7816_reset_pins[] = { GPIOX_17 }; | |
| +static const unsigned int iso7816_clk_pins[] = { GPIOX_18 }; | |
| +static const unsigned int iso7816_data_pins[] = { GPIOX_19 }; | |
| + | |
| +static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 }; | |
| +static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 }; | |
| + | |
| +static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 }; | |
| +static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 }; | |
| + | |
| +static const unsigned int pwm_e_pins[] = { GPIOX_10 }; | |
| +static const unsigned int pwm_b_x_pins[] = { GPIOX_11 }; | |
| + | |
| +/* bank Y */ | |
| +static const unsigned int uart_tx_c_pins[] = { GPIOY_0 }; | |
| +static const unsigned int uart_rx_c_pins[] = { GPIOY_1 }; | |
| +static const unsigned int uart_cts_c_pins[] = { GPIOY_2 }; | |
| +static const unsigned int uart_rts_c_pins[] = { GPIOY_3 }; | |
| + | |
| +static const unsigned int pcm_out_b_pins[] = { GPIOY_4 }; | |
| +static const unsigned int pcm_in_b_pins[] = { GPIOY_5 }; | |
| +static const unsigned int pcm_fs_b_pins[] = { GPIOY_6 }; | |
| +static const unsigned int pcm_clk_b_pins[] = { GPIOY_7 }; | |
| + | |
| +static const unsigned int i2c_sda_c0_pins[] = { GPIOY_0 }; | |
| +static const unsigned int i2c_sck_c0_pins[] = { GPIOY_1 }; | |
| + | |
| +static const unsigned int pwm_a_y_pins[] = { GPIOY_16 }; | |
| + | |
| +static const unsigned int i2s_out_ch45_pins[] = { GPIOY_0 }; | |
| +static const unsigned int i2s_out_ch23_pins[] = { GPIOY_1 }; | |
| +static const unsigned int i2s_out_ch01_pins[] = { GPIOY_4 }; | |
| +static const unsigned int i2s_in_ch01_pins[] = { GPIOY_5 }; | |
| +static const unsigned int i2s_lr_clk_in_pins[] = { GPIOY_6 }; | |
| +static const unsigned int i2s_ao_clk_in_pins[] = { GPIOY_7 }; | |
| +static const unsigned int i2s_am_clk_pins[] = { GPIOY_8 }; | |
| +static const unsigned int i2s_out_ch78_pins[] = { GPIOY_9 }; | |
| + | |
| +static const unsigned int spdif_in_pins[] = { GPIOY_2 }; | |
| +static const unsigned int spdif_out_pins[] = { GPIOY_3 }; | |
| + | |
| +/* bank DV */ | |
| +static const unsigned int dvin_rgb_pins[] = { | |
| + GPIODV_0, GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, | |
| + GPIODV_6, GPIODV_7, GPIODV_8, GPIODV_9, GPIODV_10, GPIODV_11, | |
| + GPIODV_12, GPIODV_13, GPIODV_14, GPIODV_15, GPIODV_16, GPIODV_17, | |
| + GPIODV_18, GPIODV_19, GPIODV_20, GPIODV_21, GPIODV_22, GPIODV_23 | |
| +}; | |
| +static const unsigned int dvin_vs_pins[] = { GPIODV_24 }; | |
| +static const unsigned int dvin_hs_pins[] = { GPIODV_25 }; | |
| +static const unsigned int dvin_clk_pins[] = { GPIODV_26 }; | |
| +static const unsigned int dvin_de_pins[] = { GPIODV_27 }; | |
| + | |
| +static const unsigned int enc_0_pins[] = { GPIODV_0 }; | |
| +static const unsigned int enc_1_pins[] = { GPIODV_1 }; | |
| +static const unsigned int enc_2_pins[] = { GPIODV_2 }; | |
| +static const unsigned int enc_3_pins[] = { GPIODV_3 }; | |
| +static const unsigned int enc_4_pins[] = { GPIODV_4 }; | |
| +static const unsigned int enc_5_pins[] = { GPIODV_5 }; | |
| +static const unsigned int enc_6_pins[] = { GPIODV_6 }; | |
| +static const unsigned int enc_7_pins[] = { GPIODV_7 }; | |
| +static const unsigned int enc_8_pins[] = { GPIODV_8 }; | |
| +static const unsigned int enc_9_pins[] = { GPIODV_9 }; | |
| +static const unsigned int enc_10_pins[] = { GPIODV_10 }; | |
| +static const unsigned int enc_11_pins[] = { GPIODV_11 }; | |
| +static const unsigned int enc_12_pins[] = { GPIODV_12 }; | |
| +static const unsigned int enc_13_pins[] = { GPIODV_13 }; | |
| +static const unsigned int enc_14_pins[] = { GPIODV_14 }; | |
| +static const unsigned int enc_15_pins[] = { GPIODV_15 }; | |
| +static const unsigned int enc_16_pins[] = { GPIODV_16 }; | |
| +static const unsigned int enc_17_pins[] = { GPIODV_17 }; | |
| + | |
| +static const unsigned int uart_tx_b1_pins[] = { GPIODV_24 }; | |
| +static const unsigned int uart_rx_b1_pins[] = { GPIODV_25 }; | |
| +static const unsigned int uart_cts_b1_pins[] = { GPIODV_26 }; | |
| +static const unsigned int uart_rts_b1_pins[] = { GPIODV_27 }; | |
| + | |
| +static const unsigned int vga_vs_pins[] = { GPIODV_24 }; | |
| +static const unsigned int vga_hs_pins[] = { GPIODV_25 }; | |
| + | |
| +static const unsigned int pwm_c_dv9_pins[] = { GPIODV_9 }; | |
| +static const unsigned int pwm_c_dv29_pins[] = { GPIODV_29 }; | |
| +static const unsigned int pwm_d_pins[] = { GPIODV_28 }; | |
| + | |
| +/* bank H */ | |
| +static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 }; | |
| +static const unsigned int hdmi_sda_pins[] = { GPIOH_1 }; | |
| +static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; | |
| +static const unsigned int hdmi_cec_pins[] = { GPIOH_3 }; | |
| + | |
| +static const unsigned int spi_ss0_0_pins[] = { GPIOH_3 }; | |
| +static const unsigned int spi_miso_0_pins[] = { GPIOH_4 }; | |
| +static const unsigned int spi_mosi_0_pins[] = { GPIOH_5 }; | |
| +static const unsigned int spi_sclk_0_pins[] = { GPIOH_6 }; | |
| + | |
| +static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 }; | |
| +static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 }; | |
| + | |
| +/* bank Z */ | |
| +static const unsigned int spi_ss0_1_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int spi_ss1_1_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int spi_sclk_1_pins[] = { GPIOZ_11 }; | |
| +static const unsigned int spi_mosi_1_pins[] = { GPIOZ_12 }; | |
| +static const unsigned int spi_miso_1_pins[] = { GPIOZ_13 }; | |
| +static const unsigned int spi_ss2_1_pins[] = { GPIOZ_14 }; | |
| + | |
| +static const unsigned int eth_txd3_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int eth_txd2_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int eth_rxd3_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int eth_rxd2_pins[] = { GPIOZ_3 }; | |
| +static const unsigned int eth_tx_clk_50m_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int eth_tx_en_pins[] = { GPIOZ_5 }; | |
| +static const unsigned int eth_txd1_pins[] = { GPIOZ_6 }; | |
| +static const unsigned int eth_txd0_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int eth_rx_clk_in_pins[] = { GPIOZ_8 }; | |
| +static const unsigned int eth_rx_dv_pins[] = { GPIOZ_9 }; | |
| +static const unsigned int eth_rxd1_pins[] = { GPIOZ_10 }; | |
| +static const unsigned int eth_rxd0_pins[] = { GPIOZ_11 }; | |
| +static const unsigned int eth_mdio_pins[] = { GPIOZ_12 }; | |
| +static const unsigned int eth_mdc_pins[] = { GPIOZ_13 }; | |
| + | |
| +static const unsigned int i2c_sda_a0_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int i2c_sck_a0_pins[] = { GPIOZ_1 }; | |
| + | |
| +static const unsigned int i2c_sda_b_pins[] = { GPIOZ_2 }; | |
| +static const unsigned int i2c_sck_b_pins[] = { GPIOZ_3 }; | |
| + | |
| +static const unsigned int i2c_sda_c1_pins[] = { GPIOZ_4 }; | |
| +static const unsigned int i2c_sck_c1_pins[] = { GPIOZ_5 }; | |
| + | |
| +static const unsigned int i2c_sda_a1_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int i2c_sck_a1_pins[] = { GPIOZ_1 }; | |
| + | |
| +static const unsigned int i2c_sda_a2_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int i2c_sck_a2_pins[] = { GPIOZ_1 }; | |
| + | |
| +static const unsigned int pwm_a_z0_pins[] = { GPIOZ_0 }; | |
| +static const unsigned int pwm_a_z7_pins[] = { GPIOZ_7 }; | |
| +static const unsigned int pwm_b_z_pins[] = { GPIOZ_1 }; | |
| +static const unsigned int pwm_c_z_pins[] = { GPIOZ_8 }; | |
| + | |
| +/* bank BOOT */ | |
| +static const unsigned int sd_d0_c_pins[] = { BOOT_0 }; | |
| +static const unsigned int sd_d1_c_pins[] = { BOOT_1 }; | |
| +static const unsigned int sd_d2_c_pins[] = { BOOT_2 }; | |
| +static const unsigned int sd_d3_c_pins[] = { BOOT_3 }; | |
| +static const unsigned int sd_cmd_c_pins[] = { BOOT_16 }; | |
| +static const unsigned int sd_clk_c_pins[] = { BOOT_17 }; | |
| + | |
| +static const unsigned int sdxc_d0_c_pins[] = { BOOT_0}; | |
| +static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2, BOOT_3 }; | |
| +static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5, BOOT_6, | |
| + BOOT_7 }; | |
| +static const unsigned int sdxc_cmd_c_pins[] = { BOOT_16 }; | |
| +static const unsigned int sdxc_clk_c_pins[] = { BOOT_17 }; | |
| + | |
| +static const unsigned int nand_io_pins[] = { | |
| + BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7 | |
| +}; | |
| +static const unsigned int nand_io_ce0_pins[] = { BOOT_8 }; | |
| +static const unsigned int nand_io_ce1_pins[] = { BOOT_9 }; | |
| +static const unsigned int nand_io_rb0_pins[] = { BOOT_10 }; | |
| +static const unsigned int nand_ale_pins[] = { BOOT_11 }; | |
| +static const unsigned int nand_cle_pins[] = { BOOT_12 }; | |
| +static const unsigned int nand_wen_clk_pins[] = { BOOT_13 }; | |
| +static const unsigned int nand_ren_clk_pins[] = { BOOT_14 }; | |
| +static const unsigned int nand_dqs_pins[] = { BOOT_15 }; | |
| +static const unsigned int nand_ce2_pins[] = { BOOT_16 }; | |
| +static const unsigned int nand_ce3_pins[] = { BOOT_17 }; | |
| + | |
| +static const unsigned int nor_d_pins[] = { BOOT_11 }; | |
| +static const unsigned int nor_q_pins[] = { BOOT_12 }; | |
| +static const unsigned int nor_c_pins[] = { BOOT_13 }; | |
| +static const unsigned int nor_cs_pins[] = { BOOT_18 }; | |
| + | |
| +/* bank CARD */ | |
| +static const unsigned int sd_d1_b_pins[] = { CARD_0 }; | |
| +static const unsigned int sd_d0_b_pins[] = { CARD_1 }; | |
| +static const unsigned int sd_clk_b_pins[] = { CARD_2 }; | |
| +static const unsigned int sd_cmd_b_pins[] = { CARD_3 }; | |
| +static const unsigned int sd_d3_b_pins[] = { CARD_4 }; | |
| +static const unsigned int sd_d2_b_pins[] = { CARD_5 }; | |
| + | |
| +static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4, CARD_5 }; | |
| +static const unsigned int sdxc_d0_b_pins[] = { CARD_1 }; | |
| +static const unsigned int sdxc_clk_b_pins[] = { CARD_2 }; | |
| +static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 }; | |
| + | |
| +/* bank AO */ | |
| +static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 }; | |
| +static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 }; | |
| +static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 }; | |
| +static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 }; | |
| + | |
| +static const unsigned int remote_input_pins[] = { GPIOAO_7 }; | |
| +static const unsigned int remote_output_ao_pins[] = { GPIOAO_13 }; | |
| + | |
| +static const unsigned int i2c_slave_sck_ao_pins[] = { GPIOAO_4 }; | |
| +static const unsigned int i2c_slave_sda_ao_pins[] = { GPIOAO_5 }; | |
| + | |
| +static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 }; | |
| +static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 }; | |
| + | |
| +static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 }; | |
| +static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 }; | |
| + | |
| +static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 }; | |
| +static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 }; | |
| + | |
| +static const unsigned int pwm_f_ao_pins[] = { GPIO_TEST_N }; | |
| + | |
| +static const unsigned int i2s_am_clk_out_ao_pins[] = { GPIOAO_8 }; | |
| +static const unsigned int i2s_ao_clk_out_ao_pins[] = { GPIOAO_9 }; | |
| +static const unsigned int i2s_lr_clk_out_ao_pins[] = { GPIOAO_10 }; | |
| +static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 }; | |
| + | |
| +static const unsigned int hdmi_cec_ao_pins[] = { GPIOAO_12 }; | |
| + | |
| +static const struct meson_pmx_group meson8_cbus_groups[] = { | |
| + GPIO_GROUP(GPIOX_0), | |
| + GPIO_GROUP(GPIOX_1), | |
| + GPIO_GROUP(GPIOX_2), | |
| + GPIO_GROUP(GPIOX_3), | |
| + GPIO_GROUP(GPIOX_4), | |
| + GPIO_GROUP(GPIOX_5), | |
| + GPIO_GROUP(GPIOX_6), | |
| + GPIO_GROUP(GPIOX_7), | |
| + GPIO_GROUP(GPIOX_8), | |
| + GPIO_GROUP(GPIOX_9), | |
| + GPIO_GROUP(GPIOX_10), | |
| + GPIO_GROUP(GPIOX_11), | |
| + GPIO_GROUP(GPIOX_12), | |
| + GPIO_GROUP(GPIOX_13), | |
| + GPIO_GROUP(GPIOX_14), | |
| + GPIO_GROUP(GPIOX_15), | |
| + GPIO_GROUP(GPIOX_16), | |
| + GPIO_GROUP(GPIOX_17), | |
| + GPIO_GROUP(GPIOX_18), | |
| + GPIO_GROUP(GPIOX_19), | |
| + GPIO_GROUP(GPIOX_20), | |
| + GPIO_GROUP(GPIOX_21), | |
| + GPIO_GROUP(GPIOY_0), | |
| + GPIO_GROUP(GPIOY_1), | |
| + GPIO_GROUP(GPIOY_2), | |
| + GPIO_GROUP(GPIOY_3), | |
| + GPIO_GROUP(GPIOY_4), | |
| + GPIO_GROUP(GPIOY_5), | |
| + GPIO_GROUP(GPIOY_6), | |
| + GPIO_GROUP(GPIOY_7), | |
| + GPIO_GROUP(GPIOY_8), | |
| + GPIO_GROUP(GPIOY_9), | |
| + GPIO_GROUP(GPIOY_10), | |
| + GPIO_GROUP(GPIOY_11), | |
| + GPIO_GROUP(GPIOY_12), | |
| + GPIO_GROUP(GPIOY_13), | |
| + GPIO_GROUP(GPIOY_14), | |
| + GPIO_GROUP(GPIOY_15), | |
| + GPIO_GROUP(GPIOY_16), | |
| + GPIO_GROUP(GPIODV_0), | |
| + GPIO_GROUP(GPIODV_1), | |
| + GPIO_GROUP(GPIODV_2), | |
| + GPIO_GROUP(GPIODV_3), | |
| + GPIO_GROUP(GPIODV_4), | |
| + GPIO_GROUP(GPIODV_5), | |
| + GPIO_GROUP(GPIODV_6), | |
| + GPIO_GROUP(GPIODV_7), | |
| + GPIO_GROUP(GPIODV_8), | |
| + GPIO_GROUP(GPIODV_9), | |
| + GPIO_GROUP(GPIODV_10), | |
| + GPIO_GROUP(GPIODV_11), | |
| + GPIO_GROUP(GPIODV_12), | |
| + GPIO_GROUP(GPIODV_13), | |
| + GPIO_GROUP(GPIODV_14), | |
| + GPIO_GROUP(GPIODV_15), | |
| + GPIO_GROUP(GPIODV_16), | |
| + GPIO_GROUP(GPIODV_17), | |
| + GPIO_GROUP(GPIODV_18), | |
| + GPIO_GROUP(GPIODV_19), | |
| + GPIO_GROUP(GPIODV_20), | |
| + GPIO_GROUP(GPIODV_21), | |
| + GPIO_GROUP(GPIODV_22), | |
| + GPIO_GROUP(GPIODV_23), | |
| + GPIO_GROUP(GPIODV_24), | |
| + GPIO_GROUP(GPIODV_25), | |
| + GPIO_GROUP(GPIODV_26), | |
| + GPIO_GROUP(GPIODV_27), | |
| + GPIO_GROUP(GPIODV_28), | |
| + GPIO_GROUP(GPIODV_29), | |
| + GPIO_GROUP(GPIOH_0), | |
| + GPIO_GROUP(GPIOH_1), | |
| + GPIO_GROUP(GPIOH_2), | |
| + GPIO_GROUP(GPIOH_3), | |
| + GPIO_GROUP(GPIOH_4), | |
| + GPIO_GROUP(GPIOH_5), | |
| + GPIO_GROUP(GPIOH_6), | |
| + GPIO_GROUP(GPIOH_7), | |
| + GPIO_GROUP(GPIOH_8), | |
| + GPIO_GROUP(GPIOH_9), | |
| + GPIO_GROUP(GPIOZ_0), | |
| + GPIO_GROUP(GPIOZ_1), | |
| + GPIO_GROUP(GPIOZ_2), | |
| + GPIO_GROUP(GPIOZ_3), | |
| + GPIO_GROUP(GPIOZ_4), | |
| + GPIO_GROUP(GPIOZ_5), | |
| + GPIO_GROUP(GPIOZ_6), | |
| + GPIO_GROUP(GPIOZ_7), | |
| + GPIO_GROUP(GPIOZ_8), | |
| + GPIO_GROUP(GPIOZ_9), | |
| + GPIO_GROUP(GPIOZ_10), | |
| + GPIO_GROUP(GPIOZ_11), | |
| + GPIO_GROUP(GPIOZ_12), | |
| + GPIO_GROUP(GPIOZ_13), | |
| + GPIO_GROUP(GPIOZ_14), | |
| + GPIO_GROUP(CARD_0), | |
| + GPIO_GROUP(CARD_1), | |
| + GPIO_GROUP(CARD_2), | |
| + GPIO_GROUP(CARD_3), | |
| + GPIO_GROUP(CARD_4), | |
| + GPIO_GROUP(CARD_5), | |
| + GPIO_GROUP(CARD_6), | |
| + GPIO_GROUP(BOOT_0), | |
| + GPIO_GROUP(BOOT_1), | |
| + GPIO_GROUP(BOOT_2), | |
| + GPIO_GROUP(BOOT_3), | |
| + GPIO_GROUP(BOOT_4), | |
| + GPIO_GROUP(BOOT_5), | |
| + GPIO_GROUP(BOOT_6), | |
| + GPIO_GROUP(BOOT_7), | |
| + GPIO_GROUP(BOOT_8), | |
| + GPIO_GROUP(BOOT_9), | |
| + GPIO_GROUP(BOOT_10), | |
| + GPIO_GROUP(BOOT_11), | |
| + GPIO_GROUP(BOOT_12), | |
| + GPIO_GROUP(BOOT_13), | |
| + GPIO_GROUP(BOOT_14), | |
| + GPIO_GROUP(BOOT_15), | |
| + GPIO_GROUP(BOOT_16), | |
| + GPIO_GROUP(BOOT_17), | |
| + GPIO_GROUP(BOOT_18), | |
| + | |
| + /* bank X */ | |
| + GROUP(sd_d0_a, 8, 5), | |
| + GROUP(sd_d1_a, 8, 4), | |
| + GROUP(sd_d2_a, 8, 3), | |
| + GROUP(sd_d3_a, 8, 2), | |
| + GROUP(sd_clk_a, 8, 1), | |
| + GROUP(sd_cmd_a, 8, 0), | |
| + | |
| + GROUP(sdxc_d0_a, 5, 14), | |
| + GROUP(sdxc_d13_a, 5, 13), | |
| + GROUP(sdxc_d47_a, 5, 12), | |
| + GROUP(sdxc_clk_a, 5, 11), | |
| + GROUP(sdxc_cmd_a, 5, 10), | |
| + | |
| + GROUP(pcm_out_a, 3, 30), | |
| + GROUP(pcm_in_a, 3, 29), | |
| + GROUP(pcm_fs_a, 3, 28), | |
| + GROUP(pcm_clk_a, 3, 27), | |
| + | |
| + GROUP(uart_tx_a0, 4, 17), | |
| + GROUP(uart_rx_a0, 4, 16), | |
| + GROUP(uart_cts_a0, 4, 15), | |
| + GROUP(uart_rts_a0, 4, 14), | |
| + | |
| + GROUP(uart_tx_a1, 4, 13), | |
| + GROUP(uart_rx_a1, 4, 12), | |
| + GROUP(uart_cts_a1, 4, 11), | |
| + GROUP(uart_rts_a1, 4, 10), | |
| + | |
| + GROUP(uart_tx_b0, 4, 9), | |
| + GROUP(uart_rx_b0, 4, 8), | |
| + GROUP(uart_cts_b0, 4, 7), | |
| + GROUP(uart_rts_b0, 4, 6), | |
| + | |
| + GROUP(iso7816_det, 4, 21), | |
| + GROUP(iso7816_reset, 4, 20), | |
| + GROUP(iso7816_clk, 4, 19), | |
| + GROUP(iso7816_data, 4, 18), | |
| + | |
| + GROUP(i2c_sda_d0, 4, 5), | |
| + GROUP(i2c_sck_d0, 4, 4), | |
| + | |
| + GROUP(xtal_32k_out, 3, 22), | |
| + GROUP(xtal_24m_out, 3, 23), | |
| + | |
| + GROUP(pwm_e, 9, 19), | |
| + GROUP(pwm_b_x, 2, 3), | |
| + | |
| + /* bank Y */ | |
| + GROUP(uart_tx_c, 1, 19), | |
| + GROUP(uart_rx_c, 1, 18), | |
| + GROUP(uart_cts_c, 1, 17), | |
| + GROUP(uart_rts_c, 1, 16), | |
| + | |
| + GROUP(pcm_out_b, 4, 25), | |
| + GROUP(pcm_in_b, 4, 24), | |
| + GROUP(pcm_fs_b, 4, 23), | |
| + GROUP(pcm_clk_b, 4, 22), | |
| + | |
| + GROUP(i2c_sda_c0, 1, 15), | |
| + GROUP(i2c_sck_c0, 1, 14), | |
| + | |
| + GROUP(pwm_a_y, 9, 14), | |
| + | |
| + GROUP(i2s_out_ch45, 1, 10), | |
| + GROUP(i2s_out_ch23, 1, 19), | |
| + GROUP(i2s_out_ch01, 1, 6), | |
| + GROUP(i2s_in_ch01, 1, 5), | |
| + GROUP(i2s_lr_clk_in, 1, 4), | |
| + GROUP(i2s_ao_clk_in, 1, 2), | |
| + GROUP(i2s_am_clk, 1, 0), | |
| + GROUP(i2s_out_ch78, 1, 11), | |
| + | |
| + GROUP(spdif_in, 1, 8), | |
| + GROUP(spdif_out, 1, 7), | |
| + | |
| + /* bank DV */ | |
| + GROUP(dvin_rgb, 0, 6), | |
| + GROUP(dvin_vs, 0, 9), | |
| + GROUP(dvin_hs, 0, 8), | |
| + GROUP(dvin_clk, 0, 7), | |
| + GROUP(dvin_de, 0, 10), | |
| + | |
| + GROUP(enc_0, 7, 0), | |
| + GROUP(enc_1, 7, 1), | |
| + GROUP(enc_2, 7, 2), | |
| + GROUP(enc_3, 7, 3), | |
| + GROUP(enc_4, 7, 4), | |
| + GROUP(enc_5, 7, 5), | |
| + GROUP(enc_6, 7, 6), | |
| + GROUP(enc_7, 7, 7), | |
| + GROUP(enc_8, 7, 8), | |
| + GROUP(enc_9, 7, 9), | |
| + GROUP(enc_10, 7, 10), | |
| + GROUP(enc_11, 7, 11), | |
| + GROUP(enc_12, 7, 12), | |
| + GROUP(enc_13, 7, 13), | |
| + GROUP(enc_14, 7, 14), | |
| + GROUP(enc_15, 7, 15), | |
| + GROUP(enc_16, 7, 16), | |
| + GROUP(enc_17, 7, 17), | |
| + | |
| + GROUP(uart_tx_b1, 6, 23), | |
| + GROUP(uart_rx_b1, 6, 22), | |
| + GROUP(uart_cts_b1, 6, 21), | |
| + GROUP(uart_rts_b1, 6, 20), | |
| + | |
| + GROUP(vga_vs, 0, 21), | |
| + GROUP(vga_hs, 0, 20), | |
| + | |
| + GROUP(pwm_c_dv9, 3, 24), | |
| + GROUP(pwm_c_dv29, 3, 25), | |
| + GROUP(pwm_d, 3, 26), | |
| + | |
| + /* bank H */ | |
| + GROUP(hdmi_hpd, 1, 26), | |
| + GROUP(hdmi_sda, 1, 25), | |
| + GROUP(hdmi_scl, 1, 24), | |
| + GROUP(hdmi_cec, 1, 23), | |
| + | |
| + GROUP(spi_ss0_0, 9, 13), | |
| + GROUP(spi_miso_0, 9, 12), | |
| + GROUP(spi_mosi_0, 9, 11), | |
| + GROUP(spi_sclk_0, 9, 10), | |
| + | |
| + GROUP(i2c_sda_d1, 4, 3), | |
| + GROUP(i2c_sck_d1, 4, 2), | |
| + | |
| + /* bank Z */ | |
| + GROUP(spi_ss0_1, 8, 16), | |
| + GROUP(spi_ss1_1, 8, 12), | |
| + GROUP(spi_sclk_1, 8, 15), | |
| + GROUP(spi_mosi_1, 8, 14), | |
| + GROUP(spi_miso_1, 8, 13), | |
| + GROUP(spi_ss2_1, 8, 17), | |
| + | |
| + GROUP(eth_tx_clk_50m, 6, 15), | |
| + GROUP(eth_tx_en, 6, 14), | |
| + GROUP(eth_txd1, 6, 13), | |
| + GROUP(eth_txd0, 6, 12), | |
| + GROUP(eth_rx_clk_in, 6, 10), | |
| + GROUP(eth_rx_dv, 6, 11), | |
| + GROUP(eth_rxd1, 6, 8), | |
| + GROUP(eth_rxd0, 6, 7), | |
| + GROUP(eth_mdio, 6, 6), | |
| + GROUP(eth_mdc, 6, 5), | |
| + | |
| + /* NOTE: the following four groups are only available on Meson8m2: */ | |
| + GROUP(eth_rxd2, 6, 3), | |
| + GROUP(eth_rxd3, 6, 2), | |
| + GROUP(eth_txd2, 6, 1), | |
| + GROUP(eth_txd3, 6, 0), | |
| + | |
| + GROUP(i2c_sda_a0, 5, 31), | |
| + GROUP(i2c_sck_a0, 5, 30), | |
| + | |
| + GROUP(i2c_sda_b, 5, 27), | |
| + GROUP(i2c_sck_b, 5, 26), | |
| + | |
| + GROUP(i2c_sda_c1, 5, 25), | |
| + GROUP(i2c_sck_c1, 5, 24), | |
| + | |
| + GROUP(i2c_sda_a1, 5, 9), | |
| + GROUP(i2c_sck_a1, 5, 8), | |
| + | |
| + GROUP(i2c_sda_a2, 5, 7), | |
| + GROUP(i2c_sck_a2, 5, 6), | |
| + | |
| + GROUP(pwm_a_z0, 9, 16), | |
| + GROUP(pwm_a_z7, 2, 0), | |
| + GROUP(pwm_b_z, 9, 15), | |
| + GROUP(pwm_c_z, 2, 1), | |
| + | |
| + /* bank BOOT */ | |
| + GROUP(sd_d0_c, 6, 29), | |
| + GROUP(sd_d1_c, 6, 28), | |
| + GROUP(sd_d2_c, 6, 27), | |
| + GROUP(sd_d3_c, 6, 26), | |
| + GROUP(sd_cmd_c, 6, 25), | |
| + GROUP(sd_clk_c, 6, 24), | |
| + | |
| + GROUP(sdxc_d0_c, 4, 30), | |
| + GROUP(sdxc_d13_c, 4, 29), | |
| + GROUP(sdxc_d47_c, 4, 28), | |
| + GROUP(sdxc_cmd_c, 4, 27), | |
| + GROUP(sdxc_clk_c, 4, 26), | |
| + | |
| + GROUP(nand_io, 2, 26), | |
| + GROUP(nand_io_ce0, 2, 25), | |
| + GROUP(nand_io_ce1, 2, 24), | |
| + GROUP(nand_io_rb0, 2, 17), | |
| + GROUP(nand_ale, 2, 21), | |
| + GROUP(nand_cle, 2, 20), | |
| + GROUP(nand_wen_clk, 2, 19), | |
| + GROUP(nand_ren_clk, 2, 18), | |
| + GROUP(nand_dqs, 2, 27), | |
| + GROUP(nand_ce2, 2, 23), | |
| + GROUP(nand_ce3, 2, 22), | |
| + | |
| + GROUP(nor_d, 5, 1), | |
| + GROUP(nor_q, 5, 3), | |
| + GROUP(nor_c, 5, 2), | |
| + GROUP(nor_cs, 5, 0), | |
| + | |
| + /* bank CARD */ | |
| + GROUP(sd_d1_b, 2, 14), | |
| + GROUP(sd_d0_b, 2, 15), | |
| + GROUP(sd_clk_b, 2, 11), | |
| + GROUP(sd_cmd_b, 2, 10), | |
| + GROUP(sd_d3_b, 2, 12), | |
| + GROUP(sd_d2_b, 2, 13), | |
| + | |
| + GROUP(sdxc_d13_b, 2, 6), | |
| + GROUP(sdxc_d0_b, 2, 7), | |
| + GROUP(sdxc_clk_b, 2, 5), | |
| + GROUP(sdxc_cmd_b, 2, 4), | |
| +}; | |
| + | |
| +static const struct meson_pmx_group meson8_aobus_groups[] = { | |
| + GPIO_GROUP(GPIOAO_0), | |
| + GPIO_GROUP(GPIOAO_1), | |
| + GPIO_GROUP(GPIOAO_2), | |
| + GPIO_GROUP(GPIOAO_3), | |
| + GPIO_GROUP(GPIOAO_4), | |
| + GPIO_GROUP(GPIOAO_5), | |
| + GPIO_GROUP(GPIOAO_6), | |
| + GPIO_GROUP(GPIOAO_7), | |
| + GPIO_GROUP(GPIOAO_8), | |
| + GPIO_GROUP(GPIOAO_9), | |
| + GPIO_GROUP(GPIOAO_10), | |
| + GPIO_GROUP(GPIOAO_11), | |
| + GPIO_GROUP(GPIOAO_12), | |
| + GPIO_GROUP(GPIOAO_13), | |
| + GPIO_GROUP(GPIO_BSD_EN), | |
| + GPIO_GROUP(GPIO_TEST_N), | |
| + | |
| + /* bank AO */ | |
| + GROUP(uart_tx_ao_a, 0, 12), | |
| + GROUP(uart_rx_ao_a, 0, 11), | |
| + GROUP(uart_cts_ao_a, 0, 10), | |
| + GROUP(uart_rts_ao_a, 0, 9), | |
| + | |
| + GROUP(remote_input, 0, 0), | |
| + GROUP(remote_output_ao, 0, 31), | |
| + | |
| + GROUP(i2c_slave_sck_ao, 0, 2), | |
| + GROUP(i2c_slave_sda_ao, 0, 1), | |
| + | |
| + GROUP(uart_tx_ao_b0, 0, 26), | |
| + GROUP(uart_rx_ao_b0, 0, 25), | |
| + | |
| + GROUP(uart_tx_ao_b1, 0, 24), | |
| + GROUP(uart_rx_ao_b1, 0, 23), | |
| + | |
| + GROUP(i2c_mst_sck_ao, 0, 6), | |
| + GROUP(i2c_mst_sda_ao, 0, 5), | |
| + | |
| + GROUP(pwm_f_ao, 0, 19), | |
| + | |
| + GROUP(i2s_am_clk_out_ao, 0, 30), | |
| + GROUP(i2s_ao_clk_out_ao, 0, 29), | |
| + GROUP(i2s_lr_clk_out_ao, 0, 28), | |
| + GROUP(i2s_out_ch01_ao, 0, 27), | |
| + | |
| + GROUP(hdmi_cec_ao, 0, 17), | |
| +}; | |
| + | |
| +static const char * const gpio_periphs_groups[] = { | |
| + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", | |
| + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", | |
| + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", | |
| + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", | |
| + "GPIOX_20", "GPIOX_21", | |
| + | |
| + "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4", | |
| + "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9", | |
| + "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14", | |
| + "GPIOY_15", "GPIOY_16", | |
| + | |
| + "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4", | |
| + "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9", | |
| + "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14", | |
| + "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19", | |
| + "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24", | |
| + "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29", | |
| + | |
| + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", | |
| + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", | |
| + | |
| + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", | |
| + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", | |
| + "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14", | |
| + | |
| + "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4", | |
| + "CARD_5", "CARD_6", | |
| + | |
| + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", | |
| + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", | |
| + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", | |
| + "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18", | |
| +}; | |
| + | |
| +static const char * const gpio_aobus_groups[] = { | |
| + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", | |
| + "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", | |
| + "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11", | |
| + "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N" | |
| +}; | |
| + | |
| +static const char * const sd_a_groups[] = { | |
| + "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", "sd_cmd_a" | |
| +}; | |
| + | |
| +static const char * const sdxc_a_groups[] = { | |
| + "sdxc_d0_a", "sdxc_d13_a", "sdxc_d47_a", "sdxc_clk_a", "sdxc_cmd_a" | |
| +}; | |
| + | |
| +static const char * const pcm_a_groups[] = { | |
| + "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a" | |
| +}; | |
| + | |
| +static const char * const uart_a_groups[] = { | |
| + "uart_tx_a0", "uart_rx_a0", "uart_cts_a0", "uart_rts_a0", | |
| + "uart_tx_a1", "uart_rx_a1", "uart_cts_a1", "uart_rts_a1" | |
| +}; | |
| + | |
| +static const char * const uart_b_groups[] = { | |
| + "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0", | |
| + "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1" | |
| +}; | |
| + | |
| +static const char * const iso7816_groups[] = { | |
| + "iso7816_det", "iso7816_reset", "iso7816_clk", "iso7816_data" | |
| +}; | |
| + | |
| +static const char * const i2c_d_groups[] = { | |
| + "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1" | |
| +}; | |
| + | |
| +static const char * const xtal_groups[] = { | |
| + "xtal_32k_out", "xtal_24m_out" | |
| +}; | |
| + | |
| +static const char * const uart_c_groups[] = { | |
| + "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c" | |
| +}; | |
| + | |
| +static const char * const pcm_b_groups[] = { | |
| + "pcm_out_b", "pcm_in_b", "pcm_fs_b", "pcm_clk_b" | |
| +}; | |
| + | |
| +static const char * const i2c_c_groups[] = { | |
| + "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1" | |
| +}; | |
| + | |
| +static const char * const dvin_groups[] = { | |
| + "dvin_rgb", "dvin_vs", "dvin_hs", "dvin_clk", "dvin_de" | |
| +}; | |
| + | |
| +static const char * const enc_groups[] = { | |
| + "enc_0", "enc_1", "enc_2", "enc_3", "enc_4", "enc_5", | |
| + "enc_6", "enc_7", "enc_8", "enc_9", "enc_10", "enc_11", | |
| + "enc_12", "enc_13", "enc_14", "enc_15", "enc_16", "enc_17" | |
| +}; | |
| + | |
| +static const char * const vga_groups[] = { | |
| + "vga_vs", "vga_hs" | |
| +}; | |
| + | |
| +static const char * const hdmi_groups[] = { | |
| + "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec" | |
| +}; | |
| + | |
| +static const char * const spi_groups[] = { | |
| + "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0", | |
| + "spi_ss0_1", "spi_ss1_1", "spi_sclk_1", "spi_mosi_1", | |
| + "spi_miso_1", "spi_ss2_1" | |
| +}; | |
| + | |
| +static const char * const ethernet_groups[] = { | |
| + "eth_tx_clk_50m", "eth_tx_en", "eth_txd1", | |
| + "eth_txd0", "eth_rx_clk_in", "eth_rx_dv", | |
| + "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc", "eth_rxd2", | |
| + "eth_rxd3", "eth_txd2", "eth_txd3" | |
| +}; | |
| + | |
| +static const char * const i2c_a_groups[] = { | |
| + "i2c_sda_a0", "i2c_sck_a0", "i2c_sda_a1", "i2c_sck_a1", | |
| + "i2c_sda_a2", "i2c_sck_a2" | |
| +}; | |
| + | |
| +static const char * const i2c_b_groups[] = { | |
| + "i2c_sda_b", "i2c_sck_b" | |
| +}; | |
| + | |
| +static const char * const i2s_groups[] = { | |
| + "i2s_out_ch45", "i2s_out_ch23_pins", "i2s_out_ch01_pins", | |
| + "i2s_in_ch01_pins", "i2s_lr_clk_in_pins", "i2s_ao_clk_in_pins", | |
| + "i2s_am_clk_pins", "i2s_out_ch78_pins" | |
| +}; | |
| + | |
| +static const char * const sd_c_groups[] = { | |
| + "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c", | |
| + "sd_cmd_c", "sd_clk_c" | |
| +}; | |
| + | |
| +static const char * const sdxc_c_groups[] = { | |
| + "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c", | |
| + "sdxc_clk_c" | |
| +}; | |
| + | |
| +static const char * const nand_groups[] = { | |
| + "nand_io", "nand_io_ce0", "nand_io_ce1", | |
| + "nand_io_rb0", "nand_ale", "nand_cle", | |
| + "nand_wen_clk", "nand_ren_clk", "nand_dqs", | |
| + "nand_ce2", "nand_ce3" | |
| +}; | |
| + | |
| +static const char * const nor_groups[] = { | |
| + "nor_d", "nor_q", "nor_c", "nor_cs" | |
| +}; | |
| + | |
| +static const char * const pwm_a_groups[] = { | |
| + "pwm_a_y", "pwm_a_z0", "pwm_a_z7" | |
| +}; | |
| + | |
| +static const char * const pwm_b_groups[] = { | |
| + "pwm_b_x", "pwm_b_z" | |
| +}; | |
| + | |
| +static const char * const pwm_c_groups[] = { | |
| + "pwm_c_dv9", "pwm_c_dv29", "pwm_c_z" | |
| +}; | |
| + | |
| +static const char * const pwm_d_groups[] = { | |
| + "pwm_d" | |
| +}; | |
| + | |
| +static const char * const pwm_e_groups[] = { | |
| + "pwm_e" | |
| +}; | |
| + | |
| +static const char * const sd_b_groups[] = { | |
| + "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b", | |
| + "sd_d3_b", "sd_d2_b" | |
| +}; | |
| + | |
| +static const char * const sdxc_b_groups[] = { | |
| + "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b" | |
| +}; | |
| + | |
| +static const char * const spdif_groups[] = { | |
| + "spdif_in", "spdif_out" | |
| +}; | |
| + | |
| +static const char * const uart_ao_groups[] = { | |
| + "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a" | |
| +}; | |
| + | |
| +static const char * const remote_groups[] = { | |
| + "remote_input", "remote_output_ao" | |
| +}; | |
| + | |
| +static const char * const i2c_slave_ao_groups[] = { | |
| + "i2c_slave_sck_ao", "i2c_slave_sda_ao" | |
| +}; | |
| + | |
| +static const char * const uart_ao_b_groups[] = { | |
| + "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1" | |
| +}; | |
| + | |
| +static const char * const i2c_mst_ao_groups[] = { | |
| + "i2c_mst_sck_ao", "i2c_mst_sda_ao" | |
| +}; | |
| + | |
| +static const char * const pwm_f_ao_groups[] = { | |
| + "pwm_f_ao" | |
| +}; | |
| + | |
| +static const char * const i2s_ao_groups[] = { | |
| + "i2s_am_clk_out_ao", "i2s_ao_clk_out_ao", "i2s_lr_clk_out_ao", | |
| + "i2s_out_ch01_ao" | |
| +}; | |
| + | |
| +static const char * const hdmi_cec_ao_groups[] = { | |
| + "hdmi_cec_ao" | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson8_cbus_functions[] = { | |
| + FUNCTION(gpio_periphs), | |
| + FUNCTION(sd_a), | |
| + FUNCTION(sdxc_a), | |
| + FUNCTION(pcm_a), | |
| + FUNCTION(uart_a), | |
| + FUNCTION(uart_b), | |
| + FUNCTION(iso7816), | |
| + FUNCTION(i2c_d), | |
| + FUNCTION(xtal), | |
| + FUNCTION(uart_c), | |
| + FUNCTION(pcm_b), | |
| + FUNCTION(i2c_c), | |
| + FUNCTION(dvin), | |
| + FUNCTION(enc), | |
| + FUNCTION(vga), | |
| + FUNCTION(hdmi), | |
| + FUNCTION(spi), | |
| + FUNCTION(ethernet), | |
| + FUNCTION(i2c_a), | |
| + FUNCTION(i2c_b), | |
| + FUNCTION(sd_c), | |
| + FUNCTION(sdxc_c), | |
| + FUNCTION(nand), | |
| + FUNCTION(nor), | |
| + FUNCTION(sd_b), | |
| + FUNCTION(sdxc_b), | |
| + FUNCTION(pwm_a), | |
| + FUNCTION(pwm_b), | |
| + FUNCTION(pwm_c), | |
| + FUNCTION(pwm_d), | |
| + FUNCTION(pwm_e), | |
| + FUNCTION(i2s), | |
| + FUNCTION(spdif), | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson8_aobus_functions[] = { | |
| + FUNCTION(gpio_aobus), | |
| + FUNCTION(uart_ao), | |
| + FUNCTION(remote), | |
| + FUNCTION(i2c_slave_ao), | |
| + FUNCTION(uart_ao_b), | |
| + FUNCTION(i2c_mst_ao), | |
| + FUNCTION(pwm_f_ao), | |
| + FUNCTION(i2s_ao), | |
| + FUNCTION(hdmi_cec_ao), | |
| +}; | |
| + | |
| +static const struct meson_bank meson8_cbus_banks[] = { | |
| + /* name first last irq pullen pull dir out in */ | |
| + BANK("X", GPIOX_0, GPIOX_21, 112, 133, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), | |
| + BANK("Y", GPIOY_0, GPIOY_16, 95, 111, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), | |
| + BANK("DV", GPIODV_0, GPIODV_29, 65, 94, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), | |
| + BANK("H", GPIOH_0, GPIOH_9, 29, 38, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), | |
| + BANK("Z", GPIOZ_0, GPIOZ_14, 14, 28, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17), | |
| + BANK("CARD", CARD_0, CARD_6, 58, 64, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), | |
| + BANK("BOOT", BOOT_0, BOOT_18, 39, 57, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), | |
| +}; | |
| + | |
| +static const struct meson_bank meson8_aobus_banks[] = { | |
| + /* name first last irq pullen pull dir out in */ | |
| + BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0), | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data meson8_cbus_pinctrl_data = { | |
| + .name = "cbus-banks", | |
| + .pins = meson8_cbus_pins, | |
| + .groups = meson8_cbus_groups, | |
| + .funcs = meson8_cbus_functions, | |
| + .banks = meson8_cbus_banks, | |
| + .num_pins = ARRAY_SIZE(meson8_cbus_pins), | |
| + .num_groups = ARRAY_SIZE(meson8_cbus_groups), | |
| + .num_funcs = ARRAY_SIZE(meson8_cbus_functions), | |
| + .num_banks = ARRAY_SIZE(meson8_cbus_banks), | |
| + .pmx_ops = &meson8_pmx_ops, | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data meson8_aobus_pinctrl_data = { | |
| + .name = "ao-bank", | |
| + .pins = meson8_aobus_pins, | |
| + .groups = meson8_aobus_groups, | |
| + .funcs = meson8_aobus_functions, | |
| + .banks = meson8_aobus_banks, | |
| + .num_pins = ARRAY_SIZE(meson8_aobus_pins), | |
| + .num_groups = ARRAY_SIZE(meson8_aobus_groups), | |
| + .num_funcs = ARRAY_SIZE(meson8_aobus_functions), | |
| + .num_banks = ARRAY_SIZE(meson8_aobus_banks), | |
| + .pmx_ops = &meson8_pmx_ops, | |
| + .parse_dt = &meson8_aobus_parse_dt_extra, | |
| +}; | |
| + | |
| +static const struct of_device_id meson8_pinctrl_dt_match[] = { | |
| + { | |
| + .compatible = "amlogic,meson8-cbus-pinctrl", | |
| + .data = &meson8_cbus_pinctrl_data, | |
| + }, | |
| + { | |
| + .compatible = "amlogic,meson8-aobus-pinctrl", | |
| + .data = &meson8_aobus_pinctrl_data, | |
| + }, | |
| + { | |
| + .compatible = "amlogic,meson8m2-cbus-pinctrl", | |
| + .data = &meson8_cbus_pinctrl_data, | |
| + }, | |
| + { | |
| + .compatible = "amlogic,meson8m2-aobus-pinctrl", | |
| + .data = &meson8_aobus_pinctrl_data, | |
| + }, | |
| + { }, | |
| +}; | |
| + | |
| +static struct platform_driver meson8_pinctrl_driver = { | |
| + .probe = meson_pinctrl_probe, | |
| + .driver = { | |
| + .name = "meson8-pinctrl", | |
| + .of_match_table = meson8_pinctrl_dt_match, | |
| + }, | |
| +}; | |
| +builtin_platform_driver(meson8_pinctrl_driver); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c | |
| new file mode 100644 | |
| index 0000000000..a71e1f4135 | |
| --- /dev/null | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson8b.c | |
| @@ -0,0 +1,992 @@ | |
| +// SPDX-License-Identifier: GPL-2.0-only | |
| +/* | |
| + * Pin controller and GPIO driver for Amlogic Meson8b. | |
| + * | |
| + * Copyright (C) 2015 Endless Mobile, Inc. | |
| + * Author: Carlo Caione <carlo@endlessm.com> | |
| + */ | |
| + | |
| +#include <dt-bindings/gpio/meson8b-gpio.h> | |
| +#include "pinctrl-meson.h" | |
| +#include "pinctrl-meson8-pmx.h" | |
| + | |
| +static const struct pinctrl_pin_desc meson8b_cbus_pins[] = { | |
| + MESON_PIN(GPIOX_0), | |
| + MESON_PIN(GPIOX_1), | |
| + MESON_PIN(GPIOX_2), | |
| + MESON_PIN(GPIOX_3), | |
| + MESON_PIN(GPIOX_4), | |
| + MESON_PIN(GPIOX_5), | |
| + MESON_PIN(GPIOX_6), | |
| + MESON_PIN(GPIOX_7), | |
| + MESON_PIN(GPIOX_8), | |
| + MESON_PIN(GPIOX_9), | |
| + MESON_PIN(GPIOX_10), | |
| + MESON_PIN(GPIOX_11), | |
| + MESON_PIN(GPIOX_16), | |
| + MESON_PIN(GPIOX_17), | |
| + MESON_PIN(GPIOX_18), | |
| + MESON_PIN(GPIOX_19), | |
| + MESON_PIN(GPIOX_20), | |
| + MESON_PIN(GPIOX_21), | |
| + | |
| + MESON_PIN(GPIOY_0), | |
| + MESON_PIN(GPIOY_1), | |
| + MESON_PIN(GPIOY_3), | |
| + MESON_PIN(GPIOY_6), | |
| + MESON_PIN(GPIOY_7), | |
| + MESON_PIN(GPIOY_8), | |
| + MESON_PIN(GPIOY_9), | |
| + MESON_PIN(GPIOY_10), | |
| + MESON_PIN(GPIOY_11), | |
| + MESON_PIN(GPIOY_12), | |
| + MESON_PIN(GPIOY_13), | |
| + MESON_PIN(GPIOY_14), | |
| + | |
| + MESON_PIN(GPIODV_9), | |
| + MESON_PIN(GPIODV_24), | |
| + MESON_PIN(GPIODV_25), | |
| + MESON_PIN(GPIODV_26), | |
| + MESON_PIN(GPIODV_27), | |
| + MESON_PIN(GPIODV_28), | |
| + MESON_PIN(GPIODV_29), | |
| + | |
| + MESON_PIN(GPIOH_0), | |
| + MESON_PIN(GPIOH_1), | |
| + MESON_PIN(GPIOH_2), | |
| + MESON_PIN(GPIOH_3), | |
| + MESON_PIN(GPIOH_4), | |
| + MESON_PIN(GPIOH_5), | |
| + MESON_PIN(GPIOH_6), | |
| + MESON_PIN(GPIOH_7), | |
| + MESON_PIN(GPIOH_8), | |
| + MESON_PIN(GPIOH_9), | |
| + | |
| + MESON_PIN(CARD_0), | |
| + MESON_PIN(CARD_1), | |
| + MESON_PIN(CARD_2), | |
| + MESON_PIN(CARD_3), | |
| + MESON_PIN(CARD_4), | |
| + MESON_PIN(CARD_5), | |
| + MESON_PIN(CARD_6), | |
| + | |
| + MESON_PIN(BOOT_0), | |
| + MESON_PIN(BOOT_1), | |
| + MESON_PIN(BOOT_2), | |
| + MESON_PIN(BOOT_3), | |
| + MESON_PIN(BOOT_4), | |
| + MESON_PIN(BOOT_5), | |
| + MESON_PIN(BOOT_6), | |
| + MESON_PIN(BOOT_7), | |
| + MESON_PIN(BOOT_8), | |
| + MESON_PIN(BOOT_9), | |
| + MESON_PIN(BOOT_10), | |
| + MESON_PIN(BOOT_11), | |
| + MESON_PIN(BOOT_12), | |
| + MESON_PIN(BOOT_13), | |
| + MESON_PIN(BOOT_14), | |
| + MESON_PIN(BOOT_15), | |
| + MESON_PIN(BOOT_16), | |
| + MESON_PIN(BOOT_17), | |
| + MESON_PIN(BOOT_18), | |
| + | |
| + MESON_PIN(DIF_0_P), | |
| + MESON_PIN(DIF_0_N), | |
| + MESON_PIN(DIF_1_P), | |
| + MESON_PIN(DIF_1_N), | |
| + MESON_PIN(DIF_2_P), | |
| + MESON_PIN(DIF_2_N), | |
| + MESON_PIN(DIF_3_P), | |
| + MESON_PIN(DIF_3_N), | |
| + MESON_PIN(DIF_4_P), | |
| + MESON_PIN(DIF_4_N), | |
| +}; | |
| + | |
| +static const struct pinctrl_pin_desc meson8b_aobus_pins[] = { | |
| + MESON_PIN(GPIOAO_0), | |
| + MESON_PIN(GPIOAO_1), | |
| + MESON_PIN(GPIOAO_2), | |
| + MESON_PIN(GPIOAO_3), | |
| + MESON_PIN(GPIOAO_4), | |
| + MESON_PIN(GPIOAO_5), | |
| + MESON_PIN(GPIOAO_6), | |
| + MESON_PIN(GPIOAO_7), | |
| + MESON_PIN(GPIOAO_8), | |
| + MESON_PIN(GPIOAO_9), | |
| + MESON_PIN(GPIOAO_10), | |
| + MESON_PIN(GPIOAO_11), | |
| + MESON_PIN(GPIOAO_12), | |
| + MESON_PIN(GPIOAO_13), | |
| + | |
| + /* | |
| + * The following 2 pins are not mentionned in the public datasheet | |
| + * According to this datasheet, they can't be used with the gpio | |
| + * interrupt controller | |
| + */ | |
| + MESON_PIN(GPIO_BSD_EN), | |
| + MESON_PIN(GPIO_TEST_N), | |
| +}; | |
| + | |
| +/* bank X */ | |
| +static const unsigned int sd_d0_a_pins[] = { GPIOX_0 }; | |
| +static const unsigned int sd_d1_a_pins[] = { GPIOX_1 }; | |
| +static const unsigned int sd_d2_a_pins[] = { GPIOX_2 }; | |
| +static const unsigned int sd_d3_a_pins[] = { GPIOX_3 }; | |
| +static const unsigned int sdxc_d0_0_a_pins[] = { GPIOX_4 }; | |
| +static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5, | |
| + GPIOX_6, GPIOX_7 }; | |
| +static const unsigned int sdxc_d13_0_a_pins[] = { GPIOX_5, GPIOX_6, | |
| + GPIOX_7 }; | |
| +static const unsigned int sd_clk_a_pins[] = { GPIOX_8 }; | |
| +static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 }; | |
| +static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 }; | |
| +static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 }; | |
| +static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 }; | |
| +static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 }; | |
| +static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 }; | |
| +static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 }; | |
| + | |
| +static const unsigned int sdxc_d0_1_a_pins[] = { GPIOX_0 }; | |
| +static const unsigned int sdxc_d13_1_a_pins[] = { GPIOX_1, GPIOX_2, | |
| + GPIOX_3 }; | |
| +static const unsigned int pcm_out_a_pins[] = { GPIOX_4 }; | |
| +static const unsigned int pcm_in_a_pins[] = { GPIOX_5 }; | |
| +static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 }; | |
| +static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 }; | |
| +static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 }; | |
| +static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 }; | |
| +static const unsigned int pwm_vs_0_pins[] = { GPIOX_10 }; | |
| +static const unsigned int pwm_e_pins[] = { GPIOX_10 }; | |
| +static const unsigned int pwm_vs_1_pins[] = { GPIOX_11 }; | |
| + | |
| +static const unsigned int uart_tx_a_pins[] = { GPIOX_4 }; | |
| +static const unsigned int uart_rx_a_pins[] = { GPIOX_5 }; | |
| +static const unsigned int uart_cts_a_pins[] = { GPIOX_6 }; | |
| +static const unsigned int uart_rts_a_pins[] = { GPIOX_7 }; | |
| +static const unsigned int uart_tx_b1_pins[] = { GPIOX_8 }; | |
| +static const unsigned int uart_rx_b1_pins[] = { GPIOX_9 }; | |
| +static const unsigned int uart_cts_b1_pins[] = { GPIOX_10 }; | |
| +static const unsigned int uart_rts_b1_pins[] = { GPIOX_20 }; | |
| + | |
| +static const unsigned int iso7816_0_clk_pins[] = { GPIOX_6 }; | |
| +static const unsigned int iso7816_0_data_pins[] = { GPIOX_7 }; | |
| +static const unsigned int spi_sclk_0_pins[] = { GPIOX_8 }; | |
| +static const unsigned int spi_miso_0_pins[] = { GPIOX_9 }; | |
| +static const unsigned int spi_mosi_0_pins[] = { GPIOX_10 }; | |
| +static const unsigned int iso7816_det_pins[] = { GPIOX_16 }; | |
| +static const unsigned int iso7816_reset_pins[] = { GPIOX_17 }; | |
| +static const unsigned int iso7816_1_clk_pins[] = { GPIOX_18 }; | |
| +static const unsigned int iso7816_1_data_pins[] = { GPIOX_19 }; | |
| +static const unsigned int spi_ss0_0_pins[] = { GPIOX_20 }; | |
| + | |
| +static const unsigned int tsin_clk_b_pins[] = { GPIOX_8 }; | |
| +static const unsigned int tsin_sop_b_pins[] = { GPIOX_9 }; | |
| +static const unsigned int tsin_d0_b_pins[] = { GPIOX_10 }; | |
| +static const unsigned int pwm_b_pins[] = { GPIOX_11 }; | |
| +static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 }; | |
| +static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 }; | |
| +static const unsigned int tsin_d_valid_b_pins[] = { GPIOX_20 }; | |
| + | |
| +/* bank Y */ | |
| +static const unsigned int tsin_d_valid_a_pins[] = { GPIOY_0 }; | |
| +static const unsigned int tsin_sop_a_pins[] = { GPIOY_1 }; | |
| +static const unsigned int tsin_d17_a_pins[] = { | |
| + GPIOY_6, GPIOY_7, GPIOY_10, GPIOY_11, GPIOY_12, GPIOY_13, GPIOY_14, | |
| +}; | |
| +static const unsigned int tsin_clk_a_pins[] = { GPIOY_8 }; | |
| +static const unsigned int tsin_d0_a_pins[] = { GPIOY_9 }; | |
| + | |
| +static const unsigned int spdif_out_0_pins[] = { GPIOY_3 }; | |
| + | |
| +static const unsigned int xtal_24m_pins[] = { GPIOY_3 }; | |
| +static const unsigned int iso7816_2_clk_pins[] = { GPIOY_13 }; | |
| +static const unsigned int iso7816_2_data_pins[] = { GPIOY_14 }; | |
| + | |
| +/* bank DV */ | |
| +static const unsigned int pwm_d_pins[] = { GPIODV_28 }; | |
| +static const unsigned int pwm_c0_pins[] = { GPIODV_29 }; | |
| + | |
| +static const unsigned int pwm_vs_2_pins[] = { GPIODV_9 }; | |
| +static const unsigned int pwm_vs_3_pins[] = { GPIODV_28 }; | |
| +static const unsigned int pwm_vs_4_pins[] = { GPIODV_29 }; | |
| + | |
| +static const unsigned int xtal24_out_pins[] = { GPIODV_29 }; | |
| + | |
| +static const unsigned int uart_tx_c_pins[] = { GPIODV_24 }; | |
| +static const unsigned int uart_rx_c_pins[] = { GPIODV_25 }; | |
| +static const unsigned int uart_cts_c_pins[] = { GPIODV_26 }; | |
| +static const unsigned int uart_rts_c_pins[] = { GPIODV_27 }; | |
| + | |
| +static const unsigned int pwm_c1_pins[] = { GPIODV_9 }; | |
| + | |
| +static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 }; | |
| +static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 }; | |
| +static const unsigned int i2c_sda_b0_pins[] = { GPIODV_26 }; | |
| +static const unsigned int i2c_sck_b0_pins[] = { GPIODV_27 }; | |
| +static const unsigned int i2c_sda_c0_pins[] = { GPIODV_28 }; | |
| +static const unsigned int i2c_sck_c0_pins[] = { GPIODV_29 }; | |
| + | |
| +/* bank H */ | |
| +static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 }; | |
| +static const unsigned int hdmi_sda_pins[] = { GPIOH_1 }; | |
| +static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; | |
| +static const unsigned int hdmi_cec_0_pins[] = { GPIOH_3 }; | |
| +static const unsigned int eth_txd1_0_pins[] = { GPIOH_5 }; | |
| +static const unsigned int eth_txd0_0_pins[] = { GPIOH_6 }; | |
| +static const unsigned int eth_rxd3_h_pins[] = { GPIOH_5 }; | |
| +static const unsigned int eth_rxd2_h_pins[] = { GPIOH_6 }; | |
| +static const unsigned int clk_24m_out_pins[] = { GPIOH_9 }; | |
| + | |
| +static const unsigned int spi_ss1_pins[] = { GPIOH_0 }; | |
| +static const unsigned int spi_ss2_pins[] = { GPIOH_1 }; | |
| +static const unsigned int spi_ss0_1_pins[] = { GPIOH_3 }; | |
| +static const unsigned int spi_miso_1_pins[] = { GPIOH_4 }; | |
| +static const unsigned int spi_mosi_1_pins[] = { GPIOH_5 }; | |
| +static const unsigned int spi_sclk_1_pins[] = { GPIOH_6 }; | |
| + | |
| +static const unsigned int eth_txd3_pins[] = { GPIOH_7 }; | |
| +static const unsigned int eth_txd2_pins[] = { GPIOH_8 }; | |
| +static const unsigned int eth_tx_clk_pins[] = { GPIOH_9 }; | |
| + | |
| +static const unsigned int i2c_sda_b1_pins[] = { GPIOH_3 }; | |
| +static const unsigned int i2c_sck_b1_pins[] = { GPIOH_4 }; | |
| +static const unsigned int i2c_sda_c1_pins[] = { GPIOH_5 }; | |
| +static const unsigned int i2c_sck_c1_pins[] = { GPIOH_6 }; | |
| +static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 }; | |
| +static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 }; | |
| + | |
| +/* bank BOOT */ | |
| +static const unsigned int nand_io_pins[] = { | |
| + BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7 | |
| +}; | |
| +static const unsigned int nand_io_ce0_pins[] = { BOOT_8 }; | |
| +static const unsigned int nand_io_ce1_pins[] = { BOOT_9 }; | |
| +static const unsigned int nand_io_rb0_pins[] = { BOOT_10 }; | |
| +static const unsigned int nand_ale_pins[] = { BOOT_11 }; | |
| +static const unsigned int nand_cle_pins[] = { BOOT_12 }; | |
| +static const unsigned int nand_wen_clk_pins[] = { BOOT_13 }; | |
| +static const unsigned int nand_ren_clk_pins[] = { BOOT_14 }; | |
| +static const unsigned int nand_dqs_15_pins[] = { BOOT_15 }; | |
| +static const unsigned int nand_dqs_18_pins[] = { BOOT_18 }; | |
| + | |
| +static const unsigned int sdxc_d0_c_pins[] = { BOOT_0}; | |
| +static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2, | |
| + BOOT_3 }; | |
| +static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5, | |
| + BOOT_6, BOOT_7 }; | |
| +static const unsigned int sdxc_clk_c_pins[] = { BOOT_8 }; | |
| +static const unsigned int sdxc_cmd_c_pins[] = { BOOT_10 }; | |
| +static const unsigned int nor_d_pins[] = { BOOT_11 }; | |
| +static const unsigned int nor_q_pins[] = { BOOT_12 }; | |
| +static const unsigned int nor_c_pins[] = { BOOT_13 }; | |
| +static const unsigned int nor_cs_pins[] = { BOOT_18 }; | |
| + | |
| +static const unsigned int sd_d0_c_pins[] = { BOOT_0 }; | |
| +static const unsigned int sd_d1_c_pins[] = { BOOT_1 }; | |
| +static const unsigned int sd_d2_c_pins[] = { BOOT_2 }; | |
| +static const unsigned int sd_d3_c_pins[] = { BOOT_3 }; | |
| +static const unsigned int sd_cmd_c_pins[] = { BOOT_8 }; | |
| +static const unsigned int sd_clk_c_pins[] = { BOOT_10 }; | |
| + | |
| +/* bank CARD */ | |
| +static const unsigned int sd_d1_b_pins[] = { CARD_0 }; | |
| +static const unsigned int sd_d0_b_pins[] = { CARD_1 }; | |
| +static const unsigned int sd_clk_b_pins[] = { CARD_2 }; | |
| +static const unsigned int sd_cmd_b_pins[] = { CARD_3 }; | |
| +static const unsigned int sd_d3_b_pins[] = { CARD_4 }; | |
| +static const unsigned int sd_d2_b_pins[] = { CARD_5 }; | |
| + | |
| +static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4, | |
| + CARD_5 }; | |
| +static const unsigned int sdxc_d0_b_pins[] = { CARD_1 }; | |
| +static const unsigned int sdxc_clk_b_pins[] = { CARD_2 }; | |
| +static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 }; | |
| + | |
| +/* bank AO */ | |
| +static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 }; | |
| +static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 }; | |
| +static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 }; | |
| +static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 }; | |
| +static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 }; | |
| +static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 }; | |
| +static const unsigned int clk_32k_in_out_pins[] = { GPIOAO_6 }; | |
| +static const unsigned int remote_input_pins[] = { GPIOAO_7 }; | |
| +static const unsigned int hdmi_cec_1_pins[] = { GPIOAO_12 }; | |
| +static const unsigned int ir_blaster_pins[] = { GPIOAO_13 }; | |
| + | |
| +static const unsigned int pwm_c2_pins[] = { GPIOAO_3 }; | |
| +static const unsigned int i2c_sck_ao_pins[] = { GPIOAO_4 }; | |
| +static const unsigned int i2c_sda_ao_pins[] = { GPIOAO_5 }; | |
| +static const unsigned int ir_remote_out_pins[] = { GPIOAO_7 }; | |
| +static const unsigned int i2s_am_clk_out_pins[] = { GPIOAO_8 }; | |
| +static const unsigned int i2s_ao_clk_out_pins[] = { GPIOAO_9 }; | |
| +static const unsigned int i2s_lr_clk_out_pins[] = { GPIOAO_10 }; | |
| +static const unsigned int i2s_out_01_pins[] = { GPIOAO_11 }; | |
| + | |
| +static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 }; | |
| +static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 }; | |
| +static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 }; | |
| +static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 }; | |
| +static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 }; | |
| +static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 }; | |
| +static const unsigned int spdif_out_1_pins[] = { GPIOAO_6 }; | |
| + | |
| +static const unsigned int i2s_in_ch01_pins[] = { GPIOAO_6 }; | |
| +static const unsigned int i2s_ao_clk_in_pins[] = { GPIOAO_9 }; | |
| +static const unsigned int i2s_lr_clk_in_pins[] = { GPIOAO_10 }; | |
| + | |
| +/* bank DIF */ | |
| +static const unsigned int eth_rxd1_pins[] = { DIF_0_P }; | |
| +static const unsigned int eth_rxd0_pins[] = { DIF_0_N }; | |
| +static const unsigned int eth_rx_dv_pins[] = { DIF_1_P }; | |
| +static const unsigned int eth_rx_clk_pins[] = { DIF_1_N }; | |
| +static const unsigned int eth_txd0_1_pins[] = { DIF_2_P }; | |
| +static const unsigned int eth_txd1_1_pins[] = { DIF_2_N }; | |
| +static const unsigned int eth_rxd3_pins[] = { DIF_2_P }; | |
| +static const unsigned int eth_rxd2_pins[] = { DIF_2_N }; | |
| +static const unsigned int eth_tx_en_pins[] = { DIF_3_P }; | |
| +static const unsigned int eth_ref_clk_pins[] = { DIF_3_N }; | |
| +static const unsigned int eth_mdc_pins[] = { DIF_4_P }; | |
| +static const unsigned int eth_mdio_en_pins[] = { DIF_4_N }; | |
| + | |
| +static const struct meson_pmx_group meson8b_cbus_groups[] = { | |
| + GPIO_GROUP(GPIOX_0), | |
| + GPIO_GROUP(GPIOX_1), | |
| + GPIO_GROUP(GPIOX_2), | |
| + GPIO_GROUP(GPIOX_3), | |
| + GPIO_GROUP(GPIOX_4), | |
| + GPIO_GROUP(GPIOX_5), | |
| + GPIO_GROUP(GPIOX_6), | |
| + GPIO_GROUP(GPIOX_7), | |
| + GPIO_GROUP(GPIOX_8), | |
| + GPIO_GROUP(GPIOX_9), | |
| + GPIO_GROUP(GPIOX_10), | |
| + GPIO_GROUP(GPIOX_11), | |
| + GPIO_GROUP(GPIOX_16), | |
| + GPIO_GROUP(GPIOX_17), | |
| + GPIO_GROUP(GPIOX_18), | |
| + GPIO_GROUP(GPIOX_19), | |
| + GPIO_GROUP(GPIOX_20), | |
| + GPIO_GROUP(GPIOX_21), | |
| + | |
| + GPIO_GROUP(GPIOY_0), | |
| + GPIO_GROUP(GPIOY_1), | |
| + GPIO_GROUP(GPIOY_3), | |
| + GPIO_GROUP(GPIOY_6), | |
| + GPIO_GROUP(GPIOY_7), | |
| + GPIO_GROUP(GPIOY_8), | |
| + GPIO_GROUP(GPIOY_9), | |
| + GPIO_GROUP(GPIOY_10), | |
| + GPIO_GROUP(GPIOY_11), | |
| + GPIO_GROUP(GPIOY_12), | |
| + GPIO_GROUP(GPIOY_13), | |
| + GPIO_GROUP(GPIOY_14), | |
| + | |
| + GPIO_GROUP(GPIODV_9), | |
| + GPIO_GROUP(GPIODV_24), | |
| + GPIO_GROUP(GPIODV_25), | |
| + GPIO_GROUP(GPIODV_26), | |
| + GPIO_GROUP(GPIODV_27), | |
| + GPIO_GROUP(GPIODV_28), | |
| + GPIO_GROUP(GPIODV_29), | |
| + | |
| + GPIO_GROUP(GPIOH_0), | |
| + GPIO_GROUP(GPIOH_1), | |
| + GPIO_GROUP(GPIOH_2), | |
| + GPIO_GROUP(GPIOH_3), | |
| + GPIO_GROUP(GPIOH_4), | |
| + GPIO_GROUP(GPIOH_5), | |
| + GPIO_GROUP(GPIOH_6), | |
| + GPIO_GROUP(GPIOH_7), | |
| + GPIO_GROUP(GPIOH_8), | |
| + GPIO_GROUP(GPIOH_9), | |
| + | |
| + GPIO_GROUP(CARD_0), | |
| + GPIO_GROUP(CARD_1), | |
| + GPIO_GROUP(CARD_2), | |
| + GPIO_GROUP(CARD_3), | |
| + GPIO_GROUP(CARD_4), | |
| + GPIO_GROUP(CARD_5), | |
| + GPIO_GROUP(CARD_6), | |
| + | |
| + GPIO_GROUP(BOOT_0), | |
| + GPIO_GROUP(BOOT_1), | |
| + GPIO_GROUP(BOOT_2), | |
| + GPIO_GROUP(BOOT_3), | |
| + GPIO_GROUP(BOOT_4), | |
| + GPIO_GROUP(BOOT_5), | |
| + GPIO_GROUP(BOOT_6), | |
| + GPIO_GROUP(BOOT_7), | |
| + GPIO_GROUP(BOOT_8), | |
| + GPIO_GROUP(BOOT_9), | |
| + GPIO_GROUP(BOOT_10), | |
| + GPIO_GROUP(BOOT_11), | |
| + GPIO_GROUP(BOOT_12), | |
| + GPIO_GROUP(BOOT_13), | |
| + GPIO_GROUP(BOOT_14), | |
| + GPIO_GROUP(BOOT_15), | |
| + GPIO_GROUP(BOOT_16), | |
| + GPIO_GROUP(BOOT_17), | |
| + GPIO_GROUP(BOOT_18), | |
| + | |
| + GPIO_GROUP(DIF_0_P), | |
| + GPIO_GROUP(DIF_0_N), | |
| + GPIO_GROUP(DIF_1_P), | |
| + GPIO_GROUP(DIF_1_N), | |
| + GPIO_GROUP(DIF_2_P), | |
| + GPIO_GROUP(DIF_2_N), | |
| + GPIO_GROUP(DIF_3_P), | |
| + GPIO_GROUP(DIF_3_N), | |
| + GPIO_GROUP(DIF_4_P), | |
| + GPIO_GROUP(DIF_4_N), | |
| + | |
| + /* bank X */ | |
| + GROUP(sd_d0_a, 8, 5), | |
| + GROUP(sd_d1_a, 8, 4), | |
| + GROUP(sd_d2_a, 8, 3), | |
| + GROUP(sd_d3_a, 8, 2), | |
| + GROUP(sdxc_d0_0_a, 5, 29), | |
| + GROUP(sdxc_d47_a, 5, 12), | |
| + GROUP(sdxc_d13_0_a, 5, 28), | |
| + GROUP(sd_clk_a, 8, 1), | |
| + GROUP(sd_cmd_a, 8, 0), | |
| + GROUP(xtal_32k_out, 3, 22), | |
| + GROUP(xtal_24m_out, 3, 20), | |
| + GROUP(uart_tx_b0, 4, 9), | |
| + GROUP(uart_rx_b0, 4, 8), | |
| + GROUP(uart_cts_b0, 4, 7), | |
| + GROUP(uart_rts_b0, 4, 6), | |
| + GROUP(sdxc_d0_1_a, 5, 14), | |
| + GROUP(sdxc_d13_1_a, 5, 13), | |
| + GROUP(pcm_out_a, 3, 30), | |
| + GROUP(pcm_in_a, 3, 29), | |
| + GROUP(pcm_fs_a, 3, 28), | |
| + GROUP(pcm_clk_a, 3, 27), | |
| + GROUP(sdxc_clk_a, 5, 11), | |
| + GROUP(sdxc_cmd_a, 5, 10), | |
| + GROUP(pwm_vs_0, 7, 31), | |
| + GROUP(pwm_e, 9, 19), | |
| + GROUP(pwm_vs_1, 7, 30), | |
| + GROUP(uart_tx_a, 4, 17), | |
| + GROUP(uart_rx_a, 4, 16), | |
| + GROUP(uart_cts_a, 4, 15), | |
| + GROUP(uart_rts_a, 4, 14), | |
| + GROUP(uart_tx_b1, 6, 19), | |
| + GROUP(uart_rx_b1, 6, 18), | |
| + GROUP(uart_cts_b1, 6, 17), | |
| + GROUP(uart_rts_b1, 6, 16), | |
| + GROUP(iso7816_0_clk, 5, 9), | |
| + GROUP(iso7816_0_data, 5, 8), | |
| + GROUP(spi_sclk_0, 4, 22), | |
| + GROUP(spi_miso_0, 4, 24), | |
| + GROUP(spi_mosi_0, 4, 23), | |
| + GROUP(iso7816_det, 4, 21), | |
| + GROUP(iso7816_reset, 4, 20), | |
| + GROUP(iso7816_1_clk, 4, 19), | |
| + GROUP(iso7816_1_data, 4, 18), | |
| + GROUP(spi_ss0_0, 4, 25), | |
| + GROUP(tsin_clk_b, 3, 6), | |
| + GROUP(tsin_sop_b, 3, 7), | |
| + GROUP(tsin_d0_b, 3, 8), | |
| + GROUP(pwm_b, 2, 3), | |
| + GROUP(i2c_sda_d0, 4, 5), | |
| + GROUP(i2c_sck_d0, 4, 4), | |
| + GROUP(tsin_d_valid_b, 3, 9), | |
| + | |
| + /* bank Y */ | |
| + GROUP(tsin_d_valid_a, 3, 2), | |
| + GROUP(tsin_sop_a, 3, 1), | |
| + GROUP(tsin_d17_a, 3, 5), | |
| + GROUP(tsin_clk_a, 3, 0), | |
| + GROUP(tsin_d0_a, 3, 4), | |
| + GROUP(spdif_out_0, 1, 7), | |
| + GROUP(xtal_24m, 3, 18), | |
| + GROUP(iso7816_2_clk, 5, 7), | |
| + GROUP(iso7816_2_data, 5, 6), | |
| + | |
| + /* bank DV */ | |
| + GROUP(pwm_d, 3, 26), | |
| + GROUP(pwm_c0, 3, 25), | |
| + GROUP(pwm_vs_2, 7, 28), | |
| + GROUP(pwm_vs_3, 7, 27), | |
| + GROUP(pwm_vs_4, 7, 26), | |
| + GROUP(xtal24_out, 7, 25), | |
| + GROUP(uart_tx_c, 6, 23), | |
| + GROUP(uart_rx_c, 6, 22), | |
| + GROUP(uart_cts_c, 6, 21), | |
| + GROUP(uart_rts_c, 6, 20), | |
| + GROUP(pwm_c1, 3, 24), | |
| + GROUP(i2c_sda_a, 9, 31), | |
| + GROUP(i2c_sck_a, 9, 30), | |
| + GROUP(i2c_sda_b0, 9, 29), | |
| + GROUP(i2c_sck_b0, 9, 28), | |
| + GROUP(i2c_sda_c0, 9, 27), | |
| + GROUP(i2c_sck_c0, 9, 26), | |
| + | |
| + /* bank H */ | |
| + GROUP(hdmi_hpd, 1, 26), | |
| + GROUP(hdmi_sda, 1, 25), | |
| + GROUP(hdmi_scl, 1, 24), | |
| + GROUP(hdmi_cec_0, 1, 23), | |
| + GROUP(eth_txd1_0, 7, 21), | |
| + GROUP(eth_txd0_0, 7, 20), | |
| + GROUP(clk_24m_out, 4, 1), | |
| + GROUP(spi_ss1, 8, 11), | |
| + GROUP(spi_ss2, 8, 12), | |
| + GROUP(spi_ss0_1, 9, 13), | |
| + GROUP(spi_miso_1, 9, 12), | |
| + GROUP(spi_mosi_1, 9, 11), | |
| + GROUP(spi_sclk_1, 9, 10), | |
| + GROUP(eth_rxd3_h, 6, 15), | |
| + GROUP(eth_rxd2_h, 6, 14), | |
| + GROUP(eth_txd3, 6, 13), | |
| + GROUP(eth_txd2, 6, 12), | |
| + GROUP(eth_tx_clk, 6, 11), | |
| + GROUP(i2c_sda_b1, 5, 27), | |
| + GROUP(i2c_sck_b1, 5, 26), | |
| + GROUP(i2c_sda_c1, 5, 25), | |
| + GROUP(i2c_sck_c1, 5, 24), | |
| + GROUP(i2c_sda_d1, 4, 3), | |
| + GROUP(i2c_sck_d1, 4, 2), | |
| + | |
| + /* bank BOOT */ | |
| + GROUP(nand_io, 2, 26), | |
| + GROUP(nand_io_ce0, 2, 25), | |
| + GROUP(nand_io_ce1, 2, 24), | |
| + GROUP(nand_io_rb0, 2, 17), | |
| + GROUP(nand_ale, 2, 21), | |
| + GROUP(nand_cle, 2, 20), | |
| + GROUP(nand_wen_clk, 2, 19), | |
| + GROUP(nand_ren_clk, 2, 18), | |
| + GROUP(nand_dqs_15, 2, 27), | |
| + GROUP(nand_dqs_18, 2, 28), | |
| + GROUP(sdxc_d0_c, 4, 30), | |
| + GROUP(sdxc_d13_c, 4, 29), | |
| + GROUP(sdxc_d47_c, 4, 28), | |
| + GROUP(sdxc_clk_c, 7, 19), | |
| + GROUP(sdxc_cmd_c, 7, 18), | |
| + GROUP(nor_d, 5, 1), | |
| + GROUP(nor_q, 5, 3), | |
| + GROUP(nor_c, 5, 2), | |
| + GROUP(nor_cs, 5, 0), | |
| + GROUP(sd_d0_c, 6, 29), | |
| + GROUP(sd_d1_c, 6, 28), | |
| + GROUP(sd_d2_c, 6, 27), | |
| + GROUP(sd_d3_c, 6, 26), | |
| + GROUP(sd_cmd_c, 6, 30), | |
| + GROUP(sd_clk_c, 6, 31), | |
| + | |
| + /* bank CARD */ | |
| + GROUP(sd_d1_b, 2, 14), | |
| + GROUP(sd_d0_b, 2, 15), | |
| + GROUP(sd_clk_b, 2, 11), | |
| + GROUP(sd_cmd_b, 2, 10), | |
| + GROUP(sd_d3_b, 2, 12), | |
| + GROUP(sd_d2_b, 2, 13), | |
| + GROUP(sdxc_d13_b, 2, 6), | |
| + GROUP(sdxc_d0_b, 2, 7), | |
| + GROUP(sdxc_clk_b, 2, 5), | |
| + GROUP(sdxc_cmd_b, 2, 4), | |
| + | |
| + /* bank DIF */ | |
| + GROUP(eth_rxd1, 6, 0), | |
| + GROUP(eth_rxd0, 6, 1), | |
| + GROUP(eth_rx_dv, 6, 2), | |
| + GROUP(eth_rx_clk, 6, 3), | |
| + GROUP(eth_txd0_1, 6, 4), | |
| + GROUP(eth_txd1_1, 6, 5), | |
| + GROUP(eth_tx_en, 6, 6), | |
| + GROUP(eth_ref_clk, 6, 8), | |
| + GROUP(eth_mdc, 6, 9), | |
| + GROUP(eth_mdio_en, 6, 10), | |
| + GROUP(eth_rxd3, 7, 22), | |
| + GROUP(eth_rxd2, 7, 23), | |
| +}; | |
| + | |
| +static const struct meson_pmx_group meson8b_aobus_groups[] = { | |
| + GPIO_GROUP(GPIOAO_0), | |
| + GPIO_GROUP(GPIOAO_1), | |
| + GPIO_GROUP(GPIOAO_2), | |
| + GPIO_GROUP(GPIOAO_3), | |
| + GPIO_GROUP(GPIOAO_4), | |
| + GPIO_GROUP(GPIOAO_5), | |
| + GPIO_GROUP(GPIOAO_6), | |
| + GPIO_GROUP(GPIOAO_7), | |
| + GPIO_GROUP(GPIOAO_8), | |
| + GPIO_GROUP(GPIOAO_9), | |
| + GPIO_GROUP(GPIOAO_10), | |
| + GPIO_GROUP(GPIOAO_11), | |
| + GPIO_GROUP(GPIOAO_12), | |
| + GPIO_GROUP(GPIOAO_13), | |
| + GPIO_GROUP(GPIO_BSD_EN), | |
| + GPIO_GROUP(GPIO_TEST_N), | |
| + | |
| + /* bank AO */ | |
| + GROUP(uart_tx_ao_a, 0, 12), | |
| + GROUP(uart_rx_ao_a, 0, 11), | |
| + GROUP(uart_cts_ao_a, 0, 10), | |
| + GROUP(uart_rts_ao_a, 0, 9), | |
| + GROUP(i2c_mst_sck_ao, 0, 6), | |
| + GROUP(i2c_mst_sda_ao, 0, 5), | |
| + GROUP(clk_32k_in_out, 0, 18), | |
| + GROUP(remote_input, 0, 0), | |
| + GROUP(hdmi_cec_1, 0, 17), | |
| + GROUP(ir_blaster, 0, 31), | |
| + GROUP(pwm_c2, 0, 22), | |
| + GROUP(i2c_sck_ao, 0, 2), | |
| + GROUP(i2c_sda_ao, 0, 1), | |
| + GROUP(ir_remote_out, 0, 21), | |
| + GROUP(i2s_am_clk_out, 0, 30), | |
| + GROUP(i2s_ao_clk_out, 0, 29), | |
| + GROUP(i2s_lr_clk_out, 0, 28), | |
| + GROUP(i2s_out_01, 0, 27), | |
| + GROUP(uart_tx_ao_b0, 0, 26), | |
| + GROUP(uart_rx_ao_b0, 0, 25), | |
| + GROUP(uart_cts_ao_b, 0, 8), | |
| + GROUP(uart_rts_ao_b, 0, 7), | |
| + GROUP(uart_tx_ao_b1, 0, 24), | |
| + GROUP(uart_rx_ao_b1, 0, 23), | |
| + GROUP(spdif_out_1, 0, 16), | |
| + GROUP(i2s_in_ch01, 0, 13), | |
| + GROUP(i2s_ao_clk_in, 0, 15), | |
| + GROUP(i2s_lr_clk_in, 0, 14), | |
| +}; | |
| + | |
| +static const char * const gpio_periphs_groups[] = { | |
| + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", | |
| + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", | |
| + "GPIOX_10", "GPIOX_11", "GPIOX_16", "GPIOX_17", "GPIOX_18", | |
| + "GPIOX_19", "GPIOX_20", "GPIOX_21", | |
| + | |
| + "GPIOY_0", "GPIOY_1", "GPIOY_3", "GPIOY_6", "GPIOY_7", | |
| + "GPIOY_8", "GPIOY_9", "GPIOY_10", "GPIOY_11", "GPIOY_12", | |
| + "GPIOY_13", "GPIOY_14", | |
| + | |
| + "GPIODV_9", "GPIODV_24", "GPIODV_25", "GPIODV_26", | |
| + "GPIODV_27", "GPIODV_28", "GPIODV_29", | |
| + | |
| + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", | |
| + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", | |
| + | |
| + "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4", | |
| + "CARD_5", "CARD_6", | |
| + | |
| + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", | |
| + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", | |
| + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", | |
| + "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18", | |
| + | |
| + "DIF_0_P", "DIF_0_N", "DIF_1_P", "DIF_1_N", | |
| + "DIF_2_P", "DIF_2_N", "DIF_3_P", "DIF_3_N", | |
| + "DIF_4_P", "DIF_4_N" | |
| +}; | |
| + | |
| +static const char * const gpio_aobus_groups[] = { | |
| + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", | |
| + "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", | |
| + "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11", | |
| + "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N" | |
| +}; | |
| + | |
| +static const char * const sd_a_groups[] = { | |
| + "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", | |
| + "sd_cmd_a" | |
| +}; | |
| + | |
| +static const char * const sdxc_a_groups[] = { | |
| + "sdxc_d0_0_a", "sdxc_d13_0_a", "sdxc_d47_a", "sdxc_clk_a", | |
| + "sdxc_cmd_a", "sdxc_d0_1_a", "sdxc_d13_1_a" | |
| +}; | |
| + | |
| +static const char * const pcm_a_groups[] = { | |
| + "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a" | |
| +}; | |
| + | |
| +static const char * const uart_a_groups[] = { | |
| + "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a" | |
| +}; | |
| + | |
| +static const char * const uart_b_groups[] = { | |
| + "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0", | |
| + "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1" | |
| +}; | |
| + | |
| +static const char * const iso7816_groups[] = { | |
| + "iso7816_det", "iso7816_reset", "iso7816_0_clk", "iso7816_0_data", | |
| + "iso7816_1_clk", "iso7816_1_data", "iso7816_2_clk", "iso7816_2_data" | |
| +}; | |
| + | |
| +static const char * const i2c_d_groups[] = { | |
| + "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1" | |
| +}; | |
| + | |
| +static const char * const xtal_groups[] = { | |
| + "xtal_32k_out", "xtal_24m_out", "xtal_24m", "xtal24_out" | |
| +}; | |
| + | |
| +static const char * const uart_c_groups[] = { | |
| + "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c" | |
| +}; | |
| + | |
| +static const char * const i2c_c_groups[] = { | |
| + "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1" | |
| +}; | |
| + | |
| +static const char * const hdmi_groups[] = { | |
| + "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0" | |
| +}; | |
| + | |
| +static const char * const hdmi_cec_groups[] = { | |
| + "hdmi_cec_1" | |
| +}; | |
| + | |
| +static const char * const spi_groups[] = { | |
| + "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0", | |
| + "spi_ss0_1", "spi_ss1", "spi_sclk_1", "spi_mosi_1", | |
| + "spi_miso_1", "spi_ss2" | |
| +}; | |
| + | |
| +static const char * const ethernet_groups[] = { | |
| + "eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1", | |
| + "eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv", | |
| + "eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk", | |
| + "eth_txd2", "eth_txd3", "eth_rxd3", "eth_rxd2", | |
| + "eth_rxd3_h", "eth_rxd2_h" | |
| +}; | |
| + | |
| +static const char * const i2c_a_groups[] = { | |
| + "i2c_sda_a", "i2c_sck_a", | |
| +}; | |
| + | |
| +static const char * const i2c_b_groups[] = { | |
| + "i2c_sda_b0", "i2c_sck_b0", "i2c_sda_b1", "i2c_sck_b1" | |
| +}; | |
| + | |
| +static const char * const sd_c_groups[] = { | |
| + "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c", | |
| + "sd_cmd_c", "sd_clk_c" | |
| +}; | |
| + | |
| +static const char * const sdxc_c_groups[] = { | |
| + "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c", | |
| + "sdxc_clk_c" | |
| +}; | |
| + | |
| +static const char * const nand_groups[] = { | |
| + "nand_io", "nand_io_ce0", "nand_io_ce1", | |
| + "nand_io_rb0", "nand_ale", "nand_cle", | |
| + "nand_wen_clk", "nand_ren_clk", "nand_dqs_15", | |
| + "nand_dqs_18" | |
| +}; | |
| + | |
| +static const char * const nor_groups[] = { | |
| + "nor_d", "nor_q", "nor_c", "nor_cs" | |
| +}; | |
| + | |
| +static const char * const sd_b_groups[] = { | |
| + "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b", | |
| + "sd_d3_b", "sd_d2_b" | |
| +}; | |
| + | |
| +static const char * const sdxc_b_groups[] = { | |
| + "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b" | |
| +}; | |
| + | |
| +static const char * const uart_ao_groups[] = { | |
| + "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a" | |
| +}; | |
| + | |
| +static const char * const remote_groups[] = { | |
| + "remote_input", "ir_blaster", "ir_remote_out" | |
| +}; | |
| + | |
| +static const char * const i2c_slave_ao_groups[] = { | |
| + "i2c_sck_ao", "i2c_sda_ao" | |
| +}; | |
| + | |
| +static const char * const uart_ao_b_groups[] = { | |
| + "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1", | |
| + "uart_cts_ao_b", "uart_rts_ao_b" | |
| +}; | |
| + | |
| +static const char * const i2c_mst_ao_groups[] = { | |
| + "i2c_mst_sck_ao", "i2c_mst_sda_ao" | |
| +}; | |
| + | |
| +static const char * const clk_24m_groups[] = { | |
| + "clk_24m_out" | |
| +}; | |
| + | |
| +static const char * const clk_32k_groups[] = { | |
| + "clk_32k_in_out" | |
| +}; | |
| + | |
| +static const char * const spdif_0_groups[] = { | |
| + "spdif_out_0" | |
| +}; | |
| + | |
| +static const char * const spdif_1_groups[] = { | |
| + "spdif_out_1" | |
| +}; | |
| + | |
| +static const char * const i2s_groups[] = { | |
| + "i2s_am_clk_out", "i2s_ao_clk_out", "i2s_lr_clk_out", | |
| + "i2s_out_01", "i2s_in_ch01", "i2s_ao_clk_in", | |
| + "i2s_lr_clk_in" | |
| +}; | |
| + | |
| +static const char * const pwm_b_groups[] = { | |
| + "pwm_b" | |
| +}; | |
| + | |
| +static const char * const pwm_c_groups[] = { | |
| + "pwm_c0", "pwm_c1" | |
| +}; | |
| + | |
| +static const char * const pwm_c_ao_groups[] = { | |
| + "pwm_c2" | |
| +}; | |
| + | |
| +static const char * const pwm_d_groups[] = { | |
| + "pwm_d" | |
| +}; | |
| + | |
| +static const char * const pwm_e_groups[] = { | |
| + "pwm_e" | |
| +}; | |
| + | |
| +static const char * const pwm_vs_groups[] = { | |
| + "pwm_vs_0", "pwm_vs_1", "pwm_vs_2", | |
| + "pwm_vs_3", "pwm_vs_4" | |
| +}; | |
| + | |
| +static const char * const tsin_a_groups[] = { | |
| + "tsin_d0_a", "tsin_d17_a", "tsin_clk_a", "tsin_sop_a", | |
| + "tsin_d_valid_a" | |
| +}; | |
| + | |
| +static const char * const tsin_b_groups[] = { | |
| + "tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b" | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson8b_cbus_functions[] = { | |
| + FUNCTION(gpio_periphs), | |
| + FUNCTION(sd_a), | |
| + FUNCTION(sdxc_a), | |
| + FUNCTION(pcm_a), | |
| + FUNCTION(uart_a), | |
| + FUNCTION(uart_b), | |
| + FUNCTION(iso7816), | |
| + FUNCTION(i2c_d), | |
| + FUNCTION(xtal), | |
| + FUNCTION(uart_c), | |
| + FUNCTION(i2c_c), | |
| + FUNCTION(hdmi), | |
| + FUNCTION(spi), | |
| + FUNCTION(ethernet), | |
| + FUNCTION(i2c_a), | |
| + FUNCTION(i2c_b), | |
| + FUNCTION(sd_c), | |
| + FUNCTION(sdxc_c), | |
| + FUNCTION(nand), | |
| + FUNCTION(nor), | |
| + FUNCTION(sd_b), | |
| + FUNCTION(sdxc_b), | |
| + FUNCTION(spdif_0), | |
| + FUNCTION(pwm_b), | |
| + FUNCTION(pwm_c), | |
| + FUNCTION(pwm_d), | |
| + FUNCTION(pwm_e), | |
| + FUNCTION(pwm_vs), | |
| + FUNCTION(tsin_a), | |
| + FUNCTION(tsin_b), | |
| + FUNCTION(clk_24m), | |
| +}; | |
| + | |
| +static const struct meson_pmx_func meson8b_aobus_functions[] = { | |
| + FUNCTION(gpio_aobus), | |
| + FUNCTION(uart_ao), | |
| + FUNCTION(uart_ao_b), | |
| + FUNCTION(i2c_slave_ao), | |
| + FUNCTION(i2c_mst_ao), | |
| + FUNCTION(i2s), | |
| + FUNCTION(remote), | |
| + FUNCTION(clk_32k), | |
| + FUNCTION(pwm_c_ao), | |
| + FUNCTION(spdif_1), | |
| + FUNCTION(hdmi_cec), | |
| +}; | |
| + | |
| +static const struct meson_bank meson8b_cbus_banks[] = { | |
| + /* name first last irq pullen pull dir out in */ | |
| + BANK("X0..11", GPIOX_0, GPIOX_11, 97, 108, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), | |
| + BANK("X16..21", GPIOX_16, GPIOX_21, 113, 118, 4, 16, 4, 16, 0, 16, 1, 16, 2, 16), | |
| + BANK("Y0..1", GPIOY_0, GPIOY_1, 80, 81, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), | |
| + BANK("Y3", GPIOY_3, GPIOY_3, 83, 83, 3, 3, 3, 3, 3, 3, 4, 3, 5, 3), | |
| + BANK("Y6..14", GPIOY_6, GPIOY_14, 86, 94, 3, 6, 3, 6, 3, 6, 4, 6, 5, 6), | |
| + BANK("DV9", GPIODV_9, GPIODV_9, 59, 59, 0, 9, 0, 9, 7, 9, 8, 9, 9, 9), | |
| + BANK("DV24..29", GPIODV_24, GPIODV_29, 74, 79, 0, 24, 0, 24, 7, 24, 8, 24, 9, 24), | |
| + BANK("H", GPIOH_0, GPIOH_9, 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), | |
| + BANK("CARD", CARD_0, CARD_6, 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), | |
| + BANK("BOOT", BOOT_0, BOOT_18, 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), | |
| + | |
| + /* | |
| + * The following bank is not mentionned in the public datasheet | |
| + * There is no information whether it can be used with the gpio | |
| + * interrupt controller | |
| + */ | |
| + BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12), | |
| +}; | |
| + | |
| +static const struct meson_bank meson8b_aobus_banks[] = { | |
| + /* name first lastc irq pullen pull dir out in */ | |
| + BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0), | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { | |
| + .name = "cbus-banks", | |
| + .pins = meson8b_cbus_pins, | |
| + .groups = meson8b_cbus_groups, | |
| + .funcs = meson8b_cbus_functions, | |
| + .banks = meson8b_cbus_banks, | |
| + .num_pins = ARRAY_SIZE(meson8b_cbus_pins), | |
| + .num_groups = ARRAY_SIZE(meson8b_cbus_groups), | |
| + .num_funcs = ARRAY_SIZE(meson8b_cbus_functions), | |
| + .num_banks = ARRAY_SIZE(meson8b_cbus_banks), | |
| + .pmx_ops = &meson8_pmx_ops, | |
| +}; | |
| + | |
| +static const struct meson_pinctrl_data meson8b_aobus_pinctrl_data = { | |
| + .name = "aobus-banks", | |
| + .pins = meson8b_aobus_pins, | |
| + .groups = meson8b_aobus_groups, | |
| + .funcs = meson8b_aobus_functions, | |
| + .banks = meson8b_aobus_banks, | |
| + .num_pins = ARRAY_SIZE(meson8b_aobus_pins), | |
| + .num_groups = ARRAY_SIZE(meson8b_aobus_groups), | |
| + .num_funcs = ARRAY_SIZE(meson8b_aobus_functions), | |
| + .num_banks = ARRAY_SIZE(meson8b_aobus_banks), | |
| + .pmx_ops = &meson8_pmx_ops, | |
| + .parse_dt = &meson8_aobus_parse_dt_extra, | |
| +}; | |
| + | |
| +static const struct of_device_id meson8b_pinctrl_dt_match[] = { | |
| + { | |
| + .compatible = "amlogic,meson8b-cbus-pinctrl", | |
| + .data = &meson8b_cbus_pinctrl_data, | |
| + }, | |
| + { | |
| + .compatible = "amlogic,meson8b-aobus-pinctrl", | |
| + .data = &meson8b_aobus_pinctrl_data, | |
| + }, | |
| + { }, | |
| +}; | |
| + | |
| +static struct platform_driver meson8b_pinctrl_driver = { | |
| + .probe = meson_pinctrl_probe, | |
| + .driver = { | |
| + .name = "meson8b-pinctrl", | |
| + .of_match_table = meson8b_pinctrl_dt_match, | |
| + }, | |
| +}; | |
| +builtin_platform_driver(meson8b_pinctrl_driver); | |
| diff --git a/include/pinctrl.h b/include/pinctrl.h | |
| index 5c031fb400..841e68449a 100644 | |
| --- a/include/pinctrl.h | |
| +++ b/include/pinctrl.h | |
| @@ -22,6 +22,9 @@ struct pinctrl_device { | |
| unsigned int base, npins; | |
| }; | |
| +/* Convenience macro to define a single named or anonymous pin descriptor */ | |
| +#define PINCTRL_PIN(a, b) { .number = a, .name = b } | |
| + | |
| int pinctrl_register(struct pinctrl_device *pdev); | |
| void pinctrl_unregister(struct pinctrl_device *pdev); | |
| -- | |
| 2.43.0 | |
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| From bf7450208a7d40d9b1ec9560263b228efddd8944 Mon Sep 17 00:00:00 2001 | |
| From: Sohaib Mohamed <sohaib.amhmd@gmail.com> | |
| Date: Mon, 16 Mar 2026 19:34:11 +0100 | |
| Subject: [PATCH 2/2] claude port | |
| Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> | |
| --- | |
| drivers/pinctrl/meson/pinctrl-amlogic-a4.c | 1042 +++++------------ | |
| drivers/pinctrl/meson/pinctrl-amlogic-c3.c | 12 +- | |
| drivers/pinctrl/meson/pinctrl-amlogic-t7.c | 12 +- | |
| drivers/pinctrl/meson/pinctrl-meson-a1.c | 12 +- | |
| drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | 21 +- | |
| drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h | 4 +- | |
| drivers/pinctrl/meson/pinctrl-meson-axg.c | 14 +- | |
| drivers/pinctrl/meson/pinctrl-meson-g12a.c | 14 +- | |
| drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 14 +- | |
| drivers/pinctrl/meson/pinctrl-meson-gxl.c | 14 +- | |
| drivers/pinctrl/meson/pinctrl-meson-s4.c | 12 +- | |
| drivers/pinctrl/meson/pinctrl-meson.c | 525 +++------ | |
| drivers/pinctrl/meson/pinctrl-meson.h | 50 +- | |
| drivers/pinctrl/meson/pinctrl-meson8-pmx.c | 24 +- | |
| drivers/pinctrl/meson/pinctrl-meson8-pmx.h | 7 +- | |
| drivers/pinctrl/meson/pinctrl-meson8.c | 14 +- | |
| drivers/pinctrl/meson/pinctrl-meson8b.c | 14 +- | |
| 17 files changed, 591 insertions(+), 1214 deletions(-) | |
| diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c | |
| index d9e3a8d593..da926bfd59 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c | |
| @@ -2,30 +2,24 @@ | |
| /* | |
| * Copyright (c) 2024 Amlogic, Inc. All rights reserved. | |
| * Author: Xianwei Zhao <xianwei.zhao@amlogic.com> | |
| + * | |
| + * Ported to barebox by Sohaib Mohamed <sohaib.amhmd@gmail.com> | |
| */ | |
| -#include <linux/err.h> | |
| -#include <linux/gpio/driver.h> | |
| -#include <linux/init.h> | |
| +#include <driver.h> | |
| +#include <gpio.h> | |
| +#include <init.h> | |
| #include <linux/io.h> | |
| #include <linux/module.h> | |
| -#include <linux/of.h> | |
| -#include <linux/of_address.h> | |
| -#include <linux/platform_device.h> | |
| +#include <of.h> | |
| +#include <of_address.h> | |
| +#include <of_device.h> | |
| +#include <linux/device.h> | |
| #include <linux/regmap.h> | |
| -#include <linux/seq_file.h> | |
| #include <linux/slab.h> | |
| -#include <linux/string_helpers.h> | |
| - | |
| -#include <linux/pinctrl/consumer.h> | |
| -#include <linux/pinctrl/pinconf.h> | |
| -#include <linux/pinctrl/pinctrl.h> | |
| -#include <linux/pinctrl/pinmux.h> | |
| +#include <pinctrl.h> | |
| #include <dt-bindings/pinctrl/amlogic,pinctrl.h> | |
| -#include "../core.h" | |
| -#include "../pinconf.h" | |
| - | |
| #define gpio_chip_to_bank(chip) \ | |
| container_of(chip, struct aml_gpio_bank, gpio_chip) | |
| @@ -51,7 +45,7 @@ struct aml_pio_control { | |
| }; | |
| /* | |
| - * partial bank(subordinate) pins mux config use other bank(main) mux registgers | |
| + * partial bank(subordinate) pins mux config use other bank(main) mux registers | |
| * m_bank_id: the main bank which pin_id from 0, but register bit not from bit 0 | |
| * m_bit_offs: bit offset the main bank mux register | |
| * sid: start pin_id of subordinate bank | |
| @@ -69,19 +63,6 @@ struct aml_pctl_data { | |
| const struct multi_mux *p_mux; | |
| }; | |
| -struct aml_pmx_func { | |
| - const char *name; | |
| - const char **groups; | |
| - unsigned int ngroups; | |
| -}; | |
| - | |
| -struct aml_pctl_group { | |
| - const char *name; | |
| - unsigned int npins; | |
| - unsigned int *pins; | |
| - unsigned int *func; | |
| -}; | |
| - | |
| struct aml_gpio_bank { | |
| struct gpio_chip gpio_chip; | |
| struct aml_pio_control pc; | |
| @@ -96,14 +77,9 @@ struct aml_gpio_bank { | |
| struct aml_pinctrl { | |
| struct device *dev; | |
| - struct pinctrl_dev *pctl; | |
| + struct pinctrl_device pctl; | |
| struct aml_gpio_bank *banks; | |
| int nbanks; | |
| - struct aml_pmx_func *functions; | |
| - int nfunctions; | |
| - struct aml_pctl_group *groups; | |
| - int ngroups; | |
| - | |
| const struct aml_pctl_data *data; | |
| }; | |
| @@ -115,13 +91,6 @@ static const unsigned int aml_def_regoffs[AML_NUM_REG] = { | |
| 3, 4, 2, 1, 0, 7 | |
| }; | |
| -static const char *aml_bank_name[31] = { | |
| -"GPIOA", "GPIOB", "GPIOC", "GPIOD", "GPIOE", "GPIOF", "GPIOG", | |
| -"GPIOH", "GPIOI", "GPIOJ", "GPIOK", "GPIOL", "GPIOM", "GPION", | |
| -"GPIOO", "GPIOP", "GPIOQ", "GPIOR", "GPIOS", "GPIOT", "GPIOU", | |
| -"GPIOV", "GPIOW", "GPIOX", "GPIOY", "GPIOZ", "GPIODV", "GPIOAO", | |
| -"GPIOCC", "TEST_N", "ANALOG" | |
| -}; | |
| static const struct multi_mux multi_mux_s7[] = { | |
| { | |
| @@ -156,49 +125,65 @@ static const struct aml_pctl_data s6_priv_data = { | |
| .p_mux = multi_mux_s6, | |
| }; | |
| -static int aml_pmx_calc_reg_and_offset(struct pinctrl_gpio_range *range, | |
| - unsigned int pin, unsigned int *reg, | |
| - unsigned int *offset) | |
| +/* Find the bank that owns a global pin_id (bank_id << 8 | local_offset) */ | |
| +static struct aml_gpio_bank *aml_find_bank(struct aml_pinctrl *info, | |
| + unsigned int pin_id) | |
| { | |
| - unsigned int shift; | |
| + unsigned int bank_id = pin_id >> 8; | |
| + int i; | |
| - shift = ((pin - range->pin_base) << 2) + *offset; | |
| - *reg = (shift / 32) * 4; | |
| - *offset = shift % 32; | |
| + for (i = 0; i < info->nbanks; i++) { | |
| + if (info->banks[i].bank_id == bank_id) | |
| + return &info->banks[i]; | |
| + } | |
| + return NULL; | |
| +} | |
| - return 0; | |
| +/* Calculate register byte offset and bit position for a pin within a bank */ | |
| +static void aml_calc_reg_and_bit(struct aml_gpio_bank *bank, | |
| + unsigned int local_pin, | |
| + unsigned int reg_type, | |
| + unsigned int *reg, unsigned int *bit) | |
| +{ | |
| + *bit = local_pin * aml_bit_strides[reg_type] + bank->pc.bit_offset[reg_type]; | |
| + *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; | |
| + *bit &= 0x1f; | |
| } | |
| +/* Set pinmux function for a global pin_id */ | |
| static int aml_pctl_set_function(struct aml_pinctrl *info, | |
| - struct pinctrl_gpio_range *range, | |
| - int pin_id, int func) | |
| + unsigned int pin_id, unsigned int func) | |
| { | |
| - struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| - unsigned int shift; | |
| - int reg; | |
| - int i; | |
| - unsigned int offset = bank->mux_bit_offs; | |
| + struct aml_gpio_bank *bank; | |
| const struct multi_mux *p_mux; | |
| + unsigned int shift, reg, offset; | |
| + unsigned int local_pin; | |
| + int i; | |
| - /* peculiar mux reg set */ | |
| + bank = aml_find_bank(info, pin_id); | |
| + if (!bank) | |
| + return -EINVAL; | |
| + | |
| + /* peculiar mux reg set: subordinate bank pins use main bank's registers */ | |
| if (bank->p_mux) { | |
| p_mux = bank->p_mux; | |
| if (pin_id >= p_mux->sid && pin_id <= p_mux->eid) { | |
| - bank = NULL; | |
| + struct aml_gpio_bank *main_bank = NULL; | |
| + | |
| for (i = 0; i < info->nbanks; i++) { | |
| if (info->banks[i].bank_id == p_mux->m_bank_id) { | |
| - bank = &info->banks[i]; | |
| - break; | |
| + main_bank = &info->banks[i]; | |
| + break; | |
| } | |
| } | |
| - if (!bank || !bank->reg_mux) | |
| + if (!main_bank || !main_bank->reg_mux) | |
| return -EINVAL; | |
| shift = (pin_id - p_mux->sid) << 2; | |
| reg = (shift / 32) * 4; | |
| offset = shift % 32; | |
| - return regmap_update_bits(bank->reg_mux, reg, | |
| + return regmap_update_bits(main_bank->reg_mux, reg, | |
| 0xf << offset, (func & 0xf) << offset); | |
| } | |
| } | |
| @@ -207,266 +192,44 @@ static int aml_pctl_set_function(struct aml_pinctrl *info, | |
| if (!bank->reg_mux) | |
| return 0; | |
| - aml_pmx_calc_reg_and_offset(range, pin_id, ®, &offset); | |
| + local_pin = pin_id - bank->pin_base; | |
| + shift = (local_pin << 2) + bank->mux_bit_offs; | |
| + reg = (shift / 32) * 4; | |
| + offset = shift % 32; | |
| return regmap_update_bits(bank->reg_mux, reg, | |
| - 0xf << offset, (func & 0xf) << offset); | |
| -} | |
| - | |
| -static int aml_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
| -{ | |
| - struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| - | |
| - return info->nfunctions; | |
| -} | |
| - | |
| -static const char *aml_pmx_get_fname(struct pinctrl_dev *pctldev, | |
| - unsigned int selector) | |
| -{ | |
| - struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| - | |
| - return info->functions[selector].name; | |
| -} | |
| - | |
| -static int aml_pmx_get_groups(struct pinctrl_dev *pctldev, | |
| - unsigned int selector, | |
| - const char * const **grps, | |
| - unsigned * const ngrps) | |
| -{ | |
| - struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| - | |
| - *grps = info->functions[selector].groups; | |
| - *ngrps = info->functions[selector].ngroups; | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -static int aml_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned int fselector, | |
| - unsigned int group_id) | |
| -{ | |
| - struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| - struct aml_pctl_group *group = &info->groups[group_id]; | |
| - struct pinctrl_gpio_range *range; | |
| - int i; | |
| - | |
| - for (i = 0; i < group->npins; i++) { | |
| - range = pinctrl_find_gpio_range_from_pin(pctldev, group->pins[i]); | |
| - aml_pctl_set_function(info, range, group->pins[i], group->func[i]); | |
| - } | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -static int aml_pmx_request_gpio(struct pinctrl_dev *pctldev, | |
| - struct pinctrl_gpio_range *range, | |
| - unsigned int pin) | |
| -{ | |
| - struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| - | |
| - return aml_pctl_set_function(info, range, pin, 0); | |
| -} | |
| - | |
| -static const struct pinmux_ops aml_pmx_ops = { | |
| - .set_mux = aml_pmx_set_mux, | |
| - .get_functions_count = aml_pmx_get_funcs_count, | |
| - .get_function_name = aml_pmx_get_fname, | |
| - .get_function_groups = aml_pmx_get_groups, | |
| - .gpio_request_enable = aml_pmx_request_gpio, | |
| -}; | |
| - | |
| -static int aml_calc_reg_and_bit(struct pinctrl_gpio_range *range, | |
| - unsigned int pin, | |
| - unsigned int reg_type, | |
| - unsigned int *reg, unsigned int *bit) | |
| -{ | |
| - struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| - | |
| - *bit = (pin - range->pin_base) * aml_bit_strides[reg_type] | |
| - + bank->pc.bit_offset[reg_type]; | |
| - *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; | |
| - *bit &= 0x1f; | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -static int aml_pinconf_get_pull(struct aml_pinctrl *info, unsigned int pin) | |
| -{ | |
| - struct pinctrl_gpio_range *range = | |
| - pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| - struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| - unsigned int reg, bit, val; | |
| - int ret, conf; | |
| - | |
| - aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); | |
| - | |
| - ret = regmap_read(bank->reg_gpio, reg, &val); | |
| - if (ret) | |
| - return ret; | |
| - | |
| - if (!(val & BIT(bit))) { | |
| - conf = PIN_CONFIG_BIAS_DISABLE; | |
| - } else { | |
| - aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); | |
| - | |
| - ret = regmap_read(bank->reg_gpio, reg, &val); | |
| - if (ret) | |
| - return ret; | |
| - | |
| - if (val & BIT(bit)) | |
| - conf = PIN_CONFIG_BIAS_PULL_UP; | |
| - else | |
| - conf = PIN_CONFIG_BIAS_PULL_DOWN; | |
| - } | |
| - | |
| - return conf; | |
| -} | |
| - | |
| -static int aml_pinconf_get_drive_strength(struct aml_pinctrl *info, | |
| - unsigned int pin, | |
| - u16 *drive_strength_ua) | |
| -{ | |
| - struct pinctrl_gpio_range *range = | |
| - pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| - struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| - unsigned int reg, bit; | |
| - unsigned int val; | |
| - int ret; | |
| - | |
| - if (!bank->reg_ds) | |
| - return -EOPNOTSUPP; | |
| - | |
| - aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); | |
| - ret = regmap_read(bank->reg_ds, reg, &val); | |
| - if (ret) | |
| - return ret; | |
| - | |
| - switch ((val >> bit) & 0x3) { | |
| - case PINCONF_DRV_500UA: | |
| - *drive_strength_ua = 500; | |
| - break; | |
| - case PINCONF_DRV_2500UA: | |
| - *drive_strength_ua = 2500; | |
| - break; | |
| - case PINCONF_DRV_3000UA: | |
| - *drive_strength_ua = 3000; | |
| - break; | |
| - case PINCONF_DRV_4000UA: | |
| - *drive_strength_ua = 4000; | |
| - break; | |
| - default: | |
| - return -EINVAL; | |
| - } | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -static int aml_pinconf_get_gpio_bit(struct aml_pinctrl *info, | |
| - unsigned int pin, | |
| - unsigned int reg_type) | |
| -{ | |
| - struct pinctrl_gpio_range *range = | |
| - pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| - struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| - unsigned int reg, bit, val; | |
| - int ret; | |
| - | |
| - aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); | |
| - ret = regmap_read(bank->reg_gpio, reg, &val); | |
| - if (ret) | |
| - return ret; | |
| - | |
| - return BIT(bit) & val ? 1 : 0; | |
| + 0xf << offset, (func & 0xf) << offset); | |
| } | |
| -static int aml_pinconf_get_output(struct aml_pinctrl *info, | |
| - unsigned int pin) | |
| -{ | |
| - int ret = aml_pinconf_get_gpio_bit(info, pin, AML_REG_DIR); | |
| - | |
| - if (ret < 0) | |
| - return ret; | |
| - | |
| - return !ret; | |
| -} | |
| - | |
| -static int aml_pinconf_get_drive(struct aml_pinctrl *info, | |
| - unsigned int pin) | |
| -{ | |
| - return aml_pinconf_get_gpio_bit(info, pin, AML_REG_OUT); | |
| -} | |
| - | |
| -static int aml_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, | |
| - unsigned long *config) | |
| -{ | |
| - struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); | |
| - enum pin_config_param param = pinconf_to_config_param(*config); | |
| - u16 arg; | |
| - int ret; | |
| - | |
| - switch (param) { | |
| - case PIN_CONFIG_BIAS_DISABLE: | |
| - case PIN_CONFIG_BIAS_PULL_DOWN: | |
| - case PIN_CONFIG_BIAS_PULL_UP: | |
| - if (aml_pinconf_get_pull(info, pin) == param) | |
| - arg = 1; | |
| - else | |
| - return -EINVAL; | |
| - break; | |
| - case PIN_CONFIG_DRIVE_STRENGTH_UA: | |
| - ret = aml_pinconf_get_drive_strength(info, pin, &arg); | |
| - if (ret) | |
| - return ret; | |
| - break; | |
| - case PIN_CONFIG_OUTPUT_ENABLE: | |
| - ret = aml_pinconf_get_output(info, pin); | |
| - if (ret <= 0) | |
| - return -EINVAL; | |
| - arg = 1; | |
| - break; | |
| - case PIN_CONFIG_LEVEL: | |
| - ret = aml_pinconf_get_output(info, pin); | |
| - if (ret <= 0) | |
| - return -EINVAL; | |
| - | |
| - ret = aml_pinconf_get_drive(info, pin); | |
| - if (ret < 0) | |
| - return -EINVAL; | |
| - | |
| - arg = ret; | |
| - break; | |
| - | |
| - default: | |
| - return -ENOTSUPP; | |
| - } | |
| - | |
| - *config = pinconf_to_config_packed(param, arg); | |
| - dev_dbg(info->dev, "pinconf for pin %u is %lu\n", pin, *config); | |
| - | |
| - return 0; | |
| -} | |
| +/* --- Pin configuration helpers --- */ | |
| static int aml_pinconf_disable_bias(struct aml_pinctrl *info, | |
| - unsigned int pin) | |
| + unsigned int pin_id) | |
| { | |
| - struct pinctrl_gpio_range *range = | |
| - pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| - struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| + struct aml_gpio_bank *bank; | |
| unsigned int reg, bit = 0; | |
| - aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); | |
| + bank = aml_find_bank(info, pin_id); | |
| + if (!bank) | |
| + return -EINVAL; | |
| + aml_calc_reg_and_bit(bank, pin_id - bank->pin_base, | |
| + AML_REG_PULLEN, ®, &bit); | |
| return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); | |
| } | |
| -static int aml_pinconf_enable_bias(struct aml_pinctrl *info, unsigned int pin, | |
| - bool pull_up) | |
| +static int aml_pinconf_enable_bias(struct aml_pinctrl *info, | |
| + unsigned int pin_id, bool pull_up) | |
| { | |
| - struct pinctrl_gpio_range *range = | |
| - pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| - struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| + struct aml_gpio_bank *bank; | |
| unsigned int reg, bit, val = 0; | |
| int ret; | |
| - aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); | |
| + bank = aml_find_bank(info, pin_id); | |
| + if (!bank) | |
| + return -EINVAL; | |
| + | |
| + aml_calc_reg_and_bit(bank, pin_id - bank->pin_base, | |
| + AML_REG_PULL, ®, &bit); | |
| if (pull_up) | |
| val = BIT(bit); | |
| @@ -474,25 +237,29 @@ static int aml_pinconf_enable_bias(struct aml_pinctrl *info, unsigned int pin, | |
| if (ret) | |
| return ret; | |
| - aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); | |
| + aml_calc_reg_and_bit(bank, pin_id - bank->pin_base, | |
| + AML_REG_PULLEN, ®, &bit); | |
| return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); | |
| } | |
| static int aml_pinconf_set_drive_strength(struct aml_pinctrl *info, | |
| - unsigned int pin, | |
| - u16 drive_strength_ua) | |
| + unsigned int pin_id, | |
| + u32 drive_strength_ua) | |
| { | |
| - struct pinctrl_gpio_range *range = | |
| - pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| - struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| + struct aml_gpio_bank *bank; | |
| unsigned int reg, bit, ds_val; | |
| + bank = aml_find_bank(info, pin_id); | |
| + if (!bank) | |
| + return -EINVAL; | |
| + | |
| if (!bank->reg_ds) { | |
| dev_err(info->dev, "drive-strength not supported\n"); | |
| return -EOPNOTSUPP; | |
| } | |
| - aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); | |
| + aml_calc_reg_and_bit(bank, pin_id - bank->pin_base, | |
| + AML_REG_DS, ®, &bit); | |
| if (drive_strength_ua <= 500) { | |
| ds_val = PINCONF_DRV_500UA; | |
| @@ -505,397 +272,173 @@ static int aml_pinconf_set_drive_strength(struct aml_pinctrl *info, | |
| } else { | |
| dev_warn_once(info->dev, | |
| "pin %u: invalid drive-strength : %d , default to 4mA\n", | |
| - pin, drive_strength_ua); | |
| + pin_id, drive_strength_ua); | |
| ds_val = PINCONF_DRV_4000UA; | |
| } | |
| return regmap_update_bits(bank->reg_ds, reg, 0x3 << bit, ds_val << bit); | |
| } | |
| -static int aml_pinconf_set_gpio_bit(struct aml_pinctrl *info, | |
| - unsigned int pin, | |
| - unsigned int reg_type, | |
| - bool arg) | |
| -{ | |
| - struct pinctrl_gpio_range *range = | |
| - pinctrl_find_gpio_range_from_pin(info->pctl, pin); | |
| - struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); | |
| - unsigned int reg, bit; | |
| - | |
| - aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); | |
| - return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), | |
| - arg ? BIT(bit) : 0); | |
| -} | |
| - | |
| -static int aml_pinconf_set_output(struct aml_pinctrl *info, | |
| - unsigned int pin, | |
| - bool out) | |
| -{ | |
| - return aml_pinconf_set_gpio_bit(info, pin, AML_REG_DIR, !out); | |
| -} | |
| - | |
| -static int aml_pinconf_set_drive(struct aml_pinctrl *info, | |
| - unsigned int pin, | |
| - bool high) | |
| -{ | |
| - return aml_pinconf_set_gpio_bit(info, pin, AML_REG_OUT, high); | |
| -} | |
| - | |
| -static int aml_pinconf_set_output_drive(struct aml_pinctrl *info, | |
| - unsigned int pin, | |
| - bool high) | |
| -{ | |
| - int ret; | |
| - | |
| - ret = aml_pinconf_set_output(info, pin, true); | |
| - if (ret) | |
| - return ret; | |
| - | |
| - return aml_pinconf_set_drive(info, pin, high); | |
| -} | |
| - | |
| -static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, | |
| - unsigned long *configs, unsigned int num_configs) | |
| -{ | |
| - struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); | |
| - enum pin_config_param param; | |
| - unsigned int arg = 0; | |
| - int i, ret; | |
| - | |
| - for (i = 0; i < num_configs; i++) { | |
| - param = pinconf_to_config_param(configs[i]); | |
| - | |
| - switch (param) { | |
| - case PIN_CONFIG_DRIVE_STRENGTH_UA: | |
| - case PIN_CONFIG_OUTPUT_ENABLE: | |
| - case PIN_CONFIG_LEVEL: | |
| - arg = pinconf_to_config_argument(configs[i]); | |
| - break; | |
| - | |
| - default: | |
| - break; | |
| - } | |
| - | |
| - switch (param) { | |
| - case PIN_CONFIG_BIAS_DISABLE: | |
| - ret = aml_pinconf_disable_bias(info, pin); | |
| - break; | |
| - case PIN_CONFIG_BIAS_PULL_UP: | |
| - ret = aml_pinconf_enable_bias(info, pin, true); | |
| - break; | |
| - case PIN_CONFIG_BIAS_PULL_DOWN: | |
| - ret = aml_pinconf_enable_bias(info, pin, false); | |
| - break; | |
| - case PIN_CONFIG_DRIVE_STRENGTH_UA: | |
| - ret = aml_pinconf_set_drive_strength(info, pin, arg); | |
| - break; | |
| - case PIN_CONFIG_OUTPUT_ENABLE: | |
| - ret = aml_pinconf_set_output(info, pin, arg); | |
| - break; | |
| - case PIN_CONFIG_LEVEL: | |
| - ret = aml_pinconf_set_output_drive(info, pin, arg); | |
| - break; | |
| - default: | |
| - ret = -ENOTSUPP; | |
| - } | |
| - | |
| - if (ret) | |
| - return ret; | |
| - } | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -static int aml_pinconf_group_set(struct pinctrl_dev *pcdev, | |
| - unsigned int num_group, | |
| - unsigned long *configs, | |
| - unsigned int num_configs) | |
| -{ | |
| - struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); | |
| - int i; | |
| - | |
| - for (i = 0; i < info->groups[num_group].npins; i++) { | |
| - aml_pinconf_set(pcdev, info->groups[num_group].pins[i], configs, | |
| - num_configs); | |
| - } | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -static int aml_pinconf_group_get(struct pinctrl_dev *pcdev, | |
| - unsigned int group, unsigned long *config) | |
| -{ | |
| - return -EOPNOTSUPP; | |
| -} | |
| - | |
| -static const struct pinconf_ops aml_pinconf_ops = { | |
| - .pin_config_get = aml_pinconf_get, | |
| - .pin_config_set = aml_pinconf_set, | |
| - .pin_config_group_get = aml_pinconf_group_get, | |
| - .pin_config_group_set = aml_pinconf_group_set, | |
| - .is_generic = true, | |
| -}; | |
| - | |
| -static int aml_get_groups_count(struct pinctrl_dev *pctldev) | |
| +/* Apply optional bias/drive-strength config from a DT node to a single pin */ | |
| +static void aml_apply_pin_config(struct aml_pinctrl *info, | |
| + unsigned int pin_id, | |
| + struct device_node *np) | |
| { | |
| - struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| - | |
| - return info->ngroups; | |
| -} | |
| + u32 ua; | |
| -static const char *aml_get_group_name(struct pinctrl_dev *pctldev, | |
| - unsigned int selector) | |
| -{ | |
| - struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| + if (of_find_property(np, "bias-disable", NULL)) | |
| + aml_pinconf_disable_bias(info, pin_id); | |
| + else if (of_find_property(np, "bias-pull-up", NULL)) | |
| + aml_pinconf_enable_bias(info, pin_id, true); | |
| + else if (of_find_property(np, "bias-pull-down", NULL)) | |
| + aml_pinconf_enable_bias(info, pin_id, false); | |
| - return info->groups[selector].name; | |
| + if (!of_property_read_u32(np, "drive-strength-microamp", &ua)) | |
| + aml_pinconf_set_drive_strength(info, pin_id, ua); | |
| } | |
| -static int aml_get_group_pins(struct pinctrl_dev *pctldev, | |
| - unsigned int selector, const unsigned int **pins, | |
| - unsigned int *npins) | |
| -{ | |
| - struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
| - | |
| - if (selector >= info->ngroups) | |
| - return -EINVAL; | |
| - | |
| - *pins = info->groups[selector].pins; | |
| - *npins = info->groups[selector].npins; | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -static void aml_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, | |
| - unsigned int offset) | |
| +/* | |
| + * Apply mux (and optional pin config) from a node that carries a "pinmux" | |
| + * property. Each entry is encoded as AML_PINMUX(bank, offset, mode): | |
| + * bits [31:8] = global pin_id = (bank_id << 8) + local_offset | |
| + * bits [7:0] = mux function value | |
| + */ | |
| +static int aml_apply_pinmux_node(struct aml_pinctrl *info, | |
| + struct device_node *np) | |
| { | |
| - seq_printf(s, " %s", dev_name(pcdev->dev)); | |
| -} | |
| + const __be32 *list; | |
| + int size, i, ret; | |
| -static const struct pinctrl_ops aml_pctrl_ops = { | |
| - .get_groups_count = aml_get_groups_count, | |
| - .get_group_name = aml_get_group_name, | |
| - .get_group_pins = aml_get_group_pins, | |
| - .dt_node_to_map = pinconf_generic_dt_node_to_map_pinmux, | |
| - .dt_free_map = pinconf_generic_dt_free_map, | |
| - .pin_dbg_show = aml_pin_dbg_show, | |
| -}; | |
| + list = of_get_property(np, "pinmux", &size); | |
| + if (!list) | |
| + return 0; | |
| -static int aml_pctl_parse_functions(struct device_node *np, | |
| - struct aml_pinctrl *info, u32 index, | |
| - int *grp_index) | |
| -{ | |
| - struct device *dev = info->dev; | |
| - struct aml_pmx_func *func; | |
| - struct aml_pctl_group *grp; | |
| - int ret, i; | |
| - | |
| - func = &info->functions[index]; | |
| - func->name = np->name; | |
| - func->ngroups = of_get_child_count(np); | |
| - if (func->ngroups == 0) | |
| - return dev_err_probe(dev, -EINVAL, "No groups defined\n"); | |
| - | |
| - func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); | |
| - if (!func->groups) | |
| - return -ENOMEM; | |
| + size /= sizeof(u32); | |
| + for (i = 0; i < size; i++) { | |
| + u32 val = be32_to_cpup(list + i); | |
| + unsigned int pin_id = val >> 8; | |
| + unsigned int func = val & 0xff; | |
| - i = 0; | |
| - for_each_child_of_node_scoped(np, child) { | |
| - func->groups[i++] = child->name; | |
| - grp = &info->groups[*grp_index]; | |
| - grp->name = child->name; | |
| - *grp_index += 1; | |
| - ret = pinconf_generic_parse_dt_pinmux(child, dev, &grp->pins, | |
| - &grp->func, &grp->npins); | |
| + ret = aml_pctl_set_function(info, pin_id, func); | |
| if (ret) { | |
| - dev_err(dev, "function :%s, groups:%s fail\n", func->name, child->name); | |
| + dev_err(info->dev, | |
| + "failed to set mux for pin 0x%x func %u\n", | |
| + pin_id, func); | |
| return ret; | |
| } | |
| + aml_apply_pin_config(info, pin_id, np); | |
| } | |
| - dev_dbg(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); | |
| return 0; | |
| } | |
| -static u32 aml_bank_pins(struct device_node *np) | |
| -{ | |
| - struct of_phandle_args of_args; | |
| - | |
| - if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, | |
| - 0, &of_args)) | |
| - return 0; | |
| - else | |
| - return of_args.args[2]; | |
| -} | |
| - | |
| -static int aml_bank_number(struct device_node *np) | |
| -{ | |
| - struct of_phandle_args of_args; | |
| - | |
| - if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, | |
| - 0, &of_args)) | |
| - return -EINVAL; | |
| - else | |
| - return of_args.args[1] >> 8; | |
| -} | |
| - | |
| -static unsigned int aml_count_pins(struct device_node *np) | |
| -{ | |
| - struct device_node *child; | |
| - unsigned int pins = 0; | |
| - | |
| - for_each_child_of_node(np, child) { | |
| - if (of_property_read_bool(child, "gpio-controller")) | |
| - pins += aml_bank_pins(child); | |
| - } | |
| - | |
| - return pins; | |
| -} | |
| - | |
| /* | |
| - * A pinctrl device contains two types of nodes. The one named GPIO | |
| - * bank which includes gpio-controller property. The other one named | |
| - * function which includes one or more pin groups. The pin group | |
| - * include pinmux property(global index in pinctrl dev, and mux vlaue | |
| - * in mux reg) and pin configuration properties. | |
| + * barebox pinctrl set_state callback. | |
| + * | |
| + * np is the pin-state node referenced by the device (e.g. pinctrl-0 = <&node>). | |
| + * For the Amlogic a4 binding this node is a function node whose children carry | |
| + * "pinmux" properties (nested format). Flat format (pinmux directly on np) is | |
| + * also supported. | |
| */ | |
| -static void aml_pctl_dt_child_count(struct aml_pinctrl *info, | |
| - struct device_node *np) | |
| +static int aml_pctl_set_state(struct pinctrl_device *pdev, | |
| + struct device_node *np) | |
| { | |
| + struct aml_pinctrl *info = | |
| + container_of(pdev, struct aml_pinctrl, pctl); | |
| struct device_node *child; | |
| + int ret; | |
| + | |
| + /* flat format: the state node itself carries "pinmux" */ | |
| + if (of_find_property(np, "pinmux", NULL)) | |
| + return aml_apply_pinmux_node(info, np); | |
| + /* nested format: traverse child nodes */ | |
| for_each_child_of_node(np, child) { | |
| - if (of_property_read_bool(child, "gpio-controller")) { | |
| - info->nbanks++; | |
| - } else { | |
| - info->nfunctions++; | |
| - info->ngroups += of_get_child_count(child); | |
| - } | |
| + ret = aml_apply_pinmux_node(info, child); | |
| + if (ret) | |
| + return ret; | |
| } | |
| -} | |
| - | |
| -static struct regmap *aml_map_resource(struct device *dev, unsigned int id, | |
| - struct device_node *node, char *name) | |
| -{ | |
| - struct resource res; | |
| - void __iomem *base; | |
| - int i; | |
| - | |
| - struct regmap_config aml_regmap_config = { | |
| - .reg_bits = 32, | |
| - .val_bits = 32, | |
| - .reg_stride = 4, | |
| - }; | |
| - i = of_property_match_string(node, "reg-names", name); | |
| - if (i < 0) | |
| - return NULL; | |
| - if (of_address_to_resource(node, i, &res)) | |
| - return NULL; | |
| - base = devm_ioremap_resource(dev, &res); | |
| - if (IS_ERR(base)) | |
| - return ERR_CAST(base); | |
| + return 0; | |
| +} | |
| - aml_regmap_config.max_register = resource_size(&res) - 4; | |
| - aml_regmap_config.name = devm_kasprintf(dev, GFP_KERNEL, | |
| - "%s-%s", aml_bank_name[id], name); | |
| - if (!aml_regmap_config.name) | |
| - return ERR_PTR(-ENOMEM); | |
| +static struct pinctrl_ops aml_pctrl_ops = { | |
| + .set_state = aml_pctl_set_state, | |
| +}; | |
| - return devm_regmap_init_mmio(dev, base, &aml_regmap_config); | |
| -} | |
| +/* --- GPIO chip operations --- */ | |
| -static inline int aml_gpio_calc_reg_and_bit(struct aml_gpio_bank *bank, | |
| - unsigned int reg_type, | |
| - unsigned int gpio, | |
| - unsigned int *reg, | |
| - unsigned int *bit) | |
| +static void aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) | |
| { | |
| - *bit = gpio * aml_bit_strides[reg_type] + bank->pc.bit_offset[reg_type]; | |
| - *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; | |
| - *bit &= 0x1f; | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(chip); | |
| + unsigned int bit, reg; | |
| - return 0; | |
| + aml_calc_reg_and_bit(bank, gpio, AML_REG_OUT, ®, &bit); | |
| + regmap_update_bits(bank->reg_gpio, reg, BIT(bit), | |
| + value ? BIT(bit) : 0); | |
| } | |
| -static int aml_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) | |
| +static int aml_gpio_get(struct gpio_chip *chip, unsigned int gpio) | |
| { | |
| - struct aml_gpio_bank *bank = gpiochip_get_data(chip); | |
| - unsigned int bit, reg, val; | |
| - int ret; | |
| - | |
| - aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(chip); | |
| + unsigned int reg, bit, val; | |
| - ret = regmap_read(bank->reg_gpio, reg, &val); | |
| - if (ret) | |
| - return ret; | |
| + aml_calc_reg_and_bit(bank, gpio, AML_REG_IN, ®, &bit); | |
| + regmap_read(bank->reg_gpio, reg, &val); | |
| - return BIT(bit) & val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; | |
| + return !!(val & BIT(bit)); | |
| } | |
| static int aml_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) | |
| { | |
| - struct aml_gpio_bank *bank = gpiochip_get_data(chip); | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(chip); | |
| unsigned int bit, reg; | |
| - aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); | |
| - | |
| + aml_calc_reg_and_bit(bank, gpio, AML_REG_DIR, ®, &bit); | |
| return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); | |
| } | |
| -static int aml_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, | |
| - int value) | |
| +static int aml_gpio_direction_output(struct gpio_chip *chip, | |
| + unsigned int gpio, int value) | |
| { | |
| - struct aml_gpio_bank *bank = gpiochip_get_data(chip); | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(chip); | |
| unsigned int bit, reg; | |
| int ret; | |
| - aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); | |
| + aml_calc_reg_and_bit(bank, gpio, AML_REG_DIR, ®, &bit); | |
| ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); | |
| if (ret < 0) | |
| return ret; | |
| - aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); | |
| - | |
| + aml_calc_reg_and_bit(bank, gpio, AML_REG_OUT, ®, &bit); | |
| return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), | |
| value ? BIT(bit) : 0); | |
| } | |
| -static int aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) | |
| -{ | |
| - struct aml_gpio_bank *bank = gpiochip_get_data(chip); | |
| - unsigned int bit, reg; | |
| - | |
| - aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); | |
| - | |
| - return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), | |
| - value ? BIT(bit) : 0); | |
| -} | |
| - | |
| -static int aml_gpio_get(struct gpio_chip *chip, unsigned int gpio) | |
| +static int aml_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) | |
| { | |
| - struct aml_gpio_bank *bank = gpiochip_get_data(chip); | |
| - unsigned int reg, bit, val; | |
| + struct aml_gpio_bank *bank = gpio_chip_to_bank(chip); | |
| + unsigned int bit, reg, val; | |
| + int ret; | |
| - aml_gpio_calc_reg_and_bit(bank, AML_REG_IN, gpio, ®, &bit); | |
| - regmap_read(bank->reg_gpio, reg, &val); | |
| + aml_calc_reg_and_bit(bank, gpio, AML_REG_DIR, ®, &bit); | |
| + ret = regmap_read(bank->reg_gpio, reg, &val); | |
| + if (ret) | |
| + return ret; | |
| - return !!(val & BIT(bit)); | |
| + return BIT(bit) & val ? GPIOF_DIR_IN : GPIOF_DIR_OUT; | |
| } | |
| -static const struct gpio_chip aml_gpio_template = { | |
| - .request = gpiochip_generic_request, | |
| - .free = gpiochip_generic_free, | |
| - .set_config = gpiochip_generic_config, | |
| - .set = aml_gpio_set, | |
| - .get = aml_gpio_get, | |
| - .direction_input = aml_gpio_direction_input, | |
| - .direction_output = aml_gpio_direction_output, | |
| - .get_direction = aml_gpio_get_direction, | |
| - .can_sleep = false, | |
| +static struct gpio_ops aml_gpio_ops = { | |
| + .direction_input = aml_gpio_direction_input, | |
| + .direction_output = aml_gpio_direction_output, | |
| + .get_direction = aml_gpio_get_direction, | |
| + .get = aml_gpio_get, | |
| + .set = aml_gpio_set, | |
| }; | |
| +/* --- Bank initialisation helpers --- */ | |
| + | |
| static void init_bank_register_bit(struct aml_pinctrl *info, | |
| struct aml_gpio_bank *bank) | |
| { | |
| @@ -925,12 +468,62 @@ static void init_bank_register_bit(struct aml_pinctrl *info, | |
| } | |
| } | |
| +static u32 aml_bank_pins(struct device_node *np) | |
| +{ | |
| + struct of_phandle_args of_args; | |
| + | |
| + if (__of_parse_phandle_with_args(np, "gpio-ranges", NULL, 3, | |
| + 0, &of_args)) | |
| + return 0; | |
| + return of_args.args[2]; | |
| +} | |
| + | |
| +static int aml_bank_number(struct device_node *np) | |
| +{ | |
| + struct of_phandle_args of_args; | |
| + | |
| + if (__of_parse_phandle_with_args(np, "gpio-ranges", NULL, 3, | |
| + 0, &of_args)) | |
| + return -EINVAL; | |
| + return of_args.args[1] >> 8; | |
| +} | |
| + | |
| +static struct regmap *aml_map_resource(struct device *dev, | |
| + struct device_node *node, char *name) | |
| +{ | |
| + struct resource res; | |
| + void __iomem *base; | |
| + int i; | |
| + | |
| + struct regmap_config aml_regmap_config = { | |
| + .reg_bits = 32, | |
| + .val_bits = 32, | |
| + .reg_stride = 4, | |
| + }; | |
| + | |
| + i = of_property_match_string(node, "reg-names", name); | |
| + if (i < 0) | |
| + return NULL; | |
| + if (of_address_to_resource(node, i, &res)) | |
| + return NULL; | |
| + | |
| + base = devm_ioremap(dev, res.start, resource_size(&res)); | |
| + if (IS_ERR(base)) | |
| + return ERR_CAST(base); | |
| + | |
| + aml_regmap_config.max_register = resource_size(&res) - 4; | |
| + aml_regmap_config.name = name; | |
| + | |
| + return regmap_init_mmio(dev, base, &aml_regmap_config); | |
| +} | |
| + | |
| static int aml_gpiolib_register_bank(struct aml_pinctrl *info, | |
| int bank_nr, struct device_node *np) | |
| { | |
| struct aml_gpio_bank *bank = &info->banks[bank_nr]; | |
| struct device *dev = info->dev; | |
| - int ret = 0; | |
| + struct device *gpio_dev; | |
| + int ret; | |
| ret = aml_bank_number(np); | |
| if (ret < 0) { | |
| @@ -939,151 +532,98 @@ static int aml_gpiolib_register_bank(struct aml_pinctrl *info, | |
| } | |
| bank->bank_id = ret; | |
| - bank->reg_mux = aml_map_resource(dev, bank->bank_id, np, "mux"); | |
| + bank->reg_mux = aml_map_resource(dev, np, "mux"); | |
| if (IS_ERR_OR_NULL(bank->reg_mux)) { | |
| if (bank->bank_id == AMLOGIC_GPIO_TEST_N || | |
| bank->bank_id == AMLOGIC_GPIO_ANALOG) | |
| bank->reg_mux = NULL; | |
| else | |
| - return dev_err_probe(dev, bank->reg_mux ? PTR_ERR(bank->reg_mux) : -ENOENT, | |
| + return dev_err_probe(dev, | |
| + bank->reg_mux ? PTR_ERR(bank->reg_mux) : -ENOENT, | |
| "mux registers not found\n"); | |
| } | |
| - bank->reg_gpio = aml_map_resource(dev, bank->bank_id, np, "gpio"); | |
| + bank->reg_gpio = aml_map_resource(dev, np, "gpio"); | |
| if (IS_ERR_OR_NULL(bank->reg_gpio)) | |
| - return dev_err_probe(dev, bank->reg_gpio ? PTR_ERR(bank->reg_gpio) : -ENOENT, | |
| + return dev_err_probe(dev, | |
| + bank->reg_gpio ? PTR_ERR(bank->reg_gpio) : -ENOENT, | |
| "gpio registers not found\n"); | |
| - bank->reg_ds = aml_map_resource(dev, bank->bank_id, np, "ds"); | |
| + bank->reg_ds = aml_map_resource(dev, np, "ds"); | |
| if (IS_ERR_OR_NULL(bank->reg_ds)) { | |
| - dev_dbg(info->dev, "ds registers not found - skipping\n"); | |
| + dev_dbg(dev, "ds registers not found - skipping\n"); | |
| bank->reg_ds = bank->reg_gpio; | |
| } | |
| - bank->gpio_chip = aml_gpio_template; | |
| - bank->gpio_chip.base = -1; | |
| - bank->gpio_chip.ngpio = aml_bank_pins(np); | |
| - bank->gpio_chip.fwnode = of_fwnode_handle(np); | |
| - bank->gpio_chip.parent = dev; | |
| - | |
| init_bank_register_bit(info, bank); | |
| - bank->gpio_chip.label = aml_bank_name[bank->bank_id]; | |
| - | |
| bank->pin_base = bank->bank_id << 8; | |
| - return 0; | |
| -} | |
| - | |
| -static int aml_pctl_probe_dt(struct platform_device *pdev, | |
| - struct pinctrl_desc *pctl_desc, | |
| - struct aml_pinctrl *info) | |
| -{ | |
| - struct device *dev = &pdev->dev; | |
| - struct pinctrl_pin_desc *pdesc; | |
| - struct device_node *np = dev->of_node; | |
| - int grp_index = 0; | |
| - int i = 0, j = 0, k = 0, bank; | |
| - int ret = 0; | |
| - | |
| - aml_pctl_dt_child_count(info, np); | |
| - if (!info->nbanks) | |
| - return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); | |
| - | |
| - dev_dbg(dev, "nbanks = %d\n", info->nbanks); | |
| - dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); | |
| - dev_dbg(dev, "ngroups = %d\n", info->ngroups); | |
| - | |
| - info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); | |
| - | |
| - info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); | |
| - | |
| - info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); | |
| - | |
| - if (!info->functions || !info->groups || !info->banks) | |
| - return -ENOMEM; | |
| - | |
| - info->data = (struct aml_pctl_data *)of_device_get_match_data(dev); | |
| - | |
| - pctl_desc->npins = aml_count_pins(np); | |
| - | |
| - pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); | |
| - if (!pdesc) | |
| - return -ENOMEM; | |
| - | |
| - pctl_desc->pins = pdesc; | |
| - | |
| - bank = 0; | |
| - for_each_child_of_node_scoped(np, child) { | |
| - if (of_property_read_bool(child, "gpio-controller")) { | |
| - const char *bank_name = NULL; | |
| - char **pin_names; | |
| - | |
| - ret = aml_gpiolib_register_bank(info, bank, child); | |
| - if (ret) | |
| - return ret; | |
| - | |
| - k = info->banks[bank].pin_base; | |
| - bank_name = info->banks[bank].gpio_chip.label; | |
| + gpio_dev = of_platform_device_create(np, dev); | |
| + if (!gpio_dev) { | |
| + dev_err(dev, "failed to create gpio child device\n"); | |
| + return -ENODEV; | |
| + } | |
| + of_platform_device_dummy_drv(gpio_dev); | |
| - pin_names = devm_kasprintf_strarray(dev, bank_name, | |
| - info->banks[bank].gpio_chip.ngpio); | |
| - if (IS_ERR(pin_names)) | |
| - return PTR_ERR(pin_names); | |
| + bank->gpio_chip.dev = gpio_dev; | |
| + bank->gpio_chip.ops = &aml_gpio_ops; | |
| + bank->gpio_chip.base = -1; | |
| + bank->gpio_chip.ngpio = aml_bank_pins(np); | |
| - for (j = 0; j < info->banks[bank].gpio_chip.ngpio; j++, k++) { | |
| - pdesc->number = k; | |
| - pdesc->name = pin_names[j]; | |
| - pdesc++; | |
| - } | |
| - bank++; | |
| - } else { | |
| - ret = aml_pctl_parse_functions(child, info, | |
| - i++, &grp_index); | |
| - if (ret) | |
| - return ret; | |
| - } | |
| - } | |
| + ret = gpiochip_add(&bank->gpio_chip); | |
| + if (ret) | |
| + return dev_err_probe(dev, ret, | |
| + "Failed to add gpiochip for bank %u\n", | |
| + bank->bank_id); | |
| return 0; | |
| } | |
| -static int aml_pctl_probe(struct platform_device *pdev) | |
| +static int aml_pctl_probe(struct device *dev) | |
| { | |
| - struct device *dev = &pdev->dev; | |
| + struct device_node *np = dev->of_node; | |
| + struct device_node *child; | |
| struct aml_pinctrl *info; | |
| - struct pinctrl_desc *pctl_desc; | |
| - int ret, i; | |
| - | |
| - pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); | |
| - if (!pctl_desc) | |
| - return -ENOMEM; | |
| + int bank = 0, ret; | |
| info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); | |
| if (!info) | |
| return -ENOMEM; | |
| - info->dev = dev; | |
| - platform_set_drvdata(pdev, info); | |
| - ret = aml_pctl_probe_dt(pdev, pctl_desc, info); | |
| - if (ret) | |
| - return ret; | |
| + info->dev = dev; | |
| + info->data = of_device_get_match_data(dev); | |
| + dev_set_drvdata(dev, info); | |
| - pctl_desc->owner = THIS_MODULE; | |
| - pctl_desc->pctlops = &aml_pctrl_ops; | |
| - pctl_desc->pmxops = &aml_pmx_ops; | |
| - pctl_desc->confops = &aml_pinconf_ops; | |
| - pctl_desc->name = dev_name(dev); | |
| + /* Count GPIO bank child nodes */ | |
| + for_each_child_of_node(np, child) { | |
| + if (of_property_read_bool(child, "gpio-controller")) | |
| + info->nbanks++; | |
| + } | |
| - info->pctl = devm_pinctrl_register(dev, pctl_desc, info); | |
| - if (IS_ERR(info->pctl)) | |
| - return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); | |
| + if (!info->nbanks) | |
| + return dev_err_probe(dev, -EINVAL, | |
| + "you need at least one gpio bank\n"); | |
| - for (i = 0; i < info->nbanks; i++) { | |
| - ret = gpiochip_add_data(&info->banks[i].gpio_chip, &info->banks[i]); | |
| + info->banks = devm_kcalloc(dev, info->nbanks, | |
| + sizeof(*info->banks), GFP_KERNEL); | |
| + if (!info->banks) | |
| + return -ENOMEM; | |
| + | |
| + for_each_child_of_node(np, child) { | |
| + if (!of_property_read_bool(child, "gpio-controller")) | |
| + continue; | |
| + ret = aml_gpiolib_register_bank(info, bank++, child); | |
| if (ret) | |
| - return dev_err_probe(dev, ret, "Failed to add gpiochip(%d)!\n", i); | |
| + return ret; | |
| } | |
| + info->pctl.dev = dev; | |
| + info->pctl.ops = &aml_pctrl_ops; | |
| + | |
| + ret = pinctrl_register(&info->pctl); | |
| + if (ret) | |
| + return dev_err_probe(dev, ret, "Failed pinctrl registration\n"); | |
| + | |
| return 0; | |
| } | |
| @@ -1095,14 +635,12 @@ static const struct of_device_id aml_pctl_of_match[] = { | |
| }; | |
| MODULE_DEVICE_TABLE(of, aml_pctl_of_match); | |
| -static struct platform_driver aml_pctl_driver = { | |
| - .driver = { | |
| - .name = "amlogic-pinctrl", | |
| - .of_match_table = aml_pctl_of_match, | |
| - }, | |
| +static struct driver aml_pctl_driver = { | |
| + .name = "amlogic-pinctrl", | |
| + .of_match_table = aml_pctl_of_match, | |
| .probe = aml_pctl_probe, | |
| }; | |
| -module_platform_driver(aml_pctl_driver); | |
| +core_platform_driver(aml_pctl_driver); | |
| MODULE_AUTHOR("Xianwei Zhao <xianwei.zhao@amlogic.com>"); | |
| MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic SoC"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-c3.c b/drivers/pinctrl/meson/pinctrl-amlogic-c3.c | |
| index 776d32465a..94d5ab157b 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-amlogic-c3.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-amlogic-c3.c | |
| @@ -1080,7 +1080,7 @@ static const struct meson_pinctrl_data c3_periphs_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(c3_periphs_groups), | |
| .num_funcs = ARRAY_SIZE(c3_periphs_functions), | |
| .num_banks = ARRAY_SIZE(c3_periphs_banks), | |
| - .pmx_ops = &meson_axg_pmx_ops, | |
| + //.pmx_ops = &meson_axg_pmx_ops, | |
| .pmx_data = &c3_periphs_pmx_banks_data, | |
| .parse_dt = &meson_a1_parse_dt_extra, | |
| }; | |
| @@ -1094,14 +1094,12 @@ static const struct of_device_id c3_pinctrl_dt_match[] = { | |
| }; | |
| MODULE_DEVICE_TABLE(of, c3_pinctrl_dt_match); | |
| -static struct platform_driver c3_pinctrl_driver = { | |
| +static struct driver c3_pinctrl_driver = { | |
| .probe = meson_pinctrl_probe, | |
| - .driver = { | |
| - .name = "amlogic-c3-pinctrl", | |
| - .of_match_table = c3_pinctrl_dt_match, | |
| - }, | |
| + .name = "amlogic-c3-pinctrl", | |
| + .of_match_table = c3_pinctrl_dt_match, | |
| }; | |
| -module_platform_driver(c3_pinctrl_driver); | |
| +core_platform_driver(c3_pinctrl_driver); | |
| MODULE_AUTHOR("Huqiang Qin <huqiang.qin@amlogic.com>"); | |
| MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic C3 SoC"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-t7.c b/drivers/pinctrl/meson/pinctrl-amlogic-t7.c | |
| index cfd98b9dcb..e4806b573f 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-amlogic-t7.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-amlogic-t7.c | |
| @@ -1583,7 +1583,7 @@ static const struct meson_pinctrl_data t7_periphs_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(t7_periphs_groups), | |
| .num_funcs = ARRAY_SIZE(t7_periphs_functions), | |
| .num_banks = ARRAY_SIZE(t7_periphs_banks), | |
| - .pmx_ops = &meson_axg_pmx_ops, | |
| + //.pmx_ops = &meson_axg_pmx_ops, | |
| .pmx_data = &t7_periphs_pmx_banks_data, | |
| .parse_dt = &meson_a1_parse_dt_extra, | |
| }; | |
| @@ -1597,14 +1597,12 @@ static const struct of_device_id t7_pinctrl_dt_match[] = { | |
| }; | |
| MODULE_DEVICE_TABLE(of, t7_pinctrl_dt_match); | |
| -static struct platform_driver t7_pinctrl_driver = { | |
| +static struct driver t7_pinctrl_driver = { | |
| .probe = meson_pinctrl_probe, | |
| - .driver = { | |
| - .name = "amlogic-t7-pinctrl", | |
| - .of_match_table = t7_pinctrl_dt_match, | |
| - }, | |
| + .name = "amlogic-t7-pinctrl", | |
| + .of_match_table = t7_pinctrl_dt_match, | |
| }; | |
| -module_platform_driver(t7_pinctrl_driver); | |
| +core_platform_driver(t7_pinctrl_driver); | |
| MODULE_AUTHOR("Huqiang Qin <huqiang.qin@amlogic.com>"); | |
| MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic T7 SoC"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-a1.c b/drivers/pinctrl/meson/pinctrl-meson-a1.c | |
| index 20c4323d42..e27bc24a6e 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson-a1.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-a1.c | |
| @@ -913,7 +913,7 @@ static const struct meson_pinctrl_data meson_a1_periphs_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson_a1_periphs_groups), | |
| .num_funcs = ARRAY_SIZE(meson_a1_periphs_functions), | |
| .num_banks = ARRAY_SIZE(meson_a1_periphs_banks), | |
| - .pmx_ops = &meson_axg_pmx_ops, | |
| + .set_mux = meson_axg_pmx_set_mux, | |
| .pmx_data = &meson_a1_periphs_pmx_banks_data, | |
| .parse_dt = &meson_a1_parse_dt_extra, | |
| }; | |
| @@ -927,14 +927,12 @@ static const struct of_device_id meson_a1_pinctrl_dt_match[] = { | |
| }; | |
| MODULE_DEVICE_TABLE(of, meson_a1_pinctrl_dt_match); | |
| -static struct platform_driver meson_a1_pinctrl_driver = { | |
| +static struct driver meson_a1_pinctrl_driver = { | |
| .probe = meson_pinctrl_probe, | |
| - .driver = { | |
| - .name = "meson-a1-pinctrl", | |
| - .of_match_table = meson_a1_pinctrl_dt_match, | |
| - }, | |
| + .name = "meson-a1-pinctrl", | |
| + .of_match_table = meson_a1_pinctrl_dt_match, | |
| }; | |
| -module_platform_driver(meson_a1_pinctrl_driver); | |
| +core_platform_driver(meson_a1_pinctrl_driver); | |
| MODULE_DESCRIPTION("Amlogic Meson A1 SoC pinctrl driver"); | |
| MODULE_LICENSE("Dual BSD/GPL"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | |
| index 00c3829216..e7032606c8 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | |
| @@ -19,8 +19,7 @@ | |
| */ | |
| #include <linux/device.h> | |
| #include <linux/regmap.h> | |
| -#include <linux/pinctrl/pinctrl.h> | |
| -#include <linux/pinctrl/pinmux.h> | |
| +#include <pinctrl.h> | |
| #include "pinctrl-meson.h" | |
| #include "pinctrl-meson-axg-pmx.h" | |
| @@ -76,7 +75,7 @@ static int meson_axg_pmx_update_function(struct meson_pinctrl *pc, | |
| return ret; | |
| } | |
| -static int meson_axg_pmx_set_mux(struct pinctrl_dev *pcdev, | |
| +int meson_axg_pmx_set_mux(struct pinctrl_device *pcdev, | |
| unsigned int func_num, unsigned int group_num) | |
| { | |
| int i; | |
| @@ -100,22 +99,6 @@ static int meson_axg_pmx_set_mux(struct pinctrl_dev *pcdev, | |
| return 0; | |
| } | |
| -static int meson_axg_pmx_request_gpio(struct pinctrl_dev *pcdev, | |
| - struct pinctrl_gpio_range *range, unsigned int offset) | |
| -{ | |
| - struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| - | |
| - return meson_axg_pmx_update_function(pc, offset, 0); | |
| -} | |
| - | |
| -const struct pinmux_ops meson_axg_pmx_ops = { | |
| - .set_mux = meson_axg_pmx_set_mux, | |
| - .get_functions_count = meson_pmx_get_funcs_count, | |
| - .get_function_name = meson_pmx_get_func_name, | |
| - .get_function_groups = meson_pmx_get_groups, | |
| - .gpio_request_enable = meson_axg_pmx_request_gpio, | |
| -}; | |
| -EXPORT_SYMBOL_GPL(meson_axg_pmx_ops); | |
| MODULE_DESCRIPTION("Amlogic Meson AXG second generation pinmux driver"); | |
| MODULE_LICENSE("Dual BSD/GPL"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h | |
| index 63b9d471e9..2546e2e7ab 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h | |
| @@ -59,4 +59,6 @@ struct meson_pmx_axg_data { | |
| }, \ | |
| } | |
| -extern const struct pinmux_ops meson_axg_pmx_ops; | |
| +struct pinctrl_device; | |
| +int meson_axg_pmx_set_mux(struct pinctrl_device *pcdev, | |
| + unsigned int func_num, unsigned int group_num); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c | |
| index fa2df48963..63ac6a09b7 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson-axg.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c | |
| @@ -1050,7 +1050,7 @@ static const struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson_axg_periphs_groups), | |
| .num_funcs = ARRAY_SIZE(meson_axg_periphs_functions), | |
| .num_banks = ARRAY_SIZE(meson_axg_periphs_banks), | |
| - .pmx_ops = &meson_axg_pmx_ops, | |
| + .set_mux = meson_axg_pmx_set_mux, | |
| .pmx_data = &meson_axg_periphs_pmx_banks_data, | |
| }; | |
| @@ -1064,7 +1064,7 @@ static const struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson_axg_aobus_groups), | |
| .num_funcs = ARRAY_SIZE(meson_axg_aobus_functions), | |
| .num_banks = ARRAY_SIZE(meson_axg_aobus_banks), | |
| - .pmx_ops = &meson_axg_pmx_ops, | |
| + .set_mux = meson_axg_pmx_set_mux, | |
| .pmx_data = &meson_axg_aobus_pmx_banks_data, | |
| .parse_dt = meson8_aobus_parse_dt_extra, | |
| }; | |
| @@ -1082,14 +1082,12 @@ static const struct of_device_id meson_axg_pinctrl_dt_match[] = { | |
| }; | |
| MODULE_DEVICE_TABLE(of, meson_axg_pinctrl_dt_match); | |
| -static struct platform_driver meson_axg_pinctrl_driver = { | |
| +static struct driver meson_axg_pinctrl_driver = { | |
| .probe = meson_pinctrl_probe, | |
| - .driver = { | |
| - .name = "meson-axg-pinctrl", | |
| - .of_match_table = meson_axg_pinctrl_dt_match, | |
| - }, | |
| + .name = "meson-axg-pinctrl", | |
| + .of_match_table = meson_axg_pinctrl_dt_match, | |
| }; | |
| -module_platform_driver(meson_axg_pinctrl_driver); | |
| +core_platform_driver(meson_axg_pinctrl_driver); | |
| MODULE_DESCRIPTION("Amlogic Meson AXG pinctrl driver"); | |
| MODULE_LICENSE("Dual BSD/GPL"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c | |
| index 117e72b4ff..d1046a1d61 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c | |
| @@ -1409,7 +1409,7 @@ static const struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson_g12a_periphs_groups), | |
| .num_funcs = ARRAY_SIZE(meson_g12a_periphs_functions), | |
| .num_banks = ARRAY_SIZE(meson_g12a_periphs_banks), | |
| - .pmx_ops = &meson_axg_pmx_ops, | |
| + .set_mux = meson_axg_pmx_set_mux, | |
| .pmx_data = &meson_g12a_periphs_pmx_banks_data, | |
| }; | |
| @@ -1423,7 +1423,7 @@ static const struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson_g12a_aobus_groups), | |
| .num_funcs = ARRAY_SIZE(meson_g12a_aobus_functions), | |
| .num_banks = ARRAY_SIZE(meson_g12a_aobus_banks), | |
| - .pmx_ops = &meson_axg_pmx_ops, | |
| + .set_mux = meson_axg_pmx_set_mux, | |
| .pmx_data = &meson_g12a_aobus_pmx_banks_data, | |
| .parse_dt = meson_g12a_aobus_parse_dt_extra, | |
| }; | |
| @@ -1441,14 +1441,12 @@ static const struct of_device_id meson_g12a_pinctrl_dt_match[] = { | |
| }; | |
| MODULE_DEVICE_TABLE(of, meson_g12a_pinctrl_dt_match); | |
| -static struct platform_driver meson_g12a_pinctrl_driver = { | |
| +static struct driver meson_g12a_pinctrl_driver = { | |
| .probe = meson_pinctrl_probe, | |
| - .driver = { | |
| - .name = "meson-g12a-pinctrl", | |
| - .of_match_table = meson_g12a_pinctrl_dt_match, | |
| - }, | |
| + .name = "meson-g12a-pinctrl", | |
| + .of_match_table = meson_g12a_pinctrl_dt_match, | |
| }; | |
| -module_platform_driver(meson_g12a_pinctrl_driver); | |
| +core_platform_driver(meson_g12a_pinctrl_driver); | |
| MODULE_DESCRIPTION("Amlogic Meson G12A SoC pinctrl driver"); | |
| MODULE_LICENSE("Dual BSD/GPL"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c | |
| index 4e8b9d7c2e..e7f503d311 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c | |
| @@ -872,7 +872,7 @@ static const struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups), | |
| .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions), | |
| .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks), | |
| - .pmx_ops = &meson8_pmx_ops, | |
| + .set_mux = meson8_pmx_set_mux, | |
| }; | |
| static const struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { | |
| @@ -885,7 +885,7 @@ static const struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups), | |
| .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions), | |
| .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks), | |
| - .pmx_ops = &meson8_pmx_ops, | |
| + .set_mux = meson8_pmx_set_mux, | |
| .parse_dt = meson8_aobus_parse_dt_extra, | |
| }; | |
| @@ -902,13 +902,11 @@ static const struct of_device_id meson_gxbb_pinctrl_dt_match[] = { | |
| }; | |
| MODULE_DEVICE_TABLE(of, meson_gxbb_pinctrl_dt_match); | |
| -static struct platform_driver meson_gxbb_pinctrl_driver = { | |
| +static struct driver meson_gxbb_pinctrl_driver = { | |
| .probe = meson_pinctrl_probe, | |
| - .driver = { | |
| - .name = "meson-gxbb-pinctrl", | |
| - .of_match_table = meson_gxbb_pinctrl_dt_match, | |
| - }, | |
| + .name = "meson-gxbb-pinctrl", | |
| + .of_match_table = meson_gxbb_pinctrl_dt_match, | |
| }; | |
| -module_platform_driver(meson_gxbb_pinctrl_driver); | |
| +core_platform_driver(meson_gxbb_pinctrl_driver); | |
| MODULE_DESCRIPTION("Amlogic Meson GXBB pinctrl driver"); | |
| MODULE_LICENSE("GPL v2"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c | |
| index a75762e4d2..7d59b67c76 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c | |
| @@ -843,7 +843,7 @@ static const struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson_gxl_periphs_groups), | |
| .num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions), | |
| .num_banks = ARRAY_SIZE(meson_gxl_periphs_banks), | |
| - .pmx_ops = &meson8_pmx_ops, | |
| + .set_mux = meson8_pmx_set_mux, | |
| }; | |
| static const struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { | |
| @@ -856,7 +856,7 @@ static const struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson_gxl_aobus_groups), | |
| .num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions), | |
| .num_banks = ARRAY_SIZE(meson_gxl_aobus_banks), | |
| - .pmx_ops = &meson8_pmx_ops, | |
| + .set_mux = meson8_pmx_set_mux, | |
| .parse_dt = meson8_aobus_parse_dt_extra, | |
| }; | |
| @@ -873,13 +873,11 @@ static const struct of_device_id meson_gxl_pinctrl_dt_match[] = { | |
| }; | |
| MODULE_DEVICE_TABLE(of, meson_gxl_pinctrl_dt_match); | |
| -static struct platform_driver meson_gxl_pinctrl_driver = { | |
| +static struct driver meson_gxl_pinctrl_driver = { | |
| .probe = meson_pinctrl_probe, | |
| - .driver = { | |
| - .name = "meson-gxl-pinctrl", | |
| - .of_match_table = meson_gxl_pinctrl_dt_match, | |
| - }, | |
| + .name = "meson-gxl-pinctrl", | |
| + .of_match_table = meson_gxl_pinctrl_dt_match, | |
| }; | |
| -module_platform_driver(meson_gxl_pinctrl_driver); | |
| +core_platform_driver(meson_gxl_pinctrl_driver); | |
| MODULE_DESCRIPTION("Amlogic Meson GXL pinctrl driver"); | |
| MODULE_LICENSE("GPL v2"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson-s4.c b/drivers/pinctrl/meson/pinctrl-meson-s4.c | |
| index 872948699e..6f577e14f9 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson-s4.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson-s4.c | |
| @@ -1207,7 +1207,7 @@ static const struct meson_pinctrl_data meson_s4_periphs_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson_s4_periphs_groups), | |
| .num_funcs = ARRAY_SIZE(meson_s4_periphs_functions), | |
| .num_banks = ARRAY_SIZE(meson_s4_periphs_banks), | |
| - .pmx_ops = &meson_axg_pmx_ops, | |
| + .set_mux = meson_axg_pmx_set_mux, | |
| .pmx_data = &meson_s4_periphs_pmx_banks_data, | |
| .parse_dt = &meson_a1_parse_dt_extra, | |
| }; | |
| @@ -1221,14 +1221,12 @@ static const struct of_device_id meson_s4_pinctrl_dt_match[] = { | |
| }; | |
| MODULE_DEVICE_TABLE(of, meson_s4_pinctrl_dt_match); | |
| -static struct platform_driver meson_s4_pinctrl_driver = { | |
| +static struct driver meson_s4_pinctrl_driver = { | |
| .probe = meson_pinctrl_probe, | |
| - .driver = { | |
| - .name = "meson-s4-pinctrl", | |
| - .of_match_table = meson_s4_pinctrl_dt_match, | |
| - }, | |
| + .name = "meson-s4-pinctrl", | |
| + .of_match_table = meson_s4_pinctrl_dt_match, | |
| }; | |
| -module_platform_driver(meson_s4_pinctrl_driver); | |
| +core_platform_driver(meson_s4_pinctrl_driver); | |
| MODULE_DESCRIPTION("Amlogic Meson S4 SoC pinctrl driver"); | |
| MODULE_LICENSE("Dual BSD/GPL"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c | |
| index 4507dc8b55..cb4107cf00 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson.c | |
| @@ -38,22 +38,18 @@ | |
| */ | |
| #include <linux/device.h> | |
| -#include <linux/gpio/driver.h> | |
| -#include <linux/init.h> | |
| +#include <driver.h> | |
| +#include <of_device.h> | |
| +#include <gpio.h> | |
| +#include <init.h> | |
| #include <linux/io.h> | |
| -#include <linux/of.h> | |
| -#include <linux/of_address.h> | |
| +#include <of.h> | |
| +#include <of_address.h> | |
| #include <linux/pinctrl/pinconf-generic.h> | |
| -#include <linux/pinctrl/pinconf.h> | |
| -#include <linux/pinctrl/pinctrl.h> | |
| -#include <linux/pinctrl/pinmux.h> | |
| -#include <linux/platform_device.h> | |
| -#include <linux/property.h> | |
| +#include <pinctrl.h> | |
| +#include <linux/device.h> | |
| #include <linux/regmap.h> | |
| -#include <linux/seq_file.h> | |
| -#include "../core.h" | |
| -#include "../pinctrl-utils.h" | |
| #include "pinctrl-meson.h" | |
| static const unsigned int meson_bit_strides[] = { | |
| @@ -106,48 +102,7 @@ static void meson_calc_reg_and_bit(const struct meson_bank *bank, | |
| *bit &= 0x1f; | |
| } | |
| -static int meson_get_groups_count(struct pinctrl_dev *pcdev) | |
| -{ | |
| - struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| - | |
| - return pc->data->num_groups; | |
| -} | |
| - | |
| -static const char *meson_get_group_name(struct pinctrl_dev *pcdev, | |
| - unsigned selector) | |
| -{ | |
| - struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| - | |
| - return pc->data->groups[selector].name; | |
| -} | |
| - | |
| -static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, | |
| - const unsigned **pins, unsigned *num_pins) | |
| -{ | |
| - struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| - | |
| - *pins = pc->data->groups[selector].pins; | |
| - *num_pins = pc->data->groups[selector].num_pins; | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, | |
| - unsigned offset) | |
| -{ | |
| - seq_printf(s, " %s", dev_name(pcdev->dev)); | |
| -} | |
| - | |
| -static const struct pinctrl_ops meson_pctrl_ops = { | |
| - .get_groups_count = meson_get_groups_count, | |
| - .get_group_name = meson_get_group_name, | |
| - .get_group_pins = meson_get_group_pins, | |
| - .dt_node_to_map = pinconf_generic_dt_node_to_map_all, | |
| - .dt_free_map = pinctrl_utils_free_map, | |
| - .pin_dbg_show = meson_pin_dbg_show, | |
| -}; | |
| - | |
| -int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) | |
| +int meson_pmx_get_funcs_count(struct pinctrl_device *pcdev) | |
| { | |
| struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| @@ -155,7 +110,7 @@ int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) | |
| } | |
| EXPORT_SYMBOL_GPL(meson_pmx_get_funcs_count); | |
| -const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, | |
| +const char *meson_pmx_get_func_name(struct pinctrl_device *pcdev, | |
| unsigned selector) | |
| { | |
| struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| @@ -164,7 +119,7 @@ const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, | |
| } | |
| EXPORT_SYMBOL_GPL(meson_pmx_get_func_name); | |
| -int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, | |
| +int meson_pmx_get_groups(struct pinctrl_device *pcdev, unsigned selector, | |
| const char * const **groups, | |
| unsigned * const num_groups) | |
| { | |
| @@ -240,12 +195,6 @@ static int meson_pinconf_set_drive(struct meson_pinctrl *pc, | |
| return meson_pinconf_set_gpio_bit(pc, pin, MESON_REG_OUT, high); | |
| } | |
| -static int meson_pinconf_get_drive(struct meson_pinctrl *pc, | |
| - unsigned int pin) | |
| -{ | |
| - return meson_pinconf_get_gpio_bit(pc, pin, MESON_REG_OUT); | |
| -} | |
| - | |
| static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc, | |
| unsigned int pin, | |
| bool high) | |
| @@ -346,248 +295,38 @@ static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc, | |
| return 0; | |
| } | |
| -static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, | |
| - unsigned long *configs, unsigned num_configs) | |
| -{ | |
| - struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| - enum pin_config_param param; | |
| - unsigned int arg = 0; | |
| - int i, ret; | |
| - | |
| - for (i = 0; i < num_configs; i++) { | |
| - param = pinconf_to_config_param(configs[i]); | |
| - | |
| - switch (param) { | |
| - case PIN_CONFIG_DRIVE_STRENGTH_UA: | |
| - case PIN_CONFIG_OUTPUT_ENABLE: | |
| - case PIN_CONFIG_LEVEL: | |
| - arg = pinconf_to_config_argument(configs[i]); | |
| - break; | |
| - | |
| - default: | |
| - break; | |
| - } | |
| - | |
| - switch (param) { | |
| - case PIN_CONFIG_BIAS_DISABLE: | |
| - ret = meson_pinconf_disable_bias(pc, pin); | |
| - break; | |
| - case PIN_CONFIG_BIAS_PULL_UP: | |
| - ret = meson_pinconf_enable_bias(pc, pin, true); | |
| - break; | |
| - case PIN_CONFIG_BIAS_PULL_DOWN: | |
| - ret = meson_pinconf_enable_bias(pc, pin, false); | |
| - break; | |
| - case PIN_CONFIG_DRIVE_STRENGTH_UA: | |
| - ret = meson_pinconf_set_drive_strength(pc, pin, arg); | |
| - break; | |
| - case PIN_CONFIG_OUTPUT_ENABLE: | |
| - ret = meson_pinconf_set_output(pc, pin, arg); | |
| - break; | |
| - case PIN_CONFIG_LEVEL: | |
| - ret = meson_pinconf_set_output_drive(pc, pin, arg); | |
| - break; | |
| - default: | |
| - ret = -ENOTSUPP; | |
| - } | |
| - | |
| - if (ret) | |
| - return ret; | |
| - } | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) | |
| +// SMA: GPIO | |
| +static int meson_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) | |
| { | |
| - const struct meson_bank *bank; | |
| - unsigned int reg, bit, val; | |
| - int ret, conf; | |
| - | |
| - ret = meson_get_bank(pc, pin, &bank); | |
| - if (ret) | |
| - return ret; | |
| - | |
| - meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, ®, &bit); | |
| - | |
| - ret = regmap_read(pc->reg_pullen, reg, &val); | |
| - if (ret) | |
| - return ret; | |
| - | |
| - if (!(val & BIT(bit))) { | |
| - conf = PIN_CONFIG_BIAS_DISABLE; | |
| - } else { | |
| - meson_calc_reg_and_bit(bank, pin, MESON_REG_PULL, ®, &bit); | |
| - | |
| - ret = regmap_read(pc->reg_pull, reg, &val); | |
| - if (ret) | |
| - return ret; | |
| - | |
| - if (val & BIT(bit)) | |
| - conf = PIN_CONFIG_BIAS_PULL_UP; | |
| - else | |
| - conf = PIN_CONFIG_BIAS_PULL_DOWN; | |
| - } | |
| - | |
| - return conf; | |
| -} | |
| - | |
| -static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc, | |
| - unsigned int pin, | |
| - u16 *drive_strength_ua) | |
| -{ | |
| - const struct meson_bank *bank; | |
| - unsigned int reg, bit; | |
| - unsigned int val; | |
| - int ret; | |
| - | |
| - if (!pc->reg_ds) | |
| - return -ENOTSUPP; | |
| - | |
| - ret = meson_get_bank(pc, pin, &bank); | |
| - if (ret) | |
| - return ret; | |
| - | |
| - meson_calc_reg_and_bit(bank, pin, MESON_REG_DS, ®, &bit); | |
| - | |
| - ret = regmap_read(pc->reg_ds, reg, &val); | |
| - if (ret) | |
| - return ret; | |
| - | |
| - switch ((val >> bit) & 0x3) { | |
| - case MESON_PINCONF_DRV_500UA: | |
| - *drive_strength_ua = 500; | |
| - break; | |
| - case MESON_PINCONF_DRV_2500UA: | |
| - *drive_strength_ua = 2500; | |
| - break; | |
| - case MESON_PINCONF_DRV_3000UA: | |
| - *drive_strength_ua = 3000; | |
| - break; | |
| - case MESON_PINCONF_DRV_4000UA: | |
| - *drive_strength_ua = 4000; | |
| - break; | |
| - default: | |
| - return -EINVAL; | |
| - } | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, | |
| - unsigned long *config) | |
| -{ | |
| - struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| - enum pin_config_param param = pinconf_to_config_param(*config); | |
| - u16 arg; | |
| - int ret; | |
| - | |
| - switch (param) { | |
| - case PIN_CONFIG_BIAS_DISABLE: | |
| - case PIN_CONFIG_BIAS_PULL_DOWN: | |
| - case PIN_CONFIG_BIAS_PULL_UP: | |
| - if (meson_pinconf_get_pull(pc, pin) == param) | |
| - arg = 60000; | |
| - else | |
| - return -EINVAL; | |
| - break; | |
| - case PIN_CONFIG_DRIVE_STRENGTH_UA: | |
| - ret = meson_pinconf_get_drive_strength(pc, pin, &arg); | |
| - if (ret) | |
| - return ret; | |
| - break; | |
| - case PIN_CONFIG_OUTPUT_ENABLE: | |
| - ret = meson_pinconf_get_output(pc, pin); | |
| - if (ret <= 0) | |
| - return -EINVAL; | |
| - arg = 1; | |
| - break; | |
| - case PIN_CONFIG_LEVEL: | |
| - ret = meson_pinconf_get_output(pc, pin); | |
| - if (ret <= 0) | |
| - return -EINVAL; | |
| - | |
| - ret = meson_pinconf_get_drive(pc, pin); | |
| - if (ret < 0) | |
| - return -EINVAL; | |
| - | |
| - arg = ret; | |
| - break; | |
| - | |
| - default: | |
| - return -ENOTSUPP; | |
| - } | |
| - | |
| - *config = pinconf_to_config_packed(param, arg); | |
| - dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, | |
| - unsigned int num_group, | |
| - unsigned long *configs, unsigned num_configs) | |
| -{ | |
| - struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| - const struct meson_pmx_group *group = &pc->data->groups[num_group]; | |
| - int i; | |
| - | |
| - dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); | |
| - | |
| - for (i = 0; i < group->num_pins; i++) { | |
| - meson_pinconf_set(pcdev, group->pins[i], configs, | |
| - num_configs); | |
| - } | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, | |
| - unsigned int group, unsigned long *config) | |
| -{ | |
| - return -ENOTSUPP; | |
| -} | |
| - | |
| -static const struct pinconf_ops meson_pinconf_ops = { | |
| - .pin_config_get = meson_pinconf_get, | |
| - .pin_config_set = meson_pinconf_set, | |
| - .pin_config_group_get = meson_pinconf_group_get, | |
| - .pin_config_group_set = meson_pinconf_group_set, | |
| - .is_generic = true, | |
| -}; | |
| - | |
| -static int meson_gpio_get_direction(struct gpio_chip *chip, unsigned gpio) | |
| -{ | |
| - struct meson_pinctrl *pc = gpiochip_get_data(chip); | |
| + struct meson_pinctrl *pc = chip->dev->priv; | |
| int ret; | |
| ret = meson_pinconf_get_output(pc, gpio); | |
| if (ret < 0) | |
| return ret; | |
| - return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; | |
| + return ret ? GPIOF_DIR_OUT : GPIOF_DIR_IN; | |
| } | |
| -static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) | |
| +static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) | |
| { | |
| - return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false); | |
| + return meson_pinconf_set_output(chip->dev->priv, gpio, false); | |
| } | |
| -static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, | |
| - int value) | |
| +static int meson_gpio_direction_output(struct gpio_chip *chip, | |
| + unsigned int gpio, int value) | |
| { | |
| - return meson_pinconf_set_output_drive(gpiochip_get_data(chip), | |
| - gpio, value); | |
| + return meson_pinconf_set_output_drive(chip->dev->priv, gpio, value); | |
| } | |
| -static int meson_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) | |
| +static void meson_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) | |
| { | |
| - return meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value); | |
| + meson_pinconf_set_drive(chip->dev->priv, gpio, value); | |
| } | |
| -static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) | |
| +static int meson_gpio_get(struct gpio_chip *chip, unsigned int gpio) | |
| { | |
| - struct meson_pinctrl *pc = gpiochip_get_data(chip); | |
| + struct meson_pinctrl *pc = chip->dev->priv; | |
| const struct meson_bank *bank; | |
| unsigned int reg, bit, val; | |
| int ret; | |
| @@ -602,29 +341,39 @@ static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) | |
| return !!(val & BIT(bit)); | |
| } | |
| +static struct gpio_ops meson_gpio_ops = { | |
| + .direction_input = meson_gpio_direction_input, | |
| + .direction_output = meson_gpio_direction_output, | |
| + .get_direction = meson_gpio_get_direction, | |
| + .get = meson_gpio_get, | |
| + .set = meson_gpio_set, | |
| +}; | |
| + | |
| static int meson_gpiolib_register(struct meson_pinctrl *pc) | |
| { | |
| + struct device_node *gpio_np = pc->gpio_np; | |
| + struct device *gpio_dev; | |
| int ret; | |
| - pc->chip.label = pc->data->name; | |
| - pc->chip.parent = pc->dev; | |
| - pc->chip.fwnode = pc->fwnode; | |
| - pc->chip.request = gpiochip_generic_request; | |
| - pc->chip.free = gpiochip_generic_free; | |
| - pc->chip.set_config = gpiochip_generic_config; | |
| - pc->chip.get_direction = meson_gpio_get_direction; | |
| - pc->chip.direction_input = meson_gpio_direction_input; | |
| - pc->chip.direction_output = meson_gpio_direction_output; | |
| - pc->chip.get = meson_gpio_get; | |
| - pc->chip.set = meson_gpio_set; | |
| - pc->chip.base = -1; | |
| + | |
| + gpio_dev = of_platform_device_create(gpio_np, pc->dev); | |
| + if (!gpio_dev) { | |
| + dev_err(pc->dev, "failed to create gpio child device\n"); | |
| + return -ENODEV; | |
| + } | |
| + | |
| + of_platform_device_dummy_drv(gpio_dev); | |
| + | |
| + gpio_dev->priv = pc; | |
| + | |
| + pc->chip.dev = gpio_dev; | |
| + pc->chip.ops = &meson_gpio_ops; | |
| + pc->chip.base = -1; /* auto-assign */ | |
| pc->chip.ngpio = pc->data->num_pins; | |
| - pc->chip.can_sleep = true; | |
| - ret = gpiochip_add_data(&pc->chip, pc); | |
| + ret = gpiochip_add(&pc->chip); | |
| if (ret) { | |
| - dev_err(pc->dev, "can't add gpio chip %s\n", | |
| - pc->data->name); | |
| + dev_err(pc->dev, "can't add gpio chip %s\n", pc->data->name); | |
| return ret; | |
| } | |
| @@ -637,6 +386,7 @@ static struct regmap_config meson_regmap_config = { | |
| .reg_stride = 4, | |
| }; | |
| +// SMA: DONE | |
| static struct regmap *meson_map_resource(struct meson_pinctrl *pc, | |
| struct device_node *node, char *name) | |
| { | |
| @@ -648,37 +398,40 @@ static struct regmap *meson_map_resource(struct meson_pinctrl *pc, | |
| if (of_address_to_resource(node, i, &res)) | |
| return NULL; | |
| - base = devm_ioremap_resource(pc->dev, &res); | |
| + base = devm_ioremap(pc->dev, res.start, resource_size(&res)); | |
| if (IS_ERR(base)) | |
| return ERR_CAST(base); | |
| meson_regmap_config.max_register = resource_size(&res) - 4; | |
| - meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, | |
| - "%pOFn-%s", node, | |
| - name); | |
| + meson_regmap_config.name = name; | |
| + | |
| if (!meson_regmap_config.name) | |
| return ERR_PTR(-ENOMEM); | |
| - return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); | |
| + return regmap_init_mmio(pc->dev, base, &meson_regmap_config); | |
| } | |
| static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc) | |
| { | |
| - struct device_node *gpio_np; | |
| - unsigned int chips; | |
| + struct device_node *np = pc->dev->of_node; | |
| + struct device_node *child, *gpio_np = NULL; | |
| - chips = gpiochip_node_count(pc->dev); | |
| - if (!chips) { | |
| - dev_err(pc->dev, "no gpio node found\n"); | |
| - return -EINVAL; | |
| + for_each_child_of_node(np, child) { | |
| + if (of_property_read_bool(child, "gpio-controller")) { | |
| + if (gpio_np) { | |
| + dev_err(pc->dev, "multiple gpio nodes found\n"); | |
| + return -EINVAL; | |
| + } | |
| + gpio_np = child; | |
| + } | |
| } | |
| - if (chips > 1) { | |
| - dev_err(pc->dev, "multiple gpio nodes\n"); | |
| + | |
| + if (!gpio_np) { | |
| + dev_err(pc->dev, "no gpio node found\n"); | |
| return -EINVAL; | |
| } | |
| - pc->fwnode = gpiochip_node_get_first(pc->dev); | |
| - gpio_np = to_of_node(pc->fwnode); | |
| + pc->gpio_np = gpio_np; | |
| pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); | |
| if (IS_ERR_OR_NULL(pc->reg_mux)) { | |
| @@ -733,9 +486,126 @@ int meson_a1_parse_dt_extra(struct meson_pinctrl *pc) | |
| } | |
| EXPORT_SYMBOL_GPL(meson_a1_parse_dt_extra); | |
| -int meson_pinctrl_probe(struct platform_device *pdev) | |
| +// SMA: start set_state | |
| +/* Apply mux + config for one DT node that carries "groups" + "function" */ | |
| +static int meson_pinctrl_apply_group(struct meson_pinctrl *pc, | |
| + struct pinctrl_device *pdev, | |
| + struct device_node *np) | |
| +{ | |
| + const char *func_name, *group_name; | |
| + int func_idx, group_idx, n, i, ret; | |
| + const struct meson_pmx_group *grp; | |
| + | |
| + if (of_property_read_string(np, "function", &func_name)) | |
| + return 0; /* nothing to mux in this node */ | |
| + | |
| + /* Resolve function index */ | |
| + func_idx = -1; | |
| + for (i = 0; i < pc->data->num_funcs; i++) { | |
| + if (!strcmp(pc->data->funcs[i].name, func_name)) { | |
| + func_idx = i; | |
| + break; | |
| + } | |
| + } | |
| + if (func_idx < 0) { | |
| + dev_err(pc->dev, "unknown function '%s'\n", func_name); | |
| + return -EINVAL; | |
| + } | |
| + | |
| + /* Apply mux for each group listed in the "groups" property */ | |
| + n = of_property_count_strings(np, "groups"); | |
| + if (n <= 0) { | |
| + dev_err(pc->dev, "%pOF: empty 'groups'\n", np); | |
| + return -EINVAL; | |
| + } | |
| + | |
| + for (i = 0; i < n; i++) { | |
| + ret = of_property_read_string_index(np, "groups", i, | |
| + &group_name); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + group_idx = -1; | |
| + for (int j = 0; j < pc->data->num_groups; j++) { | |
| + if (!strcmp(pc->data->groups[j].name, group_name)) { | |
| + group_idx = j; | |
| + break; | |
| + } | |
| + } | |
| + if (group_idx < 0) { | |
| + dev_err(pc->dev, "unknown group '%s'\n", group_name); | |
| + return -EINVAL; | |
| + } | |
| + | |
| + if (!pc->data->set_mux) { | |
| + dev_err(pc->dev, "no set_mux in driver data\n"); | |
| + return -ENOSYS; | |
| + } | |
| + | |
| + ret = pc->data->set_mux(pdev, func_idx, group_idx); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + /* Apply pin config to every pin in this group */ | |
| + grp = &pc->data->groups[group_idx]; | |
| + for (int p = 0; p < grp->num_pins; p++) { | |
| + unsigned int pin = grp->pins[p]; | |
| + | |
| + if (of_find_property(np, "bias-disable", NULL)) | |
| + meson_pinconf_disable_bias(pc, pin); | |
| + else if (of_find_property(np, "bias-pull-up", NULL)) | |
| + meson_pinconf_enable_bias(pc, pin, true); | |
| + else if (of_find_property(np, "bias-pull-down", NULL)) | |
| + meson_pinconf_enable_bias(pc, pin, false); | |
| + | |
| + { | |
| + u32 ua; | |
| + | |
| + if (!of_property_read_u32(np, | |
| + "drive-strength-microamp", &ua)) | |
| + meson_pinconf_set_drive_strength(pc, | |
| + pin, | |
| + ua); | |
| + } | |
| + } | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int meson_pinctrl_set_state(struct pinctrl_device *pdev, | |
| + struct device_node *np) | |
| +{ | |
| + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pdev); | |
| + struct device_node *child; | |
| + int ret; | |
| + | |
| + dev_dbg(pc->dev, "set state %pOF\n", np); | |
| + | |
| + /* | |
| + * Flat format: the pin-state node itself carries "groups"/"function". | |
| + * Nested format: child nodes carry them (typical meson binding). | |
| + */ | |
| + if (of_find_property(np, "groups", NULL)) | |
| + return meson_pinctrl_apply_group(pc, pdev, np); | |
| + | |
| + for_each_child_of_node(np, child) { | |
| + ret = meson_pinctrl_apply_group(pc, pdev, child); | |
| + if (ret) | |
| + return ret; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static struct pinctrl_ops meson_pinctrl_ops = { | |
| + .set_state = meson_pinctrl_set_state, | |
| +}; | |
| + | |
| +// SMA: end set_state | |
| + | |
| +int meson_pinctrl_probe(struct device *dev) | |
| { | |
| - struct device *dev = &pdev->dev; | |
| struct meson_pinctrl *pc; | |
| int ret; | |
| @@ -750,18 +620,13 @@ int meson_pinctrl_probe(struct platform_device *pdev) | |
| if (ret) | |
| return ret; | |
| - pc->desc.name = "pinctrl-meson"; | |
| - pc->desc.owner = THIS_MODULE; | |
| - pc->desc.pctlops = &meson_pctrl_ops; | |
| - pc->desc.pmxops = pc->data->pmx_ops; | |
| - pc->desc.confops = &meson_pinconf_ops; | |
| - pc->desc.pins = pc->data->pins; | |
| - pc->desc.npins = pc->data->num_pins; | |
| - | |
| - pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc); | |
| - if (IS_ERR(pc->pcdev)) { | |
| - dev_err(pc->dev, "can't register pinctrl device"); | |
| - return PTR_ERR(pc->pcdev); | |
| + pc->pcdev.dev = dev; | |
| + pc->pcdev.ops = &meson_pinctrl_ops; | |
| + | |
| + ret = pinctrl_register(&pc->pcdev); | |
| + if (ret) { | |
| + dev_err(dev, "can't register pinctrl device\n"); | |
| + return ret; | |
| } | |
| return meson_gpiolib_register(pc); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h | |
| index 7883ea31a0..eb08bd29c0 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson.h | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson.h | |
| @@ -5,15 +5,15 @@ | |
| * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | |
| */ | |
| -#include <linux/gpio/driver.h> | |
| -#include <linux/pinctrl/pinctrl.h> | |
| -#include <linux/platform_device.h> | |
| +#include <common.h> | |
| +#include <driver.h> | |
| +#include <pinctrl.h> | |
| +#include <gpio.h> | |
| +#include <linux/device.h> | |
| #include <linux/regmap.h> | |
| #include <linux/types.h> | |
| #include <linux/module.h> | |
| -struct fwnode_handle; | |
| - | |
| struct meson_pinctrl; | |
| /** | |
| @@ -84,6 +84,20 @@ enum meson_pinconf_drv { | |
| MESON_PINCONF_DRV_4000UA, | |
| }; | |
| +/** | |
| + * struct pinctrl_pin_desc - boards/machines provide information on their | |
| + * pins, pads or other muxable units in this struct | |
| + * @number: unique pin number from the global pin number space | |
| + * @name: a name for this pin | |
| + * @drv_data: driver-defined per-pin data. pinctrl core does not touch this | |
| + */ | |
| +// TODO: Ported from Linux: 2744e8af Linus Walleij (2011-05-02 20:50) | |
| +struct pinctrl_pin_desc { | |
| + unsigned int number; | |
| + const char *name; | |
| + void *drv_data; | |
| +}; | |
| + | |
| /** | |
| * struct meson bank | |
| * | |
| @@ -117,15 +131,19 @@ struct meson_pinctrl_data { | |
| unsigned int num_funcs; | |
| const struct meson_bank *banks; | |
| unsigned int num_banks; | |
| - const struct pinmux_ops *pmx_ops; | |
| + // SMA: REMOVEME | |
| + //const struct pinmux_ops *pmx_ops; | |
| + int (*set_mux)(struct pinctrl_device *pcdev, | |
| + unsigned int func_num, unsigned int group_num); | |
| const void *pmx_data; | |
| int (*parse_dt)(struct meson_pinctrl *pc); | |
| }; | |
| struct meson_pinctrl { | |
| struct device *dev; | |
| - struct pinctrl_dev *pcdev; | |
| - struct pinctrl_desc desc; | |
| + struct pinctrl_device pcdev; | |
| + // SMA: REMOVEME | |
| + //struct pinctrl_desc desc; | |
| struct meson_pinctrl_data *data; | |
| struct regmap *reg_mux; | |
| struct regmap *reg_pullen; | |
| @@ -133,7 +151,7 @@ struct meson_pinctrl { | |
| struct regmap *reg_gpio; | |
| struct regmap *reg_ds; | |
| struct gpio_chip chip; | |
| - struct fwnode_handle *fwnode; | |
| + struct device_node *gpio_np; | |
| }; | |
| #define FUNCTION(fn) \ | |
| @@ -164,19 +182,25 @@ struct meson_pinctrl { | |
| #define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ | |
| BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0) | |
| +// SMA: | |
| #define MESON_PIN(x) PINCTRL_PIN(x, #x) | |
| +static inline struct meson_pinctrl *pinctrl_dev_get_drvdata(struct pinctrl_device *pcdev) | |
| +{ | |
| + return container_of(pcdev, struct meson_pinctrl, pcdev); | |
| +} | |
| + | |
| /* Common pmx functions */ | |
| -int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev); | |
| -const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, | |
| +int meson_pmx_get_funcs_count(struct pinctrl_device *pcdev); | |
| +const char *meson_pmx_get_func_name(struct pinctrl_device *pcdev, | |
| unsigned selector); | |
| -int meson_pmx_get_groups(struct pinctrl_dev *pcdev, | |
| +int meson_pmx_get_groups(struct pinctrl_device *pcdev, | |
| unsigned selector, | |
| const char * const **groups, | |
| unsigned * const num_groups); | |
| /* Common probe function */ | |
| -int meson_pinctrl_probe(struct platform_device *pdev); | |
| +int meson_pinctrl_probe(struct device *dev); | |
| /* Common ao groups extra dt parse function for SoCs before g12a */ | |
| int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc); | |
| /* Common extra dt parse function for SoCs like A1 */ | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.c b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c | |
| index 10adf52edd..d7b5a9054b 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson8-pmx.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c | |
| @@ -12,8 +12,7 @@ | |
| */ | |
| #include <linux/device.h> | |
| #include <linux/regmap.h> | |
| -#include <linux/pinctrl/pinctrl.h> | |
| -#include <linux/pinctrl/pinmux.h> | |
| +#include <pinctrl.h> | |
| #include "pinctrl-meson.h" | |
| #include "pinctrl-meson8-pmx.h" | |
| @@ -53,7 +52,7 @@ static void meson8_pmx_disable_other_groups(struct meson_pinctrl *pc, | |
| } | |
| } | |
| -static int meson8_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num, | |
| +int meson8_pmx_set_mux(struct pinctrl_device *pcdev, unsigned func_num, | |
| unsigned group_num) | |
| { | |
| struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| @@ -82,24 +81,5 @@ static int meson8_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num, | |
| return ret; | |
| } | |
| -static int meson8_pmx_request_gpio(struct pinctrl_dev *pcdev, | |
| - struct pinctrl_gpio_range *range, | |
| - unsigned offset) | |
| -{ | |
| - struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
| - | |
| - meson8_pmx_disable_other_groups(pc, offset, -1); | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -const struct pinmux_ops meson8_pmx_ops = { | |
| - .set_mux = meson8_pmx_set_mux, | |
| - .get_functions_count = meson_pmx_get_funcs_count, | |
| - .get_function_name = meson_pmx_get_func_name, | |
| - .get_function_groups = meson_pmx_get_groups, | |
| - .gpio_request_enable = meson8_pmx_request_gpio, | |
| -}; | |
| -EXPORT_SYMBOL_GPL(meson8_pmx_ops); | |
| MODULE_DESCRIPTION("Amlogic Meson SoCs first generation pinmux driver"); | |
| MODULE_LICENSE("GPL v2"); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.h b/drivers/pinctrl/meson/pinctrl-meson8-pmx.h | |
| index 9390dc2f80..62e7f436f9 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson8-pmx.h | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.h | |
| @@ -6,6 +6,10 @@ | |
| * Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com> | |
| */ | |
| +#include <linux/types.h> | |
| + | |
| +struct pinctrl_device; | |
| + | |
| struct meson8_pmx_data { | |
| bool is_gpio; | |
| unsigned int reg; | |
| @@ -39,4 +43,5 @@ struct meson8_pmx_data { | |
| }, \ | |
| } | |
| -extern const struct pinmux_ops meson8_pmx_ops; | |
| +int meson8_pmx_set_mux(struct pinctrl_device *pcdev, | |
| + unsigned int func_num, unsigned int group_num); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c | |
| index 3da7f3799c..18d13dc817 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson8.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson8.c | |
| @@ -1089,7 +1089,7 @@ static const struct meson_pinctrl_data meson8_cbus_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson8_cbus_groups), | |
| .num_funcs = ARRAY_SIZE(meson8_cbus_functions), | |
| .num_banks = ARRAY_SIZE(meson8_cbus_banks), | |
| - .pmx_ops = &meson8_pmx_ops, | |
| + .set_mux = meson8_pmx_set_mux, | |
| }; | |
| static const struct meson_pinctrl_data meson8_aobus_pinctrl_data = { | |
| @@ -1102,7 +1102,7 @@ static const struct meson_pinctrl_data meson8_aobus_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson8_aobus_groups), | |
| .num_funcs = ARRAY_SIZE(meson8_aobus_functions), | |
| .num_banks = ARRAY_SIZE(meson8_aobus_banks), | |
| - .pmx_ops = &meson8_pmx_ops, | |
| + .set_mux = meson8_pmx_set_mux, | |
| .parse_dt = &meson8_aobus_parse_dt_extra, | |
| }; | |
| @@ -1126,11 +1126,9 @@ static const struct of_device_id meson8_pinctrl_dt_match[] = { | |
| { }, | |
| }; | |
| -static struct platform_driver meson8_pinctrl_driver = { | |
| +static struct driver meson8_pinctrl_driver = { | |
| .probe = meson_pinctrl_probe, | |
| - .driver = { | |
| - .name = "meson8-pinctrl", | |
| - .of_match_table = meson8_pinctrl_dt_match, | |
| - }, | |
| + .name = "meson8-pinctrl", | |
| + .of_match_table = meson8_pinctrl_dt_match, | |
| }; | |
| -builtin_platform_driver(meson8_pinctrl_driver); | |
| +core_platform_driver(meson8_pinctrl_driver); | |
| diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c | |
| index a71e1f4135..e77a512bf2 100644 | |
| --- a/drivers/pinctrl/meson/pinctrl-meson8b.c | |
| +++ b/drivers/pinctrl/meson/pinctrl-meson8b.c | |
| @@ -953,7 +953,7 @@ static const struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson8b_cbus_groups), | |
| .num_funcs = ARRAY_SIZE(meson8b_cbus_functions), | |
| .num_banks = ARRAY_SIZE(meson8b_cbus_banks), | |
| - .pmx_ops = &meson8_pmx_ops, | |
| + .set_mux = meson8_pmx_set_mux, | |
| }; | |
| static const struct meson_pinctrl_data meson8b_aobus_pinctrl_data = { | |
| @@ -966,7 +966,7 @@ static const struct meson_pinctrl_data meson8b_aobus_pinctrl_data = { | |
| .num_groups = ARRAY_SIZE(meson8b_aobus_groups), | |
| .num_funcs = ARRAY_SIZE(meson8b_aobus_functions), | |
| .num_banks = ARRAY_SIZE(meson8b_aobus_banks), | |
| - .pmx_ops = &meson8_pmx_ops, | |
| + .set_mux = meson8_pmx_set_mux, | |
| .parse_dt = &meson8_aobus_parse_dt_extra, | |
| }; | |
| @@ -982,11 +982,9 @@ static const struct of_device_id meson8b_pinctrl_dt_match[] = { | |
| { }, | |
| }; | |
| -static struct platform_driver meson8b_pinctrl_driver = { | |
| +static struct driver meson8b_pinctrl_driver = { | |
| .probe = meson_pinctrl_probe, | |
| - .driver = { | |
| - .name = "meson8b-pinctrl", | |
| - .of_match_table = meson8b_pinctrl_dt_match, | |
| - }, | |
| + .name = "meson8b-pinctrl", | |
| + .of_match_table = meson8b_pinctrl_dt_match, | |
| }; | |
| -builtin_platform_driver(meson8b_pinctrl_driver); | |
| +core_platform_driver(meson8b_pinctrl_driver); | |
| -- | |
| 2.43.0 | |
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