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| --- | |
| GPIO_EMC_00: | |
| SW_MUX_CTL: | |
| SEMC_DATA00: 0 | |
| FLEXPWM4_PWMA00: 1 | |
| LPSPI2_SCK: 2 | |
| XBAR1_XBAR_IN02: 3 | |
| FLEXIO1_FLEXIO00: 4 | |
| GPIO4_IO00: 5 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_01: | |
| SW_MUX_CTL: | |
| SEMC_DATA01: 0 | |
| FLEXPWM4_PWMB00: 1 | |
| LPSPI2_PCS0: 2 | |
| XBAR1_IN03: 3 | |
| FLEXIO1_FLEXIO01: 4 | |
| GPIO4_IO01: 5 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_02: | |
| SW_MUX_CTL: | |
| SEMC_DATA02: 0 | |
| FLEXPWM4_PWMA01: 1 | |
| LPSPI2_SDO: 2 | |
| XBAR1_INOUT04: 3 | |
| FLEXIO1_FLEXIO02: 4 | |
| GPIO4_IO02: 5 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_03: | |
| SW_MUX_CTL: | |
| SEMC_DATA03: 0 | |
| FLEXPWM4_PWMB01: 1 | |
| LPSPI2_SDI: 2 | |
| XBAR1_INOUT05: 3 | |
| FLEXIO1_FLEXIO03: 4 | |
| GPIO4_IO03: 5 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_04: | |
| SW_MUX_CTL: | |
| SEMC_DATA04: 0 | |
| FLEXPWM4_PWMA02: 1 | |
| SAI2_TX_DATA: 2 | |
| XBAR1_INOUT06: 3 | |
| FLEXIO1_FLEXIO04: 4 | |
| GPIO4_IO04: 5 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_05: | |
| SW_MUX_CTL: | |
| SEMC_DATA05: 0 | |
| FLEXPWM4_PWMB02: 1 | |
| SAI2_TX_SYNC: 2 | |
| XBAR1_INOUT07: 3 | |
| FLEXIO1_FLEXIO05: 4 | |
| GPIO4_IO05: 5 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_06: | |
| SW_MUX_CTL: | |
| SEMC_DATA06: 0 | |
| FLEXPWM2_PWMA00: 1 | |
| SAI2_TX_BCLK: 2 | |
| XBAR1_INOUT08: 3 | |
| FLEXIO1_FLEXIO06: 4 | |
| GPIO4_IO06: 5 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_07: | |
| SW_MUX_CTL: | |
| SEMC_DATA07: 0 | |
| FLEXPWM2_PWMB00: 1 | |
| SAI2_MCLK: 2 | |
| XBAR1_INOUT09: 3 | |
| FLEXIO1_FLEXIO07: 4 | |
| GPIO4_IO07: 5 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_08: | |
| SW_MUX_CTL: | |
| SEMC_DM00: 0 | |
| FLEXPWM2_PWMA01: 1 | |
| SAI2_RX_DATA: 2 | |
| XBAR1_INOUT17: 3 | |
| FLEXIO1_FLEXIO08: 4 | |
| GPIO4_IO08: 5 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_09: | |
| SW_MUX_CTL: | |
| SEMC_ADDR00: 0 | |
| FLEXPWM2_PWMB01: 1 | |
| SAI2_RX_SYNC: 2 | |
| FLEXCAN2_TX: 3 | |
| FLEXIO1_FLEXIO09: 4 | |
| GPIO4_IO09: 5 | |
| FLEXSPI2_B_SS1_B: 8 | |
| GPIO_EMC_10: | |
| SW_MUX_CTL: | |
| SEMC_ADDR01: 0 | |
| FLEXPWM2_PWMA02: 1 | |
| SAI2_RX_BCLK: 2 | |
| FLEXCAN2_RX: 3 | |
| FLEXIO1_FLEXIO10: 4 | |
| GPIO4_IO10: 5 | |
| FLEXSPI2_B_SS0_B: 8 | |
| GPIO_EMC_11: | |
| SW_MUX_CTL: | |
| SEMC_ADDR02: 0 | |
| FLEXPWM2_PWMB02: 1 | |
| LPI2C4_SDA: 2 | |
| USDHC2_RESET_B: 3 | |
| FLEXIO1_FLEXIO11: 4 | |
| GPIO4_IO11: 5 | |
| FLEXSPI2_B_DQS: 8 | |
| GPIO_EMC_12: | |
| SW_MUX_CTL: | |
| SEMC_ADDR03: 0 | |
| XBAR1_IN24: 1 | |
| LPI2C4_SCL: 2 | |
| USDHC1_WP: 3 | |
| FLEXPWM1_PWMA03: 4 | |
| GPIO4_IO12: 5 | |
| FLEXSPI2_B_SCLK: 8 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_13: | |
| SW_MUX_CTL: | |
| SEMC_ADDR04: 0 | |
| XBAR1_IN25: 1 | |
| LPUART3_TX: 2 | |
| MQS_RIGHT: 3 | |
| FLEXPWM1_PWMB03: 4 | |
| GPIO4_IO13: 5 | |
| FLEXSPI2_B_DATA00: 8 | |
| XBAR_INPUT_SELECT: 1 | |
| LPUART3_TX_INPUT_SELECT: 1 | |
| GPIO_EMC_14: | |
| SW_MUX_CTL: | |
| SEMC_ADDR05: 0 | |
| XBAR1_INOUT19: 1 | |
| LPUART3_RX: 2 | |
| MQS_LEFT: 3 | |
| LPSPI2_PCS1: 4 | |
| GPIO4_IO14: 5 | |
| FLEXSPI2_B_DATA01: 8 | |
| XBAR_INPUT_SELECT: 0 | |
| LPUART3_RX_INPUT_SELECT: 1 | |
| GPIO_EMC_15: | |
| SW_MUX_CTL: | |
| SEMC_ADDR06: 0 | |
| XBAR1_IN20: 1 | |
| LPUART3_CTS_B: 2 | |
| SPDIF_OUT: 3 | |
| QTIMER3_TIMER0: 4 | |
| GPIO4_IO15: 5 | |
| FLEXSPI2_B_DATA02: 8 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_16: | |
| SW_MUX_CTL: | |
| SEMC_ADDR07: 0 | |
| XBAR1_IN21: 1 | |
| LPUART3_RTS_B: 2 | |
| SPDIF_IN: 3 | |
| QTIMER3_TIMER1: 4 | |
| GPIO4_IO16: 5 | |
| FLEXSPI2_B_DATA03: 8 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_17: | |
| SW_MUX_CTL: | |
| SEMC_ADDR08: 0 | |
| FLEXPWM4_PWMA03: 1 | |
| LPUART4_CTS_B: 2 | |
| FLEXCAN1_TX: 3 | |
| QTIMER3_TIMER2: 4 | |
| GPIO4_IO17: 5 | |
| GPIO_EMC_18: | |
| SW_MUX_CTL: | |
| SEMC_ADDR09: 0 | |
| FLEXPWM4_PWMB03: 1 | |
| LPUART4_RTS_B: 2 | |
| FLEXCAN1_RX: 3 | |
| QTIMER3_TIMER3: 4 | |
| GPIO4_IO18: 5 | |
| SNVS_VIO_5_CTL: 6 | |
| GPIO_EMC_19: | |
| SW_MUX_CTL: | |
| SEMC_ADDR11: 0 | |
| FLEXPWM2_PWMA03: 1 | |
| LPUART4_TX: 2 | |
| ENET_RDATA01: 3 | |
| QTIMER2_TIMER0: 4 | |
| GPIO4_IO19: 5 | |
| SNVS_VIO_5: 6 | |
| LPUART4_TX_INPUT_SELECT: 1 | |
| GPIO_EMC_20: | |
| SW_MUX_CTL: | |
| SEMC_ADDR12: 0 | |
| FLEXPWM2_PWMB03: 1 | |
| LPUART4_RX: 2 | |
| ENET_RDATA00: 3 | |
| QTIMER2_TIMER1: 4 | |
| GPIO4_IO20: 5 | |
| LPUART4_RX_INPUT_SELECT: 1 | |
| GPIO_EMC_21: | |
| SW_MUX_CTL: | |
| SEMC_BA0: 0 | |
| FLEXPWM3_PWMA03: 1 | |
| LPI2C3_SDA: 2 | |
| ENET_TDATA01: 3 | |
| QTIMER2_TIMER2: 4 | |
| GPIO4_IO21: 5 | |
| GPIO_EMC_22: | |
| SW_MUX_CTL: | |
| SEMC_BA1: 0 | |
| FLEXPWM3_PWMB03: 1 | |
| LPI2C3_SCL: 2 | |
| ENET_TDATA00: 3 | |
| QTIMER2_TIMER3: 4 | |
| GPIO4_IO22: 5 | |
| FLEXSPI2_A_SS1_B: 8 | |
| GPIO_EMC_23: | |
| SW_MUX_CTL: | |
| SEMC_ADDR10: 0 | |
| FLEXPWM1_PWMA00: 1 | |
| LPUART5_TX: 2 | |
| ENET_RX_EN: 3 | |
| GPT1_CAPTURE2: 4 | |
| GPIO4_IO23: 5 | |
| FLEXSPI2_A_DQS: 8 | |
| LPUART5_TX_INPUT_SELECT: 0 | |
| GPIO_EMC_24: | |
| SW_MUX_CTL: | |
| SEMC_CAS: 0 | |
| FLEXPWM1_PWMB00: 1 | |
| LPUART5_RX: 2 | |
| ENET_TX_EN: 3 | |
| GPT1_CAPTURE1: 4 | |
| GPIO4_IO24: 5 | |
| FLEXSPI2_A_SS0_B: 8 | |
| LPUART5_RX_INPUT_SELECT: 0 | |
| GPIO_EMC_25: | |
| SW_MUX_CTL: | |
| SEMC_RAS: 0 | |
| FLEXPWM1_PWMA01: 1 | |
| LPUART6_TX: 2 | |
| ENET_TX_CLK: 3 | |
| ENET_REF_CLK: 4 | |
| GPIO4_IO25: 5 | |
| FLEXSPI2_A_SCLK: 8 | |
| LPUART6_TX_INPUT_SELECT: 0 | |
| GPIO_EMC_26: | |
| SW_MUX_CTL: | |
| SEMC_CLK: 0 | |
| FLEXPWM1_PWMB01: 1 | |
| LPUART6_RX: 2 | |
| ENET_RX_ER: 3 | |
| FLEXIO1_FLEXIO12: 4 | |
| GPIO4_IO26: 5 | |
| FLEXSPI2_A_DATA00: 8 | |
| LPUART6_RX_INPUT_SELECT: 0 | |
| GPIO_EMC_27: | |
| SW_MUX_CTL: | |
| SEMC_CKE: 0 | |
| FLEXPWM1_PWMA02: 1 | |
| LPUART5_RTS_B: 2 | |
| LPSPI1_SCK: 3 | |
| FLEXIO1_FLEXIO13: 4 | |
| GPIO4_IO27: 5 | |
| FLEXSPI2_A_DATA01: 8 | |
| GPIO_EMC_28: | |
| SW_MUX_CTL: | |
| SEMC_WE: 0 | |
| FLEXPWM1_PWMB02: 1 | |
| LPUART5_CTS_B: 2 | |
| LPSPI1_SDO: 3 | |
| FLEXIO1_FLEXIO14: 4 | |
| GPIO4_IO28: 5 | |
| FLEXSPI2_A_DATA02: 8 | |
| GPIO_EMC_29: | |
| SW_MUX_CTL: | |
| SEMC_CS0: 0 | |
| FLEXPWM3_PWMA00: 1 | |
| LPUART6_RTS_B: 2 | |
| LPSPI1_SDI: 3 | |
| FLEXIO1_FLEXIO15: 4 | |
| GPIO4_IO29: 5 | |
| FLEXSPI2_A_DATA03: 8 | |
| GPIO_EMC_30: | |
| SW_MUX_CTL: | |
| SEMC_DATA08: 0 | |
| FLEXPWM3_PWMB00: 1 | |
| LPUART6_CTS_B: 2 | |
| LPSPI1_PCS0: 3 | |
| CSI_DATA23: 4 | |
| GPIO4_IO30: 5 | |
| ENET2_TDATA00: 8 | |
| GPIO_EMC_31: | |
| SW_MUX_CTL: | |
| SEMC_DATA09: 0 | |
| FLEXPWM3_PWMA01: 1 | |
| LPUART7_TX: 2 | |
| LPSPI1_PCS1: 3 | |
| CSI_DATA22: 4 | |
| GPIO4_IO31: 5 | |
| ENET2_TDATA01: 8 | |
| LPUART7_TX_INPUT_SELECT: 1 | |
| GPIO_EMC_32: | |
| SW_MUX_CTL: | |
| SEMC_DATA10: 0 | |
| FLEXPWM3_PWMB01: 1 | |
| LPUART7_RX: 2 | |
| CCM_PMIC_RDY: 3 | |
| CSI_DATA21: 4 | |
| GPIO3_IO18: 5 | |
| ENET2_TX_EN: 8 | |
| LPUART7_RX_INPUT_SELECT: 1 | |
| GPIO_EMC_33: | |
| SW_MUX_CTL: | |
| SEMC_DATA11: 0 | |
| FLEXPWM3_PWMA02: 1 | |
| USDHC1_RESET_B: 2 | |
| SAI3_RX_DATA: 3 | |
| CSI_DATA20: 4 | |
| GPIO3_IO19: 5 | |
| ENET2_TX_CLK: 8 | |
| ENET2_REF_CLK2: 9 | |
| GPIO_EMC_34: | |
| SW_MUX_CTL: | |
| SEMC_DATA12: 0 | |
| FLEXPWM3_PWMB02: 1 | |
| USDHC1_VSELECT: 2 | |
| SAI3_RX_SYNC: 3 | |
| CSI_DATA19: 4 | |
| GPIO3_IO20: 5 | |
| ENET2_RX_ER: 8 | |
| GPIO_EMC_35: | |
| SW_MUX_CTL: | |
| SEMC_DATA13: 0 | |
| XBAR1_INOUT18: 1 | |
| GPT1_COMPARE1: 2 | |
| SAI3_RX_BCLK: 3 | |
| CSI_DATA18: 4 | |
| GPIO3_IO21: 5 | |
| USDHC1_CD_B: 6 | |
| ENET2_RDATA00: 8 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_36: | |
| SW_MUX_CTL: | |
| SEMC_DATA14: 0 | |
| XBAR1_IN22: 1 | |
| GPT1_COMPARE2: 2 | |
| SAI3_TX_DATA: 3 | |
| CSI_DATA17: 4 | |
| GPIO3_IO22: 5 | |
| USDHC1_WP: 6 | |
| ENET2_RDATA01: 8 | |
| FLEXCAN3_TX: 9 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_37: | |
| SW_MUX_CTL: | |
| SEMC_DATA15: 0 | |
| XBAR1_IN23: 1 | |
| GPT1_COMPARE3: 2 | |
| SAI3_MCLK: 3 | |
| CSI_DATA16: 4 | |
| GPIO3_IO23: 5 | |
| USDHC2_WP: 6 | |
| ENET2_RX_EN: 8 | |
| FLEXCAN3_RX: 9 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_EMC_38: | |
| SW_MUX_CTL: | |
| SEMC_DM01: 0 | |
| FLEXPWM1_PWMA03: 1 | |
| LPUART8_TX: 2 | |
| SAI3_TX_BCLK: 3 | |
| CSI_FIELD: 4 | |
| GPIO3_IO24: 5 | |
| USDHC2_VSELECT: 6 | |
| ENET2_MDC: 8 | |
| LPUART8_TX_INPUT_SELECT: 2 | |
| GPIO_EMC_39: | |
| SW_MUX_CTL: | |
| SEMC_DQS: 0 | |
| FLEXPWM1_PWMB03: 1 | |
| LPUART8_RX: 2 | |
| SAI3_TX_SYNC: 3 | |
| WDOG1_WDOG_B: 4 | |
| GPIO3_IO25: 5 | |
| USDHC2_CD_B: 6 | |
| ENET2_MDIO: 8 | |
| SEMC_DQS4: 9 | |
| LPUART8_RX_INPUT_SELECT: 2 | |
| GPIO_EMC_40: | |
| SW_MUX_CTL: | |
| SEMC_RDY: 0 | |
| GPT2_CAPTURE2: 1 | |
| LPSPI1_PCS2: 2 | |
| USB_OTG2_OC: 3 | |
| ENET_MDC: 4 | |
| GPIO3_IO26: 5 | |
| USDHC2_RESET_B: 6 | |
| SEMC_CLK5: 9 | |
| GPIO_EMC_41: | |
| SW_MUX_CTL: | |
| SEMC_CSX00: 0 | |
| GPT2_CAPTURE1: 1 | |
| LPSPI1_PCS3: 2 | |
| USB_OTG2_PWR: 3 | |
| ENET_MDIO: 4 | |
| GPIO3_IO27: 5 | |
| USDHC1_VSELECT: 6 | |
| GPIO_AD_B0_00: | |
| SW_MUX_CTL: | |
| FLEXPWM2_PWMA03: 0 | |
| XBAR1_INOUT14: 1 | |
| REF_CLK_32K: 2 | |
| USB_OTG2_ID: 3 | |
| LPI2C1_SCLS: 4 | |
| GPIO1_IO00: 5 | |
| USDHC1_RESET_B: 6 | |
| LPSPI3_SCK: 7 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_AD_B0_01: | |
| SW_MUX_CTL: | |
| FLEXPWM2_PWMB03: 0 | |
| XBAR1_INOUT15: 1 | |
| REF_CLK_24M: 2 | |
| USB_OTG1_ID: 3 | |
| LPI2C1_SDAS: 4 | |
| GPIO1_IO01: 5 | |
| EWM_OUT_B: 6 | |
| LPSPI3_SDO: 7 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_AD_B0_02: | |
| SW_MUX_CTL: | |
| FLEXCAN2_TX: 0 | |
| XBAR1_INOUT16: 1 | |
| LPUART6_TX: 2 | |
| USB_OTG1_PWR: 3 | |
| FLEXPWM1_PWMX00: 4 | |
| GPIO1_IO02: 5 | |
| LPI2C1_HREQ: 6 | |
| LPSPI3_SDI: 7 | |
| XBAR_INPUT_SELECT: 0 | |
| LPUART6_TX_INPUT_SELECT: 1 | |
| GPIO_AD_B0_03: | |
| SW_MUX_CTL: | |
| FLEXCAN2_RX: 0 | |
| XBAR1_INOUT17: 1 | |
| LPUART6_RX: 2 | |
| USB_OTG1_OC: 3 | |
| FLEXPWM1_PWMX01: 4 | |
| GPIO1_IO03: 5 | |
| REF_CLK_24M: 6 | |
| LPSPI3_PCS0: 7 | |
| XBAR_INPUT_SELECT: 1 | |
| LPUART6_RX_INPUT_SELECT: 1 | |
| GPIO_AD_B0_04: | |
| SW_MUX_CTL: | |
| SRC_BOOT_MODE00: 0 | |
| MQS_RIGHT: 1 | |
| ENET_TX_DATA03: 2 | |
| SAI2_TX_SYNC: 3 | |
| CSI_DATA09: 4 | |
| GPIO1_IO04: 5 | |
| PIT_TRIGGER00: 6 | |
| LPSPI3_PCS1: 7 | |
| GPIO_AD_B0_05: | |
| SW_MUX_CTL: | |
| SRC_BOOT_MODE01: 0 | |
| MQS_LEFT: 1 | |
| ENET_TX_DATA02: 2 | |
| SAI2_TX_BCLK: 3 | |
| CSI_DATA08: 4 | |
| GPIO1_IO05: 5 | |
| XBAR1_INOUT17: 6 | |
| LPSPI3_PCS2: 7 | |
| XBAR_INPUT_SELECT: 2 | |
| GPIO_AD_B0_06: | |
| SW_MUX_CTL: | |
| JTAG_TMS: 0 | |
| GPT2_COMPARE1: 1 | |
| ENET_RX_CLK: 2 | |
| SAI2_RX_BCLK: 3 | |
| CSI_DATA07: 4 | |
| GPIO1_IO06: 5 | |
| XBAR1_INOUT18: 6 | |
| LPSPI3_PCS3: 7 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_AD_B0_07: | |
| SW_MUX_CTL: | |
| JTAG_TCK: 0 | |
| GPT2_COMPARE2: 1 | |
| ENET_TX_ER: 2 | |
| SAI2_RX_SYNC: 3 | |
| CSI_DATA06: 4 | |
| GPIO1_IO07: 5 | |
| XBAR1_INOUT19: 6 | |
| ENET_1588_EVENT3_OUT: 7 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_AD_B0_08: | |
| SW_MUX_CTL: | |
| JTAG_MOD: 0 | |
| GPT2_COMPARE3: 1 | |
| ENET_RX_DATA03: 2 | |
| SAI2_RX_DATA: 3 | |
| CSI_DATA05: 4 | |
| GPIO1_IO08: 5 | |
| XBAR1_IN20: 6 | |
| ENET_1588_EVENT3_IN: 7 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_AD_B0_09: | |
| SW_MUX_CTL: | |
| JTAG_TDI: 0 | |
| FLEXPWM2_PWMA03: 1 | |
| ENET_RX_DATA02: 2 | |
| SAI2_TX_DATA: 3 | |
| CSI_DATA04: 4 | |
| GPIO1_IO09: 5 | |
| XBAR1_IN21: 6 | |
| GPT2_CLK: 7 | |
| SEMC_DQS4: 9 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_AD_B0_10: | |
| SW_MUX_CTL: | |
| JTAG_TDO: 0 | |
| FLEXPWM1_PWMA03: 1 | |
| ENET_CRS: 2 | |
| SAI2_MCLK: 3 | |
| CSI_DATA03: 4 | |
| GPIO1_IO10: 5 | |
| XBAR1_IN22: 6 | |
| ENET_1588_EVENT0_OUT: 7 | |
| FLEXCAN3_TX: 8 | |
| ARM_TRACE_SWO: 9 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_AD_B0_11: | |
| SW_MUX_CTL: | |
| JTAG_TRSTB: 0 | |
| FLEXPWM1_PWMB03: 1 | |
| ENET_COL: 2 | |
| WDOG1_WDOG_B: 3 | |
| CSI_DATA02: 4 | |
| GPIO1_IO11: 5 | |
| XBAR1_IN23: 6 | |
| ENET_1588_EVENT0_IN: 7 | |
| FLEXCAN3_RX: 8 | |
| SEMC_CLK6: 9 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_AD_B0_12: | |
| SW_MUX_CTL: | |
| LPI2C4_SCL: 0 | |
| CCM_PMIC_READY: 1 | |
| LPUART1_TX: 2 | |
| WDOG2_WDOG_B: 3 | |
| FLEXPWM1_PWMX02: 4 | |
| GPIO1_IO12: 5 | |
| ENET_1588_EVENT1_OUT: 6 | |
| NMI_GLUE_NMI: 7 | |
| ADC: | |
| - ADC1_IN1 | |
| GPIO_AD_B0_13: | |
| SW_MUX_CTL: | |
| LPI2C4_SDA: 0 | |
| GPT1_CLK: 1 | |
| LPUART1_RX: 2 | |
| EWM_OUT_B: 3 | |
| FLEXPWM1_PWMX03: 4 | |
| GPIO1_IO13: 5 | |
| ENET_1588_EVENT1_IN: 6 | |
| REF_CLK_24M: 7 | |
| ADC: | |
| - ADC1_IN2 | |
| GPIO_AD_B0_14: | |
| SW_MUX_CTL: | |
| USB_OTG2_OC: 0 | |
| XBAR1_IN24: 1 | |
| LPUART1_CTS_B: 2 | |
| ENET_1588_EVENT0_OUT: 3 | |
| CSI_VSYNC: 4 | |
| GPIO1_IO14: 5 | |
| FLEXCAN2_TX: 6 | |
| FLEXCAN3_TX: 8 | |
| ADC: | |
| - ADC1_IN3 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_AD_B0_15: | |
| SW_MUX_CTL: | |
| USB_OTG2_PWR: 0 | |
| XBAR1_IN25: 1 | |
| LPUART1_RTS_B: 2 | |
| ENET_1588_EVENT0_IN: 3 | |
| CSI_HSYNC: 4 | |
| GPIO1_IO15: 5 | |
| FLEXCAN2_RX: 6 | |
| WDOG1_WDOG_RST_B_DEB: 7 | |
| FLEXCAN3_RX: 8 | |
| ADC: | |
| - ADC1_IN4 | |
| XBAR_INPUT_SELECT: 0 | |
| GPIO_AD_B1_00: | |
| SW_MUX_CTL: | |
| USB_OTG2_ID: 0 | |
| QTIMER3_TIMER0: 1 | |
| LPUART2_CTS_B: 2 | |
| LPI2C1_SCL: 3 | |
| WDOG1_B: 4 | |
| GPIO1_IO16: 5 | |
| USDHC1_WP: 6 | |
| KPP_ROW07: 7 | |
| ENET2_1588_EVENT0_OUT: 8 | |
| FLEXIO3_FLEXIO00: 9 | |
| ADC: | |
| - ADC1_IN5 | |
| - ADC2_IN5 | |
| GPIO_AD_B1_01: | |
| SW_MUX_CTL: | |
| USB_OTG1_PWR: 0 | |
| QTIMER3_TIMER1: 1 | |
| LPUART2_RTS_B: 2 | |
| LPI2C1_SDA: 3 | |
| CCM_PMIC_READY: 4 | |
| GPIO1_IO17: 5 | |
| USDHC1_VSELECT: 6 | |
| KPP_COL07: 7 | |
| ENET2_1588_EVENT0_IN: 8 | |
| FLEXIO3_FLEXIO01: 9 | |
| ADC: | |
| - ADC1_IN6 | |
| - ADC2_IN6 | |
| GPIO_AD_B1_02: | |
| SW_MUX_CTL: | |
| USB_OTG1_ID: 0 | |
| QTIMER3_TIMER2: 1 | |
| LPUART2_TX: 2 | |
| SPDIF_OUT: 3 | |
| ENET_1588_EVENT2_OUT: 4 | |
| GPIO1_IO18: 5 | |
| USDHC1_CD_B: 6 | |
| KPP_ROW06: 7 | |
| GPT2_CLK: 8 | |
| FLEXIO3_FLEXIO02: 9 | |
| ADC: | |
| - ADC1_IN7 | |
| - ADC2_IN7 | |
| LPUART2_TX_INPUT_SELECT: 1 | |
| GPIO_AD_B1_03: | |
| SW_MUX_CTL: | |
| USB_OTG1_OC: 0 | |
| QTIMER3_TIMER3: 1 | |
| LPUART2_RX: 2 | |
| SPDIF_IN: 3 | |
| ENET_1588_EVENT2_IN: 4 | |
| GPIO1_IO19: 5 | |
| USDHC2_CD_B: 6 | |
| KPP_COL06: 7 | |
| GPT2_CAPTURE1: 8 | |
| FLEXIO3_FLEXIO03: 9 | |
| ADC: | |
| - ADC1_IN8 | |
| - ADC2_IN8 | |
| LPUART2_RX_INPUT_SELECT: 1 | |
| GPIO_AD_B1_04: | |
| SW_MUX_CTL: | |
| FLEXSPIB_DATA03: 0 | |
| ENET_MDC: 1 | |
| LPUART3_CTS_B: 2 | |
| SPDIF_SR_CLK: 3 | |
| CSI_PIXCLK: 4 | |
| GPIO1_IO20: 5 | |
| USDHC2_DATA0: 6 | |
| KPP_ROW05: 7 | |
| GPT2_CAPTURE2: 8 | |
| FLEXIO3_FLEXIO04: 9 | |
| ADC: | |
| - ADC1_IN9 | |
| - ADC2_IN9 | |
| GPIO_AD_B1_05: | |
| SW_MUX_CTL: | |
| FLEXSPIB_DATA02: 0 | |
| ENET_MDIO: 1 | |
| LPUART3_RTS_B: 2 | |
| SPDIF_OUT: 3 | |
| CSI_MCLK: 4 | |
| GPIO1_IO21: 5 | |
| USDHC2_DATA1: 6 | |
| KPP_COL05: 7 | |
| GPT2_COMPARE1: 8 | |
| FLEXIO3_FLEXIO05: 9 | |
| ADC: | |
| - ADC1_IN10 | |
| - ADC2_IN10 | |
| GPIO_AD_B1_06: | |
| SW_MUX_CTL: | |
| FLEXSPIB_DATA01: 0 | |
| LPI2C3_SDA: 1 | |
| LPUART3_TX: 2 | |
| SPDIF_LOCK: 3 | |
| CSI_VSYNC: 4 | |
| GPIO1_IO22: 5 | |
| USDHC2_DATA2: 6 | |
| KPP_ROW04: 7 | |
| GPT2_COMPARE2: 8 | |
| FLEXIO3_FLEXIO06: 9 | |
| ADC: | |
| - ADC1_IN11 | |
| - ADC2_IN11 | |
| LPUART3_TX_INPUT_SELECT: 0 | |
| GPIO_AD_B1_07: | |
| SW_MUX_CTL: | |
| FLEXSPIB_DATA00: 0 | |
| LPI2C3_SCL: 1 | |
| LPUART3_RX: 2 | |
| SPDIF_EXT_CLK: 3 | |
| CSI_HSYNC: 4 | |
| GPIO1_IO23: 5 | |
| USDHC2_DATA3: 6 | |
| KPP_COL04: 7 | |
| GPT2_COMPARE3: 8 | |
| FLEXIO3_FLEXIO07: 9 | |
| ADC: | |
| - ADC1_IN12 | |
| - ADC2_IN12 | |
| LPUART3_RX_INPUT_SELECT: 0 | |
| GPIO_AD_B1_08: | |
| SW_MUX_CTL: | |
| FLEXSPIA_SS1_B: 0 | |
| FLEXPWM4_PWMA00: 1 | |
| FLEXCAN1_TX: 2 | |
| CCM_PMIC_READY: 3 | |
| CSI_DATA09: 4 | |
| GPIO1_IO24: 5 | |
| USDHC2_CMD: 6 | |
| KPP_ROW03: 7 | |
| FLEXIO3_FLEXIO08: 9 | |
| ADC: | |
| - ADC1_IN13 | |
| - ADC2_IN13 | |
| GPIO_AD_B1_09: | |
| SW_MUX_CTL: | |
| FLEXSPIA_DQS: 0 | |
| FLEXPWM4_PWMA01: 1 | |
| FLEXCAN1_RX: 2 | |
| SAI1_MCLK: 3 | |
| CSI_DATA08: 4 | |
| GPIO1_IO25: 5 | |
| USDHC2_CLK: 6 | |
| KPP_COL03: 7 | |
| FLEXIO3_FLEXIO09: 9 | |
| ADC: | |
| - ADC1_IN14 | |
| - ADC2_IN14 | |
| GPIO_AD_B1_10: | |
| SW_MUX_CTL: | |
| FLEXSPIA_DATA03: 0 | |
| WDOG1_B: 1 | |
| LPUART8_TX: 2 | |
| SAI1_RX_SYNC: 3 | |
| CSI_DATA07: 4 | |
| GPIO1_IO26: 5 | |
| USDHC2_WP: 6 | |
| KPP_ROW02: 7 | |
| ENET2_1588_EVENT1_OUT: 8 | |
| FLEXIO3_FLEXIO10: 9 | |
| ADC: | |
| - ADC1_IN15 | |
| - ADC2_IN15 | |
| LPUART8_TX_INPUT_SELECT: 1 | |
| GPIO_AD_B1_11: | |
| SW_MUX_CTL: | |
| FLEXSPIA_DATA02: 0 | |
| EWM_OUT_B: 1 | |
| LPUART8_RX: 2 | |
| SAI1_RX_BCLK: 3 | |
| CSI_DATA06: 4 | |
| GPIO1_IO27: 5 | |
| USDHC2_RESET_B: 6 | |
| KPP_COL02: 7 | |
| ENET2_1588_EVENT1_IN: 8 | |
| FLEXIO3_FLEXIO11: 9 | |
| ADC: | |
| - ADC1_IN0 | |
| - ADC2_IN0 | |
| LPUART8_RX_INPUT_SELECT: 1 | |
| GPIO_AD_B1_12: | |
| SW_MUX_CTL: | |
| FLEXSPIA_DATA01: 0 | |
| ACMP_OUT00: 1 | |
| LPSPI3_PCS0: 2 | |
| SAI1_RX_DATA00: 3 | |
| CSI_DATA05: 4 | |
| GPIO1_IO28: 5 | |
| USDHC2_DATA4: 6 | |
| KPP_ROW01: 7 | |
| ENET2_1588_EVENT2_OUT: 8 | |
| FLEXIO3_FLEXIO12: 9 | |
| ADC: | |
| - ADC2_IN1 | |
| GPIO_AD_B1_13: | |
| SW_MUX_CTL: | |
| FLEXSPIA_DATA00: 0 | |
| ACMP_OUT01: 1 | |
| LPSPI3_SDI: 2 | |
| SAI1_TX_DATA00: 3 | |
| CSI_DATA04: 4 | |
| GPIO1_IO29: 5 | |
| USDHC2_DATA5: 6 | |
| KPP_COL01: 7 | |
| ENET2_1588_EVENT2_IN: 8 | |
| FLEXIO3_FLEXIO13: 9 | |
| ADC: | |
| - ADC2_IN2 | |
| GPIO_AD_B1_14: | |
| SW_MUX_CTL: | |
| FLEXSPIA_SCLK: 0 | |
| ACMP_OUT02: 1 | |
| LPSPI3_SDO: 2 | |
| SAI1_TX_BCLK: 3 | |
| CSI_DATA03: 4 | |
| GPIO1_IO30: 5 | |
| USDHC2_DATA6: 6 | |
| KPP_ROW00: 7 | |
| ENET2_1588_EVENT3_OUT: 8 | |
| FLEXIO3_FLEXIO14: 9 | |
| ADC: | |
| - ADC2_IN3 | |
| GPIO_AD_B1_15: | |
| SW_MUX_CTL: | |
| FLEXSPIA_SS0_B: 0 | |
| ACMP_OUT03: 1 | |
| LPSPI3_SCK: 2 | |
| SAI1_TX_SYNC: 3 | |
| CSI_DATA02: 4 | |
| GPIO1_IO31: 5 | |
| USDHC2_DATA7: 6 | |
| KPP_COL00: 7 | |
| ENET2_1588_EVENT3_IN: 8 | |
| FLEXIO3_FLEXIO15: 9 | |
| ADC: | |
| - ADC2_IN4 | |
| GPIO_B0_00: | |
| SW_MUX_CTL: | |
| LCD_CLK: 0 | |
| QTIMER1_TIMER0: 1 | |
| MQS_RIGHT: 2 | |
| LPSPI4_PCS0: 3 | |
| FLEXIO2_FLEXIO00: 4 | |
| GPIO2_IO00: 5 | |
| SEMC_CSX01: 6 | |
| ENET2_MDC: 8 | |
| GPIO_B0_01: | |
| SW_MUX_CTL: | |
| LCD_ENABLE: 0 | |
| QTIMER1_TIMER1: 1 | |
| MQS_LEFT: 2 | |
| LPSPI4_SDI: 3 | |
| FLEXIO2_FLEXIO01: 4 | |
| GPIO2_IO01: 5 | |
| SEMC_CSX02: 6 | |
| ENET2_MDIO: 8 | |
| GPIO_B0_02: | |
| SW_MUX_CTL: | |
| LCD_HSYNC: 0 | |
| QTIMER1_TIMER2: 1 | |
| FLEXCAN1_TX: 2 | |
| LPSPI4_SDO: 3 | |
| FLEXIO2_FLEXIO02: 4 | |
| GPIO2_IO02: 5 | |
| SEMC_CSX03: 6 | |
| ENET2_1588_EVENT0_OUT: 8 | |
| GPIO_B0_03: | |
| SW_MUX_CTL: | |
| LCD_VSYNC: 0 | |
| QTIMER2_TIMER0: 1 | |
| FLEXCAN1_RX: 2 | |
| LPSPI4_SCK: 3 | |
| FLEXIO2_FLEXIO03: 4 | |
| GPIO2_IO03: 5 | |
| WDOG2_RESET_B_DEB: 6 | |
| ENET2_1588_EVENT0_IN: 8 | |
| GPIO_B0_04: | |
| SW_MUX_CTL: | |
| LCD_DATA00: 0 | |
| QTIMER2_TIMER1: 1 | |
| LPI2C2_SCL: 2 | |
| ARM_TRACE0: 3 | |
| FLEXIO2_FLEXIO04: 4 | |
| GPIO2_IO04: 5 | |
| SRC_BOOT_CFG00: 6 | |
| ENET2_TDATA03: 8 | |
| GPIO_B0_05: | |
| SW_MUX_CTL: | |
| LCD_DATA01: 0 | |
| QTIMER2_TIMER2: 1 | |
| LPI2C2_SDA: 2 | |
| ARM_TRACE1: 3 | |
| FLEXIO2_FLEXIO05: 4 | |
| GPIO2_IO05: 5 | |
| SRC_BOOT_CFG01: 6 | |
| ENET2_TDATA02: 8 | |
| GPIO_B0_06: | |
| SW_MUX_CTL: | |
| LCD_DATA02: 0 | |
| QTIMER3_TIMER0: 1 | |
| FLEXPWM2_PWMA00: 2 | |
| ARM_TRACE2: 3 | |
| FLEXIO2_FLEXIO06: 4 | |
| GPIO2_IO06: 5 | |
| SRC_BOOT_CFG02: 6 | |
| ENET2_RX_CLK: 8 | |
| GPIO_B0_07: | |
| SW_MUX_CTL: | |
| LCD_DATA03: 0 | |
| QTIMER3_TIMER1: 1 | |
| FLEXPWM2_PWMB00: 2 | |
| ARM_TRACE3: 3 | |
| FLEXIO2_FLEXIO07: 4 | |
| GPIO2_IO07: 5 | |
| SRC_BOOT_CFG03: 6 | |
| ENET2_TX_ER: 8 | |
| GPIO_B0_08: | |
| SW_MUX_CTL: | |
| LCD_DATA04: 0 | |
| QTIMER3_TIMER2: 1 | |
| FLEXPWM2_PWMA01: 2 | |
| LPUART3_TX: 3 | |
| FLEXIO2_FLEXIO08: 4 | |
| GPIO2_IO08: 5 | |
| SRC_BOOT_CFG04: 6 | |
| ENET2_RDATA03: 8 | |
| LPUART3_TX_INPUT_SELECT: 2 | |
| GPIO_B0_09: | |
| SW_MUX_CTL: | |
| LCD_DATA05: 0 | |
| QTIMER4_TIMER0: 1 | |
| FLEXPWM2_PWMB01: 2 | |
| LPUART3_RX: 3 | |
| FLEXIO2_FLEXIO09: 4 | |
| GPIO2_IO09: 5 | |
| SRC_BOOT_CFG05: 6 | |
| ENET2_RDATA02: 8 | |
| LPUART3_RX_INPUT_SELECT: 2 | |
| GPIO_B0_10: | |
| SW_MUX_CTL: | |
| LCD_DATA06: 0 | |
| QTIMER4_TIMER1: 1 | |
| FLEXPWM2_PWMA02: 2 | |
| SAI1_TX_DATA03: 3 | |
| FLEXIO2_FLEXIO10: 4 | |
| GPIO2_IO10: 5 | |
| SRC_BOOT_CFG06: 6 | |
| ENET2_CRS: 8 | |
| GPIO_B0_11: | |
| SW_MUX_CTL: | |
| LCD_DATA07: 0 | |
| QTIMER4_TIMER2: 1 | |
| FLEXPWM2_PWMB02: 2 | |
| SAI1_TX_DATA02: 3 | |
| FLEXIO2_FLEXIO11: 4 | |
| GPIO2_IO11: 5 | |
| SRC_BOOT_CFG07: 6 | |
| ENET2_COL: 8 | |
| GPIO_B0_12: | |
| SW_MUX_CTL: | |
| LCD_DATA08: 0 | |
| XBAR1_INOUT10: 1 | |
| ARM_TRACE_CLK: 2 | |
| SAI1_TX_DATA01: 3 | |
| FLEXIO2_FLEXIO12: 4 | |
| GPIO2_IO12: 5 | |
| SRC_BOOT_CFG08: 6 | |
| ENET2_TDATA00: 8 | |
| GPIO_B0_13: | |
| SW_MUX_CTL: | |
| LCD_DATA09: 0 | |
| XBAR1_INOUT11: 1 | |
| ARM_TRACE_SWO: 2 | |
| SAI1_MCLK: 3 | |
| FLEXIO2_FLEXIO13: 4 | |
| GPIO2_IO13: 5 | |
| SRC_BOOT_CFG09: 6 | |
| ENET2_TDATA01: 8 | |
| GPIO_B0_14: | |
| SW_MUX_CTL: | |
| LCD_DATA10: 0 | |
| XBAR1_INOUT12: 1 | |
| ARM_TXEV: 2 | |
| SAI1_RX_SYNC: 3 | |
| FLEXIO2_FLEXIO14: 4 | |
| GPIO2_IO14: 5 | |
| SRC_BOOT_CFG10: 6 | |
| ENET2_TX_EN: 8 | |
| GPIO_B0_15: | |
| SW_MUX_CTL: | |
| LCD_DATA11: 0 | |
| XBAR1_INOUT13: 1 | |
| ARM_RXEV: 2 | |
| SAI1_RX_BCLK: 3 | |
| FLEXIO2_FLEXIO15: 4 | |
| GPIO2_IO15: 5 | |
| SRC_BOOT_CFG11: 6 | |
| ENET2_TX_CLK: 8 | |
| ENET2_REF_CLK2: 9 | |
| GPIO_B1_00: | |
| SW_MUX_CTL: | |
| LCD_DATA12: 0 | |
| XBAR1_INOUT14: 1 | |
| LPUART4_TX: 2 | |
| SAI1_RX_DATA00: 3 | |
| FLEXIO2_FLEXIO16: 4 | |
| GPIO2_IO16: 5 | |
| FLEXPWM1_PWMA03: 6 | |
| ENET2_RX_ER: 8 | |
| FLEXIO3_FLEXIO16: 9 | |
| XBAR_INPUT_SELECT: 1 | |
| LPUART4_TX_INPUT_SELECT: 2 | |
| GPIO_B1_01: | |
| SW_MUX_CTL: | |
| LCD_DATA13: 0 | |
| XBAR1_INOUT15: 1 | |
| LPUART4_RX: 2 | |
| SAI1_TX_DATA00: 3 | |
| FLEXIO2_FLEXIO17: 4 | |
| GPIO2_IO17: 5 | |
| FLEXPWM1_PWMB03: 6 | |
| ENET2_RDATA00: 8 | |
| FLEXIO3_FLEXIO17: 9 | |
| XBAR_INPUT_SELECT: 1 | |
| LPUART4_RX_INPUT_SELECT: 2 | |
| GPIO_B1_02: | |
| SW_MUX_CTL: | |
| LCD_DATA14: 0 | |
| XBAR1_INOUT16: 1 | |
| LPSPI4_PCS2: 2 | |
| SAI1_TX_BCLK: 3 | |
| FLEXIO2_FLEXIO18: 4 | |
| GPIO2_IO18: 5 | |
| FLEXPWM2_PWMA03: 6 | |
| ENET2_RDATA01: 8 | |
| FLEXIO3_FLEXIO18: 9 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_B1_03: | |
| SW_MUX_CTL: | |
| LCD_DATA15: 0 | |
| XBAR1_INOUT17: 1 | |
| LPSPI4_PCS1: 2 | |
| SAI1_TX_SYNC: 3 | |
| FLEXIO2_FLEXIO19: 4 | |
| GPIO2_IO19: 5 | |
| FLEXPWM2_PWMB03: 6 | |
| ENET2_RX_EN: 8 | |
| FLEXIO3_FLEXIO19: 9 | |
| XBAR_INPUT_SELECT: 3 | |
| GPIO_B1_04: | |
| SW_MUX_CTL: | |
| LCD_DATA16: 0 | |
| LPSPI4_PCS0: 1 | |
| CSI_DATA15: 2 | |
| ENET_RX_DATA00: 3 | |
| FLEXIO2_FLEXIO20: 4 | |
| GPIO2_IO20: 5 | |
| GPT1_CLK: 8 | |
| FLEXIO3_FLEXIO20: 9 | |
| GPIO_B1_05: | |
| SW_MUX_CTL: | |
| LCD_DATA17: 0 | |
| LPSPI4_SDI: 1 | |
| CSI_DATA14: 2 | |
| ENET_RX_DATA01: 3 | |
| FLEXIO2_FLEXIO21: 4 | |
| GPIO2_IO21: 5 | |
| GPT1_CAPTURE1: 8 | |
| FLEXIO3_FLEXIO21: 9 | |
| GPIO_B1_06: | |
| SW_MUX_CTL: | |
| LCD_DATA18: 0 | |
| LPSPI4_SDO: 1 | |
| CSI_DATA13: 2 | |
| ENET_RX_EN: 3 | |
| FLEXIO2_FLEXIO22: 4 | |
| GPIO2_IO22: 5 | |
| GPT1_CAPTURE2: 8 | |
| FLEXIO3_FLEXIO22: 9 | |
| GPIO_B1_07: | |
| SW_MUX_CTL: | |
| LCD_DATA19: 0 | |
| LPSPI4_SCK: 1 | |
| CSI_DATA12: 2 | |
| ENET_TX_DATA00: 3 | |
| FLEXIO2_FLEXIO23: 4 | |
| GPIO2_IO23: 5 | |
| GPT1_COMPARE1: 8 | |
| FLEXIO3_FLEXIO23: 9 | |
| GPIO_B1_08: | |
| SW_MUX_CTL: | |
| LCD_DATA20: 0 | |
| QTIMER1_TIMER3: 1 | |
| CSI_DATA11: 2 | |
| ENET_TX_DATA01: 3 | |
| FLEXIO2_FLEXIO24: 4 | |
| GPIO2_IO24: 5 | |
| FLEXCAN2_TX: 6 | |
| GPT1_COMPARE2: 8 | |
| FLEXIO3_FLEXIO24: 9 | |
| GPIO_B1_09: | |
| SW_MUX_CTL: | |
| LCD_DATA21: 0 | |
| QTIMER2_TIMER3: 1 | |
| CSI_DATA10: 2 | |
| ENET_TX_EN: 3 | |
| FLEXIO2_FLEXIO25: 4 | |
| GPIO2_IO25: 5 | |
| FLEXCAN2_RX: 6 | |
| GPT1_COMPARE3: 8 | |
| FLEXIO3_FLEXIO25: 9 | |
| GPIO_B1_10: | |
| SW_MUX_CTL: | |
| LCD_DATA22: 0 | |
| QTIMER3_TIMER3: 1 | |
| CSI_DATA00: 2 | |
| ENET_TX_CLK: 3 | |
| FLEXIO2_FLEXIO26: 4 | |
| GPIO2_IO26: 5 | |
| ENET_REF_CLK: 6 | |
| FLEXIO3_FLEXIO26: 9 | |
| GPIO_B1_11: | |
| SW_MUX_CTL: | |
| LCD_DATA23: 0 | |
| QTIMER4_TIMER3: 1 | |
| CSI_DATA01: 2 | |
| ENET_RX_ER: 3 | |
| FLEXIO2_FLEXIO27: 4 | |
| GPIO2_IO27: 5 | |
| LPSPI4_PCS3: 6 | |
| FLEXIO3_FLEXIO27: 9 | |
| GPIO_B1_12: | |
| SW_MUX_CTL: | |
| LPUART5_TX: 1 | |
| CSI_PIXCLK: 2 | |
| ENET_1588_EVENT0_IN: 3 | |
| FLEXIO2_FLEXIO28: 4 | |
| GPIO2_IO28: 5 | |
| USDHC1_CD_B: 6 | |
| FLEXIO3_FLEXIO28: 9 | |
| LPUART5_TX_INPUT_SELECT: 1 | |
| GPIO_B1_13: | |
| SW_MUX_CTL: | |
| WDOG1_B: 0 | |
| LPUART5_RX: 1 | |
| CSI_VSYNC: 2 | |
| ENET_1588_EVENT0_OUT: 3 | |
| FLEXIO2_FLEXIO29: 4 | |
| GPIO2_IO29: 5 | |
| USDHC1_WP: 6 | |
| SEMC_DQS4: 8 | |
| FLEXIO3_FLEXIO29: 9 | |
| LPUART5_RX_INPUT_SELECT: 1 | |
| GPIO_B1_14: | |
| SW_MUX_CTL: | |
| ENET_MDC: 0 | |
| FLEXPWM4_PWMA02: 1 | |
| CSI_HSYNC: 2 | |
| XBAR1_IN02: 3 | |
| FLEXIO2_FLEXIO30: 4 | |
| GPIO2_IO30: 5 | |
| USDHC1_VSELECT: 6 | |
| ENET2_TDATA00: 8 | |
| FLEXIO3_FLEXIO30: 9 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_B1_15: | |
| SW_MUX_CTL: | |
| ENET_MDIO: 0 | |
| FLEXPWM4_PWMA03: 1 | |
| CSI_MCLK: 2 | |
| XBAR1_IN03: 3 | |
| FLEXIO2_FLEXIO31: 4 | |
| GPIO2_IO31: 5 | |
| USDHC1_RESET_B: 6 | |
| ENET2_TDATA01: 8 | |
| FLEXIO3_FLEXIO31: 9 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_SD_B0_00: | |
| SW_MUX_CTL: | |
| USDHC1_CMD: 0 | |
| FLEXPWM1_PWMA00: 1 | |
| LPI2C3_SCL: 2 | |
| XBAR1_INOUT04: 3 | |
| LPSPI1_SCK: 4 | |
| GPIO3_IO12: 5 | |
| FLEXSPIA_SS1_B: 6 | |
| ENET2_TX_EN: 8 | |
| SEMC_DQS4: 9 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_SD_B0_01: | |
| SW_MUX_CTL: | |
| USDHC1_CLK: 0 | |
| FLEXPWM1_PWMB00: 1 | |
| LPI2C3_SDA: 2 | |
| XBAR1_INOUT05: 3 | |
| LPSPI1_PCS0: 4 | |
| GPIO3_IO13: 5 | |
| FLEXSPIB_SS1_B: 6 | |
| ENET2_TX_CLK: 8 | |
| ENET2_REF_CLK2: 9 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_SD_B0_02: | |
| SW_MUX_CTL: | |
| USDHC1_DATA0: 0 | |
| FLEXPWM1_PWMA01: 1 | |
| LPUART8_CTS_B: 2 | |
| XBAR1_INOUT06: 3 | |
| LPSPI1_SDO: 4 | |
| GPIO3_IO14: 5 | |
| ENET2_RX_ER: 8 | |
| SEMC_CLK5: 9 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_SD_B0_03: | |
| SW_MUX_CTL: | |
| USDHC1_DATA1: 0 | |
| FLEXPWM1_PWMB01: 1 | |
| LPUART8_RTS_B: 2 | |
| XBAR1_INOUT07: 3 | |
| LPSPI1_SDI: 4 | |
| GPIO3_IO15: 5 | |
| ENET2_RDATA00: 8 | |
| SEMC_CLK6: 9 | |
| XBAR_INPUT_SELECT: 1 | |
| GPIO_SD_B0_04: | |
| SW_MUX_CTL: | |
| USDHC1_DATA2: 0 | |
| FLEXPWM1_PWMA02: 1 | |
| LPUART8_TX: 2 | |
| XBAR1_INOUT08: 3 | |
| FLEXSPIB_SS0_B: 4 | |
| GPIO3_IO16: 5 | |
| CCM_CLKO1: 6 | |
| ENET2_RDATA01: 8 | |
| XBAR_INPUT_SELECT: 1 | |
| LPUART8_TX_INPUT_SELECT: 0 | |
| GPIO_SD_B0_05: | |
| SW_MUX_CTL: | |
| USDHC1_DATA3: 0 | |
| FLEXPWM1_PWMB02: 1 | |
| LPUART8_RX: 2 | |
| XBAR1_INOUT09: 3 | |
| FLEXSPIB_DQS: 4 | |
| GPIO3_IO17: 5 | |
| CCM_CLKO2: 6 | |
| ENET2_RX_EN: 8 | |
| XBAR_INPUT_SELECT: 1 | |
| LPUART8_RX_INPUT_SELECT: 0 | |
| GPIO_SD_B1_00: | |
| SW_MUX_CTL: | |
| USDHC2_DATA3: 0 | |
| FLEXSPIB_DATA03: 1 | |
| FLEXPWM1_PWMA03: 2 | |
| SAI1_TX_DATA03: 3 | |
| LPUART4_TX: 4 | |
| GPIO3_IO00: 5 | |
| SAI3_RX_DATA: 8 | |
| LPUART4_TX_INPUT_SELECT: 0 | |
| GPIO_SD_B1_01: | |
| SW_MUX_CTL: | |
| USDHC2_DATA2: 0 | |
| FLEXSPIB_DATA02: 1 | |
| FLEXPWM1_PWMB03: 2 | |
| SAI1_TX_DATA02: 3 | |
| LPUART4_RX: 4 | |
| GPIO3_IO01: 5 | |
| SAI3_TX_DATA: 8 | |
| LPUART4_RX_INPUT_SELECT: 0 | |
| GPIO_SD_B1_02: | |
| SW_MUX_CTL: | |
| USDHC2_DATA1: 0 | |
| FLEXSPIB_DATA01: 1 | |
| FLEXPWM2_PWMA03: 2 | |
| SAI1_TX_DATA01: 3 | |
| FLEXCAN1_TX: 4 | |
| GPIO3_IO02: 5 | |
| CCM_WAIT: 6 | |
| SAI3_TX_SYNC: 8 | |
| GPIO_SD_B1_03: | |
| SW_MUX_CTL: | |
| USDHC2_DATA0: 0 | |
| FLEXSPIB_DATA00: 1 | |
| FLEXPWM2_PWMB03: 2 | |
| SAI1_MCLK: 3 | |
| FLEXCAN1_RX: 4 | |
| GPIO3_IO03: 5 | |
| CCM_PMIC_READY: 6 | |
| SAI3_TX_BCLK: 8 | |
| GPIO_SD_B1_04: | |
| SW_MUX_CTL: | |
| USDHC2_CLK: 0 | |
| FLEXSPIB_SCLK: 1 | |
| LPI2C1_SCL: 2 | |
| SAI1_RX_SYNC: 3 | |
| FLEXSPIA_SS1_B: 4 | |
| GPIO3_IO04: 5 | |
| CCM_STOP: 6 | |
| SAI3_MCLK: 8 | |
| GPIO_SD_B1_05: | |
| SW_MUX_CTL: | |
| USDHC2_CMD: 0 | |
| FLEXSPIA_DQS: 1 | |
| LPI2C1_SDA: 2 | |
| SAI1_RX_BCLK: 3 | |
| FLEXSPIB_SS0_B: 4 | |
| GPIO3_IO05: 5 | |
| SAI3_RX_SYNC: 8 | |
| GPIO_SD_B1_06: | |
| SW_MUX_CTL: | |
| USDHC2_RESET_B: 0 | |
| FLEXSPIA_SS0_B: 1 | |
| LPUART7_CTS_B: 2 | |
| SAI1_RX_DATA00: 3 | |
| LPSPI2_PCS0: 4 | |
| GPIO3_IO06: 5 | |
| SAI3_RX_BCLK: 8 | |
| GPIO_SD_B1_07: | |
| SW_MUX_CTL: | |
| SEMC_CSX01: 0 | |
| FLEXSPIA_SCLK: 1 | |
| LPUART7_RTS_B: 2 | |
| SAI1_TX_DATA00: 3 | |
| LPSPI2_SCK: 4 | |
| GPIO3_IO07: 5 | |
| GPIO_SD_B1_08: | |
| SW_MUX_CTL: | |
| USDHC2_DATA4: 0 | |
| FLEXSPIA_DATA00: 1 | |
| LPUART7_TX: 2 | |
| SAI1_TX_BCLK: 3 | |
| LPSPI2_SD0: 4 | |
| GPIO3_IO08: 5 | |
| SEMC_CSX02: 6 | |
| LPUART7_TX_INPUT_SELECT: 0 | |
| GPIO_SD_B1_09: | |
| SW_MUX_CTL: | |
| USDHC2_DATA5: 0 | |
| FLEXSPIA_DATA01: 1 | |
| LPUART7_RX: 2 | |
| SAI1_TX_SYNC: 3 | |
| LPSPI2_SDI: 4 | |
| GPIO3_IO09: 5 | |
| LPUART7_RX_INPUT_SELECT: 0 | |
| GPIO_SD_B1_10: | |
| SW_MUX_CTL: | |
| USDHC2_DATA6: 0 | |
| FLEXSPIA_DATA02: 1 | |
| LPUART2_RX: 2 | |
| LPI2C2_SDA: 3 | |
| LPSPI2_PCS2: 4 | |
| GPIO3_IO10: 5 | |
| LPUART2_RX_INPUT_SELECT: 0 | |
| GPIO_SD_B1_11: | |
| SW_MUX_CTL: | |
| USDHC2_DATA7: 0 | |
| FLEXSPIA_DATA03: 1 | |
| LPUART2_TX: 2 | |
| LPI2C2_SCL: 3 | |
| LPSPI2_PCS3: 4 | |
| GPIO3_IO11: 5 | |
| LPUART2_TX_INPUT_SELECT: 0 | |
| ... |
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| #pragma once | |
| #include "imxrt.h" | |
| #include "pins_arduino.h" | |
| #define FLASH_BASEADDR 0x60FC0000 | |
| #define FLASH_SIZE 0x01000000 | |
| #define FLASH_SECTORS 63 | |
| #define FLASH_EEPROM_ENDADDR 0x10BB | |
| #define CORE_NUM_TOTAL_PINS 54 | |
| #define CORE_NUM_DIGITAL 54 | |
| #define CORE_NUM_INTERRUPT 54 | |
| #define CORE_NUM_ANALOG 20 | |
| #define CORE_NUM_PWM 31 | |
| #define CORE_PIN0_BIT 14 | |
| #define CORE_PIN1_BIT 15 | |
| #define CORE_PIN2_BIT 12 | |
| #define CORE_PIN3_BIT 13 | |
| #define CORE_PIN4_BIT 27 | |
| #define CORE_PIN5_BIT 19 | |
| #define CORE_PIN6_BIT 16 | |
| #define CORE_PIN7_BIT 18 | |
| #define CORE_PIN8_BIT 20 | |
| #define CORE_PIN9_BIT 17 | |
| #define CORE_PIN10_BIT 24 | |
| #define CORE_PIN11_BIT 26 | |
| #define CORE_PIN12_BIT 25 | |
| #define CORE_PIN13_BIT 21 | |
| #define CORE_PIN14_BIT 28 | |
| #define CORE_PIN15_BIT 29 | |
| #define CORE_PIN16_BIT 30 | |
| #define CORE_PIN17_BIT 2 | |
| #define CORE_PIN18_BIT 3 | |
| #define CORE_PIN19_BIT 22 | |
| #define CORE_PIN20_BIT 23 | |
| #define CORE_PIN21_BIT 31 | |
| #define CORE_PIN22_BIT 31 | |
| #define CORE_PIN23_BIT 30 | |
| #define CORE_PIN24_BIT 29 | |
| #define CORE_PIN25_BIT 28 | |
| #define CORE_PIN26_BIT 27 | |
| #define CORE_PIN27_BIT 26 | |
| #define CORE_PIN28_BIT 25 | |
| #define CORE_PIN29_BIT 24 | |
| #define CORE_PIN30_BIT 23 | |
| #define CORE_PIN31_BIT 22 | |
| #define CORE_PIN32_BIT 21 | |
| #define CORE_PIN33_BIT 20 | |
| #define CORE_PIN34_BIT 19 | |
| #define CORE_PIN35_BIT 18 | |
| #define CORE_PIN36_BIT 17 | |
| #define CORE_PIN37_BIT 16 | |
| #define CORE_PIN38_BIT 15 | |
| #define CORE_PIN39_BIT 14 | |
| #define CORE_PIN40_BIT 13 | |
| #define CORE_PIN41_BIT 12 | |
| #define CORE_PIN42_BIT 11 | |
| #define CORE_PIN43_BIT 10 | |
| #define CORE_PIN44_BIT 9 | |
| #define CORE_PIN45_BIT 8 | |
| #define CORE_PIN46_BIT 7 | |
| #define CORE_PIN47_BIT 6 | |
| #define CORE_PIN48_BIT 5 | |
| #define CORE_PIN49_BIT 4 | |
| #define CORE_PIN50_BIT 3 | |
| #define CORE_PIN51_BIT 2 | |
| #define CORE_PIN52_BIT 1 | |
| #define CORE_PIN53_BIT 0 | |
| #define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT)) | |
| #define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT)) | |
| #define CORE_PIN2_BITMASK (1<<(CORE_PIN2_BIT)) | |
| #define CORE_PIN3_BITMASK (1<<(CORE_PIN3_BIT)) | |
| #define CORE_PIN4_BITMASK (1<<(CORE_PIN4_BIT)) | |
| #define CORE_PIN5_BITMASK (1<<(CORE_PIN5_BIT)) | |
| #define CORE_PIN6_BITMASK (1<<(CORE_PIN6_BIT)) | |
| #define CORE_PIN7_BITMASK (1<<(CORE_PIN7_BIT)) | |
| #define CORE_PIN8_BITMASK (1<<(CORE_PIN8_BIT)) | |
| #define CORE_PIN9_BITMASK (1<<(CORE_PIN9_BIT)) | |
| #define CORE_PIN10_BITMASK (1<<(CORE_PIN10_BIT)) | |
| #define CORE_PIN11_BITMASK (1<<(CORE_PIN11_BIT)) | |
| #define CORE_PIN12_BITMASK (1<<(CORE_PIN12_BIT)) | |
| #define CORE_PIN13_BITMASK (1<<(CORE_PIN13_BIT)) | |
| #define CORE_PIN14_BITMASK (1<<(CORE_PIN14_BIT)) | |
| #define CORE_PIN15_BITMASK (1<<(CORE_PIN15_BIT)) | |
| #define CORE_PIN16_BITMASK (1<<(CORE_PIN16_BIT)) | |
| #define CORE_PIN17_BITMASK (1<<(CORE_PIN17_BIT)) | |
| #define CORE_PIN18_BITMASK (1<<(CORE_PIN18_BIT)) | |
| #define CORE_PIN19_BITMASK (1<<(CORE_PIN19_BIT)) | |
| #define CORE_PIN20_BITMASK (1<<(CORE_PIN20_BIT)) | |
| #define CORE_PIN21_BITMASK (1<<(CORE_PIN21_BIT)) | |
| #define CORE_PIN22_BITMASK (1<<(CORE_PIN22_BIT)) | |
| #define CORE_PIN23_BITMASK (1<<(CORE_PIN23_BIT)) | |
| #define CORE_PIN24_BITMASK (1<<(CORE_PIN24_BIT)) | |
| #define CORE_PIN25_BITMASK (1<<(CORE_PIN25_BIT)) | |
| #define CORE_PIN26_BITMASK (1<<(CORE_PIN26_BIT)) | |
| #define CORE_PIN27_BITMASK (1<<(CORE_PIN27_BIT)) | |
| #define CORE_PIN28_BITMASK (1<<(CORE_PIN28_BIT)) | |
| #define CORE_PIN29_BITMASK (1<<(CORE_PIN29_BIT)) | |
| #define CORE_PIN30_BITMASK (1<<(CORE_PIN30_BIT)) | |
| #define CORE_PIN31_BITMASK (1<<(CORE_PIN31_BIT)) | |
| #define CORE_PIN32_BITMASK (1<<(CORE_PIN32_BIT)) | |
| #define CORE_PIN33_BITMASK (1<<(CORE_PIN33_BIT)) | |
| #define CORE_PIN34_BITMASK (1<<(CORE_PIN34_BIT)) | |
| #define CORE_PIN35_BITMASK (1<<(CORE_PIN35_BIT)) | |
| #define CORE_PIN36_BITMASK (1<<(CORE_PIN36_BIT)) | |
| #define CORE_PIN37_BITMASK (1<<(CORE_PIN37_BIT)) | |
| #define CORE_PIN38_BITMASK (1<<(CORE_PIN38_BIT)) | |
| #define CORE_PIN39_BITMASK (1<<(CORE_PIN39_BIT)) | |
| #define CORE_PIN40_BITMASK (1<<(CORE_PIN40_BIT)) | |
| #define CORE_PIN41_BITMASK (1<<(CORE_PIN41_BIT)) | |
| #define CORE_PIN42_BITMASK (1<<(CORE_PIN42_BIT)) | |
| #define CORE_PIN43_BITMASK (1<<(CORE_PIN43_BIT)) | |
| #define CORE_PIN44_BITMASK (1<<(CORE_PIN44_BIT)) | |
| #define CORE_PIN45_BITMASK (1<<(CORE_PIN45_BIT)) | |
| #define CORE_PIN46_BITMASK (1<<(CORE_PIN46_BIT)) | |
| #define CORE_PIN47_BITMASK (1<<(CORE_PIN47_BIT)) | |
| #define CORE_PIN48_BITMASK (1<<(CORE_PIN48_BIT)) | |
| #define CORE_PIN49_BITMASK (1<<(CORE_PIN49_BIT)) | |
| #define CORE_PIN50_BITMASK (1<<(CORE_PIN50_BIT)) | |
| #define CORE_PIN51_BITMASK (1<<(CORE_PIN51_BIT)) | |
| #define CORE_PIN52_BITMASK (1<<(CORE_PIN52_BIT)) | |
| #define CORE_PIN53_BITMASK (1<<(CORE_PIN53_BIT)) | |
| #define CORE_PIN0_PORTREG GPIO6_DR | |
| #define CORE_PIN1_PORTREG GPIO6_DR | |
| #define CORE_PIN2_PORTREG GPIO6_DR | |
| #define CORE_PIN3_PORTREG GPIO6_DR | |
| #define CORE_PIN4_PORTREG GPIO6_DR | |
| #define CORE_PIN5_PORTREG GPIO6_DR | |
| #define CORE_PIN6_PORTREG GPIO6_DR | |
| #define CORE_PIN7_PORTREG GPIO6_DR | |
| #define CORE_PIN8_PORTREG GPIO6_DR | |
| #define CORE_PIN9_PORTREG GPIO6_DR | |
| #define CORE_PIN10_PORTREG GPIO6_DR | |
| #define CORE_PIN11_PORTREG GPIO6_DR | |
| #define CORE_PIN12_PORTREG GPIO6_DR | |
| #define CORE_PIN13_PORTREG GPIO6_DR | |
| #define CORE_PIN14_PORTREG GPIO6_DR | |
| #define CORE_PIN15_PORTREG GPIO6_DR | |
| #define CORE_PIN16_PORTREG GPIO6_DR | |
| #define CORE_PIN17_PORTREG GPIO6_DR | |
| #define CORE_PIN18_PORTREG GPIO6_DR | |
| #define CORE_PIN19_PORTREG GPIO6_DR | |
| #define CORE_PIN20_PORTREG GPIO6_DR | |
| #define CORE_PIN21_PORTREG GPIO6_DR | |
| #define CORE_PIN22_PORTREG GPIO7_DR | |
| #define CORE_PIN23_PORTREG GPIO7_DR | |
| #define CORE_PIN24_PORTREG GPIO7_DR | |
| #define CORE_PIN25_PORTREG GPIO7_DR | |
| #define CORE_PIN26_PORTREG GPIO7_DR | |
| #define CORE_PIN27_PORTREG GPIO7_DR | |
| #define CORE_PIN28_PORTREG GPIO7_DR | |
| #define CORE_PIN29_PORTREG GPIO7_DR | |
| #define CORE_PIN30_PORTREG GPIO7_DR | |
| #define CORE_PIN31_PORTREG GPIO7_DR | |
| #define CORE_PIN32_PORTREG GPIO7_DR | |
| #define CORE_PIN33_PORTREG GPIO7_DR | |
| #define CORE_PIN34_PORTREG GPIO7_DR | |
| #define CORE_PIN35_PORTREG GPIO7_DR | |
| #define CORE_PIN36_PORTREG GPIO7_DR | |
| #define CORE_PIN37_PORTREG GPIO7_DR | |
| #define CORE_PIN38_PORTREG GPIO7_DR | |
| #define CORE_PIN39_PORTREG GPIO7_DR | |
| #define CORE_PIN40_PORTREG GPIO7_DR | |
| #define CORE_PIN41_PORTREG GPIO7_DR | |
| #define CORE_PIN42_PORTREG GPIO7_DR | |
| #define CORE_PIN43_PORTREG GPIO7_DR | |
| #define CORE_PIN44_PORTREG GPIO7_DR | |
| #define CORE_PIN45_PORTREG GPIO7_DR | |
| #define CORE_PIN46_PORTREG GPIO7_DR | |
| #define CORE_PIN47_PORTREG GPIO7_DR | |
| #define CORE_PIN48_PORTREG GPIO7_DR | |
| #define CORE_PIN49_PORTREG GPIO7_DR | |
| #define CORE_PIN50_PORTREG GPIO7_DR | |
| #define CORE_PIN51_PORTREG GPIO7_DR | |
| #define CORE_PIN52_PORTREG GPIO7_DR | |
| #define CORE_PIN53_PORTREG GPIO7_DR | |
| #define CORE_PIN0_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN1_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN2_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN3_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN4_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN5_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN6_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN7_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN8_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN9_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN10_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN11_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN12_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN13_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN14_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN15_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN16_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN17_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN18_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN19_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN20_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN21_PORTSET GPIO6_DR_SET | |
| #define CORE_PIN22_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN23_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN24_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN25_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN26_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN27_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN28_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN29_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN30_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN31_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN32_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN33_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN34_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN35_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN36_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN37_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN38_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN39_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN40_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN41_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN42_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN43_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN44_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN45_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN46_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN47_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN48_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN49_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN50_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN51_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN52_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN53_PORTSET GPIO7_DR_SET | |
| #define CORE_PIN0_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN1_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN2_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN3_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN4_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN5_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN6_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN7_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN8_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN9_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN10_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN11_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN12_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN13_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN14_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN15_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN16_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN17_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN18_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN19_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN20_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN21_PORTCLEAR GPIO6_DR_CLEAR | |
| #define CORE_PIN22_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN23_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN24_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN25_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN26_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN27_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN28_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN29_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN30_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN31_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN32_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN33_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN34_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN35_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN36_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN37_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN38_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN39_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN40_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN41_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN42_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN43_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN44_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN45_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN46_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN47_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN48_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN49_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN50_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN51_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN52_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN53_PORTCLEAR GPIO7_DR_CLEAR | |
| #define CORE_PIN0_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN1_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN2_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN3_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN4_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN5_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN6_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN7_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN8_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN9_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN10_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN11_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN12_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN13_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN14_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN15_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN16_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN17_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN18_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN19_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN20_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN21_PORTTOGGLE GPIO6_DR_TOGGLE | |
| #define CORE_PIN22_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN23_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN24_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN25_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN26_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN27_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN28_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN29_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN30_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN31_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN32_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN33_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN34_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN35_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN36_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN37_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN38_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN39_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN40_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN41_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN42_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN43_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN44_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN45_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN46_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN47_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN48_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN49_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN50_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN51_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN52_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN53_PORTTOGGLE GPIO7_DR_TOGGLE | |
| #define CORE_PIN0_DDRREG GPIO6_GDIR | |
| #define CORE_PIN1_DDRREG GPIO6_GDIR | |
| #define CORE_PIN2_DDRREG GPIO6_GDIR | |
| #define CORE_PIN3_DDRREG GPIO6_GDIR | |
| #define CORE_PIN4_DDRREG GPIO6_GDIR | |
| #define CORE_PIN5_DDRREG GPIO6_GDIR | |
| #define CORE_PIN6_DDRREG GPIO6_GDIR | |
| #define CORE_PIN7_DDRREG GPIO6_GDIR | |
| #define CORE_PIN8_DDRREG GPIO6_GDIR | |
| #define CORE_PIN9_DDRREG GPIO6_GDIR | |
| #define CORE_PIN10_DDRREG GPIO6_GDIR | |
| #define CORE_PIN11_DDRREG GPIO6_GDIR | |
| #define CORE_PIN12_DDRREG GPIO6_GDIR | |
| #define CORE_PIN13_DDRREG GPIO6_GDIR | |
| #define CORE_PIN14_DDRREG GPIO6_GDIR | |
| #define CORE_PIN15_DDRREG GPIO6_GDIR | |
| #define CORE_PIN16_DDRREG GPIO6_GDIR | |
| #define CORE_PIN17_DDRREG GPIO6_GDIR | |
| #define CORE_PIN18_DDRREG GPIO6_GDIR | |
| #define CORE_PIN19_DDRREG GPIO6_GDIR | |
| #define CORE_PIN20_DDRREG GPIO6_GDIR | |
| #define CORE_PIN21_DDRREG GPIO6_GDIR | |
| #define CORE_PIN22_DDRREG GPIO7_GDIR | |
| #define CORE_PIN23_DDRREG GPIO7_GDIR | |
| #define CORE_PIN24_DDRREG GPIO7_GDIR | |
| #define CORE_PIN25_DDRREG GPIO7_GDIR | |
| #define CORE_PIN26_DDRREG GPIO7_GDIR | |
| #define CORE_PIN27_DDRREG GPIO7_GDIR | |
| #define CORE_PIN28_DDRREG GPIO7_GDIR | |
| #define CORE_PIN29_DDRREG GPIO7_GDIR | |
| #define CORE_PIN30_DDRREG GPIO7_GDIR | |
| #define CORE_PIN31_DDRREG GPIO7_GDIR | |
| #define CORE_PIN32_DDRREG GPIO7_GDIR | |
| #define CORE_PIN33_DDRREG GPIO7_GDIR | |
| #define CORE_PIN34_DDRREG GPIO7_GDIR | |
| #define CORE_PIN35_DDRREG GPIO7_GDIR | |
| #define CORE_PIN36_DDRREG GPIO7_GDIR | |
| #define CORE_PIN37_DDRREG GPIO7_GDIR | |
| #define CORE_PIN38_DDRREG GPIO7_GDIR | |
| #define CORE_PIN39_DDRREG GPIO7_GDIR | |
| #define CORE_PIN40_DDRREG GPIO7_GDIR | |
| #define CORE_PIN41_DDRREG GPIO7_GDIR | |
| #define CORE_PIN42_DDRREG GPIO7_GDIR | |
| #define CORE_PIN43_DDRREG GPIO7_GDIR | |
| #define CORE_PIN44_DDRREG GPIO7_GDIR | |
| #define CORE_PIN45_DDRREG GPIO7_GDIR | |
| #define CORE_PIN46_DDRREG GPIO7_GDIR | |
| #define CORE_PIN47_DDRREG GPIO7_GDIR | |
| #define CORE_PIN48_DDRREG GPIO7_GDIR | |
| #define CORE_PIN49_DDRREG GPIO7_GDIR | |
| #define CORE_PIN50_DDRREG GPIO7_GDIR | |
| #define CORE_PIN51_DDRREG GPIO7_GDIR | |
| #define CORE_PIN52_DDRREG GPIO7_GDIR | |
| #define CORE_PIN53_DDRREG GPIO7_GDIR | |
| #define CORE_PIN0_PINREG GPIO6_PSR | |
| #define CORE_PIN1_PINREG GPIO6_PSR | |
| #define CORE_PIN2_PINREG GPIO6_PSR | |
| #define CORE_PIN3_PINREG GPIO6_PSR | |
| #define CORE_PIN4_PINREG GPIO6_PSR | |
| #define CORE_PIN5_PINREG GPIO6_PSR | |
| #define CORE_PIN6_PINREG GPIO6_PSR | |
| #define CORE_PIN7_PINREG GPIO6_PSR | |
| #define CORE_PIN8_PINREG GPIO6_PSR | |
| #define CORE_PIN9_PINREG GPIO6_PSR | |
| #define CORE_PIN10_PINREG GPIO6_PSR | |
| #define CORE_PIN11_PINREG GPIO6_PSR | |
| #define CORE_PIN12_PINREG GPIO6_PSR | |
| #define CORE_PIN13_PINREG GPIO6_PSR | |
| #define CORE_PIN14_PINREG GPIO6_PSR | |
| #define CORE_PIN15_PINREG GPIO6_PSR | |
| #define CORE_PIN16_PINREG GPIO6_PSR | |
| #define CORE_PIN17_PINREG GPIO6_PSR | |
| #define CORE_PIN18_PINREG GPIO6_PSR | |
| #define CORE_PIN19_PINREG GPIO6_PSR | |
| #define CORE_PIN20_PINREG GPIO6_PSR | |
| #define CORE_PIN21_PINREG GPIO6_PSR | |
| #define CORE_PIN22_PINREG GPIO7_PSR | |
| #define CORE_PIN23_PINREG GPIO7_PSR | |
| #define CORE_PIN24_PINREG GPIO7_PSR | |
| #define CORE_PIN25_PINREG GPIO7_PSR | |
| #define CORE_PIN26_PINREG GPIO7_PSR | |
| #define CORE_PIN27_PINREG GPIO7_PSR | |
| #define CORE_PIN28_PINREG GPIO7_PSR | |
| #define CORE_PIN29_PINREG GPIO7_PSR | |
| #define CORE_PIN30_PINREG GPIO7_PSR | |
| #define CORE_PIN31_PINREG GPIO7_PSR | |
| #define CORE_PIN32_PINREG GPIO7_PSR | |
| #define CORE_PIN33_PINREG GPIO7_PSR | |
| #define CORE_PIN34_PINREG GPIO7_PSR | |
| #define CORE_PIN35_PINREG GPIO7_PSR | |
| #define CORE_PIN36_PINREG GPIO7_PSR | |
| #define CORE_PIN37_PINREG GPIO7_PSR | |
| #define CORE_PIN38_PINREG GPIO7_PSR | |
| #define CORE_PIN39_PINREG GPIO7_PSR | |
| #define CORE_PIN40_PINREG GPIO7_PSR | |
| #define CORE_PIN41_PINREG GPIO7_PSR | |
| #define CORE_PIN42_PINREG GPIO7_PSR | |
| #define CORE_PIN43_PINREG GPIO7_PSR | |
| #define CORE_PIN44_PINREG GPIO7_PSR | |
| #define CORE_PIN45_PINREG GPIO7_PSR | |
| #define CORE_PIN46_PINREG GPIO7_PSR | |
| #define CORE_PIN47_PINREG GPIO7_PSR | |
| #define CORE_PIN48_PINREG GPIO7_PSR | |
| #define CORE_PIN49_PINREG GPIO7_PSR | |
| #define CORE_PIN50_PINREG GPIO7_PSR | |
| #define CORE_PIN51_PINREG GPIO7_PSR | |
| #define CORE_PIN52_PINREG GPIO7_PSR | |
| #define CORE_PIN53_PINREG GPIO7_PSR | |
| // mux config registers control which peripheral uses the pin | |
| #define CORE_PIN0_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 | |
| #define CORE_PIN1_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 | |
| #define CORE_PIN2_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 | |
| #define CORE_PIN3_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 | |
| #define CORE_PIN4_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 | |
| #define CORE_PIN5_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 | |
| #define CORE_PIN6_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 | |
| #define CORE_PIN7_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 | |
| #define CORE_PIN8_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 | |
| #define CORE_PIN9_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 | |
| #define CORE_PIN10_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 | |
| #define CORE_PIN11_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 | |
| #define CORE_PIN12_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 | |
| #define CORE_PIN13_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 | |
| #define CORE_PIN14_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 | |
| #define CORE_PIN15_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 | |
| #define CORE_PIN16_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 | |
| #define CORE_PIN17_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 | |
| #define CORE_PIN18_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 | |
| #define CORE_PIN19_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 | |
| #define CORE_PIN20_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 | |
| #define CORE_PIN21_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 | |
| #define CORE_PIN22_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 | |
| #define CORE_PIN23_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 | |
| #define CORE_PIN24_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 | |
| #define CORE_PIN25_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 | |
| #define CORE_PIN26_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 | |
| #define CORE_PIN27_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 | |
| #define CORE_PIN28_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 | |
| #define CORE_PIN29_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 | |
| #define CORE_PIN30_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 | |
| #define CORE_PIN31_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 | |
| #define CORE_PIN32_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 | |
| #define CORE_PIN33_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 | |
| #define CORE_PIN34_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 | |
| #define CORE_PIN35_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 | |
| #define CORE_PIN36_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 | |
| #define CORE_PIN37_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 | |
| #define CORE_PIN38_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 | |
| #define CORE_PIN39_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 | |
| #define CORE_PIN40_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 | |
| #define CORE_PIN41_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 | |
| #define CORE_PIN42_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 | |
| #define CORE_PIN43_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 | |
| #define CORE_PIN44_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 | |
| #define CORE_PIN45_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 | |
| #define CORE_PIN46_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 | |
| #define CORE_PIN47_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 | |
| #define CORE_PIN48_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 | |
| #define CORE_PIN49_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 | |
| #define CORE_PIN50_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 | |
| #define CORE_PIN51_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 | |
| #define CORE_PIN52_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 | |
| #define CORE_PIN53_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 | |
| // pad config registers control pullup/pulldown/keeper, drive strength, etc | |
| #define CORE_PIN0_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 | |
| #define CORE_PIN1_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 | |
| #define CORE_PIN2_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 | |
| #define CORE_PIN3_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 | |
| #define CORE_PIN4_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 | |
| #define CORE_PIN5_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 | |
| #define CORE_PIN6_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 | |
| #define CORE_PIN7_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 | |
| #define CORE_PIN8_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 | |
| #define CORE_PIN9_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 | |
| #define CORE_PIN10_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 | |
| #define CORE_PIN11_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 | |
| #define CORE_PIN12_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 | |
| #define CORE_PIN13_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 | |
| #define CORE_PIN14_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 | |
| #define CORE_PIN15_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 | |
| #define CORE_PIN16_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 | |
| #define CORE_PIN17_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 | |
| #define CORE_PIN18_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 | |
| #define CORE_PIN19_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 | |
| #define CORE_PIN20_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 | |
| #define CORE_PIN21_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 | |
| #define CORE_PIN22_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 | |
| #define CORE_PIN23_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 | |
| #define CORE_PIN24_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 | |
| #define CORE_PIN25_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 | |
| #define CORE_PIN26_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 | |
| #define CORE_PIN27_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 | |
| #define CORE_PIN28_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 | |
| #define CORE_PIN29_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 | |
| #define CORE_PIN30_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 | |
| #define CORE_PIN31_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 | |
| #define CORE_PIN32_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 | |
| #define CORE_PIN33_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 | |
| #define CORE_PIN34_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 | |
| #define CORE_PIN35_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 | |
| #define CORE_PIN36_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 | |
| #define CORE_PIN37_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 | |
| #define CORE_PIN38_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 | |
| #define CORE_PIN39_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 | |
| #define CORE_PIN40_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 | |
| #define CORE_PIN41_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 | |
| #define CORE_PIN42_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 | |
| #define CORE_PIN43_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 | |
| #define CORE_PIN44_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 | |
| #define CORE_PIN45_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 | |
| #define CORE_PIN46_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 | |
| #define CORE_PIN47_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 | |
| #define CORE_PIN48_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 | |
| #define CORE_PIN49_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 | |
| #define CORE_PIN50_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 | |
| #define CORE_PIN51_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 | |
| #define CORE_PIN52_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 | |
| #define CORE_PIN53_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 | |
| #define CORE_LED0_PIN 13 | |
| #define CORE_ADC0_PIN 0 | |
| #define CORE_ADC1_PIN 1 | |
| #define CORE_ADC2_PIN 2 | |
| #define CORE_ADC3_PIN 3 | |
| #define CORE_ADC4_PIN 4 | |
| #define CORE_ADC5_PIN 5 | |
| #define CORE_ADC6_PIN 6 | |
| #define CORE_ADC7_PIN 7 | |
| #define CORE_ADC8_PIN 8 | |
| #define CORE_ADC9_PIN 9 | |
| #define CORE_ADC10_PIN 10 | |
| #define CORE_ADC11_PIN 11 | |
| #define CORE_ADC12_PIN 12 | |
| #define CORE_ADC13_PIN 13 | |
| #define CORE_ADC14_PIN 14 | |
| #define CORE_ADC15_PIN 15 | |
| #define CORE_ADC16_PIN 16 | |
| #define CORE_ADC17_PIN 19 | |
| #define CORE_ADC18_PIN 20 | |
| #define CORE_ADC19_PIN 21 | |
| #define CORE_INT0_PIN 0 | |
| #define CORE_INT1_PIN 1 | |
| #define CORE_INT2_PIN 2 | |
| #define CORE_INT3_PIN 3 | |
| #define CORE_INT4_PIN 4 | |
| #define CORE_INT5_PIN 5 | |
| #define CORE_INT6_PIN 6 | |
| #define CORE_INT7_PIN 7 | |
| #define CORE_INT8_PIN 8 | |
| #define CORE_INT9_PIN 9 | |
| #define CORE_INT10_PIN 10 | |
| #define CORE_INT11_PIN 11 | |
| #define CORE_INT12_PIN 12 | |
| #define CORE_INT13_PIN 13 | |
| #define CORE_INT14_PIN 14 | |
| #define CORE_INT15_PIN 15 | |
| #define CORE_INT16_PIN 16 | |
| #define CORE_INT17_PIN 17 | |
| #define CORE_INT18_PIN 18 | |
| #define CORE_INT19_PIN 19 | |
| #define CORE_INT20_PIN 20 | |
| #define CORE_INT21_PIN 21 | |
| #define CORE_INT22_PIN 22 | |
| #define CORE_INT23_PIN 23 | |
| #define CORE_INT24_PIN 24 | |
| #define CORE_INT25_PIN 25 | |
| #define CORE_INT26_PIN 26 | |
| #define CORE_INT27_PIN 27 | |
| #define CORE_INT28_PIN 28 | |
| #define CORE_INT29_PIN 29 | |
| #define CORE_INT30_PIN 30 | |
| #define CORE_INT31_PIN 31 | |
| #define CORE_INT32_PIN 32 | |
| #define CORE_INT33_PIN 33 | |
| #define CORE_INT34_PIN 34 | |
| #define CORE_INT35_PIN 35 | |
| #define CORE_INT36_PIN 36 | |
| #define CORE_INT37_PIN 37 | |
| #define CORE_INT38_PIN 38 | |
| #define CORE_INT39_PIN 39 | |
| #define CORE_INT40_PIN 40 | |
| #define CORE_INT41_PIN 41 | |
| #define CORE_INT42_PIN 42 | |
| #define CORE_INT43_PIN 43 | |
| #define CORE_INT44_PIN 44 | |
| #define CORE_INT45_PIN 45 | |
| #define CORE_INT46_PIN 46 | |
| #define CORE_INT47_PIN 47 | |
| #define CORE_INT48_PIN 48 | |
| #define CORE_INT49_PIN 49 | |
| #define CORE_INT50_PIN 50 | |
| #define CORE_INT51_PIN 51 | |
| #define CORE_INT52_PIN 52 | |
| #define CORE_INT53_PIN 53 | |
| #define CORE_INT_EVERY_PIN 1 | |
| #define CORE_NUM_SERIAL_INSTANCES 7 | |
| #define SERIAL1_UART_ADDR IMXRT_LPUART1_ADDRESS | |
| #define SERIAL1_IRQ IRQ_LPUART1 | |
| #define SERIAL1_CCM_REGISTER CCM_CCGR5 | |
| #define SERIAL1_CCM_VALUE CCM_CCGR5_LPUART1(CCM_CCGR_ON) | |
| #define SERIAL1_RX_PIN 3 | |
| #define SERIAL1_RX_MUX_VAL 2 | |
| #define SERIAL1_RX_INPUT_REGISTER nullptr | |
| #define SERIAL1_RX_INPUT_VALUE 0 | |
| #define SERIAL1_RX_ALT_PIN 0xff | |
| #define SERIAL1_RX_ALT_MUX_VAL 0xff | |
| #define SERIAL1_RX_ALT_INPUT_REGISTER nullptr | |
| #define SERIAL1_RX_ALT_INPUT_VALUE 0 | |
| #define SERIAL1_TX_PIN 2 | |
| #define SERIAL1_TX_MUX_VAL 2 | |
| #define SERIAL1_TX_INPUT_REGISTER nullptr | |
| #define SERIAL1_TX_INPUT_VALUE 0 | |
| #define SERIAL1_TX_ALT_PIN 0xff | |
| #define SERIAL1_TX_ALT_MUX_VAL 0xff | |
| #define SERIAL1_TX_ALT_INPUT_REGISTER nullptr | |
| #define SERIAL1_TX_ALT_INPUT_VALUE 0 | |
| #define SERIAL1_CTS_PIN 0 | |
| #define SERIAL1_CTS_MUX_VAL 2 | |
| #define SERIAL1_RTS_LOW_WATERMARK 38 | |
| #define SERIAL1_RTS_HIGH_WATERMARK 24 | |
| #define SERIAL1_XBAR_TRIGGER XBARA1_OUT_LPUART1_TRG_INPUT | |
| #define SERIAL2_UART_ADDR IMXRT_LPUART8_ADDRESS | |
| #define SERIAL2_IRQ IRQ_LPUART8 | |
| #define SERIAL2_CCM_REGISTER CCM_CCGR6 | |
| #define SERIAL2_CCM_VALUE CCM_CCGR6_LPUART8(CCM_CCGR_ON) | |
| #define SERIAL2_RX_PIN 4 | |
| #define SERIAL2_RX_MUX_VAL 2 | |
| #define SERIAL2_RX_INPUT_REGISTER &IOMUXC_LPUART8_RX_SELECT_INPUT | |
| #define SERIAL2_RX_INPUT_VALUE 1 | |
| #define SERIAL2_RX_ALT_PIN 0xff | |
| #define SERIAL2_RX_ALT_MUX_VAL 0xff | |
| #define SERIAL2_RX_ALT_INPUT_REGISTER nullptr | |
| #define SERIAL2_RX_ALT_INPUT_VALUE 0 | |
| #define SERIAL2_TX_PIN 11 | |
| #define SERIAL2_TX_MUX_VAL 2 | |
| #define SERIAL2_TX_INPUT_REGISTER &IOMUXC_LPUART8_TX_SELECT_INPUT | |
| #define SERIAL2_TX_INPUT_VALUE 1 | |
| #define SERIAL2_TX_ALT_PIN 0xff | |
| #define SERIAL2_TX_ALT_MUX_VAL 0xff | |
| #define SERIAL2_TX_ALT_INPUT_REGISTER nullptr | |
| #define SERIAL2_TX_ALT_INPUT_VALUE 0 | |
| #define SERIAL2_CTS_PIN 0xff | |
| #define SERIAL2_CTS_MUX_VAL 0 | |
| #define SERIAL2_RTS_LOW_WATERMARK 38 | |
| #define SERIAL2_RTS_HIGH_WATERMARK 24 | |
| #define SERIAL2_XBAR_TRIGGER XBARA1_OUT_LPUART8_TRG_INPUT | |
| #define SERIAL3_UART_ADDR IMXRT_LPUART2_ADDRESS | |
| #define SERIAL3_IRQ IRQ_LPUART2 | |
| #define SERIAL3_CCM_REGISTER CCM_CCGR0 | |
| #define SERIAL3_CCM_VALUE CCM_CCGR0_LPUART2(CCM_CCGR_ON) | |
| #define SERIAL3_RX_PIN 5 | |
| #define SERIAL3_RX_MUX_VAL 2 | |
| #define SERIAL3_RX_INPUT_REGISTER &IOMUXC_LPUART2_RX_SELECT_INPUT | |
| #define SERIAL3_RX_INPUT_VALUE 1 | |
| #define SERIAL3_RX_ALT_PIN 0xff | |
| #define SERIAL3_RX_ALT_MUX_VAL 0xff | |
| #define SERIAL3_RX_ALT_INPUT_REGISTER nullptr | |
| #define SERIAL3_RX_ALT_INPUT_VALUE 0 | |
| #define SERIAL3_TX_PIN 7 | |
| #define SERIAL3_TX_MUX_VAL 2 | |
| #define SERIAL3_TX_INPUT_REGISTER &IOMUXC_LPUART2_TX_SELECT_INPUT | |
| #define SERIAL3_TX_INPUT_VALUE 1 | |
| #define SERIAL3_TX_ALT_PIN 0xff | |
| #define SERIAL3_TX_ALT_MUX_VAL 0xff | |
| #define SERIAL3_TX_ALT_INPUT_REGISTER nullptr | |
| #define SERIAL3_TX_ALT_INPUT_VALUE 0 | |
| #define SERIAL3_CTS_PIN 6 | |
| #define SERIAL3_CTS_MUX_VAL 2 | |
| #define SERIAL3_RTS_LOW_WATERMARK 38 | |
| #define SERIAL3_RTS_HIGH_WATERMARK 24 | |
| #define SERIAL3_XBAR_TRIGGER XBARA1_OUT_LPUART2_TRG_INPUT | |
| #define SERIAL4_UART_ADDR IMXRT_LPUART3_ADDRESS | |
| #define SERIAL4_IRQ IRQ_LPUART3 | |
| #define SERIAL4_CCM_REGISTER CCM_CCGR0 | |
| #define SERIAL4_CCM_VALUE CCM_CCGR0_LPUART3(CCM_CCGR_ON) | |
| #define SERIAL4_RX_PIN 20 | |
| #define SERIAL4_RX_MUX_VAL 2 | |
| #define SERIAL4_RX_INPUT_REGISTER &IOMUXC_LPUART3_RX_SELECT_INPUT | |
| #define SERIAL4_RX_INPUT_VALUE 0 | |
| #define SERIAL4_RX_ALT_PIN 44 | |
| #define SERIAL4_RX_ALT_MUX_VAL 3 | |
| #define SERIAL4_RX_ALT_INPUT_REGISTER &IOMUXC_LPUART3_RX_SELECT_INPUT | |
| #define SERIAL4_RX_ALT_INPUT_VALUE 2 | |
| #define SERIAL4_TX_PIN 19 | |
| #define SERIAL4_TX_MUX_VAL 2 | |
| #define SERIAL4_TX_INPUT_REGISTER &IOMUXC_LPUART3_TX_SELECT_INPUT | |
| #define SERIAL4_TX_INPUT_VALUE 0 | |
| #define SERIAL4_TX_ALT_PIN 45 | |
| #define SERIAL4_TX_ALT_MUX_VAL 3 | |
| #define SERIAL4_TX_ALT_INPUT_REGISTER &IOMUXC_LPUART3_TX_SELECT_INPUT | |
| #define SERIAL4_TX_ALT_INPUT_VALUE 2 | |
| #define SERIAL4_CTS_PIN 8 | |
| #define SERIAL4_CTS_MUX_VAL 2 | |
| #define SERIAL4_RTS_LOW_WATERMARK 38 | |
| #define SERIAL4_RTS_HIGH_WATERMARK 24 | |
| #define SERIAL4_XBAR_TRIGGER XBARA1_OUT_LPUART3_TRG_INPUT | |
| #define SERIAL5_UART_ADDR IMXRT_LPUART6_ADDRESS | |
| #define SERIAL5_IRQ IRQ_LPUART6 | |
| #define SERIAL5_CCM_REGISTER CCM_CCGR3 | |
| #define SERIAL5_CCM_VALUE CCM_CCGR3_LPUART6(CCM_CCGR_ON) | |
| #define SERIAL5_RX_PIN 18 | |
| #define SERIAL5_RX_MUX_VAL 2 | |
| #define SERIAL5_RX_INPUT_REGISTER &IOMUXC_LPUART6_RX_SELECT_INPUT | |
| #define SERIAL5_RX_INPUT_VALUE 1 | |
| #define SERIAL5_RX_ALT_PIN 0xff | |
| #define SERIAL5_RX_ALT_MUX_VAL 0xff | |
| #define SERIAL5_RX_ALT_INPUT_REGISTER nullptr | |
| #define SERIAL5_RX_ALT_INPUT_VALUE 0 | |
| #define SERIAL5_TX_PIN 17 | |
| #define SERIAL5_TX_MUX_VAL 2 | |
| #define SERIAL5_TX_INPUT_REGISTER &IOMUXC_LPUART6_TX_SELECT_INPUT | |
| #define SERIAL5_TX_INPUT_VALUE 1 | |
| #define SERIAL5_TX_ALT_PIN 0xff | |
| #define SERIAL5_TX_ALT_MUX_VAL 0xff | |
| #define SERIAL5_TX_ALT_INPUT_REGISTER nullptr | |
| #define SERIAL5_TX_ALT_INPUT_VALUE 0 | |
| #define SERIAL5_CTS_PIN 0xff | |
| #define SERIAL5_CTS_MUX_VAL 0 | |
| #define SERIAL5_RTS_LOW_WATERMARK 38 | |
| #define SERIAL5_RTS_HIGH_WATERMARK 24 | |
| #define SERIAL5_XBAR_TRIGGER XBARA1_OUT_LPUART6_TRG_INPUT | |
| #define SERIAL6_UART_ADDR IMXRT_LPUART5_ADDRESS | |
| #define SERIAL6_IRQ IRQ_LPUART5 | |
| #define SERIAL6_CCM_REGISTER CCM_CCGR3 | |
| #define SERIAL6_CCM_VALUE CCM_CCGR3_LPUART5(CCM_CCGR_ON) | |
| #define SERIAL6_RX_PIN 24 | |
| #define SERIAL6_RX_MUX_VAL 1 | |
| #define SERIAL6_RX_INPUT_REGISTER &IOMUXC_LPUART5_RX_SELECT_INPUT | |
| #define SERIAL6_RX_INPUT_VALUE 1 | |
| #define SERIAL6_RX_ALT_PIN 0xff | |
| #define SERIAL6_RX_ALT_MUX_VAL 0xff | |
| #define SERIAL6_RX_ALT_INPUT_REGISTER nullptr | |
| #define SERIAL6_RX_ALT_INPUT_VALUE 0 | |
| #define SERIAL6_TX_PIN 25 | |
| #define SERIAL6_TX_MUX_VAL 1 | |
| #define SERIAL6_TX_INPUT_REGISTER &IOMUXC_LPUART5_TX_SELECT_INPUT | |
| #define SERIAL6_TX_INPUT_VALUE 1 | |
| #define SERIAL6_TX_ALT_PIN 0xff | |
| #define SERIAL6_TX_ALT_MUX_VAL 0xff | |
| #define SERIAL6_TX_ALT_INPUT_REGISTER nullptr | |
| #define SERIAL6_TX_ALT_INPUT_VALUE 0 | |
| #define SERIAL6_CTS_PIN 0xff | |
| #define SERIAL6_CTS_MUX_VAL 0 | |
| #define SERIAL6_RTS_LOW_WATERMARK 38 | |
| #define SERIAL6_RTS_HIGH_WATERMARK 24 | |
| #define SERIAL6_XBAR_TRIGGER XBARA1_OUT_LPUART5_TRG_INPUT | |
| #define SERIAL7_UART_ADDR IMXRT_LPUART4_ADDRESS | |
| #define SERIAL7_IRQ IRQ_LPUART4 | |
| #define SERIAL7_CCM_REGISTER CCM_CCGR1 | |
| #define SERIAL7_CCM_VALUE CCM_CCGR1_LPUART4(CCM_CCGR_ON) | |
| #define SERIAL7_RX_PIN 36 | |
| #define SERIAL7_RX_MUX_VAL 2 | |
| #define SERIAL7_RX_INPUT_REGISTER &IOMUXC_LPUART4_RX_SELECT_INPUT | |
| #define SERIAL7_RX_INPUT_VALUE 2 | |
| #define SERIAL7_RX_ALT_PIN 0xff | |
| #define SERIAL7_RX_ALT_MUX_VAL 0xff | |
| #define SERIAL7_RX_ALT_INPUT_REGISTER nullptr | |
| #define SERIAL7_RX_ALT_INPUT_VALUE 0 | |
| #define SERIAL7_TX_PIN 37 | |
| #define SERIAL7_TX_MUX_VAL 2 | |
| #define SERIAL7_TX_INPUT_REGISTER &IOMUXC_LPUART4_TX_SELECT_INPUT | |
| #define SERIAL7_TX_INPUT_VALUE 2 | |
| #define SERIAL7_TX_ALT_PIN 0xff | |
| #define SERIAL7_TX_ALT_MUX_VAL 0xff | |
| #define SERIAL7_TX_ALT_INPUT_REGISTER nullptr | |
| #define SERIAL7_TX_ALT_INPUT_VALUE 0 | |
| #define SERIAL7_CTS_PIN 0xff | |
| #define SERIAL7_CTS_MUX_VAL 0 | |
| #define SERIAL7_RTS_LOW_WATERMARK 38 | |
| #define SERIAL7_RTS_HIGH_WATERMARK 24 | |
| #define SERIAL7_XBAR_TRIGGER XBARA1_OUT_LPUART4_TRG_INPUT | |
| // used in cores/digital.c for `digital_pin_to_info_PGM[]` | |
| #define PINS_TO_DIGITAL_INFO { \ | |
| {&CORE_PIN0_PORTREG, &CORE_PIN0_CONFIG, &CORE_PIN0_PADCONFIG, CORE_PIN0_BITMASK}, \ | |
| {&CORE_PIN1_PORTREG, &CORE_PIN1_CONFIG, &CORE_PIN1_PADCONFIG, CORE_PIN1_BITMASK}, \ | |
| {&CORE_PIN2_PORTREG, &CORE_PIN2_CONFIG, &CORE_PIN2_PADCONFIG, CORE_PIN2_BITMASK}, \ | |
| {&CORE_PIN3_PORTREG, &CORE_PIN3_CONFIG, &CORE_PIN3_PADCONFIG, CORE_PIN3_BITMASK}, \ | |
| {&CORE_PIN4_PORTREG, &CORE_PIN4_CONFIG, &CORE_PIN4_PADCONFIG, CORE_PIN4_BITMASK}, \ | |
| {&CORE_PIN5_PORTREG, &CORE_PIN5_CONFIG, &CORE_PIN5_PADCONFIG, CORE_PIN5_BITMASK}, \ | |
| {&CORE_PIN6_PORTREG, &CORE_PIN6_CONFIG, &CORE_PIN6_PADCONFIG, CORE_PIN6_BITMASK}, \ | |
| {&CORE_PIN7_PORTREG, &CORE_PIN7_CONFIG, &CORE_PIN7_PADCONFIG, CORE_PIN7_BITMASK}, \ | |
| {&CORE_PIN8_PORTREG, &CORE_PIN8_CONFIG, &CORE_PIN8_PADCONFIG, CORE_PIN8_BITMASK}, \ | |
| {&CORE_PIN9_PORTREG, &CORE_PIN9_CONFIG, &CORE_PIN9_PADCONFIG, CORE_PIN9_BITMASK}, \ | |
| {&CORE_PIN10_PORTREG, &CORE_PIN10_CONFIG, &CORE_PIN10_PADCONFIG, CORE_PIN10_BITMASK}, \ | |
| {&CORE_PIN11_PORTREG, &CORE_PIN11_CONFIG, &CORE_PIN11_PADCONFIG, CORE_PIN11_BITMASK}, \ | |
| {&CORE_PIN12_PORTREG, &CORE_PIN12_CONFIG, &CORE_PIN12_PADCONFIG, CORE_PIN12_BITMASK}, \ | |
| {&CORE_PIN13_PORTREG, &CORE_PIN13_CONFIG, &CORE_PIN13_PADCONFIG, CORE_PIN13_BITMASK}, \ | |
| {&CORE_PIN14_PORTREG, &CORE_PIN14_CONFIG, &CORE_PIN14_PADCONFIG, CORE_PIN14_BITMASK}, \ | |
| {&CORE_PIN15_PORTREG, &CORE_PIN15_CONFIG, &CORE_PIN15_PADCONFIG, CORE_PIN15_BITMASK}, \ | |
| {&CORE_PIN16_PORTREG, &CORE_PIN16_CONFIG, &CORE_PIN16_PADCONFIG, CORE_PIN16_BITMASK}, \ | |
| {&CORE_PIN17_PORTREG, &CORE_PIN17_CONFIG, &CORE_PIN17_PADCONFIG, CORE_PIN17_BITMASK}, \ | |
| {&CORE_PIN18_PORTREG, &CORE_PIN18_CONFIG, &CORE_PIN18_PADCONFIG, CORE_PIN18_BITMASK}, \ | |
| {&CORE_PIN19_PORTREG, &CORE_PIN19_CONFIG, &CORE_PIN19_PADCONFIG, CORE_PIN19_BITMASK}, \ | |
| {&CORE_PIN20_PORTREG, &CORE_PIN20_CONFIG, &CORE_PIN20_PADCONFIG, CORE_PIN20_BITMASK}, \ | |
| {&CORE_PIN21_PORTREG, &CORE_PIN21_CONFIG, &CORE_PIN21_PADCONFIG, CORE_PIN21_BITMASK}, \ | |
| {&CORE_PIN22_PORTREG, &CORE_PIN22_CONFIG, &CORE_PIN22_PADCONFIG, CORE_PIN22_BITMASK}, \ | |
| {&CORE_PIN23_PORTREG, &CORE_PIN23_CONFIG, &CORE_PIN23_PADCONFIG, CORE_PIN23_BITMASK}, \ | |
| {&CORE_PIN24_PORTREG, &CORE_PIN24_CONFIG, &CORE_PIN24_PADCONFIG, CORE_PIN24_BITMASK}, \ | |
| {&CORE_PIN25_PORTREG, &CORE_PIN25_CONFIG, &CORE_PIN25_PADCONFIG, CORE_PIN25_BITMASK}, \ | |
| {&CORE_PIN26_PORTREG, &CORE_PIN26_CONFIG, &CORE_PIN26_PADCONFIG, CORE_PIN26_BITMASK}, \ | |
| {&CORE_PIN27_PORTREG, &CORE_PIN27_CONFIG, &CORE_PIN27_PADCONFIG, CORE_PIN27_BITMASK}, \ | |
| {&CORE_PIN28_PORTREG, &CORE_PIN28_CONFIG, &CORE_PIN28_PADCONFIG, CORE_PIN28_BITMASK}, \ | |
| {&CORE_PIN29_PORTREG, &CORE_PIN29_CONFIG, &CORE_PIN29_PADCONFIG, CORE_PIN29_BITMASK}, \ | |
| {&CORE_PIN30_PORTREG, &CORE_PIN30_CONFIG, &CORE_PIN30_PADCONFIG, CORE_PIN30_BITMASK}, \ | |
| {&CORE_PIN31_PORTREG, &CORE_PIN31_CONFIG, &CORE_PIN31_PADCONFIG, CORE_PIN31_BITMASK}, \ | |
| {&CORE_PIN32_PORTREG, &CORE_PIN32_CONFIG, &CORE_PIN32_PADCONFIG, CORE_PIN32_BITMASK}, \ | |
| {&CORE_PIN33_PORTREG, &CORE_PIN33_CONFIG, &CORE_PIN33_PADCONFIG, CORE_PIN33_BITMASK}, \ | |
| {&CORE_PIN34_PORTREG, &CORE_PIN34_CONFIG, &CORE_PIN34_PADCONFIG, CORE_PIN34_BITMASK}, \ | |
| {&CORE_PIN35_PORTREG, &CORE_PIN35_CONFIG, &CORE_PIN35_PADCONFIG, CORE_PIN35_BITMASK}, \ | |
| {&CORE_PIN36_PORTREG, &CORE_PIN36_CONFIG, &CORE_PIN36_PADCONFIG, CORE_PIN36_BITMASK}, \ | |
| {&CORE_PIN37_PORTREG, &CORE_PIN37_CONFIG, &CORE_PIN37_PADCONFIG, CORE_PIN37_BITMASK}, \ | |
| {&CORE_PIN38_PORTREG, &CORE_PIN38_CONFIG, &CORE_PIN38_PADCONFIG, CORE_PIN38_BITMASK}, \ | |
| {&CORE_PIN39_PORTREG, &CORE_PIN39_CONFIG, &CORE_PIN39_PADCONFIG, CORE_PIN39_BITMASK}, \ | |
| {&CORE_PIN40_PORTREG, &CORE_PIN40_CONFIG, &CORE_PIN40_PADCONFIG, CORE_PIN40_BITMASK}, \ | |
| {&CORE_PIN41_PORTREG, &CORE_PIN41_CONFIG, &CORE_PIN41_PADCONFIG, CORE_PIN41_BITMASK}, \ | |
| {&CORE_PIN42_PORTREG, &CORE_PIN42_CONFIG, &CORE_PIN42_PADCONFIG, CORE_PIN42_BITMASK}, \ | |
| {&CORE_PIN43_PORTREG, &CORE_PIN43_CONFIG, &CORE_PIN43_PADCONFIG, CORE_PIN43_BITMASK}, \ | |
| {&CORE_PIN44_PORTREG, &CORE_PIN44_CONFIG, &CORE_PIN44_PADCONFIG, CORE_PIN44_BITMASK}, \ | |
| {&CORE_PIN45_PORTREG, &CORE_PIN45_CONFIG, &CORE_PIN45_PADCONFIG, CORE_PIN45_BITMASK}, \ | |
| {&CORE_PIN46_PORTREG, &CORE_PIN46_CONFIG, &CORE_PIN46_PADCONFIG, CORE_PIN46_BITMASK}, \ | |
| {&CORE_PIN47_PORTREG, &CORE_PIN47_CONFIG, &CORE_PIN47_PADCONFIG, CORE_PIN47_BITMASK}, \ | |
| {&CORE_PIN48_PORTREG, &CORE_PIN48_CONFIG, &CORE_PIN48_PADCONFIG, CORE_PIN48_BITMASK}, \ | |
| {&CORE_PIN49_PORTREG, &CORE_PIN49_CONFIG, &CORE_PIN49_PADCONFIG, CORE_PIN49_BITMASK}, \ | |
| {&CORE_PIN50_PORTREG, &CORE_PIN50_CONFIG, &CORE_PIN50_PADCONFIG, CORE_PIN50_BITMASK}, \ | |
| {&CORE_PIN51_PORTREG, &CORE_PIN51_CONFIG, &CORE_PIN51_PADCONFIG, CORE_PIN51_BITMASK}, \ | |
| {&CORE_PIN52_PORTREG, &CORE_PIN52_CONFIG, &CORE_PIN52_PADCONFIG, CORE_PIN52_BITMASK}, \ | |
| {&CORE_PIN53_PORTREG, &CORE_PIN53_CONFIG, &CORE_PIN53_PADCONFIG, CORE_PIN53_BITMASK}, \ | |
| }; | |
| // used in cores/analog.c for `pin_to_channel[]` | |
| #define PINS_TO_ANALOG_CHANNELS { \ | |
| 3, /* 0 ADC1_IN3 GPIO_AD_B0_14 */ \ | |
| 4, /* 1 ADC1_IN4 GPIO_AD_B0_15 */ \ | |
| 1, /* 2 ADC1_IN1 GPIO_AD_B0_12 */ \ | |
| 2, /* 3 ADC1_IN2 GPIO_AD_B0_13 */ \ | |
| 0, /* 4 ADC1_IN0 GPIO_AD_B1_11 */ \ | |
| 8, /* 5 ADC1_IN8 GPIO_AD_B1_03 */ \ | |
| 5, /* 6 ADC1_IN5 GPIO_AD_B1_00 */ \ | |
| 7, /* 7 ADC1_IN7 GPIO_AD_B1_02 */ \ | |
| 9, /* 8 ADC1_IN9 GPIO_AD_B1_04 */ \ | |
| 6, /* 9 ADC1_IN6 GPIO_AD_B1_01 */ \ | |
| 13, /* 10 ADC1_IN13 GPIO_AD_B1_08 */ \ | |
| 15, /* 11 ADC1_IN15 GPIO_AD_B1_10 */ \ | |
| 14, /* 12 ADC1_IN14 GPIO_AD_B1_09 */ \ | |
| 10, /* 13 ADC1_IN10 GPIO_AD_B1_05 */ \ | |
| 128+1, /* 14 ADC2_IN1 GPIO_AD_B1_12 */ \ | |
| 128+2, /* 15 ADC2_IN2 GPIO_AD_B1_13 */ \ | |
| 128+3, /* 16 ADC2_IN3 GPIO_AD_B1_14 */ \ | |
| 255, /* 17 - GPIO_AD_B0_02 */ \ | |
| 255, /* 18 - GPIO_AD_B0_03 */ \ | |
| 11, /* 19 ADC1_IN11 GPIO_AD_B1_06 */ \ | |
| 12, /* 20 ADC1_IN12 GPIO_AD_B1_07 */ \ | |
| 128+4, /* 21 ADC2_IN4 GPIO_AD_B1_15 */ \ | |
| }; | |
| #define M(a, b) ((((a) - 1) << 4) | (b)) | |
| // used in cores/pwm.c for `pwm_pin_info[]` | |
| #define PINS_TO_PWM_INFO { \ | |
| {0, M(1, 0), 0, 0}, /* 0 - */ \ | |
| {0, M(1, 0), 0, 0}, /* 1 - */ \ | |
| {1, M(1, 2), 0, 4}, /* 2 FLEXPWM1_PWMX02 */ \ | |
| {1, M(1, 3), 0, 4}, /* 3 FLEXPWM1_PWMX03 */ \ | |
| {0, M(1, 0), 0, 0}, /* 4 - */ \ | |
| {2, M(3, 3), 0, 1}, /* 5 QTIMER3_TIMER3 */ \ | |
| {2, M(3, 0), 0, 1}, /* 6 QTIMER3_TIMER0 */ \ | |
| {2, M(3, 2), 0, 1}, /* 7 QTIMER3_TIMER2 */ \ | |
| {0, M(1, 0), 0, 0}, /* 8 - */ \ | |
| {2, M(3, 1), 0, 1}, /* 9 QTIMER3_TIMER1 */ \ | |
| {1, M(4, 0), 1, 1}, /* 10 FLEXPWM4_PWMA00 */ \ | |
| {0, M(1, 0), 0, 0}, /* 11 - */ \ | |
| {1, M(4, 1), 1, 1}, /* 12 FLEXPWM4_PWMA01 */ \ | |
| {0, M(1, 0), 0, 0}, /* 13 - */ \ | |
| {0, M(1, 0), 0, 0}, /* 14 - */ \ | |
| {0, M(1, 0), 0, 0}, /* 15 - */ \ | |
| {0, M(1, 0), 0, 0}, /* 16 - */ \ | |
| {1, M(1, 0), 0, 4}, /* 17 FLEXPWM1_PWMX00 */ \ | |
| {1, M(1, 1), 0, 4}, /* 18 FLEXPWM1_PWMX01 */ \ | |
| {0, M(1, 0), 0, 0}, /* 19 - */ \ | |
| {0, M(1, 0), 0, 0}, /* 20 - */ \ | |
| {0, M(1, 0), 0, 0}, /* 21 - */ \ | |
| {1, M(4, 3), 1, 1}, /* 22 FLEXPWM4_PWMA03 */ \ | |
| {1, M(4, 2), 1, 1}, /* 23 FLEXPWM4_PWMA02 */ \ | |
| {0, M(1, 0), 0, 0}, /* 24 - */ \ | |
| {0, M(1, 0), 0, 0}, /* 25 - */ \ | |
| {2, M(4, 3), 0, 1}, /* 26 QTIMER4_TIMER3 */ \ | |
| {0, M(1, 0), 0, 0}, /* 27 dupe QTIMER3_TIMER3 */ \ | |
| {2, M(2, 3), 0, 1}, /* 28 QTIMER2_TIMER3 */ \ | |
| {2, M(1, 3), 0, 1}, /* 29 QTIMER1_TIMER3 */ \ | |
| {0, M(1, 0), 0, 0}, /* 30 - */ \ | |
| {0, M(1, 0), 0, 0}, /* 31 - */ \ | |
| {0, M(1, 0), 0, 0}, /* 32 - */ \ | |
| {0, M(1, 0), 0, 0}, /* 33 - */ \ | |
| {1, M(2, 3), 2, 6}, /* 34 FLEXPWM2_PWMB03 */ \ | |
| {1, M(2, 3), 1, 6}, /* 35 FLEXPWM2_PWMA03 */ \ | |
| {1, M(1, 3), 2, 6}, /* 36 FLEXPWM1_PWMB03 */ \ | |
| {1, M(1, 3), 1, 6}, /* 37 FLEXPWM1_PWMA03 */ \ | |
| {0, M(1, 0), 0, 0}, /* 38 - */ \ | |
| {0, M(1, 0), 0, 0}, /* 39 - */ \ | |
| {0, M(1, 0), 0, 0}, /* 40 - */ \ | |
| {0, M(1, 0), 0, 0}, /* 41 - */ \ | |
| {1, M(2, 2), 2, 2}, /* 42 FLEXPWM2_PWMB02 */ \ | |
| {1, M(2, 2), 1, 2}, /* 43 FLEXPWM2_PWMA02 */ \ | |
| {1, M(2, 1), 2, 2}, /* 44 FLEXPWM2_PWMB01 */ \ | |
| {1, M(2, 1), 1, 2}, /* 45 FLEXPWM2_PWMA01 */ \ | |
| {1, M(2, 0), 2, 2}, /* 46 FLEXPWM2_PWMB00 */ \ | |
| {1, M(2, 0), 1, 2}, /* 47 FLEXPWM2_PWMA00 */ \ | |
| {2, M(2, 2), 0, 1}, /* 48 QTIMER2_TIMER2 */ \ | |
| {2, M(2, 1), 0, 1}, /* 49 QTIMER2_TIMER1 */ \ | |
| {2, M(2, 0), 0, 1}, /* 50 QTIMER2_TIMER0 */ \ | |
| {2, M(1, 2), 0, 1}, /* 51 QTIMER1_TIMER2 */ \ | |
| {2, M(1, 1), 0, 1}, /* 52 QTIMER1_TIMER1 */ \ | |
| {2, M(1, 0), 0, 1}, /* 53 QTIMER1_TIMER0 */ \ | |
| }; | |
| // used in cores/HardwareSerial.cpp for `pin_to_xbar_info[]` | |
| #define PINS_TO_XBAR_INFO { \ | |
| { 0, 24, 1, &IOMUXC_XBAR1_IN24_SELECT_INPUT, 0x1}, \ | |
| { 1, 25, 1, nullptr, 0 }, \ | |
| {17, 16, 1, &IOMUXC_XBAR1_IN16_SELECT_INPUT, 0x0}, \ | |
| {18, 17, 1, &IOMUXC_XBAR1_IN17_SELECT_INPUT, 0x1}, \ | |
| {22, 3, 3, &IOMUXC_XBAR1_IN03_SELECT_INPUT, 0x1}, \ | |
| {23, 2, 3, &IOMUXC_XBAR1_IN02_SELECT_INPUT, 0x1}, \ | |
| {34, 17, 1, &IOMUXC_XBAR1_IN17_SELECT_INPUT, 0x3}, \ | |
| {35, 16, 1, &IOMUXC_XBAR1_IN16_SELECT_INPUT, 0x1}, \ | |
| {36, 15, 1, &IOMUXC_XBAR1_IN15_SELECT_INPUT, 0x1}, \ | |
| {37, 14, 1, &IOMUXC_XBAR1_IN14_SELECT_INPUT, 0x1}, \ | |
| }; |
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| name: Teensy DevBoard v5 | |
| flash: | |
| baseaddr: "0x60FC0000" | |
| size: "0x01000000" | |
| sectors: 63 | |
| eeprom_size: "0x10BB" | |
| extmem: | |
| type: sdram | |
| baseaddr: "0x80000000" | |
| endaddr: "0x8FFFFFFF" | |
| pins: | |
| # left/bottom header | |
| - GPIO_AD_B0_14 | |
| - GPIO_AD_B0_15 | |
| - GPIO_AD_B0_12 | |
| - GPIO_AD_B0_13 | |
| - GPIO_AD_B1_11 | |
| - GPIO_AD_B1_03 | |
| - GPIO_AD_B1_00 | |
| - GPIO_AD_B1_02 | |
| - GPIO_AD_B1_04 | |
| - GPIO_AD_B1_01 | |
| - GPIO_AD_B1_08 | |
| - GPIO_AD_B1_10 | |
| - GPIO_AD_B1_09 | |
| - GPIO_AD_B1_05 | |
| - GPIO_AD_B1_12 | |
| - GPIO_AD_B1_13 | |
| - GPIO_AD_B1_14 | |
| - GPIO_AD_B0_02 | |
| - GPIO_AD_B0_03 | |
| - GPIO_AD_B1_06 | |
| - GPIO_AD_B1_07 | |
| - GPIO_AD_B1_15 | |
| # right/top header | |
| - GPIO_B1_15 | |
| - GPIO_B1_14 | |
| - GPIO_B1_13 | |
| - GPIO_B1_12 | |
| - GPIO_B1_11 | |
| - GPIO_B1_10 | |
| - GPIO_B1_09 | |
| - GPIO_B1_08 | |
| - GPIO_B1_07 | |
| - GPIO_B1_06 | |
| - GPIO_B1_05 | |
| - GPIO_B1_04 | |
| - GPIO_B1_03 | |
| - GPIO_B1_02 | |
| - GPIO_B1_01 | |
| - GPIO_B1_00 | |
| - GPIO_B0_15 | |
| - GPIO_B0_14 | |
| - GPIO_B0_13 | |
| - GPIO_B0_12 | |
| - GPIO_B0_11 | |
| - GPIO_B0_10 | |
| - GPIO_B0_09 | |
| - GPIO_B0_08 | |
| - GPIO_B0_07 | |
| - GPIO_B0_06 | |
| - GPIO_B0_05 | |
| - GPIO_B0_04 | |
| - GPIO_B0_03 | |
| - GPIO_B0_02 | |
| - GPIO_B0_01 | |
| - GPIO_B0_00 |
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