TPS2121 Unified Reference Guide

Community-sourced design insights and troubleshooting for the TI TPS2121 power multiplexer

Device Overview

The TPS2121 is a 2:1 power multiplexer with break-before-make switching (2.8-22V, 4.5A, 56mΩ). Unlike ideal diodes, it actively manages input selection based on programmable priority logic while providing integrated protection.

Key Characteristics:

Unidirectional only (not suitable for USB OTG or bidirectional applications)
Brief output disconnection during switchover (~5µs) requires output capacitance
Cannot be paralleled (timing mismatches cause uneven loading and failures)
5µs fast switchover vs 100µs standard switchover depending on configuration
No dedicated enable pin (disable by driving both OV1 and OV2 above VREF)

Operating Modes and Real-World Performance

Control via PR1 and CP2 pins relative to internal 1.06V reference (VREF):

VCOMP Mode: Highest Voltage Selection

Config: Both PR1 and CP2 to ground
Real-world issue: Oscillation when input voltages within ~300mV due to load-induced voltage variations
Solution: Ensure >300mV separation or implement hysteresis

VREF Mode: Basic Priority

Config: PR1 voltage divider from IN1, CP2 to ground
Best for: Battery backup applications (USB vs battery)
Switching threshold: When VPR1 drops below 1.06V

XCOMP Mode: Fast Priority (Recommended)

Config: Both PR1 and CP2 > 1.06V via voltage dividers
Advantage: 5µs switchover (vs 100µs) when CP2 > VREF
Critical requirement: CP2 must be >1.06V to enable fast switchover

Design Essentials & Common Pitfalls

Input Capacitance (Most Critical)

Problem: Insufficient input capacitance is the #1 cause of oscillation. When device switches to an input, voltage sag under load causes immediate switch-back.

Solutions:

Minimum 47µF per input for stable operation (10µF absolute minimum)
Input capacitance ≥ output capacitance (design rule)
Hot-plug applications: 470µF + TVS diode for spike protection
Long cable applications: Large input capacitance dampens L×di/dt transients

Output Capacitance Sizing

Formula: C = (I_load × t_switch) / ΔV_acceptable Typical range: 10-30µF is often sufficient for most applications

During ~5µs break-before-make, only output cap supplies load
Large capacitance (>100µF) improves holdup but increases inrush current
Very large capacitance (>1000µF) can trigger thermal/overcurrent protection
Balance point: Adequate holdup without triggering thermal protection

Hysteresis Implementation (Essential for Close Voltages)

Method: 100kΩ-1MΩ resistor between ST and PR1 pins Mechanism: When IN2 selected, ST goes low → pulls PR1 down → creates different thresholds for each direction When needed: Input voltages within 1V or battery sources that sag under load Design aid: TI provides a design calculator to select optimal resistor values

Current Limiting Behavior

Formula: I_LIMIT = 65.2 / (R_ILIM^0.861) Reality: Not precision current regulation - triggers "hiccup" mode (off 25ms, retry) Design margin: Set 1.5-2× expected load current Cannot be disabled: Minimum ~1A even with large resistors Important limitation: ILIM pin cannot be used to monitor output current Pulsed loads: Consider duty cycle - brief current spikes above continuous rating may be acceptable

Soft-Start Capacitor (CSS)

Purpose: Control inrush current, especially with large output capacitance Rule: CSS must increase proportionally with COUT Typical: 100nF gives ~780V/s slew rate at 5V

Overvoltage Protection (OVx)

Purpose: Use a resistor divider to set the overvoltage lockout (OVLO) threshold for each input. The channel is disabled if its OVx pin voltage exceeds VREF. Configuration: To disable OVP, tie the OVx pin directly to GND.

Power Consumption (Battery Backup Systems)

For battery-powered applications, understanding the different current consumption specs is key to estimating battery life.

Active (Quiescent) Current - IQ, INX (~300 µA typical): This is the current drawn from the active input source (IN1 or IN2) that is powering the load.
Inactive (Standby) Current - ISBY, INX (~15 µA typical): This is the current drawn from the inactive or backup power source. This is the critical value for calculating the drain on your backup battery when the main supply is present.

PCB Design Considerations

Layout Guidelines

Thermal management: Vias directly under IN1/IN2/VOUT pads for >2A applications
Component placement: Input/output caps <5mm from device, control resistors close to pins
Power path optimization: Wide copper planes, minimize trace resistance

Physical and Mechanical Issues

Connector Disconnect Sequencing: When unplugging a power source, ensure the power and ground pins are the last to break contact. If a control signal (like a PR1 sense line) disconnects before the power rail, it can cause unexpected switchover behavior.
Input Instability ("Shaking"): A vibrating or intermittent connector can cause rapid voltage fluctuations that the device may interpret as a fault, leading to a protective shutdown. A robust mechanical connection and sufficient CIN can mitigate this.

Protection Circuits

Hot-plug: TVS diode near inputs, clamp <24V absolute maximum
Reverse polarity: External diode from device GND to system GND (reference all control voltages to device GND)
EMI: Common-mode chokes for cable-induced noise in sensitive applications

Debug Waveforms

Essential captures: IN1, IN2, VOUT, PR1, CP2, ST simultaneously during switching events

Device Failure Signature: A common failure mode from electrical overstress (EOS) is a permanent, low-impedance path between IN1 and IN2. If you measure a low resistance (e.g., < 50 kΩ) between the inputs on an unpowered board, the IC is likely damaged.

Component Selection Guidelines

Resistor Dividers

Bottom resistor: 5kΩ (per datasheet recommendation)
Total resistance: 50-100kΩ (avoid >100kΩ which creates RC delays)
Use 1% tolerance for precision applications
Account for temperature coefficient effects

Capacitor Selection

Input: Low ESR ceramic, X5R/X7R dielectric, voltage rating 2× minimum
Output: Consider DC bias derating, especially for high-capacity ceramic
CSS: Start with 100nF, increase proportionally with output capacitance

Use Alternatives For

>22V input: TPS2663 eFuse + control logic (handles 65V)
>4.5A continuous: Dual eFuse topology (TPS25947), never parallel TPS2121s
<10µA quiescent: TPS2117 (5.5V max) or TPS211x family
Bidirectional current: Dual eFuse configuration (see TI app note SLVA948)
Automotive: TPS2115A-Q1, TPS25940-Q1 for AEC-Q100 qualification
Handling >2 Inputs: To select between 3 or more sources, cascade multiple TPS2121 devices. The output of the first MUX feeds into an input of the second MUX.

Common Design Mistakes

Assuming precision current regulation (it's protection, not regulation)
Using constant-current electronic loads for testing (causes instability - use resistive or constant-resistance mode)
Insufficient input capacitance leading to oscillation (minimum 47µF per input)
Floating CP2 pin causing undefined behavior (verify with multimeter during debugging)
Paralleling devices for higher current (timing mismatches cause failures)
Not implementing hysteresis when input voltages are close

Quick Reference

Essential Design Rules:

Input capacitance ≥ output capacitance, minimum 47µF per input
Hysteresis resistor (100kΩ-1MΩ) between ST and PR1 if inputs within 1V
CP2 > 1.06V required for 5µs fast switchover
Current limit = 1.5-2× maximum expected load
TVS protection for hot-plug applications

Key Formulas:

VPR1 = VIN1 × (R2 / (R1 + R2))
I_LIMIT = 65.2 / (R_ILIM^0.861)
COUT = (I_load × t_switch) / ΔV_acceptable

This guide synthesizes community experience with the TPS2121. Always reference the official datasheet (SLVSEA3D) for complete specifications.

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