NVMe (Non-Volatile Memory Express) is a host-to-device protocol for PCIe-attached storage. The driver talks to the controller through paired ring buffers in host memory:
- SQ (Submission Queue): host writes commands here.
- CQ (Completion Queue): controller writes completion records here.
- SQE (Submission Queue Entry): one 64-byte command in the SQ. Each SQE has a 1-byte opcode, a 2-byte CID (Command Identifier) chosen by the host so the host can match a completion back to the request, and 16 dwords of parameters labeled
cdw0throughcdw15.cdw11is "Command Dword 11", a per-opcode parameter slot. - CQE (Completion Queue Entry): one 16-byte completion record in the CQ. Each CQE carries the CID it completes, a status code, and a phase bit that flips each time the controller wraps the ring, so the host can tell fresh entries from stale ones without polling a separate index.