basic cpu identifier (32-bit windows)

cpuidentifier.c

/* 
 * cpuidentifier by pala
 * written for 32-bit windows
 */

#include <stdio.h>
#include <string.h>

#define VERSION "1.0.0"

#if !defined(_WIN32)
int main()
{
	puts("32-bit windows only baybee");
	return 0;
}
#else

// Manufacturer IDs
const struct {
	char id[12];
	char manu[15];
} ids[28] = {
	{ "AMDisbetter!", "Old AMD"		},
	{ "AuthenticAMD", "New AMD"		},
	{ "CentaurHauls", "Centaur"		},
	{ "CyrixInstead", "Cyrix"		},
	{ "GenuineIntel", "Intel"		},
	{ "TransmetaCPU", "Transmeta"	},
	{ "GenuineTMx86", "Transmeta"	},
	{ "Geode by NSC", "NSC"			},
	{ "NexGenDriven", "NexGen"		},
	{ "RiseRiseRise", "Rise"		},
	{ "SiS SiS SiS ", "SiS"			},
	{ "UMC UMC UMC ", "UMC"			},
	{ "VIA VIA VIA ", "VIA"			},
	{ "Vortex86 SoC", "Vortex86"	},
	{ "  Shanghai  ", "Zhaoxin"		},
	{ "HygonGenuine", "Hygon"		},
	{ "E2K MACHINE",  "Elbrus"		},
	{ "GenuineAO486", "AO486"		},
	{ "bhyve bhyve ", "bhyve"		},
	{ " KVMKVMKVM ",  "KVM"			},
	{ "TCGTCGTCGTCG", "QEMU"		},
	{ "Microsoft Hv", "Hyper-V"		},
	{ " lrepepyh vr", "Parallels"	},
	{ "VMwareVMware", "VMware"		},
	{ "XenVMMXenVMM", "Xen HVM"		},
	{ "ACRNACRNACRN", "ACRN"		},
	{ " QNXQVMBSQG ", "QNX"			},
	{ "VirtualApple", "Rosetta"		}
};

// features
const struct feature
{
	char shorthand[20];
	int mask;
} edx_features[] = {
	{ "fpu",	1<<0	}, // Onboard x87 FPU
	{ "vme",	1<<1	}, // Virtual 8086 mode extensions (such as VIF, VIP, PIV)
	{ "de",		1<<2	}, // Debugging extensions (CR4 bit 3)
	{ "pse",	1<<3	}, // Page Size Extension
	{ "tsc",	1<<4	}, // Time Stamp Counter
	{ "msr",	1<<5	}, // Model-specific registers
	{ "pae",	1<<6	}, // Physical Address Extension
	{ "mce",	1<<7	}, // Machine Check Exception
	{ "cx8",	1<<8	}, // CMPXCHG8 (compare-and-swap) instruction
	{ "apic",	1<<9	}, // Onboard Advanced Programmable Interrupt Controller
	{ "sep",	1<<11	}, // SYSENTER and SYSEXIT instructions
	{ "mtrr",	1<<12	}, // Memory Type Range Registers
	{ "pge",	1<<13	}, // Page Global Enable bit in CR4
	{ "mca",	1<<14	}, // Machine check architecture
	{ "cmov",	1<<15	}, // Conditional move and FCMOV instructions
	{ "pat",	1<<16	}, // Page Attribute Table
	{ "pse-36",	1<<17	}, // 36-bit page size extension
	{ "psn",	1<<18	}, // Processor Serial Number
	{ "clfsh",	1<<19	}, // CLFLUSH instruction (SSE2)
	{ "ds",		1<<21	}, // Debug store: save trace of executed jumps
	{ "acpi",	1<<22	}, // Onboard thermal control MSRs for ACPI
	{ "mmx",	1<<23	}, // MMX instructions
	{ "fxsr",	1<<24	}, // FXSAVE, FXRESTOR instructions, CR4 bit 9
	{ "sse",	1<<25	}, // SSE instructions (a.k.a. Katmai New Instructions)
	{ "sse2",	1<<26	}, // SSE2 instructions
	{ "ss",		1<<27	}, // CPU cache implements self-snoop
	{ "htt",	1<<28	}, // Hyper-threading
	{ "tm",		1<<29	}, // Thermal monitor automatically limits temperature
	{ "ia64",	1<<30	}, // IA64 processor emulating x86
	{ "pbe",	1<<31	}  // Pending Break Enable (PBE# pin) wakeup capability
}, ecx_features[] = {
	{ "sse3",	1<<0	}, // Prescott New Instructions-SSE3 (PNI)
	{ "pclmulqdq", 1<<1	}, // PCLMULQDQ
	{ "dtes64", 1<<2	}, // 64-bit debug store (edx bit 21)
	{ "monitor", 1<<3	}, // MONITOR and MWAIT instructions (SSE3)
	{ "ds-cpl", 1<<4	}, // CPL qualified debug store
	{ "vmx",	1<<5	}, // Virtual Machine eXtensions
	{ "smx",	1<<6	}, // Safer Mode Extensions (LaGrande)
	{ "est",	1<<7	}, // Enhanced SpeedStep
	{ "tm2",	1<<8	}, // Thermal Monitor 2
	{ "ssse3",	1<<9	}, // Supplemental SSE3 instructions
	{ "cnxt-id",1<<10	}, // L1 Context ID
	{ "sdbg",	1<<11	}, // Silicon Debug interface
	{ "fma",	1<<12	}, // Fused multiply-add (FMA3)
	{ "cx16",	1<<13	}, // CMPXCHG16B instruction
	{ "xtpr",	1<<14	}, // Can disable sending task priority messages
	{ "pdcm",	1<<15	}, // Perfmon & debug capability
	{ "pcid",	1<<17	}, // Process context identifiers (CR4 bit 17)
	{ "dca",	1<<18	}, // Direct cache access for DMA writes
	{ "sse4.1", 1<<19	}, // SSE4.1 instructions
	{ "sse4.2", 1<<20	}, // SSE4.2 instructions
	{ "x2apic", 1<<21	}, // x2APIC
	{ "movbe",	1<<22	}, // MOVBE instruction (big-endian)
	{ "popcnt", 1<<23	}, // POPCNT instruction
	{ "tsc-deadline", 1<<24}, // APIC implements one-shot operation using a TSC deadline value
	{ "aes",	1<<25	}, // AES instruction set
	{ "xsave",	1<<26	}, // XSAVE, XRESTOR, XSETBV, XGETBV
	{ "osxsave",1<<27	}, // XSAVE enabled by OS
	{ "avx",	1<<28	}, // Advanced Vector Extensions
	{ "f16c",	1<<29	}, // F16C (half-precision) FP feature
	{ "rdrnd",	1<<30	}, // RDRAND (on-chip random number generator) feature
	{ "hypervisor", 1<<31} // Hypervisor present (always zero on physical CPUs)
}, ebx_ext_features[] = {
	{ "fsgsbase",	1<<0}, // Access to base of %fs and %gs
	{ "ia32tscadj", 1<<1}, // IA32_TSC_ADJUST
	{ "sgx",	1<<2	}, // Software Guard Extensions
	{ "bmi1",	1<<3	}, // Bit Manipulation Instruction Set 1
	{ "hle",	1<<4	}, // TSX Hardware Lock Elision
	{ "avx2",	1<<5	}, // Advanced Vector Extensions 2
	{ "fdpexco",1<<6	}, // FDP_EXCPTN_ONLY
	{ "smep",	1<<7	}, // Supervisor Mode Execution Prevention
	{ "bmi2",	1<<8	}, // Bit Manipulation Instruction Set 2
	{ "erms",	1<<9	}, // Enhanced REP MOVSB/STOSB
	{ "invpcid",1<<10	}, // INVPCID instruction
	{ "rtm",	1<<11	}, // TSX Restricted Transactional Memory
	{ "pqm",	1<<12	}, // Platform Quality of Service Monitoring
	{ "csdsdep",1<<13	}, // FPU CS and FPU DS deprecated
	{ "mpx",	1<<14	}, // Intel MPX (Memory Protection Extensions)
	{ "pqe",	1<<15	}, // Platform Quality of Service Enforcement
	{ "avx512_f", 1<<16	}, // AVX-512 Foundation
	{ "avx512_dq",1<<17	}, // AVX-512 Doubleword and Quadword Instructions
	{ "rdseed",	1<<18	}, // RDSEED instruction
	{ "adx",	1<<19	}, // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
	{ "smap",	1<<20	}, // Supervisor Mode Access Prevention
	{ "avx512_ifma",1<<21}, // AVX-512 Integer Fused Multiply-Add Instructions
	{ "pcommit",1<<22	}, // PCOMMIT instruction
	{ "clflushopt",1<<23}, // CLFLUSHOPT instruction
	{ "clwb",	1<<24	}, // CLWB instruction
	{ "intel_pt",1<<25	}, // Intel Processor Trace
	{ "avx512_pf",1<<26	}, // AVX-512 Prefetch Instructions
	{ "avx512_er",1<<27	}, // AVX-512 Exponential and Reciprocal Instructions
	{ "avx512_cd",1<<28	}, // AVX-512 Conflict Detection Instructions
	{ "sha",	1<<29	}, // Intel SHA extensions
	{ "avx512_bw",1<<30	}, // AVX-512 Byte and Word Instructions
	{ "avx512_vl",1<<31	}  // AVX-512 Vector Length Extensions
}, ecx_ext_features[] = {
	{ "prefetchwt1",1 << 0	}, // PREFETCHWT1 instruction
	{ "avx512_vbmi",1 << 1	}, // AVX-512 Vector Bit Manipulation Instructions
	{ "umip",	1 << 2		}, // User-mode Instruction Prevention
	{ "pku",	1 << 3		}, // Memory Protection Keys for User-mode pages
	{ "ospke",	1 << 4		}, // PKU enabled by OS
	{ "waitpkg",1 << 5		}, // Timed pause and user-level monitor/wait
	{ "avx512_vbmi2",1 << 6	}, // AVX-512 Vector Bit Manipulation Instructions 2
	{ "cet_ss",	1 << 7		}, // Control flow enforcement (CET) shadow stack
	{ "gfni",	1 << 8		}, // Galois Field instructions
	{ "vaes",	1 << 9		}, // Vector AES instruction set (VEX-256/EVEX)
	{ "vpclmulqdq",	1 << 10	}, // CLMUL instruction set (VEX-256/EVEX)
	{ "avx512_vnni",1 << 11	}, // AVX-512 Vector Neural Network Instructions
	{ "avx512_bitalg",1 << 12	}, // AVX-512 BITALG instructions
	{ "avx512_vpopcntdq",1 << 14}, // AVX-512 Vector Population Count Double and Quad-word
	{ "5lp",	1 << 16		}, // 5-level paging
	{ "rdpid",	1 << 22		}, // Read Processor ID and IA32_TSC_AUX
	{ "cldemote", 1 << 25	}, // Cache line demote
	{ "movdiri",	1<<27	}, // MOVDIRI
	{ "movdir64b",	1<<28	}, // MOVDIR64B
	{ "enqcmd",		1<<29	}, // Enqueue Stores
	{ "sgx_lc",		1<<30	}, // SGX Launch Configuration
	{ "pks",		1<<31	}  // Protection keys for supervisor-mode pages
}, edx_ext_features[] = {
	{ "avx512_4vnniw", 1<<2 }, // AVX-512 4-register Neural Network Instructions
	{ "avx512_4maps",  1<<3 }, // AVX-512 4-register Multiply Accumulation Single precision
	{ "fsrm",	1<<4		}, // Fast Short REP MOVSB
	{ "avx512_vp2intersect", 1<<8 }, // AVX-512 VP2INTERSECT Doubleword and Quadword Instructions
	{ "srbds_ctrl",		1<<9}, // Special Register Buffer Data Sampling Mitigations
	{ "md_clear",	1<<10	}, // VERW instruction clears CPU buffers
	{ "tsx_force_abort", 1<<13}, // tsx_force_abort
	{ "serialize",	1<<14	}, // Serialize instruction execution
	{ "hybrid",		1<<15	}, // Hybrid
	{ "tsxldtrk",	1<<16	}, // TSX suspend load address tracking
	{ "pconfig",	1<<18	}, // Platform configuration (Memory Encryption Technologies Instructions)
	{ "lbr",		1<<19	}, // Architectural Last Branch Records
	{ "cet_ibt",	1<<20	}, // Control flow enforcement (CET) indirect branch tracking
	{ "amx-bf16",	1<<22	}, // Tile computation on bfloat16 numbers
	{ "amx-tile",	1<<24	}, // Tile architecture
	{ "amx-int8",	1<<25	}, // Tile computation on 8-bit integers
	{ "spec_ctrl",	1<<26	}, // Speculation Control
	{ "stibp",		1<<27	}, // Single Thread Indirect Branch Predictor
	{ "l1d_flush",	1<<28	}, // IA32_FLUSH_CMD MSR
	{ "ia32_arch_cap", 1<<29}, // Speculative Side Channel Mitigations
	{ "ia32_core_cap", 1<<30}, // Support for a MSR listing model-specific core capabilities
	{ "ssbd",		1<<31	}  // Speculative Store Bypass Disable
};

int is_cpuid_supported()
{
	int res;

	__asm {
		pushfd
		pushfd
		xor DWORD PTR[esp], 0x200000
		popfd
		pushfd
		pop eax
		xor eax, [esp]
		popfd
		and eax, 0x200000
		mov res, eax
	}

	return res;
}


void vendor()
{
	int _ebx, _ecx, _edx;

	__asm {
		xor eax, eax
		cpuid

		mov _ebx, ebx
		mov _ecx, ecx
		mov _edx, edx
	}

	char id[13];
	id[12] = 0;

	id[0] = (char)_ebx;
	id[1] = (char)(_ebx >> 8);
	id[2] = (char)(_ebx >> 16);
	id[3] = (char)(_ebx >> 24);
	id[4] = (char)_edx;
	id[5] = (char)(_edx >> 8);
	id[6] = (char)(_edx >> 16);
	id[7] = (char)(_edx >> 24);
	id[8] = (char)_ecx;
	id[9] = (char)(_ecx >> 8);
	id[10] = (char)(_ecx >> 16);
	id[11] = (char)(_ecx >> 24);

	for (int i = 0; i < 28; i++) {
		if (i == 27) {
			puts("vendor: unknown");
			break;
		}

		if (!strncmp(id, ids[i].id, 12)) {
			printf("vendor: %s\n", ids[i].manu);
			break;
		}
	}
}

void proc_info_feature_bits()
{
	int _ecx, _edx;

	__asm {
		mov eax, 1
		cpuid
		mov _ecx, ecx
		mov _edx, edx
	}

	printf("features: ");

	for (int i = 0; i < 32; i++) {
		if ((edx_features[i].mask & _edx) != 0) {
			printf("%s ", edx_features[i].shorthand);
		}
	}

	for (int i = 0; i < 32; i++) {
		if ((ecx_features[i].mask & _ecx) != 0) {
			printf("%s ", ecx_features[i].shorthand);
		}
	}

	puts("\n");
}

void extended_features()
{
	int _ebx, _ecx, _edx;

	__asm {
		mov eax, 7
		mov ecx, 0
		cpuid

		mov _ebx, ebx
		mov _ecx, ecx
		mov _edx, edx
	}

	printf("extended features: ");

	for (int i = 0; i < 32; i++) {
		if ((ebx_ext_features[i].mask & _ebx) != 0) {
			printf("%s ", ebx_ext_features[i].shorthand);
		}
	}

	for (int i = 0; i < 32; i++) {
		if ((ecx_ext_features[i].mask & _ecx) != 0) {
			printf("%s ", ecx_ext_features[i].shorthand);
		}
	}

	for (int i = 0; i < 32; i++) {
		if ((edx_ext_features[i].mask & _edx) != 0) {
			printf("%s ", edx_ext_features[i].shorthand);
		}
	}

	puts("\n");
}

int main()
{
	puts("cpuidentifier " VERSION " by pala\n");

	if (!is_cpuid_supported()) {
		puts("cpuid is not supported");
		return 0;
	}

	vendor();
	proc_info_feature_bits();
	extended_features();

	return 0;
}

#endif