Creative Commons Attribution 4.0 International License |cc_by_40_logo|.
Yu Changyuan yuchangyuan
brabect1
/ sta_cdc_paths.rst
Last active
May 6, 2025 07:43
Timing constraints for clock-domain crossings. #sta #cdc
brabect1
/ coding_rtl_for_phys_impl.rst
Last active
December 14, 2024 03:38
Tips for physical implementation friendly RTL design. #sta #rtl
Quite a few digital design engineers limit their activities to architecture design and RTL coding. Missing first hand experience with later design phases is then easily detected by how much their code and architecture complicates physical implementation. Areas where this surfaces most often are clock/reset schemes, clock domain crossings (CDC) and scan/DFT aspects.