Contains notes about the U200_100G_ether_duplex design transmitting bad Ethernet packets using the CMAC, discovered running the cmac_loopback_test program.
Related:
- 000034731 - AXI4-Stream Data FIFO - Data is not always output in packet mode for short 2 beat packets -Dropped packet seen with 100G Ethernet IP describes the symptoms.
- Determining AXI4-stream Data FIFO size, understanding Packet Mode? query about packet mode
- https://electronics.stackexchange.com/q/511965/101063 question about the xpm_vhdl library.
- Where in Vivado to check for module parameter/generics and status of hard blocks (RAMs, DSPs) how to check what parameters have been used.
- XPM_FIFO_AXIS documentation for Parameterized Macro: AXI Stream FIFO
The following is an example of the test passing:
$ cmac_ethernet/cmac_loopback_test -n 1:0
Link ready
Testing U200_100G_ether_duplex Tx port 1 Rx Port 0 with 9537 packet lengths (including FCS) from 64 to 9600 bytes
U200_100G_ether_duplex port 1 statistics (over 0.045 secs):
CYCLE_COUNT : 14566402
TX_TOTAL_PACKETS : 9537
TX_TOTAL_GOOD_PACKETS : 9537
TX_TOTAL_BYTES : 46082784
TX_TOTAL_GOOD_BYTES : 46082936
TX_PACKET_65_127_BYTES : 63
TX_PACKET_128_255_BYTES : 129
TX_PACKET_256_511_BYTES : 256
TX_PACKET_512_1023_BYTES : 512
TX_PACKET_1024_1518_BYTES : 495
TX_PACKET_1519_1522_BYTES : 4
TX_PACKET_1523_1548_BYTES : 26
TX_PACKET_1549_2047_BYTES : 499
TX_PACKET_2048_4095_BYTES : 2048
TX_PACKET_4096_8191_BYTES : 4096
TX_PACKET_8192_9215_BYTES : 1024
TX_PACKET_LARGE : 385
TX_UNICAST : 9537
RX_RSFEC_CW_INC : 882812
U200_100G_ether_duplex port 0 statistics (over 0.045 secs):
CYCLE_COUNT : 14566329
RX_TOTAL_PACKETS : 9537
RX_TOTAL_GOOD_PACKETS : 9537
RX_TOTAL_BYTES : 46082784
RX_TOTAL_GOOD_BYTES : 46082784
RX_PACKET_64_BYTES : 1
RX_PACKET_65_127_BYTES : 63
RX_PACKET_128_255_BYTES : 128
RX_PACKET_256_511_BYTES : 256
RX_PACKET_512_1023_BYTES : 512
RX_PACKET_1024_1518_BYTES : 495
RX_PACKET_1519_1522_BYTES : 4
RX_PACKET_1523_1548_BYTES : 26
RX_PACKET_1549_2047_BYTES : 499
RX_PACKET_2048_4095_BYTES : 2048
RX_PACKET_4096_8191_BYTES : 4096
RX_PACKET_8192_9215_BYTES : 1024
RX_PACKET_LARGE : 385
RX_UNICAST : 9537
RX_RSFEC_CW_INC : 882808
Total byte including FCS: 46082784
Loopback test: PASS
For the rest of the output, only recorded when a test failed, since is intermittent. Haven't attempted to record the failure rate.
The initial design which reports as User access build timestamp : CA34F4E0 - 25/04/2026 15:19:32.
DAC cable between ports 0 and 1.
Port 1 to 0 can fail:
$ cmac_ethernet/cmac_loopback_test -n 1:0
Link ready
Testing U200_100G_ether_duplex Tx port 1 Rx Port 0 with 9537 packet lengths (including FCS) from 64 to 9600 bytes
U200_100G_ether_duplex port 1 statistics (over 0.000 secs):
CYCLE_COUNT : 105883
TX_TOTAL_PACKETS : 18
TX_TOTAL_GOOD_PACKETS : 18
TX_TOTAL_BYTES : 1457
TX_TOTAL_GOOD_BYTES : 1305
TX_PACKET_64_BYTES : 1
TX_PACKET_65_127_BYTES : 17
TX_UNICAST : 18
RX_RSFEC_CW_INC : 6417
U200_100G_ether_duplex port 0 statistics (over 0.000 secs):
CYCLE_COUNT : 105819
RX_BAD_CODE : 9
RX_TOTAL_PACKETS : 19
RX_TOTAL_GOOD_PACKETS : 18
RX_TOTAL_BYTES : 1441
RX_TOTAL_GOOD_BYTES : 1305
RX_PACKET_64_BYTES : 1
RX_PACKET_65_127_BYTES : 17
RX_PACKET_128_255_BYTES : 1
RX_BAD_FCS : 1
RX_PACKET_BAD_FCS : 1
RX_UNICAST : 18
RX_RSFEC_CW_INC : 6413
Total byte including FCS: 1387
Loopback test: FAIL
0000:31:00.0 C2H channel 0 failure : Rx transfer_len=132, expected 78
Port 0 to 1 can fail:
$ cmac_ethernet/cmac_loopback_test -n 0:1
Link ready
Testing U200_100G_ether_duplex Tx port 0 Rx Port 1 with 9537 packet lengths (including FCS) from 64 to 9600 bytes
U200_100G_ether_duplex port 0 statistics (over 0.000 secs):
CYCLE_COUNT : 111580
TX_TOTAL_PACKETS : 9
TX_TOTAL_GOOD_PACKETS : 9
TX_TOTAL_BYTES : 764
TX_TOTAL_GOOD_BYTES : 612
TX_PACKET_64_BYTES : 1
TX_PACKET_65_127_BYTES : 8
TX_UNICAST : 9
RX_RSFEC_CW_INC : 6762
U200_100G_ether_duplex port 1 statistics (over 0.000 secs):
CYCLE_COUNT : 111520
RX_BAD_CODE : 9
RX_TOTAL_PACKETS : 10
RX_TOTAL_GOOD_PACKETS : 9
RX_TOTAL_BYTES : 748
RX_TOTAL_GOOD_BYTES : 612
RX_PACKET_64_BYTES : 1
RX_PACKET_65_127_BYTES : 8
RX_PACKET_128_255_BYTES : 1
RX_BAD_FCS : 1
RX_PACKET_BAD_FCS : 1
RX_UNICAST : 9
RX_RSFEC_CW_INC : 6759
Total byte including FCS: 685
Loopback test: FAIL
0000:31:00.0 C2H channel 1 failure : Rx transfer_len=132, expected 69
This added a AXI Stream Switch between the XDMA and CMAC ports, to allow loopback between the CMAC ports, without needing to use the XDMA to send/receive packets from software. For these tests the AXI Stream Switch is configured with the defaults to connect the CMAC ports to XDMA.
The design reports as User access build timestamp : 4C34ACD9 - 09/08/2026 10:51:25
Port 1 to 0 can fail:
$ cmac_ethernet/cmac_loopback_test -n 1:0
Device 0000:31:00.0 design U200_100G_ether_duplex routes updated
Waiting to link to be ready to receive.
Link ready (latched rx_status initial 0x000000D8 last 0x00000003)
Testing U200_100G_ether_duplex Tx port 1 Rx Port 0 with 9537 packet lengths (including FCS) from 64 to 9600 bytes
U200_100G_ether_duplex port 1 statistics (over 0.000 secs):
CYCLE_COUNT : 130248
TX_TOTAL_PACKETS : 22
TX_TOTAL_GOOD_PACKETS : 22
TX_TOTAL_BYTES : 1791
TX_TOTAL_GOOD_BYTES : 1639
TX_PACKET_64_BYTES : 1
TX_PACKET_65_127_BYTES : 21
TX_UNICAST : 22
RX_RSFEC_CW_INC : 7894
U200_100G_ether_duplex port 0 statistics (over 0.000 secs):
CYCLE_COUNT : 130240
RX_BAD_CODE : 9
RX_TOTAL_PACKETS : 23
RX_TOTAL_GOOD_PACKETS : 22
RX_TOTAL_BYTES : 1775
RX_TOTAL_GOOD_BYTES : 1639
RX_PACKET_64_BYTES : 1
RX_PACKET_65_127_BYTES : 21
RX_PACKET_128_255_BYTES : 1
RX_BAD_FCS : 1
RX_PACKET_BAD_FCS : 1
RX_UNICAST : 22
RX_RSFEC_CW_INC : 7894
Total byte including FCS: 1725
Loopback test: FAIL
0000:31:00.0 C2H channel 0 failure : Rx transfer_len=132, expected 82
Port 0 to 1 can fail:
$ cmac_ethernet/cmac_loopback_test -n 0:1
Waiting to link to be ready to receive.
Link ready (latched rx_status initial 0x000000C8 last 0x00000003)
Testing U200_100G_ether_duplex Tx port 0 Rx Port 1 with 9537 packet lengths (including FCS) from 64 to 9600 bytes
U200_100G_ether_duplex port 0 statistics (over 0.000 secs):
CYCLE_COUNT : 117883
TX_TOTAL_PACKETS : 16
TX_TOTAL_GOOD_PACKETS : 16
TX_TOTAL_BYTES : 1296
TX_TOTAL_GOOD_BYTES : 1144
TX_PACKET_64_BYTES : 1
TX_PACKET_65_127_BYTES : 15
TX_UNICAST : 16
RX_RSFEC_CW_INC : 7144
U200_100G_ether_duplex port 1 statistics (over 0.000 secs):
CYCLE_COUNT : 117678
RX_BAD_CODE : 9
RX_TOTAL_PACKETS : 17
RX_TOTAL_GOOD_PACKETS : 16
RX_TOTAL_BYTES : 1280
RX_TOTAL_GOOD_BYTES : 1144
RX_PACKET_64_BYTES : 1
RX_PACKET_65_127_BYTES : 15
RX_PACKET_128_255_BYTES : 1
RX_BAD_FCS : 1
RX_PACKET_BAD_FCS : 1
RX_UNICAST : 16
RX_RSFEC_CW_INC : 7132
Total byte including FCS: 1224
Loopback test: FAIL
0000:31:00.0 C2H channel 1 failure : Rx transfer_len=132, expected 76
This added a DRP bridge to allow access to the CMAC RDP interfaces (e.g. allow reading or changing the min/max receive packet lengths).
The design reports as User access build timestamp : 8434D48A - 16/08/2026 13:18:10
Port 1 to 0 can fail:
$ cmac_ethernet/cmac_loopback_test -n 0:1
Link ready
Testing U200_100G_ether_duplex Tx port 0 Rx Port 1 with 9537 packet lengths (including FCS) from 64 to 9600 bytes
U200_100G_ether_duplex port 0 statistics (over 0.000 secs):
CYCLE_COUNT : 127516
TX_TOTAL_PACKETS : 30
TX_TOTAL_GOOD_PACKETS : 30
TX_TOTAL_BYTES : 2507
TX_TOTAL_GOOD_BYTES : 2355
TX_PACKET_64_BYTES : 1
TX_PACKET_65_127_BYTES : 29
TX_UNICAST : 30
RX_RSFEC_CW_INC : 7728
U200_100G_ether_duplex port 1 statistics (over 0.000 secs):
CYCLE_COUNT : 127454
RX_BAD_CODE : 9
RX_TOTAL_PACKETS : 31
RX_TOTAL_GOOD_PACKETS : 30
RX_TOTAL_BYTES : 2491
RX_TOTAL_GOOD_BYTES : 2355
RX_PACKET_64_BYTES : 1
RX_PACKET_65_127_BYTES : 29
RX_PACKET_128_255_BYTES : 1
RX_BAD_FCS : 1
RX_PACKET_BAD_FCS : 1
RX_UNICAST : 30
RX_RSFEC_CW_INC : 7725
Total byte including FCS: 2449
Loopback test: FAIL
0000:31:00.0 C2H channel 1 failure : Rx transfer_len=132, expected 90
Port 1 to 0 can fail:
$ cmac_ethernet/cmac_loopback_test -n 1:0
Waiting to link to be ready to receive.
Link ready (latched rx_status initial 0x000000C8 last 0x00000003)
Testing U200_100G_ether_duplex Tx port 1 Rx Port 0 with 9537 packet lengths (including FCS) from 64 to 9600 bytes
U200_100G_ether_duplex port 1 statistics (over 0.000 secs):
CYCLE_COUNT : 135307
TX_TOTAL_PACKETS : 26
TX_TOTAL_GOOD_PACKETS : 26
TX_TOTAL_BYTES : 2141
TX_TOTAL_GOOD_BYTES : 1989
TX_PACKET_64_BYTES : 1
TX_PACKET_65_127_BYTES : 25
TX_UNICAST : 26
RX_RSFEC_CW_INC : 8201
U200_100G_ether_duplex port 0 statistics (over 0.000 secs):
CYCLE_COUNT : 135120
RX_BAD_CODE : 9
RX_TOTAL_PACKETS : 27
RX_TOTAL_GOOD_PACKETS : 26
RX_TOTAL_BYTES : 2125
RX_TOTAL_GOOD_BYTES : 1989
RX_PACKET_64_BYTES : 1
RX_PACKET_65_127_BYTES : 25
RX_PACKET_128_255_BYTES : 1
RX_BAD_FCS : 1
RX_PACKET_BAD_FCS : 1
RX_UNICAST : 26
RX_RSFEC_CW_INC : 8189
Total byte including FCS: 2079
Loopback test: FAIL
0000:31:00.0 C2H channel 0 failure : Rx transfer_len=132, expected 86
A System ILA was added to monitor the AXI stream transmit to the CMAC, and triggered on either the cmac_usplus_1_tx_ovfout or cmac_usplus_1_tx_unfout errors from the CMAC. This design identifies as User access build timestamp : B4356EB2 - 22/08/2026 22:58:50
Port 1 to 0 can fail, albeit seems to happen less often with this design:
$ cmac_ethernet/cmac_loopback_test -n 1:0
Link ready
Testing U200_100G_ether_duplex Tx port 1 Rx Port 0 with 9537 packet lengths (including FCS) from 64 to 9600 bytes
U200_100G_ether_duplex port 1 statistics (over 0.001 secs):
CYCLE_COUNT : 172225
TX_TOTAL_PACKETS : 65
TX_TOTAL_GOOD_PACKETS : 65
TX_TOTAL_BYTES : 6392
TX_TOTAL_GOOD_BYTES : 6240
TX_PACKET_64_BYTES : 1
TX_PACKET_65_127_BYTES : 63
TX_PACKET_128_255_BYTES : 1
TX_UNICAST : 65
RX_RSFEC_CW_INC : 10438
U200_100G_ether_duplex port 0 statistics (over 0.001 secs):
CYCLE_COUNT : 172158
RX_BAD_CODE : 9
RX_TOTAL_PACKETS : 66
RX_TOTAL_GOOD_PACKETS : 65
RX_TOTAL_BYTES : 6376
RX_TOTAL_GOOD_BYTES : 6240
RX_PACKET_64_BYTES : 1
RX_PACKET_65_127_BYTES : 63
RX_PACKET_128_255_BYTES : 2
RX_BAD_FCS : 1
RX_PACKET_BAD_FCS : 1
RX_UNICAST : 65
RX_RSFEC_CW_INC : 10434
Total byte including FCS: 6369
Loopback test: FAIL
0000:31:00.0 C2H channel 0 failure : Rx transfer_len=132, expected 125
The ILA capture when the above failure happened:
The ILA capture shows:
- The CMAC reported a transmit underflow error.
- The AXI stream has a packet with two beats, with one clock cycle between the beats. That explains why the CMAC reported a transmit underflow.
- Looking at the TKEEP shows 125 bytes, which matches the expected value reported for the failed test.
Port 0 to 1 can fail:
$ cmac_ethernet/cmac_loopback_test -n 0:1
Link ready
Testing U200_100G_ether_duplex Tx port 0 Rx Port 1 with 9537 packet lengths (including FCS) from 64 to 9600 bytes
U200_100G_ether_duplex port 0 statistics (over 0.000 secs):
CYCLE_COUNT : 94481
TX_TOTAL_PACKETS : 5
TX_TOTAL_GOOD_PACKETS : 5
TX_TOTAL_BYTES : 482
TX_TOTAL_GOOD_BYTES : 330
TX_PACKET_64_BYTES : 1
TX_PACKET_65_127_BYTES : 4
TX_UNICAST : 5
RX_RSFEC_CW_INC : 5726
U200_100G_ether_duplex port 1 statistics (over 0.000 secs):
CYCLE_COUNT : 94420
RX_BAD_CODE : 9
RX_TOTAL_PACKETS : 6
RX_TOTAL_GOOD_PACKETS : 5
RX_TOTAL_BYTES : 466
RX_TOTAL_GOOD_BYTES : 330
RX_PACKET_64_BYTES : 1
RX_PACKET_65_127_BYTES : 4
RX_PACKET_128_255_BYTES : 1
RX_BAD_FCS : 1
RX_PACKET_BAD_FCS : 1
RX_UNICAST : 5
RX_RSFEC_CW_INC : 5722
Total byte including FCS: 399
Loopback test: FAIL
0000:31:00.0 C2H channel 1 failure : Rx transfer_len=132, expected 65
The ILA capture when the above failure happened:
The ILA capture shows:
- The CMAC reported a transmit underflow error.
- The AXI stream has a packet with two beats, with one clock cycle between the beats. That explains why the CMAC reported a transmit underflow.
- Looking at the TKEEP shows 65 bytes, which matches the expected value reported for the failed test.
The actual packet length on failure seems to be between 65 and 128 bytes, albeit haven't keep a note of every failure. When checked on the System ILA have allways seen:
- TKEEP matching the expected value reported by the loopback test.
- Two beats in a packet, with a clock cycle between them.
- Transmit underflow reported by the CMAC.
This does match the issue in 000034731 - AXI4-Stream Data FIFO - Data is not always output in packet mode for short 2 beat packets -Dropped packet seen with 100G Ethernet IP:
Description
When the AXI4-Stream Data FIFO is configured to be both asynchronous and in packet mode, short two beat packets can occasionally be output with a clock cycle gap between the beats.
If used with a block that requires data to be presented as full packet without any gap such as the 100G Ethernet IP (CMAC), this can cause the packet to be corrupted.
And the occasionally matches the observed intermittent failure.
The AXI-4-Stream Data FIFO's used for the CMAC transmit are configured using the following. They were configured in the block diagram, and this shows what was written by write_project_tcl:
# Create instance: axis_data_fifo_0, and set properties
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
set_property -dict [list \
CONFIG.FIFO_DEPTH {1024} \
CONFIG.FIFO_MODE {2} \
CONFIG.IS_ACLK_ASYNC {1} \
] $axis_data_fifo_0
# Create instance: axis_data_fifo_1, and set properties
set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
set_property -dict [list \
CONFIG.FIFO_DEPTH {1024} \
CONFIG.FIFO_MODE {2} \
CONFIG.IS_ACLK_ASYNC {1} \
] $axis_data_fifo_1While from the product guide for AXI4-Stream Infrastructure IP Suite LogiCORE IP Product Guide (PG085) can't seem to find a definition of FIFO_MODE, the ipshared/e33d/hdl/axis_data_fifo_v2_0_rfs.v file has:
// +---------------------------------------------------------------------------------------------------------------------+
// | PACKET_FIFO | String | Allowed values: false, true. Default value = false. |
// |---------------------------------------------------------------------------------------------------------------------|
// | |
// | "true"- Enables Packet FIFO mode |
// | "false"- Disables Packet FIFO mode |
localparam LP_PACKET_FIFO = C_FIFO_MODE == 2 ? "true" : "false";Which confirms a FIFO_MODE of 2 is Packet FIFO Mode
The design is rev 02 plus a System ILA on each side of the transmit packet FIFOs, which identifies as User access build timestamp : E4352DB1 - 28/08/2026 18:54:49.
The initial implementation of cmac_switch_test, using a fixed frame size of 1518 bytes runs successfully when using a DAC cable between both ports, and running two instances of the test each a different direction:
[mr_halfword@haswell-alma release]$ cmac_ethernet/cmac_switch_test -n 1:0 -p 1-4 -l -r 100000 -s
Device 0000:31:00.0 design U200_100G_ether_duplex routes updated
Waiting to link to be ready to receive. Press Ctrl-C to abort.
Link ready
Waiting 2 seconds after link came up for switch to accept packets (latched rx_status initial 0x000000D8 last 0x00000003)
Bit rate on interface to injection switch = 100000 (Mbps)
Requested bit rate to be generated on each switch port under test = 100000.00 (Mbps)
Not limiting frame rate, as bit-rate on interface to injection switch doesn't exceed the total across all switch ports under test
Writing per-port counts to 20260829T155652_per_port_counts_linux.csv
Using design U200_100G_ether_duplex device 0000:31:00.0 Tx port 1 Rx port 0
Test interval = 10 (secs)
Frame debug enabled = No
Expect CMAC loopback = Yes
Disable CMAC port statistics = Yes
Press Ctrl-C to stop test at end of next test interval
15:57:04.740
Tx Test Rx Test Rx Unexpected Rx Flooded Rx Other missed frames tx rate (Hz) per port Mbps
10836535 10836486 0 0 0 0 1083653.5 3341.99
Summary of missed frames : '.' none missed 'S' some missed 'A' all missed
Source Destination ports --->
port
1234
1 ...
2 . ..
3 .. .
4 ...
Total test intervals with failures = 0
15:57:14.740
Tx Test Rx Test Rx Unexpected Rx Flooded Rx Other missed frames tx rate (Hz) per port Mbps
10659628 10659628 0 0 0 0 1065962.8 3287.43
Summary of missed frames : '.' none missed 'S' some missed 'A' all missed
Source Destination ports --->
port
1234
1 ...
2 . ..
3 .. .
4 ...
Total test intervals with failures = 0
<<snip>>>
16:10:14.740
Tx Test Rx Test Rx Unexpected Rx Flooded Rx Other missed frames tx rate (Hz) per port Mbps
10483726 10483727 0 0 0 0 1048372.6 3233.18
Summary of missed frames : '.' none missed 'S' some missed 'A' all missed
Source Destination ports --->
port
1234
1 ...
2 . ..
3 .. .
4 ...
Total test intervals with failures = 0
^C
16:10:24.740
Tx Test Rx Test Rx Unexpected Rx Flooded Rx Other missed frames tx rate (Hz) per port Mbps
10650830 10650829 0 0 0 0 1065083.0 3284.72
Summary of missed frames : '.' none missed 'S' some missed 'A' all missed
Source Destination ports --->
port
1234
1 ...
2 . ..
3 .. .
4 ...
Total test intervals with failures = 0
Max pending rx frames = 5 out of 276
[mr_halfword@haswell-alma release]$ cmac_ethernet/cmac_switch_test -n 0:1 -p 1-4 -l -r 100000 -s
Waiting to link to be ready to receive. Press Ctrl-C to abort.
Link ready
Waiting 2 seconds after link came up for switch to accept packets (latched rx_status initial 0x000000C8 last 0x00000003)
Bit rate on interface to injection switch = 100000 (Mbps)
Requested bit rate to be generated on each switch port under test = 100000.00 (Mbps)
Not limiting frame rate, as bit-rate on interface to injection switch doesn't exceed the total across all switch ports under test
Writing per-port counts to 20260829T155654_per_port_counts_linux.csv
Using design U200_100G_ether_duplex device 0000:31:00.0 Tx port 0 Rx port 1
Test interval = 10 (secs)
Frame debug enabled = No
Expect CMAC loopback = Yes
Disable CMAC port statistics = Yes
Press Ctrl-C to stop test at end of next test interval
15:57:06.811
Tx Test Rx Test Rx Unexpected Rx Flooded Rx Other missed frames tx rate (Hz) per port Mbps
10284179 10284130 0 0 0 0 1028417.9 3171.64
Summary of missed frames : '.' none missed 'S' some missed 'A' all missed
Source Destination ports --->
port
1234
1 ...
2 . ..
3 .. .
4 ...
Total test intervals with failures = 0
15:57:16.811
Tx Test Rx Test Rx Unexpected Rx Flooded Rx Other missed frames tx rate (Hz) per port Mbps
10761186 10761186 0 0 0 0 1076118.6 3318.75
Summary of missed frames : '.' none missed 'S' some missed 'A' all missed
Source Destination ports --->
port
1234
1 ...
2 . ..
3 .. .
4 ...
Total test intervals with failures = 0
<<snip>>
16:10:06.811
Tx Test Rx Test Rx Unexpected Rx Flooded Rx Other missed frames tx rate (Hz) per port Mbps
10510734 10510735 0 0 0 0 1051073.4 3241.51
Summary of missed frames : '.' none missed 'S' some missed 'A' all missed
Source Destination ports --->
port
1234
1 ...
2 . ..
3 .. .
4 ...
Total test intervals with failures = 0
16:10:16.811
Tx Test Rx Test Rx Unexpected Rx Flooded Rx Other missed frames tx rate (Hz) per port Mbps
10531996 10531995 0 0 0 0 1053199.6 3248.07
Summary of missed frames : '.' none missed 'S' some missed 'A' all missed
Source Destination ports --->
port
1234
1 ...
2 . ..
3 .. .
4 ...
Total test intervals with failures = 0
^C
16:10:26.811
Tx Test Rx Test Rx Unexpected Rx Flooded Rx Other missed frames tx rate (Hz) per port Mbps
10990102 10990102 0 0 0 0 1099010.2 3389.35
Summary of missed frames : '.' none missed 'S' some missed 'A' all missed
Source Destination ports --->
port
1234
1 ...
2 . ..
3 .. .
4 ...
Total test intervals with failures = 0
Max pending rx frames = 5 out of 276
And a sample of statistics while the test was running:
16:10:18.109 collection number 81
U200_100G_ether_duplex port 0 statistics (over 10.000 secs):
CYCLE_COUNT : 3222629631
TX_TOTAL_PACKETS : 10562792
TX_TOTAL_GOOD_PACKETS : 10562792
TX_TOTAL_BYTES : 16076569424
TX_TOTAL_GOOD_BYTES : 16076569424
TX_PACKET_1519_1522_BYTES : 10562792
TX_UNICAST : 10562792
TX_VLAN : 10562792
RX_TOTAL_PACKETS : 10562666
RX_TOTAL_GOOD_PACKETS : 10562666
RX_TOTAL_BYTES : 16076377804
RX_TOTAL_GOOD_BYTES : 16076377652
RX_PACKET_1519_1522_BYTES : 10562666
RX_UNICAST : 10562666
RX_VLAN : 10562666
RX_RSFEC_CW_INC : 195310887
U200_100G_ether_duplex port 1 statistics (over 10.000 secs):
CYCLE_COUNT : 3222629626
TX_TOTAL_PACKETS : 10562667
TX_TOTAL_GOOD_PACKETS : 10562667
TX_TOTAL_BYTES : 16076379174
TX_TOTAL_GOOD_BYTES : 16076379174
TX_PACKET_1519_1522_BYTES : 10562667
TX_UNICAST : 10562667
TX_VLAN : 10562667
RX_TOTAL_PACKETS : 10562792
RX_TOTAL_GOOD_PACKETS : 10562792
RX_TOTAL_BYTES : 16076569424
RX_TOTAL_GOOD_BYTES : 16076569424
RX_PACKET_1519_1522_BYTES : 10562792
RX_UNICAST : 10562792
RX_VLAN : 10562792
RX_RSFEC_CW_INC : 195310887