Chester-Gillon

0. Introduction

Contains notes about the U200_100G_ether_duplex design transmitting bad Ethernet packets using the CMAC, discovered running the cmac_loopback_test program.

Related:

1. 000034731 - AXI4-Stream Data FIFO - Data is not always output in packet mode for short 2 beat packets -Dropped packet seen with 100G Ethernet IP describes the symptoms.
2. Determining AXI4-stream Data FIFO size, understanding Packet Mode? query about packet mode
3. https://electronics.stackexchange.com/q/511965/101063 question about the xpm_vhdl library.
4. [Where in Vivado to check for module parameter/generics and status of hard blocks (RAMs, DSPs)](https://adaptivesupport.amd.com/s/question/0D54U000089iFOxSAM/where-in-vivado-to-check-for-module-paramet

Chester-Gillon

Xilinx Alveo U280 PCIe Accelerator Card 8GB HBM2 PCIe QSFP28 Tested/working is a second hand card.

The card is EOL, Alveo™ U280 Support and Downloads - Latest Version has support resources.

In Vivado 2026.2 the XCU280-FSVH2892-2L-E part number wasn't available after installing Alveo support.

The AMD 000036719 - 2024.1 - Failure to add the board file of Alveo U280 into Vivado says:

From Vivado 2024.1 on, some part numbers for an Alveo U280 board are removed because they are EOL.

Added Alveo cards support to a Vivado 2023.2 installation and could:

Chester-Gillon

0. Introduction

Contains notes about processor stress testing, following the issue in How can I adjust the airflow in a HP Z6 G4 to stop a PCIe card overheating? where a HP Z6 G4 locked up, when it looked like one core got to the critical temperature.

Running the tests on AlmaLinux 8.10 with kernel 4.18.0-553.155.1.el8_10.x86_64.

1. Downloads

1.1. FIRESTARTER

Chester-Gillon

1. State when found the issue

U200_100G_ether_duplex just re-built with Viado 2026.1

Sensor values:

linux@DESKTOP-BVUMP11:~/fpga_sio/software_tests/eclipse_project/bin/release> xilinx_sensors/display_sensor_values 
Opening device 0000:31:00.0 (10ee:903f) with IOMMU group 82
Enabled bus master for 0000:31:00.0
Displaying SYSMON values for design U200_100G_ether_duplex in PCI device 0000:31:00.0 IOMMU group 82:

Chester-Gillon

0. Introduction

Contains notes about trying to use Vivado 2026.1 with the no-cost tiers, initially trying to rebuild projects created in previous versions of Vivado.

1. Problems with device family usage

Initially had issues trying to get use free tiers for both BASIC and ALVEO, as described below

1.1. First installation attempt

Chester-Gillon

0. Introduction

Contains notes about a Logsys XILINX Kintex-7 FPGA PCIe development Board

Logsys XILINX Kintex7 Kintex-7 FPGA PCIe development Board FOR PARTS OR REPAIR is the ebay listing which contained:

Doesn't show up the interface in the PCI device list ( should shoup as 0x10EE 0x7011 ) . Leds show activity .

Looking at the pictures in the listing was powered up in a PCI with JP1 set to JTAG for the configuration mode, so that might explain the lack of enumerating as a PCIe endpoint.

LOGSYS_Kintex7_FPGA_Board.pdf is a manual found, in Hungarian. Has schematics so should allow constraints to be determined.

Chester-Gillon

0. Introduction

Contains notes about Inspur XC7K480T FPGA development Board acceleration Card YPCB-00338-1P1

YPCB-00338-1P1 FPGA board reverse engineering has reversed engineered information for the same YPCB-00338-1P1 PCB revision as purchased.

ypcb_00338_1p1_hack has constraints and an example project.

Chester-Gillon

0. Introduction

Contains notes about XCKU5P Board FPGA Core Board Onboard 128Mbit FLASH FMC QSFP28 100G Port PCIE3.0

The board picture above show the Micron DDR4 devices have a FBGA Code of D9WFM which is MT40A512M16LY-062E-IT-E which is a 8Gb component. The XCKU5P-FFVB676.pdf schematic gives the part number of U1 and U11 as MT40A512M16LY-062E-IT-E, which matches. The XCKU5P-FFVB676.rar contained a datasheet named MT40A512M16LY-062E ITE.pdf, but was actually for 4Gb components. For now, assume MT40A512M16LY-062E-IT-E is the correct DDR4 part

Read the Device DNA over JTAG and using AMD Device Lookup reports:

Package-PinFFVB676

Device

XCKU5P

Chester-Gillon

nfmac10g

10g-low-latency-ethernet

Chester-Gillon

How to import MYIR presets

home/mr_halfword/Documents/MPSOC2019.1_DVD_V1.1/01-Document/UserManual/English/MYD-CZU3EG-4EV Tutorial.pdf was created using Vivado 2019.1. The "4.1 Create a Block Design" section selects the Presets option on the "Re-customize IP" dialog to import the configuration for the MYC-CZU4EV module.

However, in Vivado 2020.1 the Presets options is not present on the dialog.

https://www.xilinx.com/support/answers/75467.html is 'Zynq UltraScale+ MPSoC, Vivado 2020.1 - Processing System "Presets" option temporarily removed'