My answer for https://hdlbits.01xz.net/wiki/Count_clock

top_clock.sv

module counter #(parameter BGN, parameter END, parameter LOAD=0) (
    input clk,
    input reset,
    input ena,
    output c,
    output [7:0] d
	);
    logic c0, c1;
    assign c0 = (d[3:0] == 4'd9);
	assign c = ena & (d == 8'(END)); // AND `ena` here to make sure `c` is set when previous digit is counting.
        
    always @(posedge clk) begin
        if (reset) begin
            d <= 8'(LOAD);
        end else if (ena) begin
            if (c) begin
                d <= 8'(BGN);
			end else begin
                d[3:0] <= c0 ? 4'd0 : d[3:0] + 1'b1;
                if (c0) begin
                    d[7:4] <= d[7:4] + 1'b1;
                end
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    
    logic ss_c, mm_c;
    
    counter #(.BGN('h00), .END('h59)) u_ss(.clk(clk), .reset(reset), .ena(ena), .c(ss_c), .d(ss));
    counter #(.BGN('h00), .END('h59)) u_mm(.clk(clk), .reset(reset), .ena(ss_c), .c(mm_c), .d(mm));
    counter #(.BGN('h01), .END('h12), .LOAD('h12)) u_hh(.clk(clk), .reset(reset), .ena(mm_c), .c('b0), .d(hh));
        
    always @(posedge clk) begin
        if (reset) begin
           	pm <= 1'b0;
        end else if (hh == 'h11 & mm_c) begin
            pm <= ~pm;
        end
    end
endmodule