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// Problem: https://hdlbits.01xz.net/wiki/Fsm_serialdp.
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
parameter START = 4'd0, BIT0 = 4'd1, BIT1 = 4'd2, BIT2 = 4'd3, BIT3 = 4'd4,
BIT4 = 4'd5, BIT5 = 4'd6, BIT6 = 4'd7, BIT7 = 4'd8, PARITY = 4'd9,
// Problem: https://hdlbits.01xz.net/wiki/Fsm_serialdata
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
parameter START = 4'd0, BIT0 = 4'd1, BIT1 = 4'd2, BIT2 = 4'd3, BIT3 = 4'd4,
BIT4 = 4'd5, BIT5 = 4'd6, BIT6 = 4'd7, BIT7 = 4'd8, STOP = 4'd9,
module counter #(parameter BGN, parameter END, parameter LOAD=0) (
input clk,
input reset,
input ena,
output c,
output [7:0] d
);
logic c0, c1;
assign c0 = (d[3:0] == 4'd9);
assign c = ena & (d == 8'(END)); // AND `ena` here to make sure `c` is set when previous digit is counting.
@GaryLee
GaryLee / ece241_2014_q1c.sv
Created May 13, 2025 06:52
The answer of HDLBits
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
logic c;
assign {c, s} = a + b;
assign overflow = ~(a[7] ^ b[7]) & (c ^ s[7]);
endmodule
@GaryLee
GaryLee / excel_tools.py
Last active May 4, 2025 15:20
Access data frame in Excel's way.
#!python
# coding: utf-8
import os
import string
import pandas as pd
pd.set_option('future.no_silent_downcasting', True)
class Excel:
ENGINE = 'xlrd' # Specify the engine for reading .xls files
@GaryLee
GaryLee / set_ics_permanently.bat
Created April 30, 2025 03:18
How to enable ICS on windows permanently?
REM To enable ICS for interface. Set the ICS from following GUI:
REM Settings -> Network & Internet -> Open Network & Internet settings -> Change adapter options
REM -> Properties -> Sharing
REM -> Allow other network users to connect through this computer’s Internet connection.
REM After setting above option correctly, run following commands in the terminal with Administrator Privilege.
sc config SharedAccess start=auto
reg add HKLM\Software\Microsoft\Windows\CurrentVersion\SharedAccess /v EnableRebootPersistConnection /t REG_DWORD /d 1
@GaryLee
GaryLee / circular_buffer.h
Created March 8, 2025 15:06
The circular buffer class in c++.
/**
* @file circular_buffer.h The circular buffer.
*/
#ifndef CIRCULAR_BUFFER_H
#define CIRCULAR_BUFFER_H
/**
* @brief The circular buffer class.
*/
@GaryLee
GaryLee / lpf_zdomain.py
Created October 28, 2024 07:10
How to calculate the coefficient of low-pass filter of z-domain?
#!python
from math import pi
# The first-order low-pass filter has following transfer function of s-domain
# H(s) = a / (s + a).
# Its pole is s = −a, and the pole in digital filter will be z = e^−aT
# Therefore the H(z) is (1 - e^-aT)*z / ( z - e^-aT )
FREQ_SAMPLING = 50e3
TIME_SAMPLING = 1 / FREQ_SAMPLING
#!python
# coding: utf-8
import numpy as np
import matplotlib.pyplot as plt
dt = 0.1 # The time interval of sampling.
# Make input data with some white noise.
z = np.arange(1, 100, dt)
@GaryLee
GaryLee / make_reg_svg.py
Created August 31, 2024 10:07
A example to generate register definition with drawsvg module.
#!python
# -*- coding: utf-8 -*-
import drawsvg as draw
# Reference: https://github.com/cduck/drawsvg/blob/master/docs/index.md
reg = {
'31': 'EN',