EPYC/Turin 64-Core

gistfile1.txt

AMD Eng Sample

Processor                                     [AMD Eng Sample: 100-000001247-12]
|- PPIN#                                                      [  831a26b354c03b]
|- Architecture                                                     [Zen5/Turin]
|- Vendor ID                                                      [AuthenticAMD]
|- Firmware                                                        [ 94.115.0-7]
|- Microcode                                                        [0x0b001016]
|- Signature                                                           [  BF_01]
|- Stepping                                                            [      0]
|- Online CPU                                                          [128/128]
|- Base Clock                                                          [100.000]
|- Frequency            (MHz)                      Ratio                        
                 Min    600.00                    <   6 >                       
                 Max   1900.00                    <  19 >                       
|- Factory                                                             [100.000]
                       1900                       [  19 ]                       
|- Performance                                                                  
                 TGT   1500.00                    <  15 >                       
   |- Boost                                                            [   LOCK]
                 XFR   3300.00                    [  33 ]                       
                 CPB   3200.00                    [  32 ]                       
   |- P-State                                                                   
                 P1    1700.00                    <  17 >                       
                 P2    1500.00                    <  15 >                       
|- Uncore                                                              [   LOCK]
                 CLK   2400.00                    [  24 ]                       
                 MEM   2400.00                    [  24 ]                       
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y] 
|- AVX512-F     [Y]    AVX512-DQ [Y]  AVX512-IFMA [Y]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [Y]    AVX512-BW [Y]   AVX512-VL [Y] 
|- AVX512-VBMI  [Y] AVX512-VBMI2 [Y]  AVX512-VNNI [Y]  AVX512-ALG [Y] 
|- AVX512-VPOP  [Y] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [Y] 
|- AVX512-BF16  [Y] AVX-VNNI-VEX [Y]    AVX-FP128 [N]   AVX-FP256 [N] 
|- BMI1/BMI2  [Y/Y]         CLWB [Y]      CLFLUSH [Y] CLFLUSH-OPT [Y] 
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- MMX/Ext    [Y/Y] MON/MWAITX [Y/Y]        MOVBE [Y]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y] 
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/Y]      SSE4.2 [Y] 
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [Y]        UMIP [Y] 
|- VAES         [Y]   VPCLMULQDQ [Y]   PREFETCH/W [Y]       LZCNT [Y] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- 100 MHz multiplier Control                            100MHzSteps   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- Advanced Virtual Interrupt Controller                        AVIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- LOCK prefix to read CR8                                    AltMov   [Capable]
|- Clear Zero Instruction                                     CLZERO   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Capable]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Collaborative Processor Performance Control                  CPPC   [Capable]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Missing]
|- CPL Qualified Debug Store                                  DS-CPL   [Missing]
|- 64-Bit Debug Store                                         DTES64   [Missing]
|- Fast Short REP CMPSB|SCASB                                   FSRC   [Capable]
|- Fast Short REP MOVSB                                         FSRM   [Capable]
|- Fast Short REP STOSB                                         FSRS   [Capable]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                           FMA4   [Missing]
|- Fused Multiply Add                                            FMA   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Hyper-Threading Technology                                    HTT   [Capable]
|- Hardware P-state control                                      HwP   [Capable]
|- Instruction Based Sampling                                    IBS   [Capable]
|- Instruction INVLPGB                                       INVLPGB   [Capable]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Memory Bandwidth Enforcement                                  MBE   [Capable]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Instruction MCOMMIT                                       MCOMMIT   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- No-Execute Page Protection                                     NX   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- OS Visible Work-around                                       OSVW   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Missing]
|- Process Context Identifiers                                  PCID   [Capable]
|- Perfmon and Debug Capability                                 PDCM   [Missing]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- PREFETCHIT0/1 Instructions                              PREFETCHI   [Missing]
|- Resource Director Technology/PQE                      RDT-A | PQE   [Capable]
|- Resource Director Technology/PQM                      RDT-M | PQM   [Capable]
|- Read Processor Register at User level                       RDPRU   [Capable]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Missing]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Trailing Bit Manipulation                                     TBM   [Missing]
|- Translation Cache Extension                                   TCE   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Missing]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Missing]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Capable]
|- Extended xAPIC Support                                     x2APIC   [ x2APIC]
|- AVIC controller for x2APIC                                 x2AVIC   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Missing]
|- Extended Operation Support                                    XOP   [Missing]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
   |- IBRS Always-On preferred by processor                            [ Unable]
   |- IBRS preferred over software solution                            [Capable]
   |- IBRS provides same speculation limits                            [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Selective Branch Predictor Barrier                           SBPB   [ Unable]
|- Single Thread Indirect Branch Predictor                     STIBP   [ Enable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
   |- SSBD use VIRT_SPEC_CTRL register                                 [ Unable]
   |- SSBD not needed on this processor                                [ Unable]
|- No Speculative Return Stack Overflow                      SRSO_NO   [ Unable]
   |- No SRSO at the User-Kernel boundary                              [ Unable]
|- No Branch Type Confusion                                   BTC_NO   [Capable]
|- BTC on Non-Branch instruction                            BTC-NOBR   [ Unable]
|- Limited Early Redirect Window                            AGENPICK   [ Unable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [Capable]
|- Arch - Enhanced Predictive Store Forwarding                  EPSF   [Capable]
|- Arch - Cross Processor Information Leak                XPROC_LEAK   [ Unable]
Security Features                                                               
|- CET Shadow Stack features                                  CET-SS   [Capable]
|- Secure Init and Jump with Attestation                      SKINIT   [Capable]
|- Secure Encrypted Virtualization                               SEV   [Capable]
|- SEV - Encrypted State                                      SEV-ES   [Capable]
|- SEV - Secure Nested Paging                                SEV-SNP   [Capable]
|- Guest Mode Execute Trap                                      GMET   [Capable]
|- Supervisor Shadow Stack                                       SSS   [Capable]
|- VM Permission Levels                                         VMPL   [Capable]
|- VMPL Supervisor Shadow Stack                             VMPL-SSS   [Capable]
|- Secure Memory Encryption                                      SME   [Capable]
|- Transparent SME                                              TSME   [Disable]
|- Secure Multi-Key Memory Encryption                         SME-MK   [Capable]
|- DRAM Data Scrambling                                    Scrambler   [ Enable]
                                                                                
Technologies                                                                    
|- Instruction Cache Unit                                                       
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   < ON>
|- Cache Prefetchers                                                            
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L1 Stride Prefetcher                                     L1 Stride   < ON>
   |- L1 Region Prefetcher                                     L1 Region   < ON>
   |- L1 Burst Prefetch Mode                                    L1 Burst   < ON>
   |- L2 Stream HW Prefetcher                                  L2 Stream   < ON>
   |- L2 Up/Down Prefetcher                                   L2 Up/Down   < ON>
|- System Management Mode                                       SMM-Lock   [ ON]
|- Simultaneous Multithreading                                       SMT   [ ON]
|- PowerNow!                                                         CnQ   [ ON]
|- Core C-States                                                     CCx   [ ON]
|- Core Performance Boost                                            CPB   < ON>
|- Watchdog Timer                                                    WDT   < ON>
|- Virtualization                                                    SVM   [ ON]
   |- I/O MMU                                                      AMD-V   [ ON]
   |- Version                                                     [         0.1]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [  2]
|- Counters:          General                   Fixed                           
|           {  6,  6, 16 } x 48 bits            3 x 64 bits                     
|- Enhanced Halt State                                           C1E       <OFF>
|- C2 UnDemotion                                                 C2U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
|- Core C6 State                                                 CC6       < ON>
|- Package C6 State                                              PC6       < ON>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x813 ]
|- ACPI Processor C-States                                      _CST   [      2]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     1     2     0     0     0     0     0     0              
   |- Monitor-Mwait Extensions                                   EMX   [Capable]
   |- Interrupt Break-Event                                      IBE   [Capable]
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- TSC for Performance Profiling                                       [Missing]
|- Data Fabric Performance Counter                                     [Capable]
|- Core Performance Counter                                            [Capable]
|- Processor Performance Control                                _PCT   [ Enable]
|- Performance Supported States                                 _PSS   [      3]
|- Performance Present Capabilities                             _PPC   [      0]
|- Continuous Performance Control                               _CPC   [Missing]
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax [ 49: 95 C]
|- CPPC Energy Preference                                        EPP   [Capable]
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Capable]
|- Thermal Monitor 1                                             TTP   [ Enable]
|- Thermal Monitor 2                                             HTC   [ Enable]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   < Enable>
   |- Power Limit                                                PL1   <  360 W>
   |- Time Window                                                TW1   <   0 ns>
   |- Power Limit                                                PL2   <  400 W>
   |- Time Window                                                TW2   <   0 ns>
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Package Power Tracking                                        PPT   [Missing]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
|- Package Thermal Point                                                        
   |- Thermal Monitor Trip                                     Limit   [  115 C]
   |- HTC Temperature Limit                                    Limit   [  127 C]
   |- HTC Temperature Hysteresis                           Threshold   [    0 C]
|- Units                                                                        
   |- Power                                               watt   [      Missing]
   |- Energy                                             joule   [  0.000015259]
   |- Window                                            second   [  0.000976562]

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID CCD CCX ID/ID L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP    0   0  0   0  0      32  8        48 12      1024 16 i  262144 16w 
001:  0    2   0  0   1  0      32  8        48 12      1024 16 i  262144 16w 
002:  0    4   0  0   2  0      32  8        48 12      1024 16 i  262144 16w 
003:  0    6   0  0   3  0      32  8        48 12      1024 16 i  262144 16w 
004:  0    8   0  0   4  0      32  8        48 12      1024 16 i  262144 16w 
005:  0   10   0  0   5  0      32  8        48 12      1024 16 i  262144 16w 
006:  0   12   0  0   6  0      32  8        48 12      1024 16 i  262144 16w 
007:  0   14   0  0   7  0      32  8        48 12      1024 16 i  262144 16w 
008:  0   64   4  4  32  0      32  8        48 12      1024 16 i  262144 16w 
009:  0   66   4  4  33  0      32  8        48 12      1024 16 i  262144 16w 
010:  0   68   4  4  34  0      32  8        48 12      1024 16 i  262144 16w 
011:  0   70   4  4  35  0      32  8        48 12      1024 16 i  262144 16w 
012:  0   72   4  4  36  0      32  8        48 12      1024 16 i  262144 16w 
013:  0   74   4  4  37  0      32  8        48 12      1024 16 i  262144 16w 
014:  0   76   4  4  38  0      32  8        48 12      1024 16 i  262144 16w 
015:  0   78   4  4  39  0      32  8        48 12      1024 16 i  262144 16w 
016:  0   32   2  2  16  0      32  8        48 12      1024 16 i  262144 16w 
017:  0   34   2  2  17  0      32  8        48 12      1024 16 i  262144 16w 
018:  0   36   2  2  18  0      32  8        48 12      1024 16 i  262144 16w 
019:  0   38   2  2  19  0      32  8        48 12      1024 16 i  262144 16w 
020:  0   40   2  2  20  0      32  8        48 12      1024 16 i  262144 16w 
021:  0   42   2  2  21  0      32  8        48 12      1024 16 i  262144 16w 
022:  0   44   2  2  22  0      32  8        48 12      1024 16 i  262144 16w 
023:  0   46   2  2  23  0      32  8        48 12      1024 16 i  262144 16w 
024:  0   96   6  6  48  0      32  8        48 12      1024 16 i  262144 16w 
025:  0   98   6  6  49  0      32  8        48 12      1024 16 i  262144 16w 
026:  0  100   6  6  50  0      32  8        48 12      1024 16 i  262144 16w 
027:  0  102   6  6  51  0      32  8        48 12      1024 16 i  262144 16w 
028:  0  104   6  6  52  0      32  8        48 12      1024 16 i  262144 16w 
029:  0  106   6  6  53  0      32  8        48 12      1024 16 i  262144 16w 
030:  0  108   6  6  54  0      32  8        48 12      1024 16 i  262144 16w 
031:  0  110   6  6  55  0      32  8        48 12      1024 16 i  262144 16w 
032:  0   48   3  3  24  0      32  8        48 12      1024 16 i  262144 16w 
033:  0   50   3  3  25  0      32  8        48 12      1024 16 i  262144 16w 
034:  0   52   3  3  26  0      32  8        48 12      1024 16 i  262144 16w 
035:  0   54   3  3  27  0      32  8        48 12      1024 16 i  262144 16w 
036:  0   56   3  3  28  0      32  8        48 12      1024 16 i  262144 16w 
037:  0   58   3  3  29  0      32  8        48 12      1024 16 i  262144 16w 
038:  0   60   3  3  30  0      32  8        48 12      1024 16 i  262144 16w 
039:  0   62   3  3  31  0      32  8        48 12      1024 16 i  262144 16w 
040:  0  112   7  7  56  0      32  8        48 12      1024 16 i  262144 16w 
041:  0  114   7  7  57  0      32  8        48 12      1024 16 i  262144 16w 
042:  0  116   7  7  58  0      32  8        48 12      1024 16 i  262144 16w 
043:  0  118   7  7  59  0      32  8        48 12      1024 16 i  262144 16w 
044:  0  120   7  7  60  0      32  8        48 12      1024 16 i  262144 16w 
045:  0  122   7  7  61  0      32  8        48 12      1024 16 i  262144 16w 
046:  0  124   7  7  62  0      32  8        48 12      1024 16 i  262144 16w 
047:  0  126   7  7  63  0      32  8        48 12      1024 16 i  262144 16w 
048:  0   16   1  1   8  0      32  8        48 12      1024 16 i  262144 16w 
049:  0   18   1  1   9  0      32  8        48 12      1024 16 i  262144 16w 
050:  0   20   1  1  10  0      32  8        48 12      1024 16 i  262144 16w 
051:  0   22   1  1  11  0      32  8        48 12      1024 16 i  262144 16w 
052:  0   24   1  1  12  0      32  8        48 12      1024 16 i  262144 16w 
053:  0   26   1  1  13  0      32  8        48 12      1024 16 i  262144 16w 
054:  0   28   1  1  14  0      32  8        48 12      1024 16 i  262144 16w 
055:  0   30   1  1  15  0      32  8        48 12      1024 16 i  262144 16w 
056:  0   80   5  5  40  0      32  8        48 12      1024 16 i  262144 16w 
057:  0   82   5  5  41  0      32  8        48 12      1024 16 i  262144 16w 
058:  0   84   5  5  42  0      32  8        48 12      1024 16 i  262144 16w 
059:  0   86   5  5  43  0      32  8        48 12      1024 16 i  262144 16w 
060:  0   88   5  5  44  0      32  8        48 12      1024 16 i  262144 16w 
061:  0   90   5  5  45  0      32  8        48 12      1024 16 i  262144 16w 
062:  0   92   5  5  46  0      32  8        48 12      1024 16 i  262144 16w 
063:  0   94   5  5  47  0      32  8        48 12      1024 16 i  262144 16w 
064:  0    1   0  0   0  1      32  8        48 12      1024 16 i  262144 16w 
065:  0    3   0  0   1  1      32  8        48 12      1024 16 i  262144 16w 
066:  0    5   0  0   2  1      32  8        48 12      1024 16 i  262144 16w 
067:  0    7   0  0   3  1      32  8        48 12      1024 16 i  262144 16w 
068:  0    9   0  0   4  1      32  8        48 12      1024 16 i  262144 16w 
069:  0   11   0  0   5  1      32  8        48 12      1024 16 i  262144 16w 
070:  0   13   0  0   6  1      32  8        48 12      1024 16 i  262144 16w 
071:  0   15   0  0   7  1      32  8        48 12      1024 16 i  262144 16w 
072:  0   65   4  4  32  1      32  8        48 12      1024 16 i  262144 16w 
073:  0   67   4  4  33  1      32  8        48 12      1024 16 i  262144 16w 
074:  0   69   4  4  34  1      32  8        48 12      1024 16 i  262144 16w 
075:  0   71   4  4  35  1      32  8        48 12      1024 16 i  262144 16w 
076:  0   73   4  4  36  1      32  8        48 12      1024 16 i  262144 16w 
077:  0   75   4  4  37  1      32  8        48 12      1024 16 i  262144 16w 
078:  0   77   4  4  38  1      32  8        48 12      1024 16 i  262144 16w 
079:  0   79   4  4  39  1      32  8        48 12      1024 16 i  262144 16w 
080:  0   33   2  2  16  1      32  8        48 12      1024 16 i  262144 16w 
081:  0   35   2  2  17  1      32  8        48 12      1024 16 i  262144 16w 
082:  0   37   2  2  18  1      32  8        48 12      1024 16 i  262144 16w 
083:  0   39   2  2  19  1      32  8        48 12      1024 16 i  262144 16w 
084:  0   41   2  2  20  1      32  8        48 12      1024 16 i  262144 16w 
085:  0   43   2  2  21  1      32  8        48 12      1024 16 i  262144 16w 
086:  0   45   2  2  22  1      32  8        48 12      1024 16 i  262144 16w 
087:  0   47   2  2  23  1      32  8        48 12      1024 16 i  262144 16w 
088:  0   97   6  6  48  1      32  8        48 12      1024 16 i  262144 16w 
089:  0   99   6  6  49  1      32  8        48 12      1024 16 i  262144 16w 
090:  0  101   6  6  50  1      32  8        48 12      1024 16 i  262144 16w 
091:  0  103   6  6  51  1      32  8        48 12      1024 16 i  262144 16w 
092:  0  105   6  6  52  1      32  8        48 12      1024 16 i  262144 16w 
093:  0  107   6  6  53  1      32  8        48 12      1024 16 i  262144 16w 
094:  0  109   6  6  54  1      32  8        48 12      1024 16 i  262144 16w 
095:  0  111   6  6  55  1      32  8        48 12      1024 16 i  262144 16w 
096:  0   49   3  3  24  1      32  8        48 12      1024 16 i  262144 16w 
097:  0   51   3  3  25  1      32  8        48 12      1024 16 i  262144 16w 
098:  0   53   3  3  26  1      32  8        48 12      1024 16 i  262144 16w 
099:  0   55   3  3  27  1      32  8        48 12      1024 16 i  262144 16w 
100:  0   57   3  3  28  1      32  8        48 12      1024 16 i  262144 16w 
101:  0   59   3  3  29  1      32  8        48 12      1024 16 i  262144 16w 
102:  0   61   3  3  30  1      32  8        48 12      1024 16 i  262144 16w 
103:  0   63   3  3  31  1      32  8        48 12      1024 16 i  262144 16w 
104:  0  113   7  7  56  1      32  8        48 12      1024 16 i  262144 16w 
105:  0  115   7  7  57  1      32  8        48 12      1024 16 i  262144 16w 
106:  0  117   7  7  58  1      32  8        48 12      1024 16 i  262144 16w 
107:  0  119   7  7  59  1      32  8        48 12      1024 16 i  262144 16w 
108:  0  121   7  7  60  1      32  8        48 12      1024 16 i  262144 16w 
109:  0  123   7  7  61  1      32  8        48 12      1024 16 i  262144 16w 
110:  0  125   7  7  62  1      32  8        48 12      1024 16 i  262144 16w 
111:  0  127   7  7  63  1      32  8        48 12      1024 16 i  262144 16w 
112:  0   17   1  1   8  1      32  8        48 12      1024 16 i  262144 16w 
113:  0   19   1  1   9  1      32  8        48 12      1024 16 i  262144 16w 
114:  0   21   1  1  10  1      32  8        48 12      1024 16 i  262144 16w 
115:  0   23   1  1  11  1      32  8        48 12      1024 16 i  262144 16w 
116:  0   25   1  1  12  1      32  8        48 12      1024 16 i  262144 16w 
117:  0   27   1  1  13  1      32  8        48 12      1024 16 i  262144 16w 
118:  0   29   1  1  14  1      32  8        48 12      1024 16 i  262144 16w 
119:  0   31   1  1  15  1      32  8        48 12      1024 16 i  262144 16w 
120:  0   81   5  5  40  1      32  8        48 12      1024 16 i  262144 16w 
121:  0   83   5  5  41  1      32  8        48 12      1024 16 i  262144 16w 
122:  0   85   5  5  42  1      32  8        48 12      1024 16 i  262144 16w 
123:  0   87   5  5  43  1      32  8        48 12      1024 16 i  262144 16w 
124:  0   89   5  5  44  1      32  8        48 12      1024 16 i  262144 16w 
125:  0   91   5  5  45  1      32  8        48 12      1024 16 i  262144 16w 
126:  0   93   5  5  46  1      32  8        48 12      1024 16 i  262144 16w 
127:  0   95   5  5  47  1      32  8        48 12      1024 16 i  262144 16w 

                              Zen UMC  [12C0]                              
Controller #0                                               Twelve Channel 
 Bus Rate  2400 MHz       Bus Speed 2400 MHz       REG DDR5 Speed 4800 MT/s
                                                                           
 Cha   CL  RCDr RCDw  RP  RAS   RC  RRDs RRDl FAW  WTRs WTRl  WR  clRR clWW
  #0   40   39   39   39   77  116    8   12   32    6   24   72    5   41 
  #1   40   39   39   39   77  116    8   12   32    6   24   72    5   41 
  #2   40   39   39   39   77  116    8   12   32    6   24   72    5   41 
  #3   40   39   39   39   77  116    8   12   32    6   24   72    5   41 
  #4   40   39   39   39   77  116    8   12   32    6   24   72    5   41 
  #5   40   39   39   39   77  116    8   12   32    6   24   72    5   41 
  #6   40   39   39   39   77  116    8   12   32    6   24   72    5   41 
  #7   40   39   39   39   77  116    8   12   32    6   24   72    5   41 
  #8   40   39   39   39   77  116    8   12   32    6   24   72    5   41 
  #9   40   39   39   39   77  116    8   12   32    6   24   72    5   41 
  #10  40   39   39   39   77  116    8   12   32    6   24   72    5   41 
  #11  40   39   39   39   77  116    8   12   32    6   24   72    5   41 
      CWL  RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
  #0   38   18   19    5    1    1    1    1    5    5    0    0    0    0 
  #1   38   18   19    5    1    1    1    1    5    5    0    0    0    0 
  #2   38   18   20    5    1    1    1    1    5    5    0    0    0    0 
  #3   38   18   19    5    1    1    1    1    5    5    0    0    0    0 
  #4   38   18   19    5    1    1    1    1    5    5    0    0    0    0 
  #5   38   18   20    5    1    1    1    1    5    5    0    0    0    0 
  #6   38   18   20    5    1    1    1    1    5    5    0    0    0    0 
  #7   38   18   20    5    1    1    1    1    5    5    0    0    0    0 
  #8   38   18   20    5    1    1    1    1    5    5    0    0    0    0 
  #9   38   18   18    5    1    1    1    1    5    5    0    0    0    0 
  #10  38   18   19    5    1    1    1    1    5    5    0    0    0    0 
  #11  38   18   20    5    1    1    1    1    5    5    0    0    0    0 
      REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt  Ban  Page  CKE  CMD  GDM  ECC
  #0  9347  708  384  312   0    0    ON OFF  R0W0   0    3   1T   OFF   1 
  #1  9347  708  384  312   0    0    ON OFF  R0W0   0    3   1T   OFF   1 
  #2  9347  708  384  312   0    0    ON OFF  R0W0   0    3   1T   OFF   1 
  #3  9347  708  384  312   0    0    ON OFF  R0W0   0    3   1T   OFF   1 
  #4  9347  708  384  312   0    0    ON OFF  R0W0   0    3   1T   OFF   1 
  #5  9347  708  384  312   0    0    ON OFF  R0W0   0    3   1T   OFF   1 
  #6  9347  708  384  312   0    0    ON OFF  R0W0   0    3   1T   OFF   1 
  #7  9347  708  384  312   0    0    ON OFF  R0W0   0    3   1T   OFF   1 
  #8  9347  708  384  312   0    0    ON OFF  R0W0   0    3   1T   OFF   1 
  #9  9347  708  384  312   0    0    ON OFF  R0W0   0    3   1T   OFF   1 
  #10 9347  708  384  312   0    0    ON OFF  R0W0   0    3   1T   OFF   1 
  #11 9347  708  384  312   0    0    ON OFF  R0W0   0    3   1T   OFF   1 
      MRD:PDA   MOD:PDA  WRMPR STAG PDM RDDATA WRD  WRL  RDL  XS   XP CPDED
  #0   34  32    34  32    24   36 0:P:1   25   6   23   42  732   18   12 
  #1   34  32    34  32    24   36 0:P:1   25   6   23   42  732   18   12 
  #2   34  32    34  32    24   36 0:P:1   25   6   23   42  732   18   12 
  #3   34  32    34  32    24   36 0:P:1   25   6   23   40  732   18   12 
  #4   34  32    34  32    24   36 0:P:1   25   6   23   40  732   18   12 
  #5   34  32    34  32    24   36 0:P:1   25   6   23   42  732   18   12 
  #6   34  32    34  32    24   36 0:P:1   25   6   23   42  732   18   12 
  #7   34  32    34  32    24   36 0:P:1   25   6   23   42  732   18   12 
  #8   34  32    34  32    24   36 0:P:1   25   6   23   42  732   18   12 
  #9   34  32    34  32    24   36 0:P:1   25   6   23   40  732   18   12 
  #10  34  32    34  32    24   36 0:P:1   25   6   23   40  732   18   12 
  #11  34  32    34  32    24   36 0:P:1   25   6   23   42  732   18   12 
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    32    1     65536      2048          32768  M321R4GA0BB0-CQKET
       #1                                                                  
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    32    1     65536      2048          32768  M321R4GA0BB0-CQKET
       #1                                                                  
 DIMM Geometry for channel #2                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    32    1     65536      2048          32768  M321R4GA0BB0-CQKET
       #1                                                                  
 DIMM Geometry for channel #3                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    32    1     65536      2048          32768  M321R4GA0BB0-CQKET
       #1                                                                  
 DIMM Geometry for channel #4                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    32    1     65536      2048          32768  M321R4GA0BB0-CQKET
       #1                                                                  
 DIMM Geometry for channel #5                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    32    1     65536      2048          32768  M321R4GA0BB0-CQKET
       #1                                                                  
 DIMM Geometry for channel #6                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    32    1     65536      2048          32768  M321R4GA0BB0-CQKET
       #1                                                                  
 DIMM Geometry for channel #7                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    32    1     65536      2048          32768  M321R4GA0BB0-CQKET
       #1                                                                  
 DIMM Geometry for channel #8                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    32    1     65536      2048          32768  M321R4GA0BB0-CQKET
       #1                                                                  
 DIMM Geometry for channel #9                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    32    1     65536      2048          32768  M321R4GA0BB0-CQKET
       #1                                                                  
 DIMM Geometry for channel #10                                             
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    32    1     65536      2048          32768  M321R4GA0BB0-CQKET
       #1                                                                  
 DIMM Geometry for channel #11                                             
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    32    1     65536      2048          32768  M321R4GA0BB0-CQKET
       #1