- macOS 或 Linux 主机
- 已安装 OpenClaw
- Telegram bot(用于接收转录结果)
An online meetup hosted by the RISC-V International China community on April 10, 2026. Presented by:
- Jian Zhang — Open-Source RISC-V CPU Product Manager
- Guodong Xu — SW Director, RISCstar; RISC-V Ecosystem Practitioner
Research Report — February 2026 Audience: Senior kernel engineers (particularly RISC-V), for architectural comparison
Intel's introduction of hybrid (big.LITTLE-style) x86 CPUs starting with Alder Lake in 2021 created an unprecedented problem in the x86 ecosystem: heterogeneous ISA support across cores within a single package. The P-cores (Golden Cove) supported AVX-512 while the E-cores (Gracemont) did not. Intel's handling of this — disabling AVX-512 across the entire chip — and their multi-year journey toward AVX10 as a solution provides critical lessons for any ISA designer considering heterogeneous core designs. This report covers the technical details, the OS scheduling implications, and comparisons with Arm, Apple, and RISC-V approaches.
February 12, 2026
If you're a developer in China trying to use Claude Code, you've probably hit the 403 wall. This guide covers how to get it working in three scenarios:
- macOS Terminal (shell) - using
claudeCLI directly in your terminal - VS Code Terminal - using
claudeCLI inside VS Code's integrated terminal - VS Code Claude Code Extension - using the Claude Code chat panel (installed as a VS Code extension)