[RapidWright] Series 7 HP/HR IOB IBUFDS Experiment

series7_ibufds_test.py

import rapidwright
from com.xilinx.rapidwright.design import Cell, Design, Net, NetType, PinType, SiteInst, SitePinInst, Unisim
from com.xilinx.rapidwright.device import Node, PIP, Series, Site, Wire
from com.xilinx.rapidwright.edif import EDIFDirection, EDIFHierNet, EDIFNet, EDIFNetlist, EDIFPortInst, EDIFTools
from com.xilinx.rapidwright.router import Router

# Uncomment one part or the other to test IBUFDS placement at HP IOB or HR IOB site.
part = "xc7k325tffg900-2" # HP IOB
# part = "xc7a200tfbg484-3" # HR IOB
des = Design("top", part)

edif_top = des.getTopEDIFCell()

if part == "xc7k325tffg900-2":
    lut      = des.createAndPlaceCell("lut",    Unisim.AND2, "SLICE_X100Y100/D6LUT")
    ff       = des.createAndPlaceCell("ff",     Unisim.FDCE, "SLICE_X100Y101/DFF")
    ff2      = des.createAndPlaceCell("ff2",    Unisim.FDCE, "SLICE_X100Y102/DFF")
    button0  = des.createAndPlaceIOB("button0", PinType.IN,  "Y28", "LVCMOS25")
    button1  = des.createAndPlaceIOB("button1", PinType.IN,  "AA28", "LVCMOS25")
    led0     = des.createAndPlaceIOB("led0",    PinType.OUT, "AB8", "LVCMOS15")
    # clk_p:AD12, clk_n:AD11 (HP IOB)
    clk_p_si = des.createSiteInst(des.getDevice().getSiteFromPackagePin("AD12"))
    clk_n_si = des.createSiteInst(des.getDevice().getSiteFromPackagePin("AD11"))
    clk_io_std = "LVDS"
else: # part == "xc7a200tfbg484-3"
    lut      = des.createAndPlaceCell("lut",    Unisim.AND2, "SLICE_X100Y100/D6LUT")
    ff       = des.createAndPlaceCell("ff",     Unisim.FDCE, "SLICE_X100Y101/DFF")
    ff2      = des.createAndPlaceCell("ff2",    Unisim.FDCE, "SLICE_X101Y102/DFF")
    button0  = des.createAndPlaceIOB("button0", PinType.IN,  "AB8", "LVCMOS33")
    button1  = des.createAndPlaceIOB("button1", PinType.IN,  "AA8", "LVCMOS33")
    led0     = des.createAndPlaceIOB("led0",    PinType.OUT, "G3", "LVCMOS33")
    # clk_p:J19, clk_n:H19 (HR IOB)
    clk_p_si = des.createSiteInst(des.getDevice().getSiteFromPackagePin("J19"))
    clk_n_si = des.createSiteInst(des.getDevice().getSiteFromPackagePin("H19"))
    clk_io_std = "DIFF_SSTL15"

ibuf_bel_type = "INBUF_DCIEN" if clk_p_si.getBEL("INBUF_DCIEN") is not None else "INBUF_EN"
# createAndPlaceCell fails due to the following error:
# java.lang.RuntimeException: java.lang.RuntimeException: ERROR: Site type IOB33 not supported for cell type IBUFDS
# clk_ibuf = des.createAndPlaceCell("clk", Unisim.IBUFDS, clk_p_ibuf_loc) # This fails...
clk_ibuf = des.createCell("clk_ibuf", Unisim.IBUFDS)
clk_ibuf.addProperty("IOSTANDARD", clk_io_std)
# HR IOB: INBUF_EN; HP IOB: INBUF_DCIEN
ibuf_placed = des.placeCell(clk_ibuf, clk_p_si.getSite(), clk_p_si.getBEL(ibuf_bel_type))
assert ibuf_placed, f"Failed to place IBUFDS at {clk_p_si.getSiteName()}/{ibuf_bel_type}"

# check default clk site pip status
print(f"default clk site pips status:")
for site_pip in clk_p_si.getSitePIPs():
    print(f"\tclk_p_si SitePIP: {site_pip} {clk_p_si.getSitePIPStatus(site_pip.getIndex())}")
for site_pip in clk_n_si.getSitePIPs():
    print(f"\tclk_n_si SitePIP: {site_pip} {clk_n_si.getSitePIPStatus(site_pip.getIndex())}")

#         button0 & button1 -> FF -> FF2 -> led0
#                              ^     ^
#                              |     |
# clk_p,clk_n->IBUFDS->clk --->+-----+

# add BEL physical pin mapping to logical GND to resolve error:
# CRITICAL WARNING: [Constraints 18-4523] Instance clk_ibuf InstTerm GND does not exist.
clk_ibuf.addPinMapping("IBUFDISABLE", "GLOBAL_LOGIC0")
if ibuf_bel_type == "INBUF_EN":
    clk_ibuf.addPinMapping("INTERMDISABLE", "GLOBAL_LOGIC0")

# Set Site PIPs
# Note: already handled by routeIntraSiteNet
# clk_p_si.addSitePIP("IUSED", "0")
# if ibuf_bel_type == "INBUF_EN":
#     clk_p_si.addSitePIP("INTERMDISABLE_SEL", "GND")
# clk_p_si.addSitePIP("IBUFDISABLE_SEL", "GND")
# clk_p_si.addSitePIP("DIFFI_INUSED", "0")
# clk_n_si.addSitePIP("PADOUTUSED", "0")

clk_p_net = des.createNet("clk_p")
clk_n_net = des.createNet("clk_n")
edif_clk_p_port_inst = EDIFTools.createTopLevelPortInst(des, "clk_p", PinType.IN)
edif_clk_n_port_inst = EDIFTools.createTopLevelPortInst(des, "clk_n", PinType.IN)
clk_p_net.getLogicalNet().addPortInst(edif_clk_p_port_inst)
clk_n_net.getLogicalNet().addPortInst(edif_clk_n_port_inst)
clk_p_net.connect(clk_ibuf, "I")
clk_n_net.connect(clk_ibuf, "IB")

# route clk IOB site wires
clk_p_si.routeIntraSiteNet(des.getGndNet(), clk_p_si.getBELPin("IBUFDISABLE_GND", "0"), clk_p_si.getBELPin("IBUFDISABLE_SEL", "OUT"))
if ibuf_bel_type == "INBUF_EN":
    clk_p_si.routeIntraSiteNet(des.getGndNet(), clk_p_si.getBELPin("INTERMDISABLE_GND", "0"), clk_p_si.getBELPin("INTERMDISABLE_SEL", "OUT"))
clk_n_si.routeIntraSiteNet(clk_n_net, clk_n_si.getBELPin("PAD", "PAD"), clk_n_si.getBELPin("PADOUTUSED", "OUT"))

# fix WARNING: clk_n does not have a source pin associated with it.
clk_n_net.addPin(SitePinInst(PinType.OUT, "PADOUT", clk_n_si))
clk_n_net.addPin(SitePinInst(PinType.IN, "DIFFI_IN", clk_p_si))

clk_net = des.createNet("clk")
clk_net.connect(clk_ibuf, "O")
clk_net.connect(ff, "C")
clk_net.connect(ff2, "C")

button0_net = des.createNet("button0_ibuf")
button0_net.connect(button0, "O")
button0_net.connect(lut, "I0")

button1_net = des.createNet("button1_ibuf")
button1_net.connect(button1, "O")
button1_net.connect(lut, "I1")

and_out_net = des.createNet("and_out")
and_out_net.connect(lut, "O")
and_out_net.connect(ff, "D")

ffq1_net = des.createNet("ffq1")
ffq1_net.connect(ff, "Q")
ffq1_net.connect(ff2, "D")

ffq2_net = des.createNet("ffq2")
ffq2_net.connect(ff2, "Q")
ffq2_net.connect(led0, "I")

print(f"new clk site pips status:")
for site_pip in clk_p_si.getSitePIPs():
    print(f"\tclk_p_si SitePIP: {site_pip} {clk_p_si.getSitePIPStatus(site_pip.getIndex())}")
for site_pip in clk_n_si.getSitePIPs():
    print(f"\tclk_n_si SitePIP: {site_pip} {clk_n_si.getSitePIPStatus(site_pip.getIndex())}")

for cell in des.getCells():
    print(f"phys cell: {cell}")

for net in des.getNets():
    print(f"phys net: {net}")
    for pin in net.getPins():
        print(f"\tpin: {pin}")
    for pip in net.getPIPs():
        print(f"\tpip: {pip}")

for cell in edif_top.getCellInsts():
    print(f"edif cell: {cell}")

for net in edif_top.getNets():
    print(f"edif net: {net}")
    for port in net.getPortInsts():
        print(f"\tedif port: {port}")

for port in edif_top.getPorts():
    print(f"edif port: {port}")

# intra-site routing
# des.routeSites()

# perform rest of the routing
# Router(des).routeDesign()

des.writeCheckpoint(f"{part}_ibufds_test.dcp")