Skip to content

Instantly share code, notes, and snippets.

@punzik
punzik / sta_cdc_paths.rst
Created February 29, 2024 05:28 — forked from brabect1/sta_cdc_paths.rst
Timing constraints for clock-domain crossings. #sta #cdc
@punzik
punzik / Makefile
Created December 29, 2023 14:28
Yosys DPI
LIB_NAME = my_lib
SOURCES = my_lib.c
$(LIB_NAME).so: $(SOURCES)
gcc -O2 -shared -o $(LIB_NAME).so $(SOURCES)
@punzik
punzik / print-to-terminal-pts.c
Last active February 19, 2024 17:10
Print to terminal via pts
#define _GNU_SOURCE
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <signal.h>
#include <string.h>
volatile int running = 1;
@punzik
punzik / print-to-terminal.c
Last active November 20, 2023 20:22
Print to terminal
#include <stdio.h>
#include <stdlib.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#include <signal.h>
#define FIFO_FILE "/tmp/veri.log"
#define TERM_EMU_CMD "xterm -e 'cat /tmp/veri.log'"
@punzik
punzik / unary_counter.psl
Created September 1, 2023 15:01
VHDL formal verification tryout
vunit unary_counter_prop(unary_counter(unary_counter_arch)) {
constant all_zeros : std_logic_vector(LENGTH-1 downto 0) := (others => '0');
constant all_ones : std_logic_vector(LENGTH-1 downto 0) := (others => '1');
default clock is rising_edge(clk);
--
-- Check for counter code is a unary code
--
signal f_check_out: std_logic_vector(LENGTH-1 downto 0) := all_zeros;
@punzik
punzik / build.zig
Created August 18, 2023 15:32
Minimal bare-metal PicoRV32 Zig example
const std = @import("std");
const CrossTarget = @import("std").zig.CrossTarget;
const Target = @import("std").Target;
const Feature = @import("std").Target.Cpu.Feature;
pub fn build(b: *std.Build) void {
const features = Target.riscv.Feature;
var disabled_features = Feature.Set.empty;
var enabled_features = Feature.Set.empty;
@punzik
punzik / axi-transaction-filter.scm
Last active July 30, 2023 20:10
GTKWave transaction filter example
#!/usr/bin/env guile
!#
;; -*- geiser-scheme-implementation: guile -*-
(import (ice-9 textual-ports) ; read port by lines
(srfi srfi-1) ; lists
(srfi srfi-11) ; let-values
(srfi srfi-13) ; strings
(srfi srfi-26) ; cut
import pygame
import numpy as np
# Import pygame.locals for easier access to key coordinates
from pygame.locals import (
K_UP,
K_DOWN,
K_LEFT,
K_RIGHT,
K_ESCAPE,
`timescale 1ps/1ps
`default_nettype none
module seq #(parameter SEQUENCE = "")
(input wire clock,
output reg out);
int l, n;
string s;
@punzik
punzik / onehot_detector.sby
Last active November 15, 2022 16:21
One-hot state detector
# To run formal verification call SymbiYosys:
# $ sby -f onehot_detector.sby
[options]
mode prove
[engines]
smtbmc yices
[script]