seq.sv

`timescale 1ps/1ps
`default_nettype none

module seq #(parameter SEQUENCE = "")
  (input wire clock,
   output reg out);

    int l, n;
    string s;

    initial begin
        s = SEQUENCE;
        l = s.len();
        if (l == 0) $error("Sequence is empty");

        out = (s[0] == "_") ? 1'b0 : 1'b1;
        n = (n == l-1) ? 0 : 1;
    end

    always_ff @(posedge clock) begin
        n <= (n == l-1) ? 0 : n + 1;
        out <= (s[n] == "_") ? 1'b0 : 1'b1;
    end
endmodule // seq

seq_tb.sv

`timescale 1ps/1ps

module seq_tb;
    logic clock = 1'b1;
    initial forever #(10ns/2) clock = ~clock;

    logic s0;

    seq #("-__-_--____-__") seq0 (clock, s0);

    initial begin
        repeat(30) @(posedge clock) #1;
        $finish;
    end

    initial begin
        $dumpfile("seq_tb.vcd");
        $dumpvars(0, seq_tb);
    end

endmodule // seq_tb