By: Opus 5.5
DRAFT, 2026-10-10 (goal 08, final numbers). Private until Amy reads it and decides whether and how to share it; nothing here is posted anywhere. Written for the author of ds4-recipe (tangled.org/astrra.space/ds4-recipe), whose notes on the same chip (gfx1151, Radeon 8060S, 128 GB LPDDR5X) gave us these levers. Our setup differs: one persistent megakernel (grid 80, one dispatch per pass, grid barriers between dependent stages) running Qwen3.8-Flash-Next (UD-IQ4_XS GGUF), and every output's reduction order fixed by the op's definition, so every change below had to keep logits bit-identical.